An operational amplifier circuit

Abstract

The application discloses an operational amplifier circuit and relates to the technical field of integrated circuits.The application introduces two feedforward zero points in the circuit through a first feedforward transconductance module and a second feedforward transconductance module, improves the gain, bandwidth and phase of the operational amplifier, amplifies the signal again through a push-pull structure, and compensates the frequency of the operational amplifier circuit through an inverse pole splitting compensation module, so that the bandwidth of the operational amplifier is improved, and finally, the output level of the operational amplifier circuit is detected through a common-mode feedback module; the bandwidth of the operational amplifier circuit of the application is improved, so that the operational amplifier circuit of the application can have higher working performance in a high-speed and low-power consumption scene.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an operational amplifier circuit. Background Art

[0002] An operational amplifier is a DC-coupled amplifier with extremely high gain and linearity. Its basic function is to amplify the input signal. As an important component of integrated circuits, it has been widely used in digital signal processing, wireless communications, automotive electronics and other fields.

[0003] With the continuous development of integrated circuit technology, the performance requirements for operational amplifiers are also increasing. For example, operational amplifiers are required to have higher precision or lower power consumption. However, the amplification performance of current operational amplifiers in high-speed and low-power scenarios is insufficient and cannot meet application requirements. Therefore, how to design a new operational amplifier circuit that can be suitable for high-speed and low-power scenarios has become a difficult problem that needs to be solved urgently. Summary of the Invention

[0004] The present invention provides an operational amplifier circuit to solve the technical problem of how to improve the operating performance of an operational amplifier in a high-speed and low-power scenario.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides an operational amplifier circuit, comprising: a first transconductance module, a second transconductance module, a third transconductance module, a fourth transconductance module, a first feedforward transconductance module, a second feedforward transconductance module, a buffer module, an anti-pole splitting compensation module, and a common-mode feedback module;

[0006] The input end of the first transconductance module is electrically connected to the input end of the first feedforward transconductance module;

[0007] The output end of the first transconductance module is electrically connected to the input end of the second transconductance module;

[0008] The output end of the second transconductance module is electrically connected to the output end of the first feedforward transconductance module;

[0009] The output end of the buffer module is electrically connected to the input end of the fourth transconductance module;

[0010] The output end of the fourth transconductance module is electrically connected to the output end of the third transconductance module;

[0011] An input terminal of the second feedforward transconductance module is electrically connected to an input terminal of the first transconductance module;

[0012] The output end of the second feedforward transconductance module is electrically connected to the output end of the third transconductance module;

[0013] The input end of the third transconductance module is electrically connected to the output end of the second transconductance module;

[0014] The input end of the buffer module is electrically connected to the output end of the second transconductance module;

[0015] The input end of the anti-pole splitting compensation module is electrically connected to the output end of the second transconductance module;

[0016] The output end of the anti-pole splitting compensation module is electrically connected to the output end of the third transconductance module;

[0017] The input end of the common-mode feedback module is electrically connected to the output end of the third transconductance module;

[0018] The output end of the common-mode feedback module is electrically connected to the output end of the second transconductance module;

[0019] The first transconductance module is electrically connected to the buffer module;

[0020] The first transconductance module is electrically connected to the common mode feedback module;

[0021] The input end of the first transconductance module serves as the input end of the operational amplifier circuit;

[0022] The output end of the third transconductance module serves as the output end of the operational amplifier circuit.

[0023] It can be understood that, compared with the prior art, the present invention performs preliminary amplification on the input signal through the first transconductance module, the second transconductance module and the first feedforward transconductance module to obtain the first signal, and on the other hand, amplifies the input signal through the second feedforward transconductance module to obtain the second signal; the third transconductance module, the fourth transconductance module and the cache module together form a push-pull structure, and amplifies the first signal again to obtain the third signal; two feedforward zero points are introduced into the circuit through the first feedforward transconductance module and the second feedforward transconductance module, thereby improving the gain, bandwidth and phase of the operational amplifier; the signal is amplified again through the push-pull structure, and the operational amplifier circuit is frequency compensated through the anti-pole splitting compensation module, thereby improving the bandwidth of the operational amplifier; finally, the output level of the operational amplifier circuit is detected through the common-mode feedback module, and by improving the bandwidth of the operational amplifier circuit of the present invention, the operational amplifier circuit of the present invention can have higher working performance in high-speed and low-power scenarios.

[0024] As a preferred option,

[0025] The operational amplifier circuit further includes: a power supply node, a first voltage node, and a second voltage node;

[0026] The first transconductance module includes: a first transistor, a second transistor, a third transistor, an eighteenth transistor and a nineteenth transistor;

[0027] The source of the first transistor is electrically connected to the power supply node;

[0028] The drain of the first transistor, the source of the second transistor and the source of the third transistor are electrically connected;

[0029] The drain of the first transistor is electrically connected to the first feedforward transconductance module;

[0030] The drain of the first transistor is electrically connected to the second feedforward transconductance module;

[0031] The gate of the first transistor is electrically connected to the buffer module;

[0032] The gate of the first transistor is electrically connected to the common-mode feedback module;

[0033] The gate of the second transistor is electrically connected to the second voltage node;

[0034] The drain of the second transistor, the drain of the eighteenth transistor and the gate of the eighteenth transistor are electrically connected;

[0035] The drain of the second transistor is electrically connected to the second transconductance module;

[0036] The gate of the third transistor is electrically connected to the first voltage node;

[0037] The drain of the third transistor, the gate of the nineteenth transistor and the drain of the nineteenth transistor are electrically connected;

[0038] The drain of the third transistor is electrically connected to the second transconductance module;

[0039] The source of the eighteenth transistor is grounded;

[0040] The source of the nineteenth transistor is grounded;

[0041] The third transistor serves as a first input terminal of the operational amplifier circuit, and is configured to receive a first voltage input signal output from a first voltage node;

[0042] The second transistor serves as a second input terminal of the operational amplifier circuit, and is configured to receive a second voltage input signal output from a second voltage node.

[0043] This preferred solution uses the first transconductance module, the second transconductance module and the first feedforward transconductance module to preliminarily amplify the input signal to obtain a first signal, and then uses the third transconductance module, the fourth transconductance module and the cache module to form a push-pull structure to amplify the first signal again to obtain a third signal, so that the operational amplifier circuit can have higher amplification performance in high-speed and low-power scenarios.

[0044] As a preferred option,

[0045] The second transconductance module includes: a twentieth transistor and a twenty-first transistor;

[0046] The gate of the twentieth transistor is electrically connected to the drain of the second transistor;

[0047] The source of the twentieth transistor is grounded;

[0048] The drain of the twentieth transistor is electrically connected to the third transconductance module;

[0049] The drain of the twentieth transistor is electrically connected to the buffer module;

[0050] The drain of the twentieth transistor is electrically connected to the first feedforward transconductance module;

[0051] The drain of the twentieth transistor is electrically connected to the common-mode feedback module;

[0052] The drain of the twentieth transistor is electrically connected to the anti-pole splitting compensation module;

[0053] The source of the twenty-first transistor is grounded;

[0054] a gate of the twenty-first transistor being electrically connected to a drain of the third transistor;

[0055] The drain of the twenty-first transistor is electrically connected to the third transconductance module;

[0056] The drain of the twenty-first transistor is electrically connected to the buffer module;

[0057] The drain of the twenty-first transistor is electrically connected to the first feedforward transconductance module;

[0058] The drain of the twenty-first transistor is electrically connected to the common-mode feedback module;

[0059] A drain of the twenty-first transistor is electrically connected to the anti-pole splitting compensation module.

[0060] This preferred solution uses the first transconductance module, the second transconductance module and the first feedforward transconductance module to preliminarily amplify the input signal to obtain a first signal, and then uses the third transconductance module, the fourth transconductance module and the cache module to form a push-pull structure to amplify the first signal again to obtain a third signal, so that the operational amplifier circuit can have higher amplification performance in high-speed and low-power scenarios.

[0061] As a preferred option,

[0062] The first feedforward transconductance module includes: a sixth transistor and a seventh transistor;

[0063] The gate of the sixth transistor is electrically connected to the second voltage node;

[0064] The source of the sixth transistor is electrically connected to the drain of the first transistor;

[0065] a drain of the sixth transistor being electrically connected to a drain of the twenty-first transistor;

[0066] The gate of the seventh transistor is electrically connected to the first voltage node;

[0067] The source of the seventh transistor is electrically connected to the drain of the first transistor;

[0068] a drain of the seventh transistor being electrically connected to a drain of the twentieth transistor;

[0069] The sixth transistor is used to feed forward the second voltage input signal output by the second voltage node;

[0070] The seventh transistor is configured to feed forward the first voltage input signal output from the first voltage node.

[0071] This preferred solution uses the first transconductance module, the second transconductance module and the first feedforward transconductance module to preliminarily amplify the input signal to obtain a first signal, and then uses the third transconductance module, the fourth transconductance module and the cache module to form a push-pull structure to amplify the first signal again to obtain a third signal, so that the operational amplifier circuit can have higher amplification performance in high-speed and low-power scenarios; the first feedforward transconductance module introduces a feedforward zero point into the circuit, thereby improving the gain, bandwidth and phase of the operational amplifier.

[0072] As a preferred option,

[0073] The operational amplifier circuit further includes: a third voltage node and a fourth voltage node;

[0074] The third transconductance module includes: a twenty-second transistor and a twenty-third transistor;

[0075] The gate of the 22nd transistor is electrically connected to the drain of the 20th transistor;

[0076] The source of the twenty-second transistor is grounded;

[0077] The drain of the twenty-second transistor is electrically connected to the third voltage node;

[0078] The drain of the twenty-second transistor is electrically connected to the fourth transconductance module;

[0079] The drain of the twenty-second transistor is electrically connected to the second feedforward transconductance module;

[0080] The drain of the twenty-second transistor is electrically connected to the anti-pole splitting compensation module;

[0081] The drain of the twenty-second transistor is electrically connected to the common-mode feedback module;

[0082] a gate of the twenty-third transistor being electrically connected to a drain of the twenty-first transistor;

[0083] The source of the twenty-third transistor is grounded;

[0084] a drain of the twenty-third transistor being electrically connected to the fourth voltage node;

[0085] The drain of the twenty-third transistor is electrically connected to the fourth transconductance module;

[0086] The drain of the twenty-third transistor is electrically connected to the second feedforward transconductance module;

[0087] The drain of the twenty-third transistor is electrically connected to the anti-pole splitting compensation module;

[0088] The drain of the twenty-third transistor is electrically connected to the common-mode feedback module;

[0089] The twenty-second transistor serves as a first output terminal of the operational amplifier circuit, and is configured to output a first voltage output signal to a third voltage node;

[0090] The twenty-third transistor serves as the second output terminal of the operational amplifier circuit, and is configured to output a second voltage output signal to a fourth voltage node.

[0091] This preferred solution uses the first transconductance module, the second transconductance module and the first feedforward transconductance module to preliminarily amplify the input signal to obtain a first signal, and then uses the third transconductance module, the fourth transconductance module and the cache module to form a push-pull structure to amplify the first signal again to obtain a third signal, so that the operational amplifier circuit can have higher amplification performance in high-speed and low-power scenarios.

[0092] As a preferred option,

[0093] The operational amplifier circuit further includes: a fifth voltage node and a sixth voltage node;

[0094] The buffer module includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a twenty-fourth transistor, and a twenty-fifth transistor;

[0095] The gate of the tenth transistor is electrically connected to the gate of the first transistor;

[0096] The source of the tenth transistor is electrically connected to the power supply node;

[0097] The drain of the tenth transistor is electrically connected to the fourth transconductance module;

[0098] The gate of the eleventh transistor is electrically connected to the gate of the first transistor;

[0099] The source of the eleventh transistor is electrically connected to the power supply node;

[0100] The drain of the eleventh transistor is electrically connected to the fourth transconductance module;

[0101] The gate of the twelfth transistor is electrically connected to the fifth voltage node;

[0102] The gate of the twelfth transistor is electrically connected to the gate of the thirteenth transistor;

[0103] The drain of the twelfth transistor is electrically connected to the drain of the twenty-first transistor;

[0104] The source of the twelfth transistor is electrically connected to the fourth transconductance module;

[0105] a drain of the thirteenth transistor being electrically connected to a drain of the twentieth transistor;

[0106] The source of the thirteenth transistor is electrically connected to the fourth transconductance module;

[0107] The gate of the twenty-fourth transistor is electrically connected to the sixth voltage node;

[0108] a gate of the twenty-fourth transistor is electrically connected to a gate of the twenty-fifth transistor;

[0109] The drain of the twenty-fourth transistor is electrically connected to the fourth transconductance module;

[0110] a source of the twenty-fourth transistor being electrically connected to a drain of the twentieth transistor;

[0111] The drain of the twenty-fifth transistor is electrically connected to the fourth transconductance module;

[0112] The source of the twenty-fifth transistor is electrically connected to the drain of the twenty-first transistor.

[0113] This preferred solution uses the first transconductance module, the second transconductance module and the first feedforward transconductance module to preliminarily amplify the input signal to obtain a first signal, and then uses the third transconductance module, the fourth transconductance module and the cache module to form a push-pull structure to amplify the first signal again to obtain a third signal, so that the operational amplifier circuit can have higher amplification performance in high-speed and low-power scenarios.

[0114] As a preferred option,

[0115] The fourth transconductance module includes: a fourth transistor and a fifth transistor;

[0116] The drain of the fourth transistor is electrically connected to the fourth voltage node;

[0117] a drain of the fourth transistor being electrically connected to a drain of the twenty-third transistor;

[0118] The source of the fourth transistor is electrically connected to the power supply node;

[0119] The gate of the fourth transistor, the drain of the tenth transistor, the source of the twelfth transistor and the drain of the twenty-fifth transistor are electrically connected;

[0120] The drain of the fifth transistor is electrically connected to the third voltage node;

[0121] The drain of the fifth transistor is electrically connected to the drain of the twenty-second transistor;

[0122] The source of the fifth transistor is electrically connected to the power supply node;

[0123] The gate of the fifth transistor, the drain of the eleventh transistor, the drain of the twenty-fourth transistor, and the source of the thirteenth transistor are electrically connected;

[0124] The drain of the fourth transistor serves as a third output terminal of the operational amplifier circuit, and is configured to output a third voltage output signal to a fourth voltage node;

[0125] The drain of the fifth transistor serves as a fourth output terminal of the operational amplifier circuit, and is configured to output a fourth voltage output signal to the third voltage node.

[0126] This preferred solution uses the first transconductance module, the second transconductance module and the first feedforward transconductance module to preliminarily amplify the input signal to obtain a first signal, and then uses the third transconductance module, the fourth transconductance module and the cache module to form a push-pull structure to amplify the first signal again to obtain a third signal, so that the operational amplifier circuit can have higher amplification performance in high-speed and low-power scenarios.

[0127] As a preferred option,

[0128] The second feedforward transconductance module includes: an eighth transistor and a ninth transistor;

[0129] The gate of the eighth transistor is electrically connected to the second voltage node;

[0130] The drain of the eighth transistor is electrically connected to the drain of the twenty-second transistor;

[0131] The source of the eighth transistor is electrically connected to the drain of the first transistor;

[0132] The gate of the ninth transistor is electrically connected to the first voltage node;

[0133] The drain of the ninth transistor is electrically connected to the drain of the twenty-third transistor;

[0134] The source of the ninth transistor is electrically connected to the drain of the first transistor;

[0135] The eighth transistor is used to feed forward the second voltage input signal output by the second voltage node;

[0136] The ninth transistor is configured to feed forward the first voltage input signal output from the first voltage node.

[0137] This preferred solution amplifies the input signal through a second feedforward transconductance module to obtain a second signal, thereby improving the operational amplifier circuit's ability to have higher operating performance in high-speed and low-power scenarios; by introducing a feedforward zero point into the circuit through the second feedforward transconductance module, the gain, bandwidth, and phase of the operational amplifier are improved.

[0138] As a preferred option,

[0139] The operational amplifier circuit further includes: a seventh voltage node;

[0140] The common-mode feedback module includes: a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a fifth resistor, a sixth resistor, a fifth capacitor, and a sixth capacitor;

[0141] The gate of the fourteenth transistor is electrically connected to the gate of the first transistor;

[0142] The source of the fourteenth transistor is electrically connected to the power supply node;

[0143] The drain of the fourteenth transistor, the source of the fifteenth transistor, and the source of the sixteenth transistor are electrically connected;

[0144] The gate of the fifteenth transistor, the second end of the fifth resistor, the second end of the sixth resistor, the second end of the fifth capacitor, and the second end of the sixth capacitor are electrically connected;

[0145] The drain of the fifteenth transistor, the gate of the twenty-sixth transistor, the drain of the twenty-sixth transistor, the gate of the twenty-eighth transistor, and the gate of the twenty-ninth transistor are electrically connected;

[0146] The gate of the sixteenth transistor is electrically connected to the seventh voltage node;

[0147] The drain of the sixteenth transistor, the gate of the twenty-seventh transistor, and the drain of the twenty-seventh transistor are electrically connected;

[0148] The source of the twenty-sixth transistor is grounded;

[0149] The source of the twenty-seventh transistor is grounded;

[0150] a drain of the twenty-eighth transistor being electrically connected to a drain of the twentieth transistor;

[0151] The source of the twenty-eighth transistor is grounded;

[0152] a drain of the twenty-ninth transistor being electrically connected to a drain of the twenty-first transistor;

[0153] The source of the twenty-ninth transistor is grounded;

[0154] a first end of the fifth resistor is electrically connected to the drain of the twenty-second transistor;

[0155] a first end of the sixth resistor is electrically connected to the drain of the twenty-third transistor;

[0156] a first terminal of the fifth capacitor is electrically connected to the drain of the twenty-second transistor;

[0157] A first end of the sixth capacitor is electrically connected to the drain of the twenty-third transistor.

[0158] This preferred solution detects the output level of the operational amplifier circuit so that the operational amplifier circuit can output a stable DC level under the action of negative feedback.

[0159] As a preferred option,

[0160] The anti-pole splitting compensation module includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor;

[0161] a first end of the first resistor is electrically connected to the drain of the twentieth transistor;

[0162] The second end of the first resistor is electrically connected to the second end of the first capacitor;

[0163] The first end of the first capacitor is electrically connected to the drain of the twenty-second transistor;

[0164] a first end of the second resistor being electrically connected to the drain of the twenty-first transistor;

[0165] The second end of the second resistor is electrically connected to the second end of the second capacitor;

[0166] a first terminal of the second capacitor is electrically connected to the drain of the twenty-third transistor;

[0167] a first end of the third resistor is electrically connected to the drain of the twenty-first transistor;

[0168] The second end of the third resistor is electrically connected to the second end of the third capacitor;

[0169] A first terminal of the third capacitor is electrically connected to the drain of the twenty-second transistor;

[0170] a first end of the fourth resistor is electrically connected to the drain of the twentieth transistor;

[0171] The second end of the fourth resistor is electrically connected to the second end of the fourth capacitor;

[0172] A first end of the fourth capacitor is electrically connected to the drain of the twenty-third transistor.

[0173] This preferred solution performs frequency compensation on the operational amplifier circuit through an anti-pole splitting compensation module, thereby improving the bandwidth of the operational amplifier, and thus enabling the operational amplifier circuit of the present invention to have higher operating performance in high-speed and low-power scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0174] Figure 1 : A connection diagram of an operational amplifier circuit provided by an embodiment of the present invention;

[0175] Figure 2 : A schematic diagram of an operational amplifier circuit provided in an embodiment of the present invention;

[0176] Figure 3 : A transfer function diagram of an operational amplifier circuit provided in an embodiment of the present invention;

[0177] Figure 4 : A diagram showing the gain and phase simulation results of an operational amplifier circuit provided in an embodiment of the present invention;

[0178] Figure 5 : A diagram showing the gain and phase simulation results of a common-mode feedback operational amplifier circuit provided by an embodiment of the present invention;

[0179] Figure 6 : A power supply rejection ratio simulation result diagram of an operational amplifier circuit provided by an embodiment of the present invention;

[0180] Figure 7 : A diagram showing the simulation results of input noise amplified by an operational amplifier circuit provided by an embodiment of the present invention;

[0181] Among them, 101: first transconductance module; 102: second transconductance module; 103: third transconductance module; 104: fourth transconductance module; 105: first feedforward transconductance module; 106: second feedforward transconductance module; 107: buffer module; 108: anti-pole splitting compensation module; 109: common-mode feedback module; 110: bias module; MP1: first transistor; MP2: second transistor; MP3: third transistor; MP4: fourth transistor; MP5: fifth transistor; MP6: sixth transistor; MP7: seventh transistor; MP8: eighth transistor; MP9: ninth transistor; MP10: tenth transistor; MP11: eleventh transistor; MP12: twelfth transistor; MP13: thirteenth transistor; MP14: fourteenth transistor; MP15: fifteenth transistor; MP16: sixteenth transistor; MP17: seventeenth transistor; MN1: eighteenth transistor; MN2: eighteenth transistor; MN3: eighteenth transistor; MN4: eighteenth transistor; MN5: eighteenth transistor; MN6: eighteenth transistor; MN7: eighteenth transistor; MN8: eighteenth transistor; MN9: nineteenth transistor; MN1: eighteenth transistor; MN MN2: nineteenth transistor; MN3: twentieth transistor; MN4: twenty-first transistor; MN5: twenty-second transistor; MN6: twenty-third transistor; MN7: twenty-fourth transistor; MN8: twenty-fifth transistor; MN9: twenty-sixth transistor; MN10: twenty-seventh transistor; MN11: twenty-eighth transistor; MN12: twenty-ninth transistor; R1: first resistor; R2: second resistor; R3: third resistor; R4: fourth resistor; R5: fifth resistor; R6: sixth resistor; C1: first capacitor; C2: second capacitor; C3: third capacitor; C4: fourth capacitor; C5: fifth capacitor; C6: sixth capacitor; VDD: power supply node; GND: ground node; V1: first voltage node; V2: second voltage node; V3: third voltage node; V4: fourth voltage node; V5: fifth voltage node; V6: sixth voltage node; V7: seventh voltage node;

[0182] N1: first node; N2: second node; N3: third node; N4: fourth node; N5: fifth node; N6: sixth node; N9: ninth node; N10: tenth node; N11: eleventh node; N12: twelfth node; N13: thirteenth node; N14: fourteenth node. DETAILED DESCRIPTION

[0183] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0184] Operational amplifiers (OPA), a key module in integrated circuits, are widely used in digital signal processing, wireless communications, medical, and automotive electronics. With the continuous advancement of integrated circuit technology, higher performance requirements are being placed on operational amplifiers (OPA) in terms of speed, accuracy, power consumption, and noise. Designing an OPA with high speed, high accuracy, low noise, high linearity, and low power consumption is a pressing challenge.

[0185] Example 1

[0186] Please refer to Figure 1 , which is a connection diagram of an operational amplifier circuit provided by an embodiment of the present invention, including: a first transconductance module 101, a second transconductance module 102, a third transconductance module 103, a fourth transconductance module 104, a first feedforward transconductance module 105, a second feedforward transconductance module 106, a buffer module 107, an anti-pole splitting compensation module 108, and a common-mode feedback module 109;

[0187] The input end of the first transconductance module 101 is electrically connected to the input end of the first feedforward transconductance module 105;

[0188] The output end of the first transconductance module 101 is electrically connected to the input end of the second transconductance module 102;

[0189] The output end of the second transconductance module 102 is electrically connected to the output end of the first feedforward transconductance module 105;

[0190] The output end of the buffer module 107 is electrically connected to the input end of the fourth transconductance module 104;

[0191] The output end of the fourth transconductance module 104 is electrically connected to the output end of the third transconductance module 103;

[0192] An input terminal of the second feedforward transconductance module 106 is electrically connected to an input terminal of the first transconductance module 101;

[0193] The output end of the second feedforward transconductance module 106 is electrically connected to the output end of the third transconductance module 103;

[0194] The input end of the third transconductance module 103 is electrically connected to the output end of the second transconductance module 102;

[0195] The input end of the buffer module 107 is electrically connected to the output end of the second transconductance module 102;

[0196] The input end of the anti-pole splitting compensation module 108 is electrically connected to the output end of the second transconductance module 102;

[0197] The output end of the anti-pole splitting compensation module 108 is electrically connected to the output end of the third transconductance module 103;

[0198] The input end of the common mode feedback module 109 is electrically connected to the output end of the third transconductance module 103;

[0199] The output end of the common-mode feedback module 109 is electrically connected to the output end of the second transconductance module 102;

[0200] The first transconductance module 101 is electrically connected to the buffer module 107;

[0201] The first transconductance module 101 is electrically connected to the common mode feedback module 109;

[0202] The input end of the first transconductance module 101 serves as the input end of the operational amplifier circuit;

[0203] The output end of the third transconductance module 103 serves as the output end of the operational amplifier circuit.

[0204] In some implementations of this embodiment, please refer to Figure 1 , the operating principle of the operational amplifier circuit of the present invention is as follows:

[0205] The initial signal (i.e., the input signal) is amplified into a first signal by the first transconductance module 101, the second transconductance module 102, and the first feedforward transconductance module 105;

[0206] The initial signal is amplified into a second signal by the second feedforward transconductance module 106;

[0207] The first signal is amplified into a third signal through a push-pull structure composed of the third transconductance module 103, the fourth transconductance module 104 and the buffer module 107;

[0208] The output signal includes: a second signal and a third signal.

[0209] In some implementations of this embodiment, please refer to Figure 1 Two feedforward zeros are introduced into the operational amplifier circuit through the first feedforward transconductance module 105 and the second feedforward transconductance module 106, thereby changing the gain, bandwidth, and phase of the operational amplifier. The anti-pole splitting compensation module 108 performs frequency compensation on the operational amplifier circuit to increase the bandwidth of the operational amplifier. The common-mode feedback module 109 detects the output level of the operational amplifier circuit, so that under the action of negative feedback, the operational amplifier circuit outputs a stable DC level.

[0210] Please refer to Figure 2 , is a schematic diagram of an operational amplifier circuit provided in an embodiment of the present invention.

[0211] In this embodiment, the operational amplifier circuit further includes: a power supply node VDD, a first voltage node V1, a second voltage node V2, a third voltage node V3, a fourth voltage node V4, a fifth voltage node V5, a sixth voltage node V6, a seventh voltage node V7, and a ground point GND, wherein the ground point is used for grounding;

[0212] In this embodiment, please refer to Figure 2 The specific principle of the first transconductance module 101 in the operational amplifier circuit of the present invention is as follows:

[0213] The first transconductance module 101 includes: a first transistor MP1, a second transistor MP2, a third transistor MP3, an eighteenth transistor MN1 and a nineteenth transistor MN2;

[0214] The source of the first transistor MP1 is electrically connected to the power supply node VDD;

[0215] The drain of the first transistor MP1, the source of the second transistor MP2 and the source of the third transistor MP3 are electrically connected;

[0216] The drain of the first transistor MP1 is electrically connected to the first feedforward transconductance module 105;

[0217] The drain of the first transistor MP1 is electrically connected to the second feedforward transconductance module 106;

[0218] The gate of the first transistor MP1 is electrically connected to the buffer module 107;

[0219] The gate of the first transistor MP1 is electrically connected to the common-mode feedback module 109;

[0220] The gate of the second transistor MP2 is electrically connected to the second voltage node V2;

[0221] The drain of the second transistor MP2, the drain of the eighteenth transistor MN1, and the gate of the eighteenth transistor MN1 are electrically connected;

[0222] The drain of the second transistor MP2 is electrically connected to the second transconductance module 102;

[0223] The gate of the third transistor MP3 is electrically connected to the first voltage node V1;

[0224] The drain of the third transistor MP3, the gate of the nineteenth transistor MN2 and the drain of the nineteenth transistor MN2 are electrically connected;

[0225] The drain of the third transistor MP3 is electrically connected to the second transconductance module 102;

[0226] The source of the eighteenth transistor MN1 is grounded;

[0227] The source of the nineteenth transistor MN1 is grounded;

[0228] The third transistor MP3 serves as a first input terminal of the operational amplifier circuit, and is configured to receive a first voltage input signal output from the first voltage node V1;

[0229] The second transistor MP2 serves as a second input terminal of the operational amplifier circuit, and is configured to receive a second voltage input signal output from a second voltage node V2.

[0230] In this embodiment, please refer to Figure 2 The specific principle of the second transconductance module 102 in the operational amplifier circuit of the present invention is as follows:

[0231] The second transconductance module 102 includes: a twentieth transistor MN3 and a twenty-first transistor MN4;

[0232] A gate of the twentieth transistor MN3 and a drain of the second transistor MP2 are electrically connected to a third node N3;

[0233] The source of the twentieth transistor MN3 is grounded;

[0234] The drain of the twentieth transistor MN3 is electrically connected to the third transconductance module 103;

[0235] The drain of the twentieth transistor MN3 is electrically connected to the buffer module 107;

[0236] The drain of the twentieth transistor MN3 is electrically connected to the first feedforward transconductance module 105;

[0237] The drain of the twentieth transistor MN3 is electrically connected to the common-mode feedback module 109;

[0238] The drain of the twentieth transistor MN3 is electrically connected to the anti-pole splitting compensation module 108;

[0239] The source of the twenty-first transistor MN4 is grounded;

[0240] A gate of the twenty-first transistor MN4 is electrically connected to a drain of the third transistor MP3;

[0241] The drain of the twenty-first transistor MN4 is electrically connected to the third transconductance module 103;

[0242] The drain of the twenty-first transistor MN4 is electrically connected to the buffer module 107;

[0243] The drain of the twenty-first transistor MN4 is electrically connected to the first feedforward transconductance module 105;

[0244] The drain of the twenty-first transistor MN4 is electrically connected to the common-mode feedback module 109;

[0245] A drain of the twenty-first transistor MN4 is electrically connected to the anti-pole splitting compensation module 108 .

[0246] In this embodiment, please refer to Figure 2 The specific principle of the first feedforward transconductance module 105 in the operational amplifier circuit of the present invention is as follows:

[0247] The first feedforward transconductance module 105 includes: a sixth transistor MP6 and a seventh transistor MP7;

[0248] The gate of the sixth transistor MP6 is electrically connected to the second voltage node V2;

[0249] The source of the sixth transistor MP6 and the drain of the first transistor MP1 are electrically connected to the second node N2;

[0250] A drain of the sixth transistor MP6 and a drain of the twenty-first transistor MN4 are electrically connected to a sixth node N6;

[0251] The gate of the seventh transistor MP7 is electrically connected to the first voltage node V1;

[0252] The source of the seventh transistor MP7 and the drain of the first transistor MP1 are electrically connected to the second node N2;

[0253] A drain of the seventh transistor MP7 and a drain of the twentieth transistor MN3 are electrically connected to a fifth node N5;

[0254] The sixth transistor MP6 is used to feed forward the second voltage input signal output from the second voltage node V2;

[0255] The seventh transistor MP7 is configured to feedforward the first voltage input signal output from the first voltage node V1 .

[0256] In this embodiment, please refer to Figure 2 The specific principle of the third transconductance module 103 in the operational amplifier circuit of the present invention is as follows:

[0257] The third transconductance module 103 includes: a twenty-second transistor MN5 and a twenty-third transistor MN6;

[0258] A gate of the 22nd transistor MN5 and a drain of the 20th transistor MN3 are electrically connected to a fifth node N5;

[0259] The source of the twenty-second transistor MN5 is grounded;

[0260] The drain of the twenty-second transistor MN5 is electrically connected to the third voltage node V3;

[0261] The drain of the 22nd transistor MN5 is electrically connected to the fourth transconductance module 104;

[0262] The drain of the twenty-second transistor MN5 is electrically connected to the second feedforward transconductance module 106;

[0263] The drain of the twenty-second transistor MN5 is electrically connected to the anti-pole splitting compensation module 108;

[0264] The drain of the twenty-second transistor MN5 is electrically connected to the common-mode feedback module 109;

[0265] A gate of the twenty-third transistor MN6 and a drain of the twenty-first transistor MN4 are electrically connected to a sixth node N6;

[0266] The source of the twenty-third transistor MN6 is grounded;

[0267] A drain of the twenty-third transistor MN6 is electrically connected to the fourth voltage node V4;

[0268] The drain of the twenty-third transistor MN6 is electrically connected to the fourth transconductance module 104;

[0269] The drain of the twenty-third transistor MN6 is electrically connected to the second feedforward transconductance module 106;

[0270] The drain of the twenty-third transistor MN6 is electrically connected to the anti-pole splitting compensation module 108;

[0271] The drain of the twenty-third transistor MN6 is electrically connected to the common-mode feedback module 109;

[0272] The twenty-second transistor MN5 serves as a first output terminal of the operational amplifier circuit, and is configured to output a first voltage output signal to the third voltage node V3;

[0273] The twenty-third transistor MN6 serves as the second output terminal of the operational amplifier circuit, and is configured to output a second voltage output signal to the fourth voltage node V4.

[0274] In this embodiment, please refer to Figure 2 The specific principle of the buffer module 107 in the operational amplifier circuit of the present invention is as follows:

[0275] The buffer module 107 includes: a tenth transistor MP10, an eleventh transistor MP11, a twelfth transistor MP12, a thirteenth transistor MP13, a twenty-fourth transistor MN7, and a twenty-fifth transistor MN8;

[0276] The gate of the tenth transistor MP10 and the gate of the first transistor MP1 are electrically connected to a first node N1;

[0277] The source of the tenth transistor MP10 is electrically connected to the power supply node VDD;

[0278] The drain of the tenth transistor MP10 is electrically connected to the fourth transconductance module 104;

[0279] The gate of the eleventh transistor MP11 and the gate of the first transistor MP1 are electrically connected to the first node N1;

[0280] The source of the eleventh transistor MP11 is electrically connected to the power supply node VDD;

[0281] The drain of the eleventh transistor MP11 is electrically connected to the fourth transconductance module 104;

[0282] The gate of the twelfth transistor MP12 is electrically connected to the fifth voltage node V5;

[0283] The gate of the twelfth transistor MP12 and the gate of the thirteenth transistor MP13 are electrically connected to a fifth voltage node V5;

[0284] A drain of the twelfth transistor MP12 and a drain of the twenty-first transistor MN4 are electrically connected to a sixth node N6;

[0285] The source of the twelfth transistor MP12 is electrically connected to the fourth transconductance module 104;

[0286] A drain of the thirteenth transistor MP13 and a drain of the twentieth transistor MN3 are electrically connected to a fifth node N5;

[0287] The source of the thirteenth transistor MP13 is electrically connected to the fourth transconductance module 104;

[0288] A gate of the twenty-fourth transistor MN7 is electrically connected to the sixth voltage node V6;

[0289] A gate of the twenty-fourth transistor MN7 and a gate of the twenty-fifth transistor MN8 are electrically connected to a sixth voltage node V6;

[0290] The drain of the twenty-fourth transistor MN7 is electrically connected to the fourth transconductance module 104;

[0291] A source of the 24th transistor MN7 and a drain of the 20th transistor MN3 are electrically connected to a fifth node N5;

[0292] The drain of the twenty-fifth transistor MN8 is electrically connected to the fourth transconductance module 104;

[0293] A source of the 25th transistor MN8 and a drain of the 21st transistor MN4 are electrically connected to a sixth node N6.

[0294] In this embodiment, please refer to Figure 2 The fourth transconductance module 104 in the operational amplifier circuit of the present invention has the following specific principles:

[0295] The fourth transconductance module 104 includes: a fourth transistor MP4 and a fifth transistor MP5;

[0296] The drain of the fourth transistor MP4 is electrically connected to the fourth voltage node V4;

[0297] A drain of the fourth transistor MP4 and a drain of the twenty-third transistor MN6 are electrically connected to a fourth voltage node V4;

[0298] The source of the fourth transistor MP4 is electrically connected to the power supply node VDD;

[0299] The gate of the fourth transistor MP4, the drain of the tenth transistor MP10, the source of the twelfth transistor MP12, and the drain of the twenty-fifth transistor MN8 are electrically connected to a tenth node N10;

[0300] The drain of the fifth transistor MP5 is electrically connected to the third voltage node V3;

[0301] The drain of the fifth transistor MP5 and the drain of the twenty-second transistor MN5 are electrically connected to the third voltage node V3;

[0302] The source of the fifth transistor MP5 is electrically connected to the power supply node VDD;

[0303] The gate of the fifth transistor MP5, the drain of the eleventh transistor MP11, the drain of the twenty-fourth transistor MN7, and the source of the thirteenth transistor MP13 are electrically connected to a ninth node N9;

[0304] The drain of the fourth transistor MP4 serves as the third output terminal of the operational amplifier circuit, and is used to output a third voltage output signal to a fourth voltage node V4;

[0305] The drain of the fifth transistor MP5 serves as the fourth output terminal of the operational amplifier circuit, and is configured to output a fourth voltage output signal to the third voltage node V3.

[0306] In this embodiment, please refer to Figure 2 The specific principle of the second feedforward transconductance module 106 in the operational amplifier circuit of the present invention is as follows:

[0307] The second feedforward transconductance module 106 includes: an eighth transistor MP8 and a ninth transistor MP9;

[0308] The gate of the eighth transistor MP8 is electrically connected to the second voltage node V2;

[0309] The drain of the eighth transistor MP8 and the drain of the twenty-second transistor MN5 are electrically connected to the third voltage node V3;

[0310] The source of the eighth transistor MP8 and the drain of the first transistor MP1 are electrically connected to the second node N2;

[0311] The gate of the ninth transistor MP9 is electrically connected to the first voltage node V1;

[0312] A drain of the ninth transistor MP9 and a drain of the twenty-third transistor MN6 are electrically connected to a fourth voltage node V4;

[0313] The source of the ninth transistor MP9 and the drain of the first transistor MP1 are electrically connected to the second node N2;

[0314] The eighth transistor is used to feed forward the second voltage input signal output by the second voltage node;

[0315] The ninth transistor is configured to feed forward the first voltage input signal output from the first voltage node.

[0316] In this embodiment, please refer to Figure 2 The common-mode feedback module 109 in the operational amplifier circuit of the present invention has the following specific principles:

[0317] The common-mode feedback module 109 includes: a fourteenth transistor MP14, a fifteenth transistor MP15, a sixteenth transistor MP16, a twenty-sixth transistor MN9, a twenty-seventh transistor MN10, a twenty-eighth transistor MN11, a twenty-ninth transistor MN12, a fifth resistor R5, a sixth resistor R6, a fifth capacitor C5, and a sixth capacitor C6;

[0318] The gate of the fourteenth transistor MP14 and the gate of the first transistor MP1 are electrically connected to the first node N1;

[0319] The source of the fourteenth transistor MP14 is electrically connected to the power supply node VDD;

[0320] The drain of the fourteenth transistor MP14, the source of the fifteenth transistor MP15, and the source of the sixteenth transistor MP16 are electrically connected to an eleventh node N11;

[0321] The gate of the fifteenth transistor MP15, the second end of the fifth resistor R5, the second end of the sixth resistor R6, the second end of the fifth capacitor C5, and the second end of the sixth capacitor C6 are electrically connected to a twelfth node N12;

[0322] The drain of the fifteenth transistor MP15, the gate of the twenty-sixth transistor MN9, the drain of the twenty-eighth transistor MN11, and the gate of the twenty-ninth transistor MN12 are electrically connected to a fourteenth node N14;

[0323] The gate of the sixteenth transistor MP16 is electrically connected to the seventh voltage node V7;

[0324] The drain of the sixteenth transistor MP16, the gate of the twenty-seventh transistor MN10, and the drain of the twenty-seventh transistor MN10 are electrically connected to the thirteenth node N13;

[0325] The source of the twenty-sixth transistor MN9 is grounded;

[0326] The source of the twenty-seventh transistor MN10 is grounded;

[0327] A drain of the 28th transistor MN11 and a drain of the 20th transistor MN3 are electrically connected to a fifth node N5;

[0328] The source of the twenty-eighth transistor MN11 is grounded;

[0329] A drain of the twenty-ninth transistor MN12 and a drain of the twenty-first transistor MN4 are electrically connected to a sixth node N6;

[0330] The source of the twenty-ninth transistor MN12 is grounded;

[0331] A first end of the fifth resistor R5 and a drain of the twenty-second transistor MN5 are electrically connected to a third voltage node V3;

[0332] A first end of the sixth resistor R6 and a drain of the twenty-third transistor MN6 are electrically connected to a fourth voltage node V4;

[0333] A first terminal of the fifth capacitor C5 and a drain of the twenty-second transistor MN5 are electrically connected to a third voltage node V3;

[0334] A first terminal of the sixth capacitor C6 and a drain of the twenty-third transistor MN6 are electrically connected to a fourth voltage node V4.

[0335] In this embodiment, please refer to Figure 2 The specific principle of the anti-pole splitting compensation module 108 in the operational amplifier circuit of the present invention is as follows:

[0336] The anti-pole splitting compensation module 108 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4;

[0337] A first end of the first resistor R1 and a drain of the twentieth transistor MN3 are electrically connected to a fifth node N5;

[0338] The second end of the first resistor R1 is electrically connected to the second end of the first capacitor C1;

[0339] The first end of the first capacitor C1 and the drain of the twenty-second transistor MN5 are electrically connected to a third voltage node V3;

[0340] A first end of the second resistor R2 and a drain of the twenty-first transistor MN4 are electrically connected to a sixth node N6;

[0341] The second end of the second resistor R2 is electrically connected to the second end of the second capacitor C2;

[0342] A first terminal of the second capacitor C2 and a drain of the twenty-third transistor MN6 are electrically connected to a fourth voltage node V4;

[0343] A first end of the third resistor R3 and a drain of the twenty-first transistor MN4 are electrically connected to a sixth node N6;

[0344] The second end of the third resistor R3 is electrically connected to the second end of the third capacitor C3;

[0345] A first terminal of the third capacitor C3 and a drain of the twenty-second transistor MN5 are electrically connected to a third voltage node V3;

[0346] A first end of the fourth resistor R4 and a drain of the twentieth transistor MN3 are electrically connected to a fifth node N5;

[0347] The second end of the fourth resistor R4 is electrically connected to the second end of the fourth capacitor C4;

[0348] A first terminal of the fourth capacitor C4 and a drain of the twenty-third transistor MN6 are electrically connected to a fourth voltage node V4.

[0349] In this embodiment, please refer to Figure 2 The specific principle of the bias module 110 in the operational amplifier circuit of the present invention is as follows:

[0350] The operational amplifier circuit further includes: a bias module 110;

[0351] The bias module includes: a seventeenth transistor MP17;

[0352] The gate of the seventeenth transistor MP17 is electrically connected to the gate of the first transistor MP1;

[0353] The drain of the seventeenth transistor MP17 is electrically connected to the gate of the first transistor MP1;

[0354] A source of the seventeenth transistor MP17 is electrically connected to the power node VDD.

[0355] In some implementations of this embodiment, please refer to Figure 2 , the following is a specific implementation of the operational amplifier circuit of the present invention:

[0356] On the one hand, the signal of the first voltage node V1 and the signal of the second voltage node V2 are preliminarily amplified to the fourth node N4 and the third node N3;

[0357] On the other hand, the signal of the first voltage node V1 and the signal of the second voltage node V2 are fed forward to the fifth node N5 and the sixth node N6;

[0358] The signal of the first voltage node V1 and the signal of the second voltage node V2 are further fed forward to the fourth voltage node V4 and the third voltage node V3;

[0359] The voltage signals of the fourth node N4 and the third node N3 are further amplified to the fifth node N5 and the sixth node N6;

[0360] On the one hand, the signals of the fifth node N5 and the sixth node N6 are amplified by the twenty-second transistor MN5 and the twenty-third transistor MN6 to the third voltage node V3 and the fourth voltage node V4;

[0361] On the other hand, the signals of the fifth node N5 and the sixth node N6 are buffered to the ninth node N9 and the tenth node N10, and then amplified to the third voltage node V3 and the fourth voltage node V4 through the fifth transistor MP5 and the fourth transistor MP4;

[0362] The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 form an anti-pole splitting, thereby improving the bandwidth of the operational amplifier;

[0363] The fifth resistor R5, the sixth resistor R6, the fifth capacitor C5, and the sixth capacitor C6 are used to detect the output DC levels of the third voltage node V3 and the fourth voltage node V4, and feed back the detection results to the third voltage node V3 and the fourth voltage node V4 in a negative feedback manner, so that the operational amplifier circuit can output a stable DC level;

[0364] The seventeenth transistor MP17 provides a DC voltage bias for the tenth transistor MP10 , the first transistor MP1 , the eleventh transistor MP11 , and the fourteenth transistor MP14 .

[0365] Please refer to Figure 3 , is a schematic diagram of a transfer function of an operational amplifier circuit provided in an embodiment of the present invention, wherein the transfer function of the operational amplifier circuit is:

[0366]

[0367] I1=-G m1 V INP ,

[0368] I4=-G m2 V ON1 ,

[0369] I5=-G m3 V OP2 ,

[0370] I7=-G m4 V OP3 ,

[0371] I2=G mf5 V INP ,

[0372] I3=G mf6 V INP ,

[0373] I6=(V 0N -V 0P2 )Y C ,

[0374] Y 01=1 / R 01 +sC 01 ,

[0375] Y 02 =1 / R 02 +sC 02 ,

[0376] Y 03 =1 / R 03 +sC 03 ,

[0377] Y C =sC C / (1+sR Z C C )-sC F / (1+sR F C F ),

[0378] Among them, I1, I2, I3, I4, I5, I6 and I7 are currents, C 01 、C 02 、C 03 、C C and C F is the value of the capacitor; V ON1 、V 0P2 and V OP3 is the voltage signal; V INP is the input voltage signal of the operational amplifier; V 0N is the output voltage signal of the operational amplifier; HF is the amplification factor of the operational amplifier circuit; R 01 、R 02 、R 03 、R Z and R F is the resistance value; G m1 , G m2 , G m3 , G m4 , G mf5 and G mf6 is the transconductance; Y 01 、Y 02 、Y 03 and Y C is the admittance; s is the weight.

[0379] In an alternative embodiment, see Figure 4 , which is a graph showing the gain and phase simulation results of an operational amplifier circuit provided by an embodiment of the present invention; Figure 5 , which is a graph showing the gain and phase simulation results of a common-mode feedback operational amplifier circuit provided by an embodiment of the present invention; Figure 6 , which is a diagram showing simulation results of the power supply rejection ratio of an operational amplifier circuit provided by an embodiment of the present invention; Figure 7 , is a diagram showing a simulation result of input noise amplified by an operational amplifier circuit provided by an embodiment of the present invention;

[0380] Among them, Figure 4 、 Figure 5 、 Figure 6 and Figure 7 As shown, the operational amplifier circuit described in this embodiment is implemented using SMIC55nm technology, uses 1.3V power supply, and consumes 550uA of current;

[0381] Gain for the amplification part = 70.5dB, GBW = 566.6MHz, BW = 1.1MHz, PM = 64.2°;

[0382] Common-mode feedback Gain = 44.6 dB, GBW = 54.5 MHz, PM = 123°;

[0383] When the frequency is 10Hz, the power supply rejection ratio of the operational amplifier is -156dB;

[0384] When the frequency is 10MHz, the input referred noise is 5.3nV / sqrt(Hz);

[0385] Where Gain stands for gain, GBW stands for gain-bandwidth product, BW stands for -3dB bandwidth, and PM stands for phase margin.

[0386] To summarize, the embodiment of the present invention performs preliminary amplification on the input signal through the first transconductance module, the second transconductance module and the first feedforward transconductance module to obtain the first signal, and on the other hand, amplifies the input signal through the second feedforward transconductance module to obtain the second signal; the third transconductance module, the fourth transconductance module and the cache module together form a push-pull structure, and amplifies the first signal again to obtain the third signal; two feedforward zero points are introduced into the circuit through the first feedforward transconductance module and the second feedforward transconductance module, thereby improving the gain, bandwidth and phase of the operational amplifier; the signal is amplified again through the push-pull structure, and the operational amplifier circuit is frequency compensated through the anti-pole splitting compensation module, thereby improving the bandwidth of the operational amplifier; finally, the output level of the operational amplifier circuit is detected through the common-mode feedback module, and by improving the bandwidth of the operational amplifier circuit of the present invention, the operational amplifier circuit of the present invention can have higher working performance in high-speed and low-power consumption scenarios.

[0387] The specific embodiments described above further illustrate the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. An operational amplifier circuit, characterized in that: include: a first transconductance module, a second transconductance module, a third transconductance module, a fourth transconductance module, a first feedforward transconductance module, a second feedforward transconductance module, a buffer module, an anti-pole splitting compensation module, and a common-mode feedback module; The input end of the first transconductance module is electrically connected to the input end of the first feedforward transconductance module; The output end of the first transconductance module is electrically connected to the input end of the second transconductance module; The output end of the second transconductance module is electrically connected to the output end of the first feedforward transconductance module; The output end of the buffer module is electrically connected to the input end of the fourth transconductance module; The output end of the fourth transconductance module is electrically connected to the output end of the third transconductance module; An input terminal of the second feedforward transconductance module is electrically connected to an input terminal of the first transconductance module; The output end of the second feedforward transconductance module is electrically connected to the output end of the third transconductance module; The input end of the third transconductance module is electrically connected to the output end of the second transconductance module; The input end of the buffer module is electrically connected to the output end of the second transconductance module; The input end of the anti-pole splitting compensation module is electrically connected to the output end of the second transconductance module; The output end of the anti-pole splitting compensation module is electrically connected to the output end of the third transconductance module; The input end of the common-mode feedback module is electrically connected to the output end of the third transconductance module; The output end of the common-mode feedback module is electrically connected to the output end of the second transconductance module; The first transconductance module is electrically connected to the buffer module; The first transconductance module is electrically connected to the common mode feedback module; The input end of the first transconductance module serves as the input end of the operational amplifier circuit; The output end of the third transconductance module serves as the output end of the operational amplifier circuit.

2. The operational amplifier circuit according to claim 1, wherein: The operational amplifier circuit further includes: a power supply node, a first voltage node, and a second voltage node; The first transconductance module includes: a first transistor, a second transistor, a third transistor, an eighteenth transistor and a nineteenth transistor; The source of the first transistor is electrically connected to the power supply node; The drain of the first transistor, the source of the second transistor and the source of the third transistor are electrically connected; The drain of the first transistor is electrically connected to the first feedforward transconductance module; The drain of the first transistor is electrically connected to the second feedforward transconductance module; The gate of the first transistor is electrically connected to the buffer module; The gate of the first transistor is electrically connected to the common-mode feedback module; The gate of the second transistor is electrically connected to the second voltage node; The drain of the second transistor, the drain of the eighteenth transistor and the gate of the eighteenth transistor are electrically connected; The drain of the second transistor is electrically connected to the second transconductance module; The gate of the third transistor is electrically connected to the first voltage node; The drain of the third transistor, the gate of the nineteenth transistor and the drain of the nineteenth transistor are electrically connected; The drain of the third transistor is electrically connected to the second transconductance module; The source of the eighteenth transistor is grounded; The source of the nineteenth transistor is grounded; The third transistor serves as a first input terminal of the operational amplifier circuit, and is configured to receive a first voltage input signal output from a first voltage node; The second transistor serves as a second input terminal of the operational amplifier circuit, and is configured to receive a second voltage input signal output from a second voltage node.

3. The operational amplifier circuit according to claim 2, wherein: The second transconductance module includes: a twentieth transistor and a twenty-first transistor; The gate of the twentieth transistor is electrically connected to the drain of the second transistor; The source of the twentieth transistor is grounded; The drain of the twentieth transistor is electrically connected to the third transconductance module; The drain of the twentieth transistor is electrically connected to the buffer module; The drain of the twentieth transistor is electrically connected to the first feedforward transconductance module; The drain of the twentieth transistor is electrically connected to the common-mode feedback module; The drain of the twentieth transistor is electrically connected to the anti-pole splitting compensation module; The source of the twenty-first transistor is grounded; a gate of the twenty-first transistor being electrically connected to a drain of the third transistor; The drain of the twenty-first transistor is electrically connected to the third transconductance module; The drain of the twenty-first transistor is electrically connected to the buffer module; The drain of the twenty-first transistor is electrically connected to the first feedforward transconductance module; The drain of the twenty-first transistor is electrically connected to the common-mode feedback module; A drain of the twenty-first transistor is electrically connected to the anti-pole splitting compensation module.

4. The operational amplifier circuit according to claim 3, wherein: The first feedforward transconductance module includes: a sixth transistor and a seventh transistor; The gate of the sixth transistor is electrically connected to the second voltage node; The source of the sixth transistor is electrically connected to the drain of the first transistor; a drain of the sixth transistor being electrically connected to a drain of the twenty-first transistor; The gate of the seventh transistor is electrically connected to the first voltage node; The source of the seventh transistor is electrically connected to the drain of the first transistor; a drain of the seventh transistor being electrically connected to a drain of the twentieth transistor; The sixth transistor is used to feed forward the second voltage input signal output by the second voltage node; The seventh transistor is configured to feed forward the first voltage input signal output from the first voltage node.

5. The operational amplifier circuit according to claim 4, wherein: The operational amplifier circuit further includes: a third voltage node and a fourth voltage node; The third transconductance module includes: a twenty-second transistor and a twenty-third transistor; The gate of the 22nd transistor is electrically connected to the drain of the 20th transistor; The source of the twenty-second transistor is grounded; The drain of the twenty-second transistor is electrically connected to the third voltage node; The drain of the twenty-second transistor is electrically connected to the fourth transconductance module; The drain of the twenty-second transistor is electrically connected to the second feedforward transconductance module; The drain of the twenty-second transistor is electrically connected to the anti-pole splitting compensation module; The drain of the twenty-second transistor is electrically connected to the common-mode feedback module; a gate of the twenty-third transistor being electrically connected to a drain of the twenty-first transistor; The source of the twenty-third transistor is grounded; a drain of the twenty-third transistor being electrically connected to the fourth voltage node; The drain of the twenty-third transistor is electrically connected to the fourth transconductance module; The drain of the twenty-third transistor is electrically connected to the second feedforward transconductance module; The drain of the twenty-third transistor is electrically connected to the anti-pole splitting compensation module; The drain of the twenty-third transistor is electrically connected to the common-mode feedback module; The twenty-second transistor serves as a first output terminal of the operational amplifier circuit, and is configured to output a first voltage output signal to a third voltage node; The twenty-third transistor serves as the second output terminal of the operational amplifier circuit, and is configured to output a second voltage output signal to a fourth voltage node.

6. The operational amplifier circuit according to claim 5, wherein: The operational amplifier circuit further includes: a fifth voltage node and a sixth voltage node; The buffer module includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a twenty-fourth transistor, and a twenty-fifth transistor; The gate of the tenth transistor is electrically connected to the gate of the first transistor; The source of the tenth transistor is electrically connected to the power supply node; The drain of the tenth transistor is electrically connected to the fourth transconductance module; The gate of the eleventh transistor is electrically connected to the gate of the first transistor; The source of the eleventh transistor is electrically connected to the power supply node; The drain of the eleventh transistor is electrically connected to the fourth transconductance module; The gate of the twelfth transistor is electrically connected to the fifth voltage node; The gate of the twelfth transistor is electrically connected to the gate of the thirteenth transistor; The drain of the twelfth transistor is electrically connected to the drain of the twenty-first transistor; The source of the twelfth transistor is electrically connected to the fourth transconductance module; a drain of the thirteenth transistor being electrically connected to a drain of the twentieth transistor; The source of the thirteenth transistor is electrically connected to the fourth transconductance module; The gate of the twenty-fourth transistor is electrically connected to the sixth voltage node; a gate of the twenty-fourth transistor is electrically connected to a gate of the twenty-fifth transistor; The drain of the twenty-fourth transistor is electrically connected to the fourth transconductance module; a source of the twenty-fourth transistor being electrically connected to a drain of the twentieth transistor; The drain of the twenty-fifth transistor is electrically connected to the fourth transconductance module; The source of the twenty-fifth transistor is electrically connected to the drain of the twenty-first transistor.

7. The operational amplifier circuit according to claim 6, wherein: The fourth transconductance module includes: a fourth transistor and a fifth transistor; The drain of the fourth transistor is electrically connected to the fourth voltage node; a drain of the fourth transistor being electrically connected to a drain of the twenty-third transistor; The source of the fourth transistor is electrically connected to the power supply node; The gate of the fourth transistor, the drain of the tenth transistor, the source of the twelfth transistor and the drain of the twenty-fifth transistor are electrically connected; The drain of the fifth transistor is electrically connected to the third voltage node; The drain of the fifth transistor is electrically connected to the drain of the twenty-second transistor; The source of the fifth transistor is electrically connected to the power supply node; The gate of the fifth transistor, the drain of the eleventh transistor, the drain of the twenty-fourth transistor, and the source of the thirteenth transistor are electrically connected; The drain of the fourth transistor serves as a third output terminal of the operational amplifier circuit, and is configured to output a third voltage output signal to a fourth voltage node; The drain of the fifth transistor serves as a fourth output terminal of the operational amplifier circuit, and is configured to output a fourth voltage output signal to the third voltage node.

8. The operational amplifier circuit according to claim 7, wherein: The second feedforward transconductance module includes: an eighth transistor and a ninth transistor; The gate of the eighth transistor is electrically connected to the second voltage node; The drain of the eighth transistor is electrically connected to the drain of the twenty-second transistor; The source of the eighth transistor is electrically connected to the drain of the first transistor; The gate of the ninth transistor is electrically connected to the first voltage node; The drain of the ninth transistor is electrically connected to the drain of the twenty-third transistor; The source of the ninth transistor is electrically connected to the drain of the first transistor; The eighth transistor is used to feed forward the second voltage input signal output by the second voltage node; The ninth transistor is configured to feed forward the first voltage input signal output from the first voltage node.

9. The operational amplifier circuit according to claim 8, wherein: The operational amplifier circuit further includes: a seventh voltage node; The common-mode feedback module includes: a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a fifth resistor, a sixth resistor, a fifth capacitor, and a sixth capacitor; The gate of the fourteenth transistor is electrically connected to the gate of the first transistor; The source of the fourteenth transistor is electrically connected to the power supply node; The drain of the fourteenth transistor, the source of the fifteenth transistor, and the source of the sixteenth transistor are electrically connected; The gate of the fifteenth transistor, the second end of the fifth resistor, the second end of the sixth resistor, the second end of the fifth capacitor, and the second end of the sixth capacitor are electrically connected; The drain of the fifteenth transistor, the gate of the twenty-sixth transistor, the drain of the twenty-sixth transistor, the gate of the twenty-eighth transistor, and the gate of the twenty-ninth transistor are electrically connected; The gate of the sixteenth transistor is electrically connected to the seventh voltage node; The drain of the sixteenth transistor, the gate of the twenty-seventh transistor, and the drain of the twenty-seventh transistor are electrically connected; The source of the twenty-sixth transistor is grounded; The source of the twenty-seventh transistor is grounded; a drain of the twenty-eighth transistor being electrically connected to a drain of the twentieth transistor; The source of the twenty-eighth transistor is grounded; a drain of the twenty-ninth transistor being electrically connected to a drain of the twenty-first transistor; The source of the twenty-ninth transistor is grounded; a first end of the fifth resistor is electrically connected to the drain of the twenty-second transistor; a first end of the sixth resistor is electrically connected to the drain of the twenty-third transistor; a first terminal of the fifth capacitor is electrically connected to the drain of the twenty-second transistor; A first end of the sixth capacitor is electrically connected to the drain of the twenty-third transistor.

10. The operational amplifier circuit according to claim 9, wherein: The anti-pole splitting compensation module includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; a first end of the first resistor is electrically connected to the drain of the twentieth transistor; The second end of the first resistor is electrically connected to the second end of the first capacitor; The first end of the first capacitor is electrically connected to the drain of the twenty-second transistor; a first end of the second resistor being electrically connected to the drain of the twenty-first transistor; The second end of the second resistor is electrically connected to the second end of the second capacitor; a first terminal of the second capacitor is electrically connected to the drain of the twenty-third transistor; a first end of the third resistor is electrically connected to the drain of the twenty-first transistor; The second end of the third resistor is electrically connected to the second end of the third capacitor; A first terminal of the third capacitor is electrically connected to the drain of the twenty-second transistor; a first end of the fourth resistor is electrically connected to the drain of the twentieth transistor; The second end of the fourth resistor is electrically connected to the second end of the fourth capacitor; the first end of the fourth capacitor is electrically connected to the drain of the twenty-third transistor.

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