A method, device, storage medium and equipment for automating synchronization timing calibration

Abstract

The present application discloses an automated synchronization timing calibration method, device, storage medium and equipment, which obtain synchronization window information and obtain the best sampling position of each analog-to-digital converter based on the synchronization window information; combine the best sampling positions in different synchronization window information to obtain multiple synchronization window combinations; send each synchronization window combination to the register of each analog-to-digital converter in turn, and obtain the corresponding phase error value of each analog-to-digital converter; determine the best synchronization window combination according to the candidate synchronization window combination in the synchronization window combination corresponding to the phase error value less than the first preset value; use the best synchronization window combination to determine the synchronization timing of each analog-to-digital converter after calibration, construct the synchronization window combination through the best sampling position, test the synchronization window combinations one by one, screen out the best synchronization window combination, and set the synchronization signal step value under the best synchronization window combination, so as to solve the problem of unsatisfactory sampling output results between different analog-to-digital converters due to chip design reasons.

Description

Technical Field

[0001] The present application relates to the field of high-speed acquisition circuits, and in particular to an automated synchronous timing calibration method, device, storage medium and equipment. Background Art

[0002] In multi-channel acquisition scenarios, such as radar, communications, electronic countermeasures and other fields, multi-chip or module synchronization is involved. The synchronization performance directly determines the system's mission performance. If the synchronization fails, it may cause communication failure, inaccurate radar detection or degradation of countermeasure performance, which will cause great harm to the equipment application. Solving the synchronization stability problem is of great significance.

[0003] At present, when multiple chips or modules work synchronously, the timing synchronization is completely guaranteed by the hardware circuit design and the chip itself. The differences in device processes will lead to timing differences, and the stability of timing synchronization can only be guaranteed within a small temperature range, and the timing synchronization requirements within a wide temperature range cannot be met. For example, there will be timing differences between multiple hardware modules, or the same module in an environment with a large temperature difference, which will eventually lead to system synchronization failure. Summary of the invention

[0004] The main purpose of this application is to provide an automated synchronization timing calibration method, device, storage medium and equipment, aiming to solve the technical problem that when multiple chips or modules work synchronously, the timing synchronization is completely guaranteed by the hardware circuit design and the chip itself, and the device process differences will lead to timing differences.

[0005] To achieve the above-mentioned purpose, the present application provides an automated synchronization timing calibration method, comprising: obtaining synchronization window information of each analog-to-digital converter of a signal acquisition device, and obtaining the best sampling position of each analog-to-digital converter based on the synchronization window information, the best sampling position being the middle position of a string of non-metastable sampling positions in the synchronization window information; combining the best sampling positions in different synchronization window information to obtain multiple synchronization window combinations, the synchronization window combinations being used to characterize different step value combinations of synchronization signal delays of each analog-to-digital converter; sending each synchronization window combination to the register of each analog-to-digital converter in turn, and obtaining the corresponding phase error value of each analog-to-digital converter; determining the best synchronization window combination according to the candidate synchronization window combination in the synchronization window combination corresponding to the phase error value less than a first preset value; and determining the synchronization timing of each analog-to-digital converter after calibration using the best synchronization window combination.

[0006] Optionally, the signal acquisition device has multiple acquisition boards, each of which has at least two analog-to-digital converters. Before acquiring synchronization window information of each analog-to-digital converter of the signal acquisition device, the timing calibration method further includes: calibrating each analog-to-digital converter on each acquisition board.

[0007] Optionally, after determining the best synchronization window combination according to the synchronization window combination corresponding to the phase error value less than the first preset value, the timing calibration method further includes: saving the best synchronization window combination.

[0008] Optionally, after saving the optimal synchronization window combination, the timing calibration method further comprises: shutting down a synchronization signal receiving circuit of each of the analog-to-digital converters.

[0009] Optionally, the signal acquisition device has multiple acquisition boards, each of which has at least two analog-to-digital converters. The synchronization window combinations are sent to the registers of each analog-to-digital converter in turn to obtain the corresponding phase error value of each analog-to-digital converter, including: obtaining the ADC time domain waveform data corresponding to the output of each analog-to-digital converter on each of the acquisition boards according to the synchronization window combination; and determining the phase error value of each analog-to-digital converter using the ADC time domain waveform data.

[0010] Optionally, before determining the best synchronization window combination according to the candidate synchronization window combination among the synchronization window combinations corresponding to the phase error value less than the first preset value, the timing calibration method also includes: obtaining the phase error value between each acquisition board according to each synchronization window combination sent to the register of each analog-to-digital converter in sequence; if the phase error value is less than the second preset value, determining the synchronization window combination corresponding to the phase error value as the candidate synchronization window combination.

[0011] Optionally, after saving the optimal synchronization window combination, the timing calibration method also includes: obtaining the real-time synchronization window combination of each analog-to-digital converter under the current ambient temperature; determining whether the current synchronization window combination is the same as the saved optimal synchronization window combination; if they are the same, continuing to use the optimal synchronization window combination to determine the synchronization timing of each analog-to-digital converter; if they are not the same, determining a new optimal synchronization window combination based on the real-time synchronization window combination; and using the new optimal synchronization window combination to determine the calibrated synchronization timing of each analog-to-digital converter.

[0012] To achieve the above-mentioned purpose, the embodiment not applied for also provides an automated synchronization timing calibration device, including: a sampling position acquisition module, used to obtain the synchronization window information of each analog-to-digital converter of the signal acquisition device, and obtain the best sampling position of each analog-to-digital converter based on the synchronization window information, the best sampling position is the middle position of a string of non-metastable sampling positions in the synchronization window information; a window combination module, used to combine the best sampling positions in different synchronization window information to obtain multiple synchronization window combinations, the synchronization window combinations are used to characterize different step value combinations of synchronization signal delays of each analog-to-digital converter; an error determination module, used to send each synchronization window combination to the register of each analog-to-digital converter in turn, and obtain the phase error value of each analog-to-digital converter accordingly; a window combination determination module, used to determine the best synchronization window combination according to the candidate synchronization window combination in the synchronization window combination corresponding to the phase error value less than the first preset value; a timing determination module, used to use the best synchronization window combination to determine the synchronization timing of each analog-to-digital converter after calibration.

[0013] To achieve the above objectives, an embodiment of the present application further provides a computer-readable storage medium, which includes instructions. When the instructions are executed on a computer, the computer executes an automated synchronization timing calibration method.

[0014] To achieve the above-mentioned purpose, an embodiment of the present application also provides a timing calibration device, characterized in that the timing calibration device includes: at least one processor, a memory and an input and output unit; wherein the memory is used to store a computer program, and the processor is used to call the computer program stored in the memory to execute an automated synchronous timing calibration method.

[0015] An automated synchronization timing calibration method, apparatus, storage medium and device proposed in an embodiment of the present application obtain synchronization window information of each analog-to-digital converter of a signal acquisition device, and obtain the optimal sampling position of each analog-to-digital converter based on the synchronization window information, wherein the optimal sampling position is the middle position of a string of non-metastable sampling positions in the synchronization window information; the optimal sampling positions in different synchronization window information are combined to obtain multiple synchronization window combinations, and the synchronization window combinations are used to characterize different step value combinations of synchronization signal delays of each analog-to-digital converter; each synchronization window combination is sent to the register of each analog-to-digital converter in turn, and the phase error value of each analog-to-digital converter is obtained accordingly; the optimal synchronization window combination is determined according to the candidate synchronization window combination in the synchronization window combination corresponding to the phase error value less than a first preset value; the synchronization timing after calibration of each analog-to-digital converter is determined using the optimal synchronization window combination, the synchronization window combination is constructed by obtaining the optimal sampling position in the synchronization window information, the synchronization window combinations are tested one by one, and the optimal synchronization window combination less than the first preset is screened out, and the synchronization signal step value set under the optimal synchronization window combination can ensure that each digital-to-analog converter meets the requirements of interleaved sampling, and solves the problem of unsatisfactory sampling output results due to chip design reasons and temperature changes between different analog-to-digital converters. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a sampling clock and synchronization signal timing diagram flow chart provided in an embodiment of the present application;

[0017] Figure 2 A schematic diagram of synchronization failure caused by phase drift provided in an embodiment of the present application;

[0018] Figure 3 A flow chart of an automated synchronization timing calibration method provided in an embodiment of the present application;

[0019] Figure 4 A schematic diagram of the functional modules of an automated synchronous timing calibration device provided in one embodiment of the present application;

[0020] Figure 5 A schematic diagram of a storage medium structure provided in an embodiment of the present application;

[0021] Figure 6 A schematic diagram of the structure of a timing calibration device provided in one embodiment of the present application.

[0022] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0023] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0024] In the prior art, a high-speed oscilloscope is a typical large-bandwidth signal acquisition and receiving device. The acquisition signal bandwidth is large, and a single acquisition chip or module is not enough to acquire the large-bandwidth signal. Multiple signal acquisition modules are needed to increase the sampling rate and analog signal bandwidth to achieve the acquisition of large-bandwidth signals. When using multiple signal acquisition modules for signal acquisition, it is necessary to ensure the synchronization of the sampling clocks and data of multiple modules. At present, the synchronization of multiple modules requires the use of synchronization signals. The timing of the sampling clock and the synchronization signal is as follows: Figure 1 As shown in the figure, the sampling clock period is T, the minimum setup time is ts, and the minimum hold time is th. If the setup time and hold time are between ts and th, there is a sampling metastable state. Sufficient setup time and hold time must be ensured to ensure synchronization stability. Therefore, the phase relationship between the clock signal and the synchronization signal is particularly important. If the phase cannot be guaranteed to meet the setup time and hold time, synchronization failure will occur, resulting in a decrease in device performance.

[0025] In scenarios where the sampling clock frequency is higher, T is smaller, and the stable interval tok that satisfies the establishment and hold time is smaller, making it more difficult to design the relative timing of the sampling clock and the synchronization signal. Especially for devices working in wide temperature scenarios, the timing is easily affected by temperature, resulting in failure to guarantee synchronization over the full temperature range. Figure 2 As shown in the figure, assuming that the sampled clock is used as a reference, the position of the rising edge of the synchronization signal relative to the sampling clock changes with temperature. When the rising edge of the synchronization signal is close to the rising edge of the sampling clock, the setup and hold time requirements cannot be met, and there is a metastable problem. For different acquisition modules, a time difference of a sampling clock T may occur, such as Figure 2 The timing of the "synchronization signal 1 sampling identification" and "synchronization signal 2 sampling identification" signals is affected, resulting in system synchronization failure.

[0026] In order to solve the above technical problems, the present application provides an automated synchronization timing calibration method, which can be executed by timing calibration software. Figure 3 A flowchart of an automated synchronization timing calibration method provided by an embodiment of the present application is shown in FIG. Figure 3 As shown, the timing calibration method may include:

[0027] S10, obtaining synchronization window information of each analog-to-digital converter of the signal acquisition device, and obtaining the best sampling position of each analog-to-digital converter based on the synchronization window information, wherein the best sampling position is the middle position of a string of non-metastable sampling positions in the synchronization window information;

[0028] The synchronization window information is obtained by the timing synchronization software. Each synchronization window in the synchronization window information is represented by a 24-bit binary symbol string, and each bit in these symbol strings corresponds to a sampling position. In the 24-bit binary symbol string, the number 1 represents the metastable position, while the number 0 represents the non-metastable position. In order to achieve the best synchronization, the timing calibration software usually looks for the middle position of a string of continuous 0s, because such a position is less likely to be affected by the metastable state, thus providing a more stable sampling point.

[0029] For example, when the signal acquisition module has only two acquisition boards and each acquisition board has two analog-to-digital converters, Table 1 shows the synchronization window information of each analog-to-digital converter acquired by the timing calibration software. Referring to Table 1, Acq Board0 and Acq Board1 represent two different acquisition boards, and ADC1 to ADC4 represent four analog-to-digital converters.

[0030] Table 1

[0031] Acquisition module number ADC Number Synchronize window information Acq Board0 ADC1 1000_0000_1100_0000_1100_0001 Acq Board0 ADC2 1000_0110_0000_0110_0000_0011 Acq Board1 ADC1 1000_0110_0000_0011_0000_0001 Acq Board1 ADC2 1011_0000_0001_1000_0000_1101

[0032] From the synchronization window information in Table 1, we can see that each synchronization window information is a string of binary symbols, with a total of 24 bits from low to high, representing 24 sampling positions. The timing calibration software automatically analyzes and identifies the position of 0, and calculates the best position of the non-metastable state, that is, the middle position of a string of 0s, as the target for adjusting the synchronization signal delay.

[0033] For example, for ADC1: 1000_0000_1100_0000_1100_0001, its optimal sampling position is 3 or 10. For ADC2: 1011_0000_0001_1000_0000_1101, its optimal sampling position is 7 or 15. The optimal sampling position can be expressed as: ADC1_POS0=3, ADC1_POS1=10, ADC2_POS0=7, ADC2_POS1=15, wherein the optimal sampling positions 3, 10, 7, 15 also represent the step value of the synchronization signal delay adjustment.

[0034] However, for the TI interleaved sampling of the signal acquisition device, the timing synchronization must also meet the requirements for the selection of the synchronization signal window position between the ADC chips. Exemplarily, in an embodiment of the present invention, the timing calibration software obtains at least two available optimal sampling positions. If these two different sampling positions are not within one clock cycle, it does not meet the requirements. Assuming that the sampling clock is 5GHz, then the corresponding clock cycle is 200ps. When a 1GHz sinusoidal signal is input, the phase error is converted to 72° according to the formula (Degree=time×freq×360°), and the 72° phase difference is unacceptable. Therefore, for the ADC on an acquisition board, the timing calibration software needs to select two suitable optimal sampling positions as the synchronization window combination.

[0035] S20, combining the best sampling positions in different synchronization window information to obtain a plurality of synchronization window combinations, where the synchronization window combinations are used to characterize different step value combinations of synchronization signal delays of each analog-to-digital converter;

[0036] Specifically, in the case where each ADC has two optimal sampling positions, the timing calibration software can combine the four optimal sampling positions of the two ADCs to obtain the following combination results, each of which represents a synchronization window combination:

[0037] 1.[ADC1_POS0, ADC2_POS0];

[0038] 2. [ADC1_POS0, ADC2_POS1];

[0039] 3.[ADC1_POS1, ADC2_POS0];

[0040] 4.[ADC1_POS1, ADC2_POS1].

[0041] S30, sending each synchronization window combination to the register of each analog-to-digital converter in turn, and correspondingly obtaining a phase error value of each analog-to-digital converter;

[0042] Specifically, the timing calibration software first sends the first synchronization window combination to the register of the ADC, and the register of the ADC generates the step value of the synchronization signal according to the synchronization window combination. The acquisition signal acquires the input analog signal according to the step value and outputs the digital signal. The timing calibration software analyzes the output digital signal to obtain the phase error value of ADC1 and ADC2.

[0043] In the embodiment of the present application, step S30 may specifically include the following process:

[0044] S31, according to the ADC time domain waveform data corresponding to the synchronous window combination output, the phase of each analog-to-digital converter on each acquisition board is obtained; wherein the ADC time domain waveform data is the phase value obtained by processing the time domain waveform of each analog-to-digital converter using a three-parameter fitting algorithm;

[0045] S32, using the time domain waveform data of each ADC to determine the phase error value of each analog-to-digital converter.

[0046] Specifically, the timing calibration software can first collect the time domain waveforms of each analog-to-digital converter on the acquisition board, and then the timing calibration software can use a three-parameter fitting algorithm to fit the phase value of each time domain waveform. The timing calibration software calculates the phase error value based on the obtained phase values ​​of each analog-to-digital converter. The timing calibration software uses one analog-to-digital converter as a reference analog-to-digital converter, and subtracts the phase values ​​of other analog-to-digital converters from the reference analog-to-digital converter to obtain the phase error value between the analog-to-digital converters on the acquisition board.

[0047] S40, determining the best synchronization window combination according to candidate synchronization window combinations among the synchronization window combinations corresponding to the phase error value less than the first preset value;

[0048] Among them, under the condition that the sampling clock is 5GHz and the corresponding clock cycle is 200ps, if the two ADCs cross the clock cycle, the phase difference is close to 200ps, so 200ps is set as the first preset value. If the two ADCs are greater than the first preset value, it is considered that the first synchronization window combination is not the best synchronization window combination, and the timing calibration software continues to try the next group of synchronization window combinations until the synchronization window combination corresponding to the phase error value less than the first preset value is screened out, thereby obtaining the best synchronization window combination.

[0049] S50, using the best synchronization window combination to determine the synchronization timing of each analog-to-digital converter after calibration.

[0050] In an embodiment of the present application, the signal acquisition device has a plurality of acquisition boards, each of which has at least two analog-to-digital converters. Before step S10, the automatic synchronization timing calibration method further includes the following specific implementation steps:

[0051] S60, calibrating each analog-to-digital converter on each acquisition board.

[0052] Specifically, S60 may include the following specific implementation steps:

[0053] S61, calibrating each analog-to-digital converter on each acquisition board, including:

[0054] S62, respectively obtaining a time domain waveform diagram of each analog-to-digital converter;

[0055] S63, estimating the phase, offset, and gain of each of the time domain waveforms using a three-parameter simulation algorithm;

[0056] S64, adjusting the control word of the DC offset error control register, the control word of the gain error control register, and the control word of the phase error control register of each analog-to-digital converter until the phase error, the offset error, and the gain error are all smaller than a preset threshold, thereby obtaining each calibrated analog-to-digital converter.

[0057] In an embodiment of the present application, before step S10, the automated synchronization timing calibration method may further include the following specific implementation steps:

[0058] S70, save the best synchronization window combination. Specifically, according to the best synchronization window combination determined above, the timing calibration software can determine the initial calibration parameter information, and write the initial calibration parameter information into the initial calibration file for storage. The main fields of the initial calibration parameter information include: acquisition module identifier (acqboard), ADC identifier (adc), and synchronization window position (sysrefsel).

[0059] The initial calibration parameter information can be an XML file, keeping the following format:

[0060] <? xml version='1.0'encoding='utf-8'? >

[0061] <sysref>

[0062] <Item acqboard="0"adc="0"sysrefsel="3" / >

[0063] <Item acqboard="0"adc="1"sysrefsel="6" / >

[0064] <Item acqboard="1"adc="0"sysrefsel="3" / >

[0065] <Item acqboard="1"adc="1"sysrefsel="7" / >

[0066] < / sysref>

[0067] In an embodiment of the present application, after step S70, the automatic synchronization timing calibration method may further include the following specific implementation steps:

[0068] S81, obtaining a real-time synchronization window combination of each analog-to-digital converter at the current ambient temperature;

[0069] S82, determining whether the current synchronization window combination is the same as the saved optimal synchronization window combination;

[0070] S83, if they are the same, continue to use the best synchronization window combination to determine the synchronization timing of each analog-to-digital converter;

[0071] S84, if they are not the same, determining a new optimal synchronization window combination according to the real-time synchronization window combination;

[0072] S85. Determine the calibrated synchronization timing of each analog-to-digital converter using the new optimal synchronization window combination.

[0073] Specifically, after saving the initial calibration file, the timing calibration software reads and parses the initial calibration file from time to time, and sends the synchronization window sampling position to the register of each analog-to-digital converter. If the timing calibration software determines that the state of each analog-to-digital converter at this time is consistent with the state during calibration, no operation needs to be performed. However, if the external temperature changes, the synchronization window position changes due to the temperature, which can easily lead to problems with inter-chip synchronization or inter-board synchronization. As shown in Table 2, the synchronization window will drift under different temperature conditions, causing the synchronization signal and sampling clock setup / hold time to be in an unstable range, resulting in metastable problems. The following is the synchronization window data collected by the timing calibration software at different temperatures:

[0074] Table 2

[0075]

[0076]

[0077] It can be seen from the synchronization comparison that the synchronization window drifts to a lower position with the temperature change. If the synchronization signal receiving circuit is started at this time and the best sampling position used in the previous calibration is continued to be used, a metastable state will inevitably occur. For example, the data of B1.Adc1=>1100_0000_1100_0000_0110_0001 collected at a temperature of 52.166633°C, the calculated best sampling position value is 2, and if B1.Adc1=>1000_1100_0000_1100_0000_0111 collected at a temperature of 65.141651°C continues to use the best sampling position 2, a metastable state problem will inevitably occur. The embodiment of the present application can achieve timing calibration using the timing calibration software when the temperature changes by executing steps S81 to S85.

[0078] In addition, based on the above embodiments, the embodiments of the present application also provide an automated synchronization timing calibration device to solve the technical problem that when multiple chips or modules work synchronously, the timing synchronization is completely guaranteed by the hardware circuit design and the chip itself, and the device process differences will lead to timing differences. Figure 4 The automatic synchronization timing calibration device provided by an embodiment of the present application is referred to as Figure 4The timing calibration device 100 may include: a sampling position acquisition module 101, a window combination module 102, an error determination module 103, a window combination determination module 104 and a timing determination module 105, wherein the sampling position acquisition module 101 can be used to obtain the synchronization window information of each analog-to-digital converter of the signal acquisition device, and obtain the best sampling position of each analog-to-digital converter based on the synchronization window information, and the best sampling position is the middle position of a string of non-metastable sampling positions in the synchronization window information; the window combination module 102 can be used to combine the best sampling positions in different synchronization window information to obtain multiple synchronization window combinations, and the synchronization window combinations are used to characterize different step value combinations of synchronization signal delays of each analog-to-digital converter; the error determination module 103 can be used to send each synchronization window combination to the register of each analog-to-digital converter in turn, and obtain the phase error value of each analog-to-digital converter accordingly; the window combination determination module 104 can be used to determine the best synchronization window combination according to the candidate synchronization window combination in the synchronization window combination corresponding to the phase error value less than the first preset value; the timing determination module 105 can be used to determine the synchronization timing of each analog-to-digital converter after calibration using the best synchronization window combination.

[0079] In an embodiment of the present application, the timing calibration device 100 may further include a calibration module 106 , and the calibration module 106 may be used to calibrate each analog-to-digital converter on each acquisition board.

[0080] In the embodiment of the present application, the timing calibration device 100 may further include a storage module 107, which may be used to store the best synchronization window combination.

[0081] In an embodiment of the present application, the timing calibration device 100 may further include a circuit closing module 108 , and the circuit closing module 108 may be used to close the synchronization signal receiving circuit of each analog-to-digital converter.

[0082] In an embodiment of the present application, the error determination module 103 can also be used to obtain the phase error value between each acquisition board according to each synchronization window combination sent to the register of each analog-to-digital converter in sequence; if the phase error value is less than the second preset value, the synchronization window combination corresponding to the phase error value is determined as a candidate synchronization window combination.

[0083] In an embodiment of the present application, the timing calibration device 100 may further include a real-time calibration module 108, which may be used to obtain a real-time synchronization window combination of each analog-to-digital converter under the current ambient temperature; determine whether the current synchronization window combination is the same as the saved optimal synchronization window combination; if they are the same, continue to use the optimal synchronization window combination to determine the synchronization timing of each analog-to-digital converter; if they are not the same, determine a new optimal synchronization window combination based on the real-time synchronization window combination; and use the new optimal synchronization window combination to determine the calibrated synchronization timing of each analog-to-digital converter.

[0084] In addition, based on the above embodiments, the present application also provides a computer-readable storage medium, referring to Figure 5 , the computer-readable storage medium shown is a CD 50, on which a computer algorithm (i.e., an algorithm product) is stored. When the computer algorithm is executed by the processor, the steps described in the method implementation are implemented, for example, the synchronization window information of each analog-to-digital converter of the signal acquisition device is obtained, and the optimal sampling position of each analog-to-digital converter is obtained based on the synchronization window information, and the optimal sampling position is the middle position of a string of non-metastable sampling positions in the synchronization window information; the optimal sampling positions in different synchronization window information are combined to obtain multiple synchronization window combinations, and the synchronization window combinations are used to characterize different step value combinations of synchronization signal delays of each analog-to-digital converter; each synchronization window combination is sent to the register of each analog-to-digital converter in turn, and the phase error value of each analog-to-digital converter is obtained accordingly; the optimal synchronization window combination is determined according to the candidate synchronization window combination in the synchronization window combination corresponding to the phase error value less than the first preset value; the synchronization timing of each analog-to-digital converter after calibration is determined using the optimal synchronization window combination, and the specific implementation method of each step is not repeated here. It should be noted that examples of computer-readable storage media may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0085] In addition, based on the above embodiments, the present application also provides a device, Figure 6 A block diagram of an exemplary device 60 suitable for implementing the embodiments of the present application is shown, and the device 60 may be a computer system or a server. Figure 6 The device 60 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0086] refer to Figure 6 , the components of the device 60 may include, but are not limited to: one or more processors or processing units 601, a system memory 602, and a bus 603 connecting different system components (including the system memory 602 and the processing unit 601).

[0087] Device 60 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by device 60, including volatile and non-volatile media, removable and non-removable media.

[0088] The system memory 602 may include computer system readable media in the form of volatile memory, such as random access memory RAM 6021 and / or cache memory 6022. The device 60 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the ROM 6023 may be used to read and write non-removable, non-volatile magnetic media ( Figure 6 is not shown in the Figure 6 As shown in the figure, a disk drive for reading and writing a removable non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading and writing a removable non-volatile optical disk (e.g., a CD-ROM, a DVD-ROM, or other optical media) can be provided. In these cases, each drive can be connected to a bus 603 connecting different system components through one or more data medium interfaces. The system memory 602 may include at least one algorithm product, which has a set (e.g., at least one) algorithm module, which is configured to perform the functions of each embodiment of the present application.

[0089] An algorithm / utility 6025 having a set (at least one) of algorithm modules 6024 may be stored, for example, in system memory 602, and such algorithm modules 6024 include, but are not limited to, an operating system, one or more application algorithms, other algorithm modules, and algorithm data, each of which or some combination may include an implementation of a network environment. Algorithm modules 6024 generally perform the functions and / or methods of the embodiments described herein.

[0090] The device 60 may also communicate with one or more external devices 604 (e.g., a keyboard, a pointing device, a display, etc.). Such communication may be performed via an input / output I / O interface 605. Furthermore, the device 60 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 606. Figure 6 As shown, the network adapter 606 communicates with other modules of the device 60 (such as the processing unit 601, etc.) via the bus 603 that connects the different system components. Figure 6 Not shown, other hardware and / or software program modules may be used in conjunction with device 60 .

[0091] The processing unit 601 executes various functional applications and data processing by running the algorithm stored in the system memory 602, for example, obtaining the synchronization window information of each analog-to-digital converter of the signal acquisition device, and obtaining the best sampling position of each analog-to-digital converter based on the synchronization window information, the best sampling position being the middle position of a string of non-metastable sampling positions in the synchronization window information; combining the best sampling positions in different synchronization window information to obtain multiple synchronization window combinations, the synchronization window combinations are used to characterize different step value combinations of synchronization signal delays of each analog-to-digital converter; sending each synchronization window combination to the register of each analog-to-digital converter in turn, and correspondingly obtaining the phase error value of each analog-to-digital converter; determining the best synchronization window combination according to the candidate synchronization window combination in the synchronization window combination corresponding to the phase error value less than the first preset value; determining the synchronization timing of each analog-to-digital converter after calibration using the best synchronization window combination, and the specific implementation method of each step will not be repeated here. It should be noted that although several units / modules or sub-units / sub-modules of the robot's motion trajectory processing device are mentioned in the above detailed description, this division is only exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules to be embodied.

[0092] In the description of the present application, it should be noted that the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0093] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0094] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0095] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0096] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0097] If the function is implemented in the form of a software program functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software program product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., various media that can store algorithm codes.

[0098] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

[0099] In addition, although the operations of the method of the present application are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

Claims

1. An automated synchronization timing calibration method, characterized in that: include: Acquire synchronization window information of each analog-to-digital converter of the signal acquisition device, and obtain the best sampling position of each analog-to-digital converter based on the synchronization window information, wherein the best sampling position is the middle position of a series of non-metastable sampling positions in the synchronization window information; Combining the best sampling positions in different synchronization window information to obtain a plurality of synchronization window combinations, wherein the synchronization window combinations are used to characterize different step value combinations of synchronization signal delays of each analog-to-digital converter; Sending each synchronization window combination to the register of each analog-to-digital converter in turn, and obtaining the phase error value of each analog-to-digital converter accordingly; Determine the best synchronization window combination according to the candidate synchronization window combinations among the synchronization window combinations corresponding to the phase error value less than the first preset value; The optimal synchronization window combination is used to determine the synchronization timing of each of the analog-to-digital converters after calibration.

2. The automatic synchronization timing calibration method according to claim 1, characterized in that: The signal acquisition device has a plurality of acquisition boards, each of which has at least two analog-to-digital converters; Before acquiring synchronization window information of each analog-to-digital converter of the signal acquisition device, the timing calibration method further includes: Calibrate each analog-to-digital converter on each acquisition board.

3. The automatic synchronization timing calibration method according to claim 2, characterized in that: Calibrate each analog-to-digital converter on each acquisition board, including: Respectively obtain the time domain waveform diagram of each analog-to-digital converter; Using a three-parameter simulation algorithm to estimate the phase, offset, and gain of each of the time domain waveforms; The control word of the DC offset error control register, the control word of the gain error control register, and the control word of the phase error control register of each analog-to-digital converter are adjusted until the phase error, the offset error, and the gain error are all less than a preset threshold value, thereby obtaining each calibrated analog-to-digital converter.

4. The automatic synchronization timing calibration method according to claim 1, wherein: After determining the best synchronization window combination according to the synchronization window combination corresponding to the phase error value less than the first preset value, the timing calibration method further includes: Save the best synchronization window combination; The synchronization signal receiving circuit of each analog-to-digital converter is turned off.

5. The automatic synchronization timing calibration method according to claim 1, wherein: The signal acquisition device has a plurality of acquisition boards, each of which has at least two analog-to-digital converters. The synchronous window combinations are sent to the registers of the analog-to-digital converters in sequence to obtain the phase error values ​​of the analog-to-digital converters, including: According to the ADC time domain waveform data corresponding to the synchronous window combination output, the phase of each analog-to-digital converter on each acquisition board is obtained; wherein the ADC time domain waveform data is the phase value obtained by processing the time domain waveform of each analog-to-digital converter using a three-parameter fitting algorithm; The phase error value of each analog-to-digital converter is determined by using the time domain waveform data of each ADC.

6. The automatic synchronization timing calibration method according to claim 1, characterized in that: Before determining the best synchronization window combination according to the candidate synchronization window combination among the synchronization window combinations corresponding to the phase error value less than the first preset value, the timing calibration method further includes: According to each synchronization window combination sent to the register of each analog-to-digital converter in sequence, the phase error value between each acquisition board is obtained; If the phase error value is less than a second preset value, the synchronization window combination corresponding to the phase error value is determined as a candidate synchronization window combination.

7. The automatic synchronization timing calibration method according to claim 4, characterized in that: After saving the best synchronization window combination, the timing calibration method further includes: Obtain the real-time synchronization window combination of each analog-to-digital converter under the current ambient temperature; Determine whether the current synchronization window combination is the same as the saved best synchronization window combination; If they are the same, continue to use the best synchronization window combination to determine the synchronization timing of each analog-to-digital converter; If they are not the same, a new optimal synchronization window combination is determined according to the real-time synchronization window combination; The calibrated synchronization timing of each analog-to-digital converter is determined using the new optimal synchronization window combination.

8. An automated synchronous timing calibration device, characterized in that: include: A sampling position acquisition module, used to acquire synchronization window information of each analog-to-digital converter of the signal acquisition device, and obtain the best sampling position of each analog-to-digital converter based on the synchronization window information, wherein the best sampling position is the middle position of a series of non-metastable sampling positions in the synchronization window information; A window combination module, used for combining the best sampling positions in the different synchronization window information to obtain a plurality of synchronization window combinations, wherein the synchronization window combinations are used for characterizing different step value combinations of synchronization signal delays of each analog-to-digital converter; The error determination module is used to send each synchronization window combination to the register of each analog-to-digital converter in turn, and obtain the phase error value of each analog-to-digital converter accordingly; A window combination determination module, configured to determine an optimal synchronization window combination according to candidate synchronization window combinations in the synchronization window combinations corresponding to a phase error value less than a first preset value; The timing determination module is used to determine the synchronization timing of each of the analog-to-digital converters after calibration by using the optimal synchronization window combination.

9. A computer-readable storage medium, characterized in that: The method comprises instructions, which, when executed on a computer, enable the computer to execute the automatic synchronization timing calibration method according to any one of claims 1 to 7.

10. A timing calibration device, characterized in that: The timing calibration device comprises: at least one processor, memory, and input-output unit; The memory is used to store a computer program, and the processor is used to call the computer program stored in the memory to execute the automatic synchronization timing calibration method according to any one of claims 1 to 7.

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