A method for manufacturing a semiconductor memory

Abstract

The application provides a preparation method of a semiconductor memory, and is applied to the technical field of semiconductors. In the application, a support stack layer, a first mask layer and a via in a first region are sequentially formed on a substrate, then the first mask layer on the first region is removed to expose the support stack layer in the first region, then a lower electrode and a second mask layer on the first region are sequentially formed, and the support stack layer on the first region is further removed under the protection of the second mask layer, that is, the first mask layer on the first region and the second region is removed in steps, so that the top of the support stack layer on the first region is prevented from being damaged due to the synchronous removal of the first mask layer on the first region and the second region in the prior art, the support stack layer is prevented from tilting, and the stability of the capacitor, the efficiency and reliability of the memory device are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor memory. Background Technology

[0002] With the trend towards miniaturization in various electronic products, the design of semiconductor devices must also meet the requirements of high aggregation and high density. For dynamic random access memory (DRAM) with a recessed gate structure, it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current caused by capacitor structures. Therefore, under the current mainstream development trend, it has gradually replaced DRAM with only planar gate structures. Generally, DRAM with a recessed gate structure consists of a large number of memory cells arranged in an array to store information. Each memory cell can be composed of transistor components and capacitor components connected in series to receive voltage information from the word line (WL) and bit line (BL). Due to product demands, the density of memory cells in the array must continue to increase, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, existing technologies or structures need further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating a semiconductor memory, which solves the problem in the prior art where the simultaneous removal of the first mask layer on the first region and the second region causes loss at the top of the supporting stack layer on the first region, which in turn causes the supporting stack layer to tilt, reducing the stability of the capacitor, the performance of the memory device, and the reliability of the memory.

[0004] To address the aforementioned technical problems, the present invention provides a method for fabricating a semiconductor memory, which may include at least:

[0005] A substrate is provided, the substrate comprising a first region and a second region;

[0006] A support stack layer is formed on the first region and the second region;

[0007] A first mask layer is formed on the support stack layer located in the first region and the second region;

[0008] A via is formed within the first region, and the via penetrates the support stack layer and the first mask layer;

[0009] Remove the first mask layer on the first region to expose the support stack layer in the first region;

[0010] The lower electrode is located on the inner surface of the through hole;

[0011] A second mask layer is formed on the support stack layer in the first region and exposes the support stack layer in the second region;

[0012] Using the second mask layer as a barrier, the first mask layer on the second region is removed.

[0013] In some examples, the support stack includes a first sacrificial layer, a first support layer, a second sacrificial layer, and a second support layer stacked sequentially from bottom to top.

[0014] In some examples, during the step of removing the first mask layer on the first region, a portion of the first mask layer on the second region is also removed simultaneously.

[0015] In some examples, the step of forming a lower electrode located on the inner surface of the through-hole includes:

[0016] A conductive material layer is formed on the inner surface of the via and the top surface of the supporting stack between adjacent vias, as well as on the remaining first mask layer in the second region;

[0017] Remove a portion of the conductive material layer to expose the top surface and part of the sidewalls of the second support layer of the supporting stack on the first region, as well as the remaining first mask layer on the second region.

[0018] In some examples, the top surface of the lower electrode located on the inner surface of the via is lower than the top surface of the second support layer of the support stack on the first region.

[0019] In some examples, after removing the first mask layer on the second region, the process further includes:

[0020] Remove the first and second sacrificial layers of the support stack in the first and second regions.

[0021] In some examples, the process of removing the first and second sacrificial layers includes an etching process, which includes a wet etching process.

[0022] In some examples, after removing the second sacrificial layer, the following is also included:

[0023] A dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer.

[0024] In some examples, after removing the remaining first mask layer on the second region, the top surface of the exposed second support layer on the second region is flush with the top surface of the exposed second support layer on the first region.

[0025] In some examples, the top surface of the first mask layer in the first region is lower than the top surface of the first mask layer in the second region.

[0026] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects:

[0027] In the semiconductor memory fabrication method provided by the present invention, a support stack layer, a first mask layer, and a via located in a first region are first formed sequentially on a substrate. Then, the first mask layer on the first region is removed to expose the support stack layer in the first region. After that, a lower electrode and a second mask layer located on the first region are formed sequentially. Under the protection of the second mask layer, the support stack layer on the first region is further removed from the first mask layer on the second region. That is, by removing the first mask layer on the first region and the second region in a stepwise manner, the simultaneous removal of the first mask layer on the first region and the second region in the prior art is avoided, which leads to the top of the support stack layer on the first region being damaged. This avoids the tilting of the support stack layer and improves the stability of the capacitor, the performance of the memory device, and the reliability. Attached Figure Description

[0028] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0029] Figure 1 This is a schematic flowchart of the semiconductor memory fabrication method provided in the embodiments of the present invention;

[0030] Figures 2 to 10 This is a schematic diagram of the semiconductor memory fabrication method provided in this embodiment of the invention during the fabrication process.

[0031] The attached figures are labeled as follows:

[0032] 100 - Substrate, 101 - First region of substrate, 102 - Second region of substrate, 110 - Insulating layer, 120 / 120' - Support stacked layer, 121 - First sacrificial layer, 122 - First support layer, 123 - Second sacrificial layer, 124 - Second support layer, 130 / 130' - First mask layer, OP - Through hole, 140 / 140' - Lower electrode, 150 - Second mask layer, 160 - Dielectric layer, 170 - Upper electrode, CP - Capacitor.

[0033] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0034] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0035] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clarify the illustration of the embodiments of the invention. It is understood that the terms "on," "above," and "over" in this invention should be interpreted in the broadest sense, such that "on" means not only "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer.

[0036] For ease of understanding, the horizontal and vertical directions are defined below, where the horizontal direction is the direction parallel to the surface of the substrate 100, and the vertical direction is the direction perpendicular to the surface of the substrate 100.

[0037] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating the semiconductor memory fabrication method provided in an embodiment of the present invention. Figure 1 As shown, the semiconductor memory fabrication method provided in this embodiment includes at least the following steps:

[0038] Step S101: Provide a substrate, the substrate comprising a first region and a second region.

[0039] Step S102: A support stack layer is formed on the first region and the second region.

[0040] Step S103: A first mask layer is formed on the support stack layer located in the first region and the second region.

[0041] Step S104: A via is formed within the first region, and the via penetrates the support stack layer and the first mask layer.

[0042] Step S105: Remove the first mask layer on the first region to expose the support stack layer in the first region.

[0043] Step S106: Form the lower electrode located on the inner surface of the through hole.

[0044] Step S107: A second mask layer is formed on the support stack layer in the first region and exposes the support stack layer in the second region.

[0045] Step S108: Using the second mask layer as a barrier, remove the first mask layer on the second region.

[0046] In the semiconductor memory fabrication method proposed in this invention, the stepwise removal of the first mask layer on the first region and the second region avoids the loss on the top of the supporting stack layer on the first region caused by the simultaneous removal of the first mask layer on the first region and the second region in the prior art. This avoids the problem of the supporting stack layer tipping over, thereby improving the stability of the capacitor, the efficiency and reliability of the memory device.

[0047] To enable those skilled in the art to easily understand the semiconductor memory fabrication method in the embodiments of this invention, the following will further explain the semiconductor memory fabrication method proposed in this invention with reference to various structural schematic diagrams during the fabrication process. Among them, Figures 2 to 10 This is a schematic diagram of the semiconductor memory fabrication method provided in this embodiment of the invention during the fabrication process.

[0048] Please see Figure 2 The process involves performing step S101, providing a substrate 100, which includes a first region 101, such as a cell region of a semiconductor memory, and a second region 102, such as a peripheral region of a semiconductor memory. In one embodiment, the substrate 100 is any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto. The substrate 100 may contain bit line structures, sidewall structures, contact structures, and connection pad structures (not shown), but is not limited thereto.

[0049] Please continue reading. Figure 2The above steps S102-S103 are performed, using at least one deposition process such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition to sequentially form an insulating layer 110, a support stack layer 120, and a first mask layer 130 on the surface of the substrate 100. In one embodiment, the insulating layer 110 may include a single layer or multiple layers of dielectric material. Suitable dielectric materials may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, nitrogen-doped silicon carbide, low dielectric constant dielectric materials such as fluorosilicone glass, silicon carbide oxide, spin-coated silicon glass, porous low dielectric constant dielectric materials, or combinations of the above materials, but are not limited thereto. The support stack layer 120 may include a first sacrificial layer 121, a first support layer 122, a second sacrificial layer 123, and a second support layer 124 stacked sequentially from bottom to top, so as to provide a more robust support for the lower electrode by setting multiple support layers, but is not limited thereto. The first sacrificial layer 121 and the second sacrificial layer 123 may each comprise a single layer or multiple layers of oxide material, such as silicon oxide, boro-phospho-silicate glass (BPSG), or other sacrificial materials having a desired etch selectivity with the material of the support layer, but are not limited thereto. The first support layer 122 and the second support layer 124 may be silicon carbonitride (SiCN). The material of the first mask layer 130 may include amorphous silicon or polycrystalline silicon.

[0050] Please continue reading. Figure 2 In step S104, at least one of dry etching or wet etching processes is used to partially remove the first mask layer 130, the support stack layer 120, and the insulating layer 110 on the first region 101, thereby forming a plurality of vias OP on the first region 101. These vias OP penetrate the first mask layer 130 and the support stack layer 120, with their bottoms exposed above the substrate 100, but this is not a limitation. After etching, the top surface of the portion of the first mask layer 130 located on the first region 101 may be lower than the top surface of the portion located on the second region 102.

[0051] Please see Figure 3In step S105, the first mask layer 130 located on the first region 101 is removed using at least one of dry etching or wet etching processes to expose the second support layer 124 in the support stack layer 120 below it. Those skilled in the art will readily understand that, since the first mask layer 130 on the second region 102 is not masked and its thickness in the vertical direction is greater than that of the first mask layer 130 on the first region 101, when the first mask layer 130 on the first region 101 is removed using this step, a portion of the height of the first mask layer 130 on the second region 102 will also be simultaneously removed (in the vertical direction), thus obtaining... Figure 3 The first mask layer 130' shown is shown, but is not limited thereto.

[0052] Please see Figure 4 Following step S105 above, a conductive material layer is then formed on the top surface of the support stack layer 120 located on the inner surface (sidewalls and bottom) of the via OP and between adjacent via OPs, and on the remaining first mask layer 130' on the second region 102, using the deposition process described above. Figure 4 (The area corresponding to mark 140 in the middle). In one embodiment, the conductive material layer may include, but is not limited to, doped silicon, tungsten, copper, titanium nitride, or others.

[0053] Please see Figure 5 By performing step S106, a portion of the conductive material layer can be removed vertically to expose the top surface and part of the sidewalls of the second support layer 124 in the support stack 120 on the first region 101, as well as the remaining first mask layer 130' on the second region 102. This forms a lower electrode 140' that only covers the sidewalls and bottom (inner surface) of the via OP on the first region 101. In one embodiment, the lower electrode 140' may comprise a single or multiple layers of conductive material, such as doped silicon, tungsten, copper, titanium nitride, or other suitable conductive materials, and the top surface of the lower electrode 140' located on the inner surface of the via OP may be lower than the top surface of the second support layer 124 in the support stack 120 on the first region 101, but is not limited thereto.

[0054] Please see Figure 6Performing step S107 above, a second mask layer 150 is formed on the first region 101 using the above deposition process. The second mask layer 150 fills the plurality of vias OP located on the first region 101 and buries the support stack layer 120 within them. In one embodiment, the material of the second mask layer 150, such as silicon nitride or silicon oxide, can be formed on both the first region 101 and the second region 102. Then, the material of the second mask layer 150 on the second region 102 is removed using etching or chemical mechanical polishing processes, so that the top surface of the second mask layer 150 remaining on the first region 101 is flush with the top surface of the remaining first mask layer 130' on the second region 102, but this is not a limitation. The material of the second mask layer 150 can be the same as or different from the material of the first mask layer 130, and this is not a limitation.

[0055] Please see Figure 7 After performing step S108, an etching process is then used to remove the remaining first mask layer 130' on the second region 102, exposing the second support layer 124 in the support stack layer 120 located below it. In this step, the lower electrode 140' and the support stack layer 120 located on the first region 101 are both shielded by the second mask layer 150. Therefore, in the process of removing the first mask layer 130 on the first region 101 and the second region 102 in a stepwise manner as proposed in this embodiment of the invention, no damage is caused to the second support layer 124 in the support stack layer 120 located on the first region 101, thus ensuring the integrity of the support stack layer morphology and preventing the support stack layer from tilting, thereby improving the stability of the capacitor, the performance of the memory device, and the reliability. In one embodiment, after removing the remaining first mask layer 130' on the second region 102 using the above step S108, the top surface of the exposed second support layer 124 on the second region 102 can be flush with the top surface of the exposed second support layer 124 on the first region 101.

[0056] Please see Figure 8 and Figure 9 Following step S108, an etching process, such as wet etching, can be used to sequentially remove the second mask layer 150 located on the first region 101, and the first sacrificial layer 121 and the second sacrificial layer 123 in the support stack layer 120 located on the first region 101 and the second region 102, in preparation for the subsequent formation of the dielectric layer and the upper electrode of the capacitor CP.

[0057] Please see Figure 10Following step S108, a dielectric layer 160 can be formed on the lower electrode 140' using semiconductor manufacturing processes such as deposition and etching, and an upper electrode 170 can be formed on the dielectric layer 160, thus forming a capacitor CP composed of the lower electrode 140', the dielectric layer 160, and the upper electrode 170. In one embodiment, the dielectric layer 160 may include a high dielectric constant metal oxide layer, such as TaOO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST ((Ba,Sr)TiO), STO (SrTiO), BTO (BaTiO), PZT (Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)OO, Sr(Zr,Ti)O, combinations of the above materials, or other suitable dielectric materials, while the material of the upper electrode 170 may include titanium nitride, tantalum nitride, SiGe, combinations of the above materials, or other suitable conductive materials, but is not limited thereto. Furthermore, the materials of the dielectric layer 160 and the upper electrode 170 may extend to fill the regions corresponding to the first sacrificial layer 121 and the second sacrificial layer 123 of the support stack 120 located on the first region 101 and the second region 102 as removed in the above steps, but are not limited thereto.

[0058] In summary, in the semiconductor memory fabrication method provided by this invention, a support stack layer, a first mask layer, and a via located in a first region are first formed sequentially on a substrate. Then, the first mask layer on the first region is removed to expose the support stack layer in the first region. Subsequently, a lower electrode and a second mask layer located on the first region are formed sequentially, and the support stack layer on the first region is protected by the second mask layer. The first mask layer on the second region is then further removed. That is, by removing the first mask layer on the first region and the second region in a stepwise manner, the simultaneous removal of the first mask layer on the first region and the second region in the prior art is avoided, which leads to the top of the support stack layer on the first region being damaged. This prevents the support stack layer from tipping over and improves the stability of the capacitor, the performance of the memory device, and its reliability.

[0059] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0060] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, and computer-readable storage media are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0061] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor memory, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A support stack layer is formed on the first region and the second region; A first mask layer is formed on the support stack layer located in the first region and the second region; A via is formed within the first region, and the via penetrates the support stack layer and the first mask layer; Remove the first mask layer on the first region and a portion of the first mask layer on the second region to expose the support stack layer in the first region; The lower electrode is located on the inner surface of the through hole; A second mask layer is formed on the support stack layer in the first region and exposes the support stack layer in the second region; Using the second mask layer as a barrier, the first mask layer on the second region is removed.

2. The method for fabricating a semiconductor memory as described in claim 1, characterized in that, The support stack includes a first sacrificial layer, a first support layer, a second sacrificial layer, and a second support layer stacked sequentially from bottom to top.

3. The method for fabricating a semiconductor memory as described in claim 1, characterized in that, The step of forming a lower electrode located on the inner surface of the through hole includes: A conductive material layer is formed on the inner surface of the via and the top surface of the supporting stack between adjacent vias, as well as on the remaining first mask layer in the second region; Remove a portion of the conductive material layer to expose the top surface and part of the sidewalls of the second support layer of the supporting stack on the first region, as well as the remaining first mask layer on the second region.

4. The method for fabricating a semiconductor memory as described in claim 3, characterized in that, The top surface of the lower electrode located on the inner surface of the through hole is lower than the top surface of the second support layer of the support stack layer on the first region.

5. The method for fabricating a semiconductor memory as described in claim 2, characterized in that, After removing the first mask layer on the second region, the process further includes: Remove the first and second sacrificial layers of the support stack in the first and second regions.

6. The method for fabricating a semiconductor memory as described in claim 5, characterized in that, The process for removing the first and second sacrificial layers includes an etching process, which includes a wet etching process.

7. The method for fabricating a semiconductor memory as described in claim 5, characterized in that, After removing the second sacrificial layer, the following is also included: A dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer.

8. The method for fabricating a semiconductor memory as described in claim 3, characterized in that, After removing the remaining first mask layer on the second region, the top surface of the second support layer exposed on the second region is flush with the top surface of the second support layer exposed on the first region.

9. The method for fabricating a semiconductor memory as described in claim 1, characterized in that, The top surface of the first mask layer in the first region after the via is formed is lower than the top surface of the first mask layer in the second region.

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