New memory with 3D structure and its preparation method

Abstract

The present invention provides a novel memory with a 3D structure and a preparation method thereof. The present invention directly forms a memory cell on the active area after forming a gate structure process, thereby reducing the influence of the thermal budget of the memory cell-related process on the front-end process device and reducing the influence of the front layer on the memory cell profile; the lower electrode of the memory cell is directly connected to the active area, and the upper electrode of the memory cell and the active area / gate structure without the memory cell are led out through the corresponding contact structure / connection structure, thereby reducing the dielectric layer and the mask process; and through the first anti-reflection layer back etching and the memory cell mask and etching process, the memory cell is made between two adjacent gate structures, thereby increasing the effective area of ​​phase change.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a novel memory with a 3D structure and a preparation method thereof. Background Art

[0002] New memory devices such as phase change memory (PRAM) or ferroelectric memory (FeRAM) are devices that integrate memory cells in the back-end of the line (BEOL). Memory cells are inserted between metal layers, and their storage performance is proportional to the effective area of ​​the storage layer and the electrode layer. The use of a three-dimensional (3D) structure in memory cells can effectively increase storage density or achieve better cell performance / reliability at the same cell area.

[0003] After the traditional 3D structure process is integrated into the devices and contact structures of the front-end-of-line (FEOL), the thermal budget of the 3D structure process (the heat energy required for silicon exposure in the process) may affect the front-end process devices. At the same time, the profile of the 3D structure storage unit is greatly affected by the previous layer. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a new type of memory with a 3D structure and a preparation method thereof, which can reduce the impact of the thermal budget of the memory cell-related process on the front-end process devices while ensuring the connection performance of the contact structure remains unchanged, reduce the impact of the front layer on the memory cell profile, increase the effective area of ​​the phase change, improve the storage performance, save the mask process, and reduce the production cost.

[0005] In order to solve the above problems, the present invention provides a method for preparing a novel memory with a 3D structure, the method comprising the following steps: forming a semiconductor substrate, the semiconductor substrate comprising a substrate, a gate structure formed on the surface of the substrate, a groove formed between two adjacent gate structures, and an active area defined in the substrate at the bottom of the groove; forming a storage unit with a 3D structure, the storage unit is continuously distributed at the bottom and part of the sidewall of the groove, the storage unit comprises a first electrode layer, a storage layer and a second electrode layer stacked in sequence, at the bottom of the groove, the first electrode layer is in contact with the active area; forming a dielectric layer, the dielectric layer covers the substrate, all the gate structures and all the storage units, and fills the groove; forming a contact structure, the contact structure penetrates the dielectric layer in the groove area along a direction perpendicular to the substrate surface and is in contact with the second electrode layer; and forming a metal structure, the metal structure is located on the surface of the dielectric layer and is in contact with the contact structure.

[0006] In some embodiments, the storage unit is a U-shaped structure.

[0007] In some embodiments, the step of forming a 3D structured memory cell includes: forming a contact layer, wherein the contact layer covers the surface of the substrate and exposes the gate structure.

[0008] In some embodiments, the steps of forming a 3D structure storage unit specifically include: depositing a first electrode material layer, a storage material layer and a second electrode material layer on the surface of the substrate and all the gate structure surfaces in sequence; depositing an anti-reflection material on the surface of the second electrode material layer and planarizing it to form a first anti-reflection layer, and the first anti-reflection layer fills the groove; etching back to remove the first anti-reflection layer to expose the top and part of the side wall of the gate structure; depositing an anti-reflection material on the surface of the second electrode material layer and the surface of the gate structure and planarizing it to form a second anti-reflection layer, and forming a photoresist structure on the surface of the second anti-reflection layer, the second anti-reflection layer fills the groove, the photoresist structure corresponds to the groove, and the width of the photoresist structure is greater than the spacing between two adjacent gate structures; etching with the photoresist structure as a mask, etching the remaining second electrode material layer to form the second electrode layer, etching the remaining storage material layer to form the storage layer, and etching the remaining first electrode material layer to form the first electrode layer; removing the remaining photoresist structure and the second anti-reflection layer.

[0009] In some embodiments, the step of forming a dielectric layer specifically includes: forming an etch barrier layer covering the substrate, all the gate structures and all the storage cells, and forming the dielectric layer covering the etch barrier layer and filling the groove; the step of forming a contact structure specifically includes: using the etch barrier layer as an etch stop layer to etch in the dielectric layer in the groove area to form a contact hole exposing the second electrode layer, and depositing a metal material and flattening it to form the contact structure in the contact hole, wherein the top surface of the contact structure is flush with the top surface of the dielectric layer.

[0010] In some embodiments, the step of forming the metal structure specifically includes: depositing a metal material on the surface of the dielectric layer and patterning the metal material to form the metal structure.

[0011] In some embodiments, the materials of the first electrode layer and the second electrode layer are both titanium nitride, the material of the storage layer is ferroelectric material or phase change material, the material of the dielectric layer is oxide, the material of the contact structure is metal tungsten, and the material of the metal structure is selected from aluminum, copper, or aluminum-copper alloy.

[0012] In order to solve the above problems, the present invention also provides a new type of memory with a 3D structure, including: a substrate, a gate structure is formed on the surface of the substrate, a groove is formed between two adjacent gate structures, and an active area is defined in the substrate at the bottom of the groove; a storage unit, the storage unit is continuously distributed at the bottom and part of the side wall of the groove, the storage unit includes a first electrode layer, a storage layer and a second electrode layer stacked in sequence, at the bottom of the groove, the first electrode layer is in contact with the active area; a dielectric layer, covering the substrate, all the gate structures and all the storage units, and filling the groove; a contact structure, penetrating the dielectric layer in a direction perpendicular to the substrate surface and in contact with the second electrode layer; and a metal structure, located on the surface of the dielectric layer and in contact with the contact structure.

[0013] In some embodiments, the storage unit is a U-shaped structure.

[0014] In some embodiments, the materials of the first electrode layer and the second electrode layer are both titanium nitride, the material of the storage layer is ferroelectric material or phase change material, the material of the dielectric layer is oxide, the material of the contact structure is metal tungsten, and the material of the metal structure is selected from aluminum, copper, or aluminum-copper alloy.

[0015] In some embodiments, the novel memory with a 3D structure further includes: a contact layer covering the surface of the substrate and exposing the gate structure.

[0016] In some embodiments, the material of the contact layer is metal silicide.

[0017] The above technical solution forms a memory cell directly on the active area after forming the gate structure process, thereby reducing the impact of the thermal budget of the memory cell-related process on the front-end process device and reducing the impact of the front layer on the memory cell profile; the lower electrode (first electrode layer) of the memory cell is directly connected to the active area, and the upper electrode (second electrode layer) of the memory cell and the active area / gate structure without the memory cell are led out through the corresponding contact structure / connection structure, thereby reducing the dielectric layer and the photomask process; and through the first anti-reflection layer back etching and the memory cell photomask and etching process, the memory cell is made between two adjacent gate structures, thereby increasing the phase change effective area. The present invention can reduce the impact of the thermal budget of the memory cell-related process on the front-end process device, reduce the impact of the front layer on the memory cell profile, reduce the dielectric layer and the photomask process, thereby improving the storage performance, optimizing and improving the device operation efficiency and reliability, and reducing the production cost on the basis of increasing the phase change effective area of ​​the memory cell and keeping the contact structure connection performance unchanged. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of a device structure of a 3D structure memory in the prior art;

[0020] Figure 2 A schematic diagram of a contour defect of a memory with a 3D structure in the prior art;

[0021] Figure 3 A schematic diagram of the steps of a method for preparing a novel memory with a 3D structure according to an embodiment of the present invention;

[0022] Figure 4 A schematic diagram of a device structure of a semiconductor substrate provided by an embodiment of the present invention;

[0023] Figure 5A to Figure 5E A schematic diagram of a device structure for forming a storage unit according to an embodiment of the present invention;

[0024] Figure 6 A schematic diagram of a device structure for forming a dielectric layer according to an embodiment of the present invention;

[0025] Figure 7A~Figure 7B A schematic diagram of a device structure for forming a contact structure according to an embodiment of the present invention;

[0026] Figure 8 FIG. 1 is a schematic diagram of a device structure for forming a metal structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] See also Figure 1 , which is a schematic diagram of the device structure of a 3D structure memory in the prior art. Figure 1As shown, the existing 3D structure memory includes: a substrate 10, a first dielectric layer 111 formed on the substrate 10, a first connection structure 121 formed in the first dielectric layer 111, a second dielectric layer 112 formed on the first dielectric layer 111, a storage unit 14 formed in the second dielectric layer 112 and in contact with the first connection structure 121, and a second connection structure 122 in contact with the storage unit 14, a third dielectric layer 113 covering the second dielectric layer 112 and covering the storage unit 14 and the second connection structure 122, a third connection structure 123 formed in the third dielectric layer 113 and in contact with the second connection structure 122, and a metal structure 13 formed on the surface of the third dielectric layer 113 and in contact with the third connection structure 123. The storage unit 14 is composed of a lower electrode layer 141, a middle storage layer 142, and an upper electrode layer 143. A first blocking layer 191 is formed between the first dielectric layer 111 and the second dielectric layer 112 , and a second blocking layer 192 is formed between the second dielectric layer 112 and the third dielectric layer 113 .

[0029] The memory cell 14 uses a three-dimensional (3D) structure to effectively improve storage density, or achieve better unit performance / reliability under the same unit area. However, after the memory cell preparation process is integrated into the device and contact structure of the front-end process (FEOL), the thermal budget of the process will affect the front-end process device. The profile of the memory cell is greatly affected by the previous layer, such as Figure 2 As shown in the dotted box. Figure 2 In the figure, a single-layer color block is used to indicate a storage unit, and the outline of the storage unit in the dotted frame is affected by the protruding contact structure and deformed. At the same time, when preparing the memory, multiple dielectric layers need to be deposited, and the preparation of the first connection structure 121, the second connection structure 122, and the third connection structure 123 requires three mask processes, resulting in increased production costs.

[0030] In order to solve the problem in the prior art that the thermal budget of the storage unit preparation process affects the front-end process devices, the profile of the storage unit is greatly affected by the front layer, and multiple dielectric layer deposition and multiple mask processes are required, resulting in increased production costs, the present invention provides a new type of memory with a 3D structure and a preparation method thereof, which can reduce the impact of the thermal budget of the storage unit-related processes on the front-end process devices, reduce the impact of the front layer on the storage unit profile, reduce the dielectric layer and mask processes, thereby improving storage performance, optimizing and improving device operation efficiency and reliability, and reducing production costs.

[0031] An embodiment of the present invention provides a method for preparing a novel memory with a 3D structure.

[0032] Please also read Figure 3~Figure 8 ,in, Figure 3 A schematic diagram of the steps of a method for preparing a novel memory with a 3D structure according to an embodiment of the present invention; Figure 4 A schematic diagram of a device structure of a semiconductor substrate provided by an embodiment of the present invention; Figure 5A to Figure 5E A schematic diagram of a device structure for forming a storage unit according to an embodiment of the present invention; Figure 6 A schematic diagram of a device structure for forming a dielectric layer according to an embodiment of the present invention; Figure 7A~Figure 7B A schematic diagram of a device structure for forming a contact structure according to an embodiment of the present invention; Figure 8 FIG. 1 is a schematic diagram of a device structure for forming a metal structure according to an embodiment of the present invention.

[0033] like Figure 3 As shown, the preparation method of the novel memory of the 3D structure described in this embodiment includes the following steps: S1, forming a semiconductor substrate, the semiconductor substrate includes a substrate, a gate structure formed on the surface of the substrate, a groove is formed between two adjacent gate structures, and an active area is defined in the substrate at the bottom of the groove; S2, forming a storage unit of the 3D structure, the storage unit is continuously distributed at the bottom and part of the side wall of the groove, the storage unit includes a first electrode layer, a storage layer and a second electrode layer which are stacked in sequence, and at the bottom of the groove, the first electrode layer is in contact with the active area; S3, forming a dielectric layer, the dielectric layer covers the substrate, all the gate structures and all the storage units, and fills the groove; S4, forming a contact structure, the contact structure penetrates the dielectric layer in the groove area along a direction perpendicular to the substrate surface and is in contact with the second electrode layer; and S5, forming a metal structure, the metal structure is located on the surface of the dielectric layer and is in contact with the contact structure.

[0034] Please refer to step S1 and Figure 4 , forming a semiconductor substrate, the semiconductor substrate includes a substrate 40, a gate structure 49 formed on the surface of the substrate 40, a groove 490 is formed between two adjacent gate structures 49, and an active area 401 is defined in the substrate at the bottom of the groove 490.

[0035] The substrate 40 is used to support the device structure above it, and the device structure may also be formed in the substrate 40. In this embodiment, the substrate 40 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; the substrate 40 may also be a stacked structure, such as a silicon / germanium silicon stack, etc.

[0036] The gate structure 49 includes a polysilicon gate 491, a gate oxide layer 492 located below the polysilicon gate 491, and a spacer 493 located on the sidewall of the polysilicon gate 491. An active region 401 is defined in the substrate between two adjacent gate structures 49.

[0037] In this embodiment, before the step (S2) of forming the memory cell of the 3D structure, the process includes: forming a contact layer 41, wherein the contact layer 41 covers the surface of the substrate 40 and exposes the gate structure 49, such as Figure 4 As shown. The source / drain electrodes on both sides of the gate structure 49 can be led out through the contact layer 41. Specifically, the material of the contact layer 41 is metal silicide.

[0038] Please refer to step S2 and Figure 5E , forming a 3D structured storage unit 50, the storage unit 50 is continuously distributed at the bottom and part of the side wall of the groove 490, the storage unit 50 includes a first electrode layer 51, a storage layer 52 and a second electrode layer 53 which are stacked in sequence, and at the bottom of the groove 490, the first electrode layer 51 is in contact with the active area 401.

[0039] Specifically, when the surface of the substrate 40 is covered with a contact layer 41 , the first electrode layer 51 is in contact with the active region 401 through the contact layer 41 .

[0040] In this embodiment, the step S2 includes: (1) depositing a first electrode material layer 510, a storage material layer 520 and a second electrode material layer 530 on the surface of the substrate 40 and all the surfaces of the gate structure 49 in sequence, such as Figure 5A (2) Depositing an anti-reflection material on the surface of the second electrode material layer 530 and planarizing it to form a first anti-reflection layer 591, wherein the first anti-reflection layer 591 fills the groove 490, as shown in FIG. Figure 5B (3) Etch back to remove the first anti-reflection layer 591, exposing the top and part of the sidewall of the gate structure 49, as shown in FIG. Figure 5C (4) Depositing an anti-reflection material on the surface of the second electrode material layer 530 and the surface of the gate structure 49 and planarizing them to form a second anti-reflection layer 592, and forming a photoresist structure 593 on the surface of the second anti-reflection layer 592, wherein the second anti-reflection layer 592 fills the groove 490, the photoresist structure 593 corresponds to the groove 490, and the width W1 of the photoresist structure 593 is greater than the spacing W2 between two adjacent gate structures 49, as shown in FIG. Figure 5D (5) using the photoresist structure 593 as a mask to perform etching, etching the remaining second electrode material layer 530 to form the second electrode layer 53, etching the remaining storage material layer 520 to form the storage layer 52, and etching the remaining first electrode material layer 510 to form the first electrode layer 51; and (6) removing the remaining photoresist structure 593 and the second anti-reflection layer 592 to obtain a 3D structure storage unit 50, as shown. Figure 5E shown.

[0041] In the back etching described in the above step (3), since there is an etching selectivity ratio between the first anti-reflection layer 591 and the film layers of the memory cell 50, and the film thickness of the first anti-reflection layer 591 at the top of the gate structure 49 is less than the film thickness of the first anti-reflection layer 591 in other regions, after the back etching removes all of the first anti-reflection layer 591, the first electrode material layer 510, the memory material layer 520 and the second electrode material layer 530 covering the top and part of the sidewall of the gate structure 49 are also removed, exposing the top and part of the sidewall of the gate structure 49, as shown in FIG. Figure 5C The use of two anti-reflection layers can prevent the corresponding material of the memory cell from remaining on the top of the gate structure 49 .

[0042] In some embodiments, the first electrode material layer 510, the storage material layer 520 and the second electrode material layer 530 can be deposited and grown by maskless atomic layer deposition (ALD). The materials of the first electrode layer 51 and the second electrode layer 53 are both titanium nitride, and the material of the storage layer 52 is ferroelectric material or phase change material.

[0043] In some embodiments, both the first anti-reflective layer 591 and the second anti-reflective layer 592 may adopt bottom anti-reflective coating (BARC), which is a layer of organic or inorganic anti-reflective material deposited before photolithography coating to achieve the purpose of increasing the photolithography process window and improving the photolithography stripe width control. The process of forming the first anti-reflective layer 591 and the second anti-reflective layer 592 may also include a planarization process so that the formed anti-reflective layer has a relatively flat surface. The planarization can be achieved by a chemical mechanical polishing (CMP) process. The positive projection of the photoresist structure 593 on the substrate 40 completely covers the area between the two adjacent gate structures 49, and partially covers the adjacent gate structure 49.

[0044] In this embodiment, the storage unit 50 is a U-shaped structure. Specifically, the first electrode layer 51, the storage layer 52 and the second electrode layer 53 have the same shape, all of which are U-shaped. The first electrode layer 51 covers the substrate between the two adjacent gate structures (contacting the active area 401 through the contact layer 41), and also partially covers the opposite side walls of the two adjacent gate structures, and the first electrode layer 51 is a continuously distributed film layer. The storage layer 52 covers the surface of the first electrode layer 51, and the second electrode layer 53 covers the surface of the storage layer 52.

[0045] This embodiment directly forms a memory cell after forming a gate structure (further forming a contact layer) process, thereby reducing the impact of the thermal budget of the memory cell-related process on the front-end process device and reducing the impact of the front layer on the memory cell profile; the lower electrode (first electrode layer) of the memory cell is directly connected to the active area, and the subsequent upper electrode (second electrode layer) of the memory cell and the active area / gate structure without the memory cell are led out through the corresponding contact structure, thereby reducing the dielectric layer and mask process; and through the back etching of the first anti-reflection layer and the mask and etching process of the memory cell, the memory cell is placed between two adjacent gate structures to increase the effective area of ​​the phase change.

[0046] Please refer to step S3 and Figure 6 , forming a dielectric layer 61 , wherein the dielectric layer 61 covers the substrate 40 , all the gate structures 49 , and all the storage units 50 , and fills the groove 490 .

[0047] In this embodiment, the material of the dielectric layer 61 may be an oxide (OX) material, such as silicon oxide (SiO).

[0048] In this embodiment, the step of forming the dielectric layer 61 specifically includes: forming an etch stop layer 69 covering the substrate 40, all the gate structures 49 and all the memory cells 50, and forming the dielectric layer 61 covering the etch stop layer 69 and filling the groove 490. The etch stop layer 69 serves as an etch stop layer for subsequent etching of contact holes for forming contact structures. The material of the etch stop layer 69 may be silicon nitride (SiN).

[0049] Please refer to step S4 and Figure 7B , forming a contact structure 71 , wherein the contact structure 71 penetrates the dielectric layer 61 in the groove 490 region in a direction perpendicular to the surface of the substrate 40 and contacts the second electrode layer 53 .

[0050] When the step of forming the dielectric layer 61 also forms the etching stop layer 69, the step of forming the contact structure 71 specifically includes: (1) using the etching stop layer 69 as an etching stop layer, etching in the dielectric layer 61 in the region of the groove 490 to form a contact hole 701 exposing the second electrode layer 53, such as Fig. 7A and (2) depositing a metal material and planarizing the metal material to form the contact structure 71 in the contact hole 701, as shown in FIG. Figure 7B The material of the contact structure 71 can be metal tungsten.

[0051] In this embodiment, the top surface of the contact structure 71 is flush with the top surface of the dielectric layer 61 .

[0052] In this embodiment, a connection structure 72 is formed while forming the contact structure 71. The connection structure 72 penetrates the dielectric layer 61 in a direction perpendicular to the surface of the substrate 40, and the connection structure 72 is spaced apart from the contact structure 71. A portion of the connection structure 72 is used to contact the substrate 40 (specifically, to contact another active area without a storage unit in the substrate 40), and a portion of the connection structure 72 is used to contact the gate structure 49. The upper electrode (second electrode layer) of the storage unit and the active area / gate structure without a storage unit are led out through the contact structure 71 and the connection structure 72. Specifically, while etching to form the contact hole 701 exposing the second electrode layer 53, etching to form the connection hole 702 exposing the substrate 40, and etching to form the connection hole (not shown) exposing the top of the gate structure 49.

[0053] Please refer to step S5 and Figure 8 , forming a metal structure 81 , wherein the metal structure 81 is located on the surface of the dielectric layer 61 and contacts the contact structure 71 .

[0054] In this embodiment, the step of forming the metal structure 81 specifically includes: depositing and patterning a metal material on the surface of the dielectric layer 61 to form the metal structure 81. The patterning process can refer to the existing metal patterning process, which will not be described in detail here.

[0055] In this embodiment, the metal structure 81 is in one-to-one contact with the connection structure 72. The metal structure 81 serves as a lead-out structure or a pad. The material of the metal structure 81 is selected from one of aluminum, copper, or aluminum-copper alloy, preferably aluminum-copper alloy.

[0056] Based on the same inventive concept, the present invention also provides a new type of memory with a 3D structure prepared by the above method of the present invention.

[0057] See also Figure 4~Figure 8 The novel memory of the 3D structure described in this embodiment includes: a substrate 40, an active region 401, a gate structure 49, a memory cell 50, a dielectric layer 61, a contact structure 71, and a metal structure 81. The memory cell 50 covers the substrate between two adjacent gate structures 49, and also partially covers the opposite sidewalls of the two adjacent gate structures 49.

[0058] Specifically, a gate structure 49 is formed on the surface of the substrate 40, a groove 490 is formed between two adjacent gate structures 49, and an active area 401 is defined in the substrate at the bottom of the groove 490. The storage cells 50 are continuously distributed at the bottom and part of the sidewalls of the groove 490, and the storage cells 50 include a first electrode layer 51, a storage layer 52 and a second electrode layer 53 which are stacked in sequence. At the bottom of the groove 490, the first electrode layer 51 is in contact with the active area 401. The dielectric layer 61 covers the substrate 40, all the gate structures 49 and all the storage cells 50, and fills the groove 490. The contact structure 71 penetrates the dielectric layer 61 in a direction perpendicular to the surface of the substrate 40 and is in contact with the second electrode layer 53. The metal structure 81 is located on the surface of the dielectric layer 61 and is in contact with the contact structure 71.

[0059] In this embodiment, the materials of the first electrode layer 51 and the second electrode layer 53 are both titanium nitride, the material of the storage layer 52 is a ferroelectric material or a phase change material, the material of the dielectric layer 61 is an oxide (for example, silicon oxide), the material of the contact structure 71 is metal tungsten, and the material of the metal structure 81 is selected from aluminum, copper, or aluminum-copper alloy.

[0060] In this embodiment, the gate structure 49 includes a polysilicon gate (Poly Gate) 491 , a gate oxide layer (Oxide) 492 located below the polysilicon gate 491 , and a spacer (Spacer) 493 located on the sidewall of the polysilicon gate 491 .

[0061] In this embodiment, the novel memory with a 3D structure further includes: a contact layer 41, which covers the surface of the substrate 40 and exposes the gate structure 49. Specifically, the material of the contact layer 41 is metal silicide.

[0062] In this embodiment, the top surface of the contact structure 71 is flush with the top surface of the dielectric layer 61 .

[0063] In this embodiment, the novel memory of the 3D structure further includes: a connection structure 72, which is formed by the same process as the contact structure 71; the connection structure 72 penetrates the dielectric layer 61 in a direction perpendicular to the surface of the substrate 40, and the connection structure 72 is spaced apart from the contact structure 71. A portion of the connection structure 72 is used to contact the substrate 40 (specifically, another active area without a storage unit in the substrate 40), and a portion of the connection structure 72 is used to contact the gate structure 49. The upper electrode (second electrode layer) of the storage unit and the active area / gate structure without a storage unit are led out through the contact structure 71 and the connection structure 72. The metal structure 81 is also in one-to-one contact with the connection structure 72. The metal structure 81 serves as a lead-out structure or a pad.

[0064] In this embodiment, the storage unit 50 is a U-shaped structure. Specifically, the first electrode layer 51, the storage layer 52 and the second electrode layer 53 have the same shape, all of which are U-shaped. The first electrode layer 51 covers the substrate between the two adjacent gate structures (contacting the active area 401 through the contact layer 41), and also partially covers the opposite side walls of the two adjacent gate structures, and the first electrode layer 51 is a continuously distributed film layer. The storage layer 52 covers the surface of the first electrode layer 51, and the second electrode layer 53 covers the surface of the storage layer 52.

[0065] In this embodiment, after forming the gate structure (further forming the contact layer), the memory cell is directly formed on the active area, thereby reducing the impact of the thermal budget of the memory cell-related process on the front-end process device and reducing the impact of the front layer on the memory cell profile; the lower electrode (first electrode layer) of the memory cell is directly connected to the active area, and the upper electrode (second electrode layer) of the memory cell and the active area / gate structure without the memory cell are led out through the corresponding contact structure / connection structure, thereby reducing the dielectric layer and mask process; and through the back etching of the first anti-reflection layer and the mask and etching process of the memory cell, the memory cell is placed between two adjacent gate structures, thereby increasing the effective area of ​​the phase change.

[0066] In the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0067] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only include those elements, but also include other elements not clearly listed, or also include elements inherent to such process, method, article or equipment. In the absence of more restrictions, there is a sentence "also includes a ..." The elements limited do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0068] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. It should be noted that a person skilled in the art may make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications shall also be regarded as the protection scope of the present invention.

Claims

1. A method for preparing a novel memory with a 3D structure, characterized in that: The method comprises the following steps: forming a semiconductor substrate, the semiconductor substrate comprising a substrate, a gate structure formed on the surface of the substrate, a groove formed between two adjacent gate structures, and an active area defined in the substrate at the bottom of the groove; forming a storage unit of a 3D structure, the storage unit is continuously distributed at the bottom and part of the sidewall of the groove, the storage unit comprises a first electrode layer, a storage layer and a second electrode layer stacked in sequence, at the bottom of the groove, the first electrode layer is in contact with the active area, at the sidewall of the groove, the first electrode layer is in contact with the gate structure; forming a dielectric layer, the dielectric layer covers the substrate, all the gate structures and all the storage units, and fills the groove; forming a contact structure, the contact structure penetrates the dielectric layer in the groove area in a direction perpendicular to the substrate surface, and is in contact with the second electrode layer; And forming a metal structure, wherein the metal structure is located on the surface of the dielectric layer and contacts the contact structure.

2. The method according to claim 1, characterized in that The storage unit is a U-shaped structure.

3. The method according to claim 1, characterized in that The step of forming the storage unit of the 3D structure includes: forming a contact layer, wherein the contact layer covers the surface of the substrate and exposes the gate structure.

4. The method according to claim 1, characterized in that: The steps of forming a storage unit with a 3D structure specifically include: depositing a first electrode material layer, a storage material layer and a second electrode material layer on the surface of the substrate and all the surfaces of the gate structure in sequence; depositing an anti-reflection material on the surface of the second electrode material layer and flattening it to form a first anti-reflection layer, and the first anti-reflection layer fills the groove; etching back to remove the first anti-reflection layer to expose the top and part of the side wall of the gate structure; depositing an anti-reflection material on the surface of the second electrode material layer and the surface of the gate structure and flattening it to form a second anti-reflection layer, and forming a photoresist structure on the surface of the second anti-reflection layer, the second anti-reflection layer fills the groove, the photoresist structure corresponds to the groove, and the width of the photoresist structure is greater than the spacing between two adjacent gate structures; etching with the photoresist structure as a mask to etch the remaining second electrode material layer to form the second electrode layer, the remaining storage material layer to form the storage layer, and the remaining first electrode material layer to form the first electrode layer; removing the remaining photoresist structure and the second anti-reflection layer.

5. The method according to claim 1, characterized in that The step of forming a dielectric layer specifically includes: forming an etch barrier layer covering the substrate, all the gate structures and all the storage units, and forming the dielectric layer covering the etch barrier layer and filling the groove; the step of forming a contact structure specifically includes: using the etch barrier layer as an etch stop layer to etch in the dielectric layer in the groove area to form a contact hole exposing the second electrode layer, and depositing a metal material and flattening it to form the contact structure in the contact hole, wherein the top surface of the contact structure is flush with the top surface of the dielectric layer.

6. The method according to claim 1, characterized in that The step of forming the metal structure specifically includes: depositing metal material on the surface of the dielectric layer and patterning it to form the metal structure.

7. The method according to claim 1, characterized in that The materials of the first electrode layer and the second electrode layer are both titanium nitride, the material of the storage layer is ferroelectric material or phase change material, the material of the dielectric layer is oxide, the material of the contact structure is metal tungsten, and the material of the metal structure is selected from aluminum, copper, or aluminum-copper alloy.

8. A new type of memory with 3D structure, characterized in that: The invention comprises: a substrate, a gate structure is formed on the surface of the substrate, a groove is formed between two adjacent gate structures, and an active area is defined in the substrate at the bottom of the groove; A storage unit is continuously distributed at the bottom and part of the sidewall of the groove, and the storage unit includes a first electrode layer, a storage layer and a second electrode layer which are sequentially stacked, and the first electrode layer is in contact with the active area at the bottom of the groove, and the first electrode layer is in contact with the gate structure at the sidewall of the groove; a dielectric layer covers the substrate, all the gate structures and all the storage units, and fills the groove; a contact structure, penetrating the dielectric layer in a direction perpendicular to the substrate surface and contacting the second electrode layer; and a metal structure located on the surface of the dielectric layer and in contact with the contact structure.

9. The novel 3D structured memory according to claim 8, characterized in that: The storage unit is a U-shaped structure.

10. The novel 3D structured memory according to claim 8, characterized in that: The materials of the first electrode layer and the second electrode layer are both titanium nitride, the material of the storage layer is ferroelectric material or phase change material, the material of the dielectric layer is oxide, the material of the contact structure is metal tungsten, and the material of the metal structure is selected from aluminum, copper, or aluminum-copper alloy.

11. The novel 3D structured memory according to claim 8, characterized in that: Also includes: The contact layer covers the surface of the substrate and exposes the gate structure.

12. The novel 3D structured memory according to claim 11, characterized in that: The material of the contact layer is metal silicide.

Images