Server link configuration control method, device and system

Abstract

The embodiment of the present application provides a control method, device and system for server link configuration, wherein the method comprises: a controller sends a target configuration instruction to a processor, wherein the target configuration instruction is used to instruct the processor to use an initial parameter value to configure a bus link between the processor and a target memory to be accessed, and obtain an initial bus link, wherein the initial parameter value is a parameter value of a communication parameter corresponding to a target type to which the target memory belongs, and the communication parameter is a parameter used to indicate the transmission performance of a signal between the processor and the target memory; the controller obtains the current communication rate of the initial bus link reported by the processor; and when the current communication rate does not fall within the communication rate range, enters a target control mode for the processor. Through the present application, the problem of poor compatibility of the memory with the server link environment in the related art is solved, thereby achieving the effect of improving the compatibility of the memory with the server link environment.

Description

Technical Field

[0001] The embodiments of the present application relate to the computer field, and in particular, to a method, device and system for controlling server link configuration. Background Art

[0002] With the development of Internet business and the growth of data volume, servers need to increase storage capacity or improve storage performance. High-performance memory produced by some mainstream manufacturers has gradually been favored by major server manufacturers. The server data storage generated by mainstream manufacturers has obvious advantages, and there is no need to worry about data loss after power failure. The data storage performance is high, but this kind of memory has an obvious disadvantage, that is, the price is high. Therefore, in order to reduce the cost of the server, server manufacturers try to introduce memory with the same function manufactured by non-mainstream manufacturers, and use memory from different manufacturers in the same server. On the one hand, it guarantees the data storage performance of the server, and on the other hand, it reduces the configuration cost of the server. Therefore, memory from different manufacturers may be deployed on the server. In the server, the memory of non-mainstream manufacturers has little R&D experience, has not been tested in large-scale batches, and even the design differences of the server itself, which will cause various technical problems in the non-mainstream memory in the servers of various manufacturers, and then cause the memory of different manufacturers to have different transmission speed performance in the same server connection link environment, that is, different types of memory in the server may have the problem of reduced transmission speed in the current connection link environment, resulting in poor compatibility of the memory with the server link environment. Summary of the invention

[0003] The embodiments of the present application provide a method, device and system for controlling server link configuration, so as to at least solve the problem of poor compatibility of memory with server link environment in related technologies.

[0004] According to an embodiment of the present application, a method for controlling server link configuration is provided. Multiple types of memories, processors, and controllers are deployed in the server. The processor is connected to each type of memory through a bus link.

[0005] The controller sends a target configuration instruction to the processor, wherein the target configuration instruction is used to instruct the processor to configure a bus link between the processor and the target memory to be accessed using an initial parameter value to obtain an initial bus link, wherein the initial parameter value is a parameter value corresponding to the type of the target memory;

[0006] The controller obtains the current communication rate of the initial bus link reported by the processor;

[0007] When the current communication rate does not fall within the communication rate range, a target control mode for the processor is entered, wherein the target control mode is used to control the processor to adjust the initial parameter value to obtain a target bus link whose communication rate falls within the communication rate range.

[0008] Optionally, the entering a target control mode of the processor includes:

[0009] Filtering out a target sub-parameter to be modified from a plurality of sub-parameters, wherein the plurality of sub-parameters are configuration parameters of a plurality of dimensions required for configuring a bus link between the processor and the target memory;

[0010] Sending a first adjustment instruction to the processor according to the current communication rate and the communication rate range, wherein the first adjustment instruction is used to instruct the processor to adjust the initial parameter value corresponding to the target sub-parameter according to the parameter adjustment method indicated by the first adjustment instruction to obtain a reference bus link;

[0011] In a case where the reference bus link meets a communication rate condition, the reference bus link is determined as the target bus link.

[0012] Optionally, sending a first adjustment instruction to the processor according to the current communication rate and the communication rate range includes:

[0013] Acquire a target difference between the current communication rate and a reference communication rate in the communication rate range;

[0014] Filtering out a target adjustment value corresponding to the target difference value and the target sub-parameter from the difference values, sub-parameters and adjustment values ​​having a corresponding relationship;

[0015] The first adjustment instruction carrying the target adjustment value is sent to the processor, wherein the first adjustment instruction is used to instruct the processor to adjust the initial parameter value corresponding to the target sub-parameter in the initial bus link according to the target adjustment value to obtain the reference bus link.

[0016] Optionally, the step of selecting a target sub-parameter to be corrected from the plurality of sub-parameters includes:

[0017] Filter out the initial sub-parameters to be adjusted from the plurality of sub-parameters;

[0018] The target sub-parameters having a priority greater than or equal to the target priority are screened out from the initial sub-parameters according to the adjustment priorities corresponding to the sub-parameters.

[0019] Optionally, the step of selecting a target sub-parameter to be corrected from the plurality of sub-parameters includes:

[0020] Acquire a target difference between the current communication rate and a reference communication rate in the communication rate range;

[0021] The target sub-parameter corresponding to the target difference is determined from the difference and sub-parameter having a corresponding relationship.

[0022] Optionally, after sending a first adjustment instruction to the processor according to the current communication rate and the communication rate range, the method further includes:

[0023] The controller obtains the current target communication rate of the reference bus link reported by the processor;

[0024] Matching the reference target rate with the communication rate range;

[0025] In the case where it is determined that the target communication rate falls within the communication rate range, it is determined that the reference bus link satisfies the communication rate condition.

[0026] Optionally, after matching the target communication rate with the communication rate range, the method further includes:

[0027] In the case where it is determined that the target communication rate does not fall within the communication rate range, detecting the number of adjustments to the initial parameter value corresponding to the target sub-parameter in the initial bus link;

[0028] When the number of adjustment times is greater than or equal to the target number of adjustment times, searching for an initial sub-parameter in a state to be adjusted from the plurality of sub-parameters;

[0029] In a case where the initial sub-parameter does not exist in the plurality of sub-parameters, it is determined that the reference bus link satisfies the communication rate condition.

[0030] Optionally, before the controller sends the target configuration instruction to the processor, the method further includes:

[0031] Acquire target wiring information of the processor and the target storage in the server, wherein the target wiring information is used to indicate a cable connection status between the processor and the target storage;

[0032] The initial parameter value of the communication parameter required for configuring a bus link between the processor and the target memory is predicted according to the target type to which the target memory belongs and the target wiring information.

[0033] Optionally, predicting the initial parameter value required for configuring a bus link between the processor and the target memory according to the target type and the target wiring information includes:

[0034] The initial parameter value corresponding to the target type and the current target wiring information is screened out from the types, wiring information and parameter values ​​of the communication parameters that have a corresponding relationship.

[0035] Optionally, predicting the initial parameter value required for configuring a bus link between the processor and the target memory according to the target type and the target wiring information includes:

[0036] Filtering reference wiring information matching the target wiring information from a parameter configuration set, wherein the parameter configuration set records configuration conditions of parameter values ​​of the communication parameters of the target type of memory under wiring environments corresponding to different wiring information;

[0037] The initial parameter value is predicted according to the reference parameter value configured for the communication parameter by the processor and the memory of the target type under the reference wiring information recorded in the parameter configuration set.

[0038] Optionally, predicting the initial parameter value according to the reference parameter value configured for the communication parameter between the processor and the memory of the target type under the reference wiring information recorded in the parameter configuration set includes:

[0039] Obtain a candidate communication rate between the target type of memory recorded in the parameter configuration set and the processor using the reference parameter value in the reference wiring information;

[0040] matching the candidate communication rate with the communication rate range;

[0041] In a case where it is determined that the candidate communication rate falls within the communication rate range, the reference parameter value is determined as the initial parameter value.

[0042] Optionally, after matching the candidate communication rate with the communication rate range, the method further includes:

[0043] In a case where it is determined that the candidate communication rate does not fall within the communication rate range, obtaining a target difference between the candidate communication rate and a reference communication rate within the communication rate range;

[0044] Filtering out a target parameter adjustment value corresponding to the target difference value from the difference values ​​and parameter adjustment values ​​having a corresponding relationship;

[0045] The reference parameter value is adjusted according to the target parameter adjustment value to obtain the initial parameter value.

[0046] Optionally, the controller sends a target configuration instruction to the processor, including:

[0047] Sending a first configuration instruction to the processor, wherein the first configuration instruction is used to instruct the processor to set a link training state machine of the bus link to an enabled state, wherein the link training state machine is used to configure a link communication state of the bus link connected between the processor and the memory;

[0048] A second configuration instruction carrying the initial parameter value is sent to the processor, wherein the second configuration instruction is used to instruct the processor to control the link training state machine to configure the bus link between the processor and the target memory according to the initial parameter value to obtain the initial bus link, and the target configuration instruction includes the first configuration instruction and the second configuration instruction.

[0049] Optionally, the processor includes a plurality of sub-processors, each of the memories is connected to a corresponding sub-processor, the bus link includes a sub-link connecting each of the memories to the corresponding sub-processor, and the controller is connected to each of the sub-processors.

[0050] The sending a first configuration instruction to the processor includes:

[0051] Detecting a target sub-link to which the target storage device belongs;

[0052] Sending the first configuration instruction carrying the link identifier of the target sub-link to the target sub-processor corresponding to the target sub-link, wherein the first configuration instruction is used to instruct the target sub-processor to configure the target link training state machine corresponding to the target sub-link to be in an enabled state;

[0053] The sending of the second configuration carrying the initial parameter value to the processor includes:

[0054] The second configuration instruction carrying the link identifier of the target sub-link and the initial parameter value is sent to the target sub-processor, wherein the second configuration instruction is used to instruct the target sub-processor to control the target link training machine corresponding to the link identifier to configure the target sub-connection chain between the target sub-processor and the target memory according to the initial parameter value.

[0055] According to one embodiment of the present application, a control system for server link configuration is provided, comprising: a controller, a processor, and multiple types of memories, wherein the controller is connected to the processor, and the processor is connected to each type of the memories via a bus link.

[0056] The controller is used to send a target configuration instruction to the processor, wherein the target configuration instruction is used to instruct the processor to use an initial parameter value to configure the bus link between the processor and the target memory to be accessed to obtain an initial bus link, wherein the initial parameter value is a parameter value corresponding to the type of the target memory; obtain the current communication rate of the initial bus link reported by the processor; and enter a target control mode for the processor when the current communication rate does not fall within the communication rate range, wherein the target control mode is used to control the processor to adjust the initial parameter value to obtain a target communication bus with a communication rate within the communication rate range. Optionally, the processor includes a plurality of sub-processors, each of the memories is connected to a corresponding sub-processor, the bus link includes a sub-link connecting each of the memories to the corresponding sub-processor, and the controller is connected to each of the sub-processors.

[0057] The controller is used to detect the target sub-link to which the target memory belongs; send the first configuration instruction carrying the link identifier of the target sub-link to the target sub-processor corresponding to the target sub-link, wherein the first configuration instruction is used to instruct the target sub-processor to configure the target link training state machine corresponding to the target sub-link to be in an enabled state; send the second configuration instruction carrying the link identifier of the target sub-link and the initial parameter value to the target sub-processor, wherein the second configuration instruction is used to instruct the target sub-processor to control the target link training machine corresponding to the link identifier to configure the target sub-connection chain between the target sub-processor and the target memory according to the initial parameter value, and the target configuration instruction includes the first configuration instruction and the second configuration instruction.

[0058] According to another embodiment of the present application, a control device for server link configuration is provided, wherein multiple types of memories, processors, and controllers are deployed in the server, and the processor is connected to each type of memory through a bus link.

[0059] a sending module, configured to send a target configuration instruction to the processor through the controller, wherein the target configuration instruction is used to instruct the processor to configure a bus link between the processor and the target memory to be accessed using an initial parameter value to obtain an initial bus link, wherein the initial parameter value is a parameter value corresponding to the type of the target memory;

[0060] A first acquisition module, configured to acquire, through the controller, a current communication rate of the initial bus link reported by the processor;

[0061] A processing module is used to enter a target control mode for the processor when the current communication rate does not fall within the communication rate range, wherein the target control mode is used to control the processor to adjust the initial parameter value to obtain a target bus link whose communication rate falls within the communication rate range.

[0062] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0063] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0064] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0065] Through the present application, the controller first uses the initial parameter value corresponding to the target type of the target memory to control the processor to configure the bus link between the processor and the target memory, obtain the initial bus link, and obtain the current communication rate of the initial bus link reported by the processor, and when the current communication rate does not meet the communication rate requirement, enter the target control mode of the processor, and control the processor to adjust the initial parameter value according to the rate of the initial bus link, so as to dynamically adjust the communication parameters of the bus link according to the communication rate of the bus link between the processor and the memory without changing the hardware connection link, thereby ensuring that the communication rate between different types of memory and the processor in the server meets the communication rate requirement, thereby solving the problem of reduced transmission rate of different types of memory in the same connection link environment. Therefore, the problem of poor compatibility of the memory with the server link environment in the related art can be solved, and the effect of improving the compatibility of the memory with the server link environment can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 It is a hardware structure block diagram of a server device of a method for controlling server link configuration according to an embodiment of the present application;

[0067] Figure 2is a flow chart of a method for controlling server link configuration according to an embodiment of the present application;

[0068] Figure 3 is a schematic diagram of a connection structure of a control device for a server link configuration according to an embodiment of the present application;

[0069] Figure 4 is a parameter adjustment flow chart of a server link configuration according to an embodiment of the present application;

[0070] Figure 5 is a schematic diagram of configuring link parameters according to a controller in an embodiment of the present application;

[0071] Figure 6 A schematic diagram of a control system for a server link configuration according to an embodiment of the present application Figure 1 ;

[0072] Figure 7 A schematic diagram of a control system for a server link configuration according to an embodiment of the present application Figure 2 ;

[0073] Figure 8 It is a physical connection diagram of a BIOS adaptive NVME hard disk rate device according to an embodiment of the present application;

[0074] Fig. 9 It is a flow chart of a method for BIOS adaptive NVME hard disk speed according to an embodiment of the present application;

[0075] Fig.10 It is a swim lane diagram of a method for BIOS adaptive NVME hard disk rate according to an embodiment of the present application;

[0076] Fig.11 It is a structural block diagram of a control device for server link configuration according to an embodiment of the present application. DETAILED DESCRIPTION

[0077] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0078] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0079] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 1 is a hardware structure block diagram of a server device of a method for controlling a server link configuration according to an embodiment of the present application. Figure 1As shown, the server device may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned server device may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0080] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as a computer program corresponding to a control method for a server link configuration in an embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0081] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0082] In this embodiment, a method for controlling server link configuration is provided. Figure 2 is a flow chart of a method for controlling a server link configuration according to an embodiment of the present application. Multiple types of memories, processors, and controllers are deployed in the server. The processor is connected to each type of memory through a bus link, such as Figure 2 As shown, the process includes the following steps:

[0083] Step S202, the controller sends a target configuration instruction to the processor, wherein the target configuration instruction is used to instruct the processor to configure a bus link between the target memory to be accessed using an initial parameter value to obtain an initial bus link, wherein the initial parameter value is a parameter value corresponding to the type of the target memory;

[0084] Step S204, the controller obtains the current communication rate of the initial bus link reported by the processor;

[0085] Step S206, when the current communication rate does not fall within the communication rate range, enter the target control mode of the processor, wherein the target control mode is used to control the processor to adjust the initial parameter value to obtain a target bus link whose communication rate falls within the communication rate range.

[0086] Through the above steps, the controller first uses the initial parameter value corresponding to the target type of the target memory to control the processor to configure the bus link between the processor and the target memory, obtain the initial bus link, and obtain the current communication rate of the initial bus link reported by the processor, and when the current communication rate does not meet the communication rate requirement, enter the target control mode of the processor, and control the processor to adjust the initial parameter value according to the rate of the initial bus link, so as to dynamically adjust the communication parameters of the bus link according to the communication rate of the bus link between the processor and the memory without changing the hardware connection link, thereby ensuring that the communication rate between different types of memory and the processor in the server meets the communication rate requirement, thereby solving the problem of reduced transmission rate of different types of memory in the same connection link environment. Therefore, the problem of poor compatibility of memory with the server link environment in the related art can be solved, and the effect of improving the compatibility of memory with the server link environment can be achieved.

[0087] Optionally, in an embodiment of the present application, the control method of the above-mentioned server link configuration is applied to a controller deployed in the server, and the controller controls the processor to dynamically adjust the link parameters of the bus link between the target memory to be communicated with the processor through interaction with the processor, so that the communication rate of the bus link between the processor and the target memory falls within the communication rate range, thereby meeting the communication rate requirements of the communication bus.

[0088] Optionally, in the embodiment of the present application, Figure 3 is a schematic diagram of a connection structure of a control device for a server link configuration according to an embodiment of the present application, such as Figure 3As shown, a controller, a processor and multiple different types of memories are deployed in the server, wherein the controller is connected to the processor, and the processor is connected to multiple different types of memories through a bus link. After the server is powered on, the controller can control the processor to configure the communication parameters of the bus link between the processor and the memory.

[0089] Optionally, in an embodiment of the present application, the controller is used to manage the communication status between the processor and the memory, that is, when the server starts to power on, the controller controls the processor, and / or configures the communication parameters between the memory and the other end, so that the memory and the processor can communicate according to the established communication rate requirements. The controller can be but is not limited to BIOS (Basic Input / Output System), UEFI (Unified Extensible Firmware Interface), etc., or the controller can also be an operating device running a system such as BIOS or UEFI, and this solution does not limit this.

[0090] Optionally, in an embodiment of the present application, the controller and the processor can exchange information through a communication protocol or interface standard, such as LCP (Low Cost Package), SPI (Serial Peripheral Interface), QSPI (Quad SPI), etc., which is not limited in this solution.

[0091] Optionally, in an embodiment of the present application, the memory is a device for storing data in the server, and the memory may include but is not limited to data storage media such as hard disks, disks, disk arrays, memory sticks, etc., and this solution does not limit this.

[0092] Optionally, in an embodiment of the present application, the processor in the server is connected to various types of memories through a connection link, for example, connected to the signal port of the controller through a connection cable, and through the high-speed signal routing of the motherboard, providing an external interface of the motherboard, and the external interface is connected to the backplane of the NVME hard disk (memory) through a slimline cable or a GenZ cable. In order to increase the communication rate between the processor and the memory, the connection link between the processor and the memory can be configured to support a target communication protocol for high-speed signal transmission, such as: PCI (Peripheral Component Interconnect, peripheral component interconnect standard) protocol.

[0093] Optionally, in an embodiment of the present application, different types of memories have different firmware configurations, so different types of memories have different data transmission capabilities. When communicating with a processor, different types of memories have different requirements for the link environment of the connection link in order to ensure the quality of data transmission. For example, when the overall link between the processor and the memory is long, but the design meets the SI insertion loss requirements, there may be multiple memories in which the communication rate between some memories and the processor meets the communication rate requirements, and the communication rate between some memories and the processor cannot meet the communication rate requirements. In order to improve the configuration efficiency of the bus link between the processor and the target memory, the corresponding initial parameter value can be configured for the target memory in advance according to the memory type, so that the initial parameter value can be ensured to be as close as possible to the parameter value required between the memory and the processor to meet the communication rate requirements, or a communication parameter parameter value adapted to the current link environment can be generated for the target memory according to the target type of the target memory and the connection link environment parameters between the memory and the processor in the server. In this embodiment, the method of generating initial parameter values ​​for the target memory can be through a pre-trained target prediction model, that is, link environment parameters and target type input values ​​are input into the target prediction model, wherein the link environment parameters are used to indicate the connection status of the connection link between the target memory and the processor (which may include but is not limited to the length of the connection cable, the connection method, etc.), and the target prediction model records the change relationship between the parameter values ​​of the link environment parameters, the memory type and the communication parameters, and then the parameter value output by the target prediction model is determined as the initial parameter value.

[0094] Optionally, in an embodiment of the present application, the processor is used to access the memory and configure the communication parameters of the bus link between the processor and the memory. The processor may be, but is not limited to, a CPU (Central Processing Unit), an MCU (Microcontroller Unit), etc., and this solution does not limit this.

[0095] In the embodiment provided in the above step S202, the communication parameters are parameters that characterize the transmission performance of the signal between the processor and the target memory. The communication parameters may include but are not limited to Preset (PCI link equalization setting value), Precursor (signal waveform pre-parameter), Postcursor (signal waveform post-parameter), etc., and this solution does not limit this.

[0096] Optionally, in an embodiment of the present application, the communication parameter is a parameter used to indicate the transmission performance of a signal between the processor and the target memory.

[0097] Optionally, in an embodiment of the present application, after the server is powered on, the controller detects a target memory to be accessed by the processor, and stores a target configuration instruction corresponding to the target processor and sends it to the processor.

[0098] Optionally, in an embodiment of the present application, an initial parameter value will be pre-configured for the communication parameters of the target storage according to the storage type of the target storage. This may be a fixed value set uniformly for all storages based on human experience, or different initial parameter values ​​may be set for different storages based on the type of storage and the connection status of the storage in the server link. This solution does not limit this.

[0099] In the embodiment provided in the above step S204, the communication rate range is the rate range that the initial bus link is expected to achieve. For example, the lowest value of the communication rate range can be set to PCIe Gen4 (the fourth generation version of the PCIe standard). The transmission rate of PCIe Gen4 is 16GT / s (GigaTransfers per second), that is, the communication rate range can be greater than or equal to 16GT / s, and this solution does not limit this.

[0100] Optionally, in the embodiment of the present application, the controller may also actively monitor the communication rate of the initial bus link. Monitoring the current communication rate of the initial bus link may be performed by using a special bandwidth test tool to directly measure the amount of data transmitted by the initial bus link in a specific time period, thereby calculating the communication rate; or by using a logic analyzer to connect it to the bus line, directly capturing and analyzing the signal waveform and data transmission on the bus, thereby accurately measuring the communication rate of the bus link, which is not limited in the present solution.

[0101] In the embodiment provided in the above step S206, in order to ensure that the bus link between the processor and the target memory meets the communication rate requirements, when it is monitored that the current communication rate of the initial bus link does not fall within the communication rate range, the initial parameter value of the initial bus link can be adjusted according to the current communication rate and the communication rate range, so that the communication rate of the adjusted target bus link is optimal. Therefore, in order to obtain the target communication bus, the initial parameter value of the communication parameter can be adjusted for multiple rounds. In the embodiment of the present application, the communication parameter can include but is not limited to multiple sub-parameters, and the multiple sub-parameters are used to characterize the transmission capacity of the signal output by the processor and the memory on the bus link from multiple dimensions. Therefore, when adjusting the parameter value, multiple sub-parameters can be adjusted simultaneously in each round, and the multiple sub-parameters can be adjusted again according to the communication rate of the adjusted bus link. The parameter value of the parameter is adjusted for the next round; or multiple rounds of adjustment can be performed on each sub-parameter, that is, the target sub-parameter to be adjusted is screened according to the adjustment priority of the sub-parameter, and only the parameter value of the target sub-parameter is adjusted in each adjustment round, and multiple rounds of parameter adjustment are repeated on the parameter value of the target sub-parameter. For example, the communication rate range is above the Gen4 rate (that is, greater than or equal to 16GT / s), and the communication rate on the currently monitored bus is Gen3 (that is, 8GT / s). At this time, in order to increase the communication rate of the bus from Gen3 to Gen4, it is necessary to adjust the initial parameter value of the communication parameter configured on the initial bus link. The multiple sub-parameters in the communication parameters configured on the initial bus link can be prioritized first, and a parameter with the greatest impact on the current link training phase is selected from the multiple sub-parameters for adjustment.

[0102] Optionally, in the embodiment of the present application, the communication rate range is used to indicate the communication rate requirement for the bus link between the processor and the memory.

[0103] For example, Figure 4 is a parameter adjustment flow chart of a server link configuration according to an embodiment of the present application, such as Figure 4As shown, after the BIOS (i.e., the controller in this application) sets the initial parameter values ​​for the communication parameters of the PCI link (i.e., the bus link in this application) where the NVME hard disk (i.e., the memory in this application) is located, the Re-Train function of the PCI link where the NVME hard disk is located will be turned on, and then the NVME hard disk and the PCI link where it is located will perform the first PCI Training; after the Training of the NVME hard disk is completed, it is detected whether the communication rate of the PCI link is at the Gen4 rate; when the communication rate of the PCI link does not meet the Gen4 rate, the BIOS sets the TX and RX parameters of the Preset of the NVME hard disk and the PCI link where it is located to 7 and performs the second PCI Training action; after the second Training of the NVME hard disk is completed, it is detected whether the communication rate of the PCI link is at the Gen4 rate; when the communication rate of the PCI link does not meet the Gen4 rate, the BIOS sets the TX Precursor and Postcursor parameters of the PH3 of the PCI link where the NVME hard disk is located to 0.13 respectively and performs the third PCI Training action, thereby cyclically adjusting the communication parameters of the PCI link where the NVME hard disk is located in each training stage.

[0104] As an optional embodiment, the entering the target control mode of the processor includes:

[0105] Filtering out a target sub-parameter to be modified from a plurality of sub-parameters, wherein the plurality of sub-parameters are configuration parameters of a plurality of dimensions required for configuring a bus link between the processor and the target memory;

[0106] Sending a first adjustment instruction to the processor according to the current communication rate and the communication rate range, wherein the first adjustment instruction is used to instruct the processor to adjust the initial parameter value corresponding to the target sub-parameter according to the parameter adjustment method indicated by the first adjustment instruction to obtain a reference bus link;

[0107] In a case where the reference bus link meets a communication rate condition, the reference bus link is determined as the target bus link.

[0108] Optionally, in an embodiment of the present application, multiple sub-parameters are parameters that affect the communication rate of the bus link between the processor and the target memory from various dimensions. The multiple sub-parameters may include but are not limited to Preset (PCI link equalization setting value), Precursor (signal waveform pre-parameter), Postcursor (signal waveform post-parameter), etc., and this solution does not limit this.

[0109] Optionally, in an embodiment of the present application, the target sub-parameter to be corrected is selected from multiple sub-parameters based on experience and can be manually selected; or the degree of influence of different sub-parameters on the link communication rate in each link training stage can be detected first, and the degree of influence can be detected by using historical operation data to perform control variable testing, by changing the value of a single sub-parameter in each link training stage, observing and recording the changes in the bus link communication rate, thereby evaluating the sensitivity of each sub-parameter, and then prioritizing different sub-parameters according to the sensitivity of the sub-parameters, and then selecting the sub-parameter with the highest priority corresponding to the current link training stage from the corresponding link training stage and sub-parameter priority sequence for adjustment.

[0110] Through the above steps, according to the influence of the sub-parameters on the link communication rate in each link training stage, the target sub-parameter to be corrected is selected from multiple sub-parameters and adjusted, so that the communication parameter value of the bus link configuration can be adjusted more accurately, thereby improving the optimization efficiency of the bus link communication rate.

[0111] As an optional embodiment, sending a first adjustment instruction to the processor according to the current communication rate and the communication rate range includes:

[0112] Acquire a target difference between the current communication rate and a reference communication rate in the communication rate range;

[0113] Filtering out a target adjustment value corresponding to the target difference value and the target sub-parameter from the difference values, sub-parameters and adjustment values ​​having a corresponding relationship;

[0114] The first adjustment instruction carrying the target adjustment value is sent to the processor, wherein the first adjustment instruction is used to instruct the processor to adjust the initial parameter value corresponding to the target sub-parameter in the initial bus link according to the target adjustment value to obtain the reference bus link.

[0115] Optionally, in an embodiment of the present application, the reference communication rate is a rate value used to characterize the relationship between the current communication rate and the communication rate range. The reference communication rate in the communication rate range can be the minimum value corresponding to the communication rate range, or it can be the average value within the communication rate range. This scheme does not limit this.

[0116] Optionally, in an embodiment of the present application, when the current communication rate is very close to the reference communication rate, it means that the parameter value of the sub-parameter is relatively close to the ideal value at this time, so the adjustment range of the sub-parameter is small; when the current communication rate is far away from the reference communication rate, it means that the parameter value of the sub-parameter is far away from the ideal value at this time, so the adjustment range of the sub-parameter will also increase accordingly. Therefore, the adjustment amount of the initial parameter value of the target sub-parameter can be determined based on the difference between the current communication rate and the reference communication rate in the communication rate range, and a mapping table containing the corresponding relationship between the difference, sub-parameter and adjustment value can be pre-configured, and then the target difference and target sub-parameter are used as indexes to query the corresponding adjustment value, and then the initial parameter value corresponding to the target sub-parameter is adjusted according to the queried adjustment value to obtain the reference bus link.

[0117] Through the above steps, by determining the adjustment amount of the initial parameter value of the target sub-parameter according to the difference between the current communication rate and the reference communication rate in the communication rate range, the parameter value of the target sub-parameter can be adjusted more accurately.

[0118] As an optional embodiment, the step of selecting the target sub-parameter to be corrected from the multiple sub-parameters includes:

[0119] Filter out the initial sub-parameters to be adjusted from the plurality of sub-parameters;

[0120] The target sub-parameters having a priority greater than or equal to the target priority are screened out from the initial sub-parameters according to the adjustment priorities corresponding to the sub-parameters.

[0121] Optionally, in an embodiment of the present application, the adjustment priority corresponding to the sub-parameter can be manually set based on experience, or different sub-parameter priority sequences can be configured for different memories based on the type of memory. For example, a mapping table containing memory types and sub-parameter priority sequences can be created, and the corresponding sub-parameter priority sequence can be queried according to the memory type in the current bus link, and then the target sub-parameter that is greater than or equal to the target priority can be filtered out from the initial sub-parameters according to the priority sequence.

[0122] As an optional embodiment, the step of selecting the target sub-parameter to be corrected from the multiple sub-parameters includes:

[0123] Acquire a target difference between the current communication rate and a reference communication rate in the communication rate range;

[0124] The target sub-parameter corresponding to the target difference is determined from the difference and sub-parameter having a corresponding relationship.

[0125] Optionally, in an embodiment of the present application, since different sub-parameters have different degrees of influence on the link communication rate, changes in the parameter values ​​of some sub-parameters will have a greater impact on the current communication rate. Therefore, the target sub-parameter to be corrected can be selected from multiple sub-parameters and determined based on the difference between the current communication rate and the reference communication rate in the communication rate range. A mapping table containing the correspondence between the difference and the sub-parameters can be pre-configured, and then the target difference is used as an index to query the corresponding sub-parameter, and the queried sub-parameter is determined as the target sub-parameter.

[0126] Through the above steps, the target sub-parameter to be corrected is determined according to the difference between the current communication rate and the reference communication rate in the communication rate range, so that the target sub-parameter to be adjusted first can be determined more accurately from multiple sub-parameters, thereby improving the efficiency of screening the target sub-parameters.

[0127] As an optional embodiment, after sending the first adjustment instruction to the processor according to the current communication rate and the communication rate range, the method further includes:

[0128] The controller obtains the current target communication rate of the reference bus link reported by the processor;

[0129] Matching the target communication rate with the communication rate range;

[0130] In the case where it is determined that the target communication rate falls within the communication rate range, it is determined that the reference bus link satisfies the communication rate condition.

[0131] Optionally, in an embodiment of the present application, after the initial bus link is updated using the adjusted initial parameter value to obtain a reference bus link, in order to verify the adjustment effect of the target sub-parameter, it is necessary to further detect whether the current target communication rate of the adjusted reference bus link meets the communication rate range. If it is detected that the target communication rate falls within the communication rate range, it is determined that the reference bus link meets the communication rate condition; if it is detected that the target communication rate does not fall within the communication rate range, the target sub-parameter is adjusted again.

[0132] Through the above steps, by matching the current target communication rate of the reference bus link with the communication rate range, and then determining whether the reference bus link meets the communication rate condition, the effect of adjusting the target sub-parameters in the above steps can be verified.

[0133] As an optional embodiment, after matching the target communication rate with the communication rate range, the method further includes:

[0134] In the case where it is determined that the target communication rate does not fall within the communication rate range, detecting the number of adjustments to the initial parameter value corresponding to the target sub-parameter in the initial bus link;

[0135] When the number of adjustment times is greater than or equal to the target number of adjustment times, searching for an initial sub-parameter in a state to be adjusted from the plurality of sub-parameters;

[0136] In a case where the initial sub-parameter does not exist in the plurality of sub-parameters, it is determined that the reference bus link satisfies the communication rate condition.

[0137] Optionally, in an embodiment of the present application, a counter may be configured in the bus link to record the number of times a specific target sub-parameter is adjusted. Each time a parameter adjustment is performed, the counter is updated. In order to improve the adjustment efficiency of the target sub-parameter value, a target number of times threshold is set for the number of times the initial parameter value corresponding to the target sub-parameter is adjusted, that is, there is a maximum number of times the target sub-parameter can be adjusted. When it is detected that the target communication rate does not fall within the communication rate range, the value of the counter corresponding to the current target sub-parameter can be read. If the read number value is less than the target number of times threshold, the target sub-parameter continues to be adjusted; if the read number value is greater than or equal to the target number of times threshold, the initial sub-parameter in the state to be adjusted is searched from multiple sub-parameters, and the initial sub-parameter in the state to be adjusted is adjusted. If the initial sub-parameter to be adjusted is not found in all adjustable sub-parameters, this indicates that all sub-parameters within the optional range have been optimized and adjusted. In this case, even if the target communication rate has not yet fully reached the communication rate range, the default system accepts the current communication rate based on certain policies (such as business continuity requirements, resource constraints, etc.) and determines that the reference bus link has met the communication rate conditions.

[0138] Through the above steps, when it is detected that the target communication rate does not fall within the communication rate range, by limiting the number of adjustments of the target sub-parameters and traversing the sub-parameters to be adjusted, all sub-parameters configured on the bus link can be comprehensively optimized and adjusted while maintaining the efficiency of adjusting the target sub-parameters, thereby achieving maximum optimization of the bus link communication rate.

[0139] As an optional embodiment, before the controller sends the target configuration instruction to the processor, the method further includes:

[0140] Acquire target wiring information of the processor and the target storage in the server, wherein the target wiring information is used to indicate a cable connection status between the processor and the target storage;

[0141] The initial parameter value of the communication parameter required for configuring a bus link between the processor and the target memory is predicted according to the target type to which the target memory belongs and the target wiring information.

[0142] Optionally, in an embodiment of the present application, the target wiring information may include, but is not limited to, the cable type, cable length, connection method, etc. of the cable connected between the target memory and the processor, and this solution does not limit this.

[0143] Optionally, in an embodiment of the present application, the cable connection conditions between different types of memories and processors may be different, and the cable connection conditions between the memories and processors may also affect the communication rate of the bus link. For example, some manufacturers' hard disk slot backplane wiring has a longer overall link, but the design meets the SI insertion loss requirements, and there have been no problems when adapting to hard disks from other manufacturers. When adapting to this model of NVME hard disk, there are compatibility issues, which causes the current long link signal to attenuate and cause the signal quality to weaken. Therefore, the initial parameter value can also be predicted according to the cable connection between the processor and the target memory, which can be: query the server BIOS / UEFI settings, query the real-time connection status between the processor and the target memory through the server management interface (such as IPMI, BMC, etc.), and obtain the target wiring information, wherein the target wiring information records in detail the physical connection path between the processor (such as CPU) and the target memory (such as DDR4 memory stick, SSD hard disk, etc.), which can include but is not limited to interface type (such as PCIe, SATA, DIMM slot, etc.), cable type (such as SAS cable, HDMI cable, etc.), connection port number, cable connection status (such as cable length, whether it passes through a relay or converter, etc.), etc., and then build a machine learning model based on historical operation data, memory type and target wiring information. The model is used to learn the relationship between communication parameters and performance of the bus link between the processor and the target memory under different wiring configurations, and then predict the optimal initial parameter value according to the model.

[0144] Through the above steps, by predicting the initial parameter value according to the cable connection between the processor and the target memory, the predicted initial parameter value can more accurately match the actual condition of the current cable connection, thereby improving the optimization efficiency of the link communication parameters.

[0145] As an optional embodiment, predicting the initial parameter value required for configuring a bus link between the processor and the target memory according to the target type and the target wiring information includes:

[0146] The initial parameter value corresponding to the target type and the current target wiring information is screened out from the types, wiring information and parameter values ​​of the communication parameters that have a corresponding relationship.

[0147] Optionally, in an embodiment of the present application, the initial parameter values ​​required to configure the bus link between the processor and the target memory are predicted based on the target type and target wiring information. A mapping table containing the correspondence between the type, wiring information, and parameter values ​​of the communication parameters can be constructed, and then the target type and target wiring information are used as indexes to query the initial parameter values ​​corresponding to the target type and the current target wiring information.

[0148] Through the above steps, the accuracy of the prediction of the initial parameter value is improved by predicting the initial parameter value from the perspective of the wiring situation between the memory and the processor.

[0149] As an optional embodiment, predicting the initial parameter value required for configuring a bus link between the processor and the target memory according to the target type and the target wiring information includes:

[0150] Filtering reference wiring information matching the target wiring information from a parameter configuration set, wherein the parameter configuration set records configuration conditions of parameter values ​​of the communication parameters of the target type of memory under wiring environments corresponding to different wiring information;

[0151] The initial parameter value is predicted according to the reference parameter value configured for the communication parameter by the processor and the memory of the target type under the reference wiring information recorded in the parameter configuration set.

[0152] Optionally, in an embodiment of the present application, each type of memory includes a parameter configuration set, which is used to record the communication parameter configuration status of the current type of memory and the processor under different wiring conditions. The parameter configuration set can be a database or mapping table constructed through historical data or experimental data that contains the corresponding relationship between the wiring status between the memory and the processor, communication parameter values, and communication rates. This solution does not limit this.

[0153] Optionally, in an embodiment of the present application, predicting the initial parameter values ​​required for configuring the bus link between the processor and the target memory based on the target type and the target wiring information can be: querying the parameter configuration set to which the target memory belongs based on the target type, decomposing the target wiring information into different sub-attributes, such as cable type, length, interface model, etc., traversing the parameter configuration set according to each sub-attribute of the target wiring information, finding the reference wiring information that is closest to or completely matches the target wiring information, and then predicting the initial parameter values ​​based on the reference parameter values ​​configured for the communication parameters under the reference wiring information.

[0154] Through the above steps, by screening out reference wiring information that matches the target wiring information from the parameter configuration set, and then predicting the initial parameter value based on the reference wiring information, an automated prediction and configuration process can be achieved, reducing the need for manual intervention. The system can quickly determine the appropriate initial parameter value based on the cable connection situation, thereby improving the prediction efficiency of the initial parameter value.

[0155] As an optional embodiment, predicting the initial parameter value according to the reference parameter value configured for the communication parameter between the processor and the memory of the target type recorded in the parameter configuration set under the reference wiring information includes:

[0156] Obtain a candidate communication rate between the target type of memory recorded in the parameter configuration set and the processor using the reference parameter value in the reference wiring information;

[0157] matching the candidate communication rate with the communication rate range;

[0158] In a case where it is determined that the candidate communication rate falls within the communication rate range, the reference parameter value is determined as the initial parameter value.

[0159] Optionally, in an embodiment of the present application, after querying the reference wiring information that matches the target wiring information from the parameter configuration set, it is necessary to further verify whether the communication parameter value corresponding to the reference wiring information used by the target memory can meet the current communication rate requirement. Therefore, the parameter configuration set can be further used to query the candidate communication rate that the target memory can achieve when communicating with the processor using the reference parameter value under the reference wiring information, and then match the queried candidate communication rate with the communication rate range required by the system. If the matching result is that the candidate communication rate falls within the communication rate range, it means that under the current wiring information and target memory type, the use of these reference parameter values ​​can ensure that the communication rate meets the system requirements. At this time, the reference parameter value can be determined as the initial parameter value.

[0160] Through the above steps, by matching the candidate communication rate and communication rate range between the target type of memory using the reference parameter value in the reference wiring information and the processor, it is possible to further verify whether the communication parameter value corresponding to the reference wiring information used by the target memory can meet the current communication rate requirement, thereby improving the accuracy of the initial parameter value prediction.

[0161] As an optional embodiment, after matching the candidate communication rate with the communication rate range, the method further includes:

[0162] In a case where it is determined that the candidate communication rate does not fall within the communication rate range, obtaining a target difference between the candidate communication rate and a reference communication rate within the communication rate range;

[0163] Filtering out a target parameter adjustment value corresponding to the target difference value from the difference values ​​and parameter adjustment values ​​having a corresponding relationship;

[0164] The reference parameter value is adjusted according to the target parameter adjustment value to obtain the initial parameter value.

[0165] Optionally, in an embodiment of the present application, after matching the candidate communication rate with the communication rate range, if the matching result is that the candidate communication rate does not fall within the communication rate range, it means that the communication parameter value corresponding to the reference wiring information used by the target memory cannot meet the current communication rate requirement. At this time, the reference parameter value needs to be adjusted, which can be: calculating the target difference between the candidate communication rate and the reference communication rate within the communication rate range, wherein the reference communication rate can be the minimum value corresponding to the communication rate range, or the average value within the communication rate range, and this scheme does not limit this; using the target difference as an index from a mapping table containing the correspondence between the difference and the parameter adjustment value, querying the corresponding target parameter adjustment value; using the queried target parameter adjustment value to adjust the reference parameter value to obtain the initial parameter value.

[0166] Through the above steps, when it is determined that the candidate communication rate does not fall within the communication rate range, the reference communication value is adjusted according to the difference between the candidate communication rate and the reference communication rate to obtain the initial parameter value, which can make the initial parameter value more accurately adjusted, thereby improving the prediction accuracy of the initial parameter value.

[0167] As an optional embodiment, the controller sends a target configuration instruction to the processor, including:

[0168] Sending a first configuration instruction to the processor, wherein the first configuration instruction is used to instruct the processor to set a link training state machine of the bus link to an enabled state, wherein the link training state machine is used to configure a link communication state of the bus link connected between the processor and the memory;

[0169] A second configuration instruction carrying the initial parameter value is sent to the processor, wherein the second configuration instruction is used to instruct the processor to control the link training state machine to configure the bus link between the processor and the target memory according to the initial parameter value to obtain the initial bus link, and the target configuration instruction includes the first configuration instruction and the second configuration instruction.

[0170] Optionally, in an embodiment of the present application, the link training state machine of the bus link is set to an enabled state, and the controller may send an enable signal to the link training state machine through an interface between the controller and the link training state machine, wherein the enable signal is a signal for controlling the start of the bus link connected between the processor and the memory.

[0171] As an optional embodiment, the processor includes a plurality of sub-processors, each of the memories is connected to a corresponding sub-processor, the bus link includes a sub-link connecting each of the memories to the corresponding sub-processor, and the controller is connected to each of the sub-processors.

[0172] The sending a first configuration instruction to the processor includes:

[0173] Detecting a target sub-link to which the target storage device belongs;

[0174] Sending the first configuration instruction carrying the link identifier of the target sub-link to the target sub-processor corresponding to the target sub-link, wherein the first configuration instruction is used to instruct the target sub-processor to configure the target link training state machine corresponding to the target sub-link to be in an enabled state;

[0175] The sending of the second configuration carrying the initial parameter value to the processor includes:

[0176] The second configuration instruction carrying the link identifier of the target sub-link and the initial parameter value is sent to the target sub-processor, wherein the second configuration instruction is used to instruct the target sub-processor to control the target link training machine corresponding to the link identifier to configure the target sub-connection chain between the target sub-processor and the target memory according to the initial parameter value.

[0177] Optionally, in the embodiment of the present application, Figure 5 is a schematic diagram of configuring link parameters according to a controller in an embodiment of the present application, such as Figure 5 As shown, the controller sends a target instruction carrying an initial parameter value to the target link training state machine, and then after receiving the target instruction, the target link training state machine configures the communication parameters of the target sub-link between the target memory and the target sub-processor according to the initial parameter value carried by the target instruction.

[0178] According to one embodiment of the present application, a control system for server link configuration is provided, comprising: a controller, a processor, and multiple types of memories, wherein the controller is connected to the processor, and the processor is connected to each type of the memories via a bus link.

[0179] The controller is used to send a target configuration instruction to the processor, wherein the target configuration instruction is used to instruct the processor to use an initial parameter value to configure a bus link between the processor and a target memory to be accessed to obtain an initial bus link, wherein the initial parameter value is a parameter value corresponding to the type of the target memory; obtain a current communication rate of the initial bus link reported by the processor; and enter a target control mode for the processor when the current communication rate does not fall within a communication rate range, wherein the target control mode is used to control the processor to adjust the initial parameter value to obtain a target communication bus whose communication rate falls within the communication rate range.

[0180] Through the above content, the controller first uses the initial parameter value corresponding to the target type of the target memory to control the processor to configure the bus link between the processor and the target memory, obtain the initial bus link, and obtain the current communication rate of the initial bus link reported by the processor, and when the current communication rate does not meet the communication rate requirement, enter the target control mode of the processor, and control the processor to adjust the initial parameter value according to the rate of the initial bus link, so as to dynamically adjust the communication parameters of the bus link according to the communication rate of the bus link between the processor and the memory without changing the hardware connection link, thereby ensuring that the communication rate between different types of memory and the processor in the server meets the communication rate requirement, thereby solving the problem of reduced transmission rate of different types of memory in the same connection link environment. Therefore, the problem of poor compatibility of memory with the server link environment in the related technology can be solved, and the effect of improving the compatibility of memory with the server link environment can be achieved.

[0181] Optionally, in the embodiment of the present application, Figure 6 A schematic diagram of a control system for a server link configuration according to an embodiment of the present application Figure 1 ,like Figure 6 As shown, a controller, a processor and multiple different types of memories are deployed in the server, wherein the controller is connected to the processor, and the processor is connected to multiple different types of memories through a bus link. When the server is powered on and started, if there is a target memory to be accessed by the processor in the memory, the controller will use the initial parameter values ​​of the communication parameters corresponding to the target type to which the target memory belongs to configure the bus link between the processor and the target memory to obtain an initial bus link.

[0182] As an optional embodiment, the processor includes a plurality of sub-processors, each of the memories is connected to a corresponding sub-processor, the bus link includes a sub-link connecting each of the memories to the corresponding sub-processor, and the controller is connected to each of the sub-processors.

[0183] The controller is used to detect the target sub-link to which the target memory belongs; send the first configuration instruction carrying the link identifier of the target sub-link to the target sub-processor corresponding to the target sub-link, wherein the first configuration instruction is used to instruct the target sub-processor to configure the target link training state machine corresponding to the target sub-link to be in an enabled state; send the second configuration instruction carrying the link identifier of the target sub-link and the initial parameter value to the target sub-processor, wherein the second configuration instruction is used to instruct the target sub-processor to control the target link training machine corresponding to the link identifier to configure the target sub-connection chain between the target sub-processor and the target memory according to the initial parameter value, and the target configuration instruction includes the first configuration instruction and the second configuration instruction.

[0184] Optionally, in the embodiment of the present application, Figure 7 A schematic diagram of a control system for a server link configuration according to an embodiment of the present application Figure 2 ,like Figure 7 As shown, a controller, a processor, and multiple different types of memories are deployed in the server, wherein the processor includes multiple sub-processors (such as Figure 7 Processor 1, processor 2 in the figure), each memory is connected to a sub-processor (such as Figure 7 The memories 1-4 are connected to the processor 1, and the memories 5-8 are connected to the processor 2), the link between each memory and the corresponding sub-processor is a sub-link in the bus link, and the controller is connected to each sub-processor.

[0185] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0186] As an optional implementation, the present application also provides a method for BIOS adaptive NVME hard disk speed, the core idea of ​​which is: the PCI link goes directly out from the CPU port, passes through the PCI link high-speed signal routing of the motherboard, provides the motherboard with an external interface, and the external interface is connected to the backplane of the NVME hard disk through a slimline cable or a GenZ cable. The NVME hard disk backplane is physically connected to the NVME hard disk actually used. When the NVME hard disk slows down, the above components may have problems. No matter which component has a problem, the core is the root cause of the signal attenuation problem. How to solve the problem of NVME hard disk maintaining the rate of Gen4 and 16GT / S while keeping the hardware link unchanged is the core key point. Through the analysis of the PCI link data captured by the protocol analyzer, the server side failed to successfully receive the TS1 sequence sent by the NVME disk side Tx in the phase 1 stage, and the signal quality of the NVME disk side Tx and the server side Rx was relatively poor. At the same time, the overall link of the wiring of the slot backplane is relatively long, but the design meets the SI insertion loss requirements, and there have been no problems when adapting to hard disks from other manufacturers. When adapting to this type of NVME hard disk, there is a compatibility problem, which causes the current long link signal to attenuate and weaken the signal quality. The server-side request for the NVME disk-side preset link in phase0 / 1 does not fully meet the negotiation standard, resulting in a probability that the server host and the NVME hard disk PCI link establishment timeout will result in negotiation to gen3, that is, 8GT / S rate. For this problem, we verified the negotiation speed drop problem by using the preset value used when the server-side BIOS locked phase1. The speed drop phenomenon still occurred during the test; after the BIOS failed to lock the preset value in phase1, when the PCIe speed drop occurred, the server-side host initiated the retrain function. After testing and verification, the speed drop phenomenon still occurred; finally, by debugging the Preset parameter value of the PCIe negotiation process on the BIOS side and turning on the Retrain function on the BIOS side, when the PCI link negotiation of the NVME hard disk failed, that is, it was reduced from Gen4 to Gen3, the server-side initiated the PCI link protocol again. At this time, it was verified that the NVME hard disk speed drop problem was solved. However, some manufacturers' NVME hard drives still fail even if the BIOS is set with the above settings. At this time, we need to continue to set the TX signal setting value of the PH3 stage of the PCI link to a fixed value to solve the speed reduction problem of other NVME hard drive manufacturers.

[0187] Figure 8 : is a physical connection diagram of a BIOS adaptive NVME hard disk speed device according to an embodiment of the present application, such as Figure 8As shown in the figure, the NVME hard disk on the BIOS side is physically connected to the PCI link on the CPU side. When the BIOS starts the PCI initialization Training phase, it will train all PCI devices. When the PCI device slows down, the BIOS will re-train the PCI device connected to the current PCI link by default to repair it. After the re-training is completed, regardless of whether the PCI device of the current PCI link has been repaired, that is, the maximum supported rate has been restored, it will be used at the current training rate. The current training result includes the maximum supported rate of the device or the maximum rate that can be supported after the training fails. At this time, the training phase of the BIOS startup process has been completed, and the NVME disk is used according to the actual training result. Because there are many NVME hard disk manufacturers, in order to count and simplify the method of setting the NVME hard disk rate, the BIOS judges the manufacturer information and device of the NVME hard disk in the PCI stage of startup to achieve the purpose of dynamically setting parameters, that is, dynamically set the Retrain function of the PCI link where the NVME disk is located to be turned on, and a maximum of 3 training actions can be performed on the PCI device that failed in Training during the PCI initialization Training stage. Within the 3 training processes, as long as the training result rate is normal, the training action is terminated. If the first training process still slows down, the Preset parameter value is modified after confirming the manufacturer information and device information. If it still fails after modification, the second training action is performed and the PH3 Tx parameter setting is modified. If the second time still fails, the third training will continue and the relevant setting values ​​will be modified. Regardless of whether the third time is successful or failed, it will be operated and used according to the third training result.

[0188] The core words are explained as follows:

[0189] Preset is the link equalization setting value, which is used to establish a stable connection between devices. By adjusting the Tx (transmitter) and Rx (receiver) settings, the signal quality is improved, so that the PCIe link can transmit at the most stable and faster rate.

[0190] Phase 1: In order to fully optimize the link so that training sequences can be exchanged and the remaining link equalization phase for fine-tuning purposes is completed, the same training sequence will be sent repeatedly to ensure that the downstream port receives the correct preset value despite the possibility of poor link quality.

[0191] Phase 2: After the link bit error rate achieves BER ≤ 10e-4 in Phase 1, enter Phase 2, and then further optimize the preset value of the upstream port until the optimal setting is obtained. The link bit error rate should meet BER ≤ 1E -12 .

[0192] Phase 3: Perform the same negotiation on the downstream port in phase 3. The upstream port sends an equalization request through a training sequence to adjust the preset value of the downstream port until the optimal setting is obtained. The bit error rate of the link should meet BER ≤ 1E -12 .

[0193] Retrain: This state is entered when the link needs to be retrained. This could be due to an error in L0, or recovery from L1 to L0, or recovery from L0s (if the link was not trained correctly using the FTS sequence).

[0194] Fig. 9 is a flow chart of a method for BIOS adaptive NVME hard disk speed according to an embodiment of the present application, Fig.10 is a swim lane diagram of a method for BIOS adaptive NVME hard disk speed according to an embodiment of the present application, such as Fig. 9 As shown, the specific implementation steps are as follows:

[0195] (1) When the server starts, during the PCI enumeration phase of the BIOS, the BIOS reads the manufacturer information and device information of the NVME hard disk through the PCI configuration space, and makes judgments on the obtained manufacturer information and device information of the NVME hard disk;

[0196] (2) Assuming that the NVME hard disk is confirmed to be manufacturer A through the manufacturer information and device information, the PCI link of the CPU where the current NVME hard disk is located is confirmed through the bus number of the current NVME hard disk. After confirming the PCI link location information, the Re-train function of this PCI link is enabled;

[0197] (3) When the NVME hard disk of manufacturer A is at the rate of Gen4 during the first PCI training, the second and third PCI training processes will not be continued; if the first PCI training fails, the TX and RX Preset parameters of the PCI link where the current NVME hard disk of manufacturer A is located will be set to 7, and the second PCI training action will be continued to confirm whether the training result sets the NVME hard disk of manufacturer A to Gen4. At this time, the NVME hard disk of manufacturer A has been set to the rate of Gen4, and the third PCI training action will not be performed and PCI will continue to enumerate the next NVME hard disk;

[0198] (4) In step 2, when it is confirmed that the NVME hard disk manufacturer is B, that is, the NVME hard disk of manufacturer B, when the NVME hardware rate of manufacturer B's NVME hard disk is Gen4 during the first PCI training process, the second and third PCI training processes will not be continued; if the first PCI training fails, the TX and RX Preset parameters of the PCI link where the current NVME hard disk of manufacturer B is located are set to 7, and then the second PCI training action is continued to confirm whether the training result sets the NVME hard disk of manufacturer B to Gen4. If the NVME hard disk still fails after the second PCI Training action is completed, the TX Precursor and Postcursor parameters of the PH3 of the PCI link where the NVME hard disk of manufacturer B is located are set to 0 and 13 respectively, and the third PCI Training action is performed. At this time, the NVME hard disk of manufacturer B has been set to the Gen4 rate and the PCI enumeration of the next NVME hard disk continues;

[0199] (5) Poll steps 2-4 to set the Gen4 rate for all NVME hard disks in the server. When all NVME hard disks are set, the server starts normally.

[0200] The present application relates to a method for implementing BIOS adaptive NVME hard disk rate. In view of the technical problem of NVME hard disk manufacturers slowing down during server startup, combined with the Train characteristics of the PCI link and the attenuation characteristics of the link signal, and considering the general adaptability of the hard disk FW, the decoupling of the solution and other considerations, the Preset value of the hard disk FW for the TX and RX signals of the receiving end is set by the BIOS end. At the same time, the BIOS confirms that the NVME hard disk is the specific manufacturer information through the manufacturer information and device information at startup, and sets the PCI link according to the different requirements of each manufacturer. For example, when the hard disk of manufacturer A is connected, when the first PCI Train negotiation fails, the BIOS actively updates and adjusts the Preset value of RX and Tx to 7 and performs a second Train action. During the second PCI training, the NVME hard disk of manufacturer A is set at the GEN4 rate. Similarly, when the NVME hard disk of manufacturer B is started on the server, when the BIOS loads the NVME hard disk FW in the PCI initialization Train phase, it is confirmed whether to adopt a re-negotiation mechanism according to the PCI Train negotiation result of the NVME hard disk FW. When re-negotiation, that is, the second PCI During Train, the BIOS will renegotiate according to the preset values ​​of TX and RX of 7. At this time, the NVME hard disk will maintain the PCI link protocol on the CPU side at the rate of Gen4. If the second PCI Train negotiation still fails, the TX Precursor and Postcursor parameters of PH3 of the PCI link where the NVME hard disk of manufacturer B is located will be set to 0 and 13 respectively on the BIOS side. At this time, the third PCI Training action will be performed. At this time, the PCI link between the NVME hard disk and the CPU side will definitely be maintained at the GEN4 rate. Therefore, this solution can completely solve the problem that the NVME hard disk cannot use the GEN3 rate through the GENZ cable. At this time, the NVME hard disk of manufacturer B has been set to the Gen4 rate and continues to enumerate the next NVME hard disk by PCI. The above solution changes only involve the PCI re-train, RX, TX Preset, PH3 TX Precursor and Postcursor parameter settings on the BIOS side, which are actively controlled by the BIOS side. After polling the current NVME hard disk, other NVME hard disks will be polled until all NVME hard disks are polled.

[0201] This application uses the BIOS to set the Train function of the PCI link where the NVME hard disk is located for three Train actions. At the same time, the BIOS will confirm whether to start setting the RX and TX Preset values ​​to 7 based on the first PCItrain result of the PCI link on the CPU side and the NVME hard disk when the server is started. When the first PCI Train fails, the BIOS will perform the second PCI Train action. At the same time, the BIOS will use the Rx and TX Preset values ​​​​of 7 to perform PCI Train with the NVME hard disk of manufacturer A. The fixed value setting can satisfy the CPU-side PCI link Train to fix the NVME hard disk rate at GEN4. At the same time, when the NVME hard disk of manufacturer B is in the PCI link, the NVME hard disk of manufacturer A can be repeated in the same way. When the second PCI training still fails, the TXPrecursor and Postcursor parameters of PH3 are set to 0 and 13 respectively for the PCI link where the NVME hard disk of manufacturer B is located. At this time, the third PCI Training action, at this time, the PCI link between the NVME hard disk and the CPU side will be maintained at the GEN4 rate. After the current NVME hard disk is Trained to GEN4, the next NVME hard disk will be Trained until all NVME hard disks are Trained to the GEN4 rate. This solution is not affected by the CPU architecture and can be applied to servers with any architecture that supports PCI links.

[0202] This application uses the BIOS to perform a maximum of three Train actions for the Train function of the PCI link where the NVME hard disk is located. At the same time, the BIOS evaluates whether the Preset values ​​of the RX and Tx signals required by the NVME hard disk are set to 7 based on the Train results of the PCI link with the first CPU end. When the first PCI Train is successful, no changes are made. Once the first PCI Train fails, the BIOS forces the Preset of the RX and Tx signals of the PCI link where the current NVME hard disk is located to be set to 7 and the BIOS performs the second PCI link Train action to ensure that the NVME hard disk is fixed at the GEN4 rate and achieve the maximum performance advantage of the NVME hard disk. If the second PCI training result still fails, the PH3 TX Precursor and Postcursor parameters of the PCI link where the NVME hard disk corresponding to the BIOS end is set to 0 and 13 respectively, and the third PCI Training action is performed. At this time, the PCI link between the NVME hard disk and the CPU end will definitely maintain the GEN4 rate. After the current NVME hard disk is Trained to GEN4, the next NVME hard disk will continue to Train until all NVME hard disks are Trained to GEN4 rate. Because PCI Train will consume BIOS startup time multiple times, it is necessary to confirm the PCI link where the NVME hard disk is located in advance, and set the PCI Train function of the NVME hard disk three times in a targeted manner, so as to ensure that the server can fix the speed of the NVME hard disk GEN4 while ensuring that the server startup time is not too long. This solution can be applied to servers with one or more NVME hard disks mixed or plugged in separately, which is highly flexible and greatly improves the flexibility of the server. In summary, for server operators, it can effectively reduce the procurement cost of the server, and at the same time, ensure that the beneficial effects of the NVME hard disk are outstanding and the technical advantages are obvious. This solution can be extended to various types of PCI devices, such as PCI network cards, PCI RAID cards and other PCI devices.

[0203] In this embodiment, a control device for server link configuration is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0204] Fig.11 is a structural block diagram of a control device for server link configuration according to an embodiment of the present application, such as Fig.11As shown, multiple types of memories, processors and controllers are deployed in the server, and the processor is connected to each type of memory through a bus link.

[0205] a sending module, configured to send a target configuration instruction to the processor through the controller, wherein the target configuration instruction is used to instruct the processor to configure a bus link between the processor and the target memory to be accessed using an initial parameter value to obtain an initial bus link, wherein the initial parameter value is a parameter value corresponding to the type of the target memory;

[0206] A first acquisition module, configured to acquire, through the controller, a current communication rate of the initial bus link reported by the processor;

[0207] A processing module is used to enter a target control mode for the processor when the current communication rate does not fall within the communication rate range, wherein the target control mode is used to control the processor to adjust the initial parameter value to obtain a target bus link whose communication rate falls within the communication rate range.

[0208] Through the above content, the controller first uses the initial parameter value corresponding to the target type of the target memory to control the processor to configure the bus link between the processor and the target memory, obtain the initial bus link, and obtain the current communication rate of the initial bus link reported by the processor, and when the current communication rate does not meet the communication rate requirement, enter the target control mode of the processor, and control the processor to adjust the initial parameter value according to the rate of the initial bus link, so as to dynamically adjust the communication parameters of the bus link according to the communication rate of the bus link between the processor and the memory without changing the hardware connection link, thereby ensuring that the communication rate between different types of memory and the processor in the server meets the communication rate requirement, thereby solving the problem of reduced transmission rate of different types of memory in the same connection link environment. Therefore, the problem of poor compatibility of memory with the server link environment in the related technology can be solved, and the effect of improving the compatibility of memory with the server link environment can be achieved.

[0209] Optionally, the processing module includes:

[0210] A screening unit, used for screening out a target sub-parameter to be modified currently from a plurality of sub-parameters, wherein the plurality of sub-parameters are a plurality of dimensional configuration parameters required for configuring a bus link between the processor and the target memory;

[0211] a sending unit, configured to send a first adjustment instruction to the processor according to the current communication rate and the communication rate range, wherein the first adjustment instruction is used to instruct the processor to adjust the initial parameter value corresponding to the target sub-parameter according to the parameter adjustment method indicated by the first adjustment instruction to obtain a reference bus link;

[0212] A determining unit is used to determine the reference bus link as the target bus link when the reference bus link meets the communication rate condition.

[0213] Optionally, the sending unit is used to:

[0214] Acquire a target difference between the current communication rate and a reference communication rate in the communication rate range;

[0215] Filtering out a target adjustment value corresponding to the target difference value and the target sub-parameter from the difference values, sub-parameters and adjustment values ​​having a corresponding relationship;

[0216] The first adjustment instruction carrying the target adjustment value is sent to the processor, wherein the first adjustment instruction is used to instruct the processor to adjust the initial parameter value corresponding to the target sub-parameter in the initial bus link according to the target adjustment value to obtain the reference bus link.

[0217] Optionally, the screening unit is used to:

[0218] Filter out the initial sub-parameters to be adjusted from the plurality of sub-parameters;

[0219] The target sub-parameters having a priority greater than or equal to the target priority are screened out from the initial sub-parameters according to the adjustment priorities corresponding to the sub-parameters.

[0220] Optionally, the screening unit is used to:

[0221] Acquire a target difference between the current communication rate and a reference communication rate in the communication rate range;

[0222] The target sub-parameter corresponding to the target difference is determined from the difference and sub-parameter having a corresponding relationship.

[0223] Optionally, the device further comprises:

[0224] A second acquisition module, configured to enable the controller to acquire a current target communication rate of the reference bus link reported by the processor after sending a first adjustment instruction to the processor according to the current communication rate and the communication rate range;

[0225] A matching module, used for matching the target communication rate with the communication rate range;

[0226] The first determination module is used to determine that the reference bus link meets the communication rate condition when it is determined that the target communication rate falls within the communication rate range.

[0227] Optionally, the device further comprises:

[0228] a detection module, configured to detect the number of adjustments to the initial parameter value corresponding to the target sub-parameter in the initial bus link after matching the target communication rate with the communication rate range and in the case where it is determined that the target communication rate does not fall within the communication rate range;

[0229] A search module, used for searching an initial sub-parameter in a state to be adjusted from the plurality of sub-parameters when the number of adjustment times is greater than or equal to the target number of adjustment times;

[0230] The second determination module is configured to determine whether the reference bus link satisfies the communication rate condition when the initial sub-parameter does not exist in the plurality of sub-parameters.

[0231] Optionally, the device further comprises:

[0232] A third acquisition module, configured to acquire target wiring information of the processor and the target storage in the server before the controller sends the target configuration instruction to the processor, wherein the target wiring information is used to indicate a cable connection status between the processor and the target storage;

[0233] A configuration module is used to predict the initial parameter value of the communication parameter required for configuring a bus link between the processor and the target memory according to the target type to which the target memory belongs and the target wiring information.

[0234] Optionally, the configuration module includes:

[0235] The determining unit is configured to filter out the initial parameter value corresponding to the target type and the current target wiring information from the types, wiring information and parameter values ​​of the communication parameters that have a corresponding relationship.

[0236] Optionally, the configuration module includes:

[0237] A screening unit, configured to screen out reference wiring information matching the target wiring information from a parameter configuration set, wherein the parameter configuration set records configuration conditions of parameter values ​​of the communication parameters of the target type of memory under wiring environments corresponding to different wiring information;

[0238] A prediction unit is used to predict the initial parameter value according to the reference parameter value configured for the communication parameter by the processor and the target type of memory under the reference wiring information recorded in the parameter configuration set.

[0239] Optionally, the prediction unit is used to:

[0240] Obtain a candidate communication rate between the target type of memory recorded in the parameter configuration set and the processor using the reference parameter value in the reference wiring information;

[0241] matching the candidate communication rate with the communication rate range;

[0242] In a case where it is determined that the candidate communication rate falls within the communication rate range, the reference parameter value is determined as the initial parameter value.

[0243] Optionally, the device further comprises:

[0244] a fourth acquisition module, configured to, after matching the candidate communication rate with the communication rate range, acquire a target difference between the candidate communication rate and a reference communication rate within the communication rate range if it is determined that the candidate communication rate does not fall within the communication rate range;

[0245] A screening module, used for screening out a target parameter adjustment value corresponding to the target difference value from the difference values ​​and parameter adjustment values ​​having a corresponding relationship;

[0246] The reference parameter value is adjusted according to the target parameter adjustment value to obtain the initial parameter value.

[0247] Optionally, the sending module includes:

[0248] A first generating unit, configured to send a first configuration instruction to the processor, wherein the first configuration instruction is used to instruct the processor to set a link training state machine of the bus link to an enabled state, wherein the link training state machine is used to configure a link communication state of the bus link connected between the processor and the memory;

[0249] A second sending unit is used to send a second configuration instruction carrying the initial parameter value to the processor, wherein the second configuration instruction is used to instruct the processor to control the link training state machine to configure the bus link between the processor and the target memory according to the initial parameter value to obtain the initial bus link, and the target configuration instruction includes the first configuration instruction and the second configuration instruction.

[0250] Optionally, the processor includes a plurality of sub-processors, each of the memories is connected to a corresponding sub-processor, the bus link includes a sub-link connecting each of the memories to the corresponding sub-processor, and the controller is connected to each of the sub-processors.

[0251] The first sending unit is used to:

[0252] Detecting a target sub-link to which the target storage device belongs;

[0253] Sending the first configuration instruction carrying the link identifier of the target sub-link to the target sub-processor corresponding to the target sub-link, wherein the first configuration instruction is used to instruct the target sub-processor to configure the target link training state machine corresponding to the target sub-link to be in an enabled state;

[0254] The second sending unit is used for:

[0255] The second configuration instruction carrying the link identifier of the target sub-link and the initial parameter value is sent to the target sub-processor, wherein the second configuration instruction is used to instruct the target sub-processor to control the target link training machine corresponding to the link identifier to configure the target sub-connection chain between the target sub-processor and the target memory according to the initial parameter value.

[0256] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0257] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0258] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0259] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0260] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0261] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0262] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0263] An embodiment of the present application also provides a computer program, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in any one of the above method embodiments.

[0264] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0265] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0266] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for controlling server link configuration, characterized in that: Multiple types of memories, processors, and controllers are deployed in the server, and the processor is connected to each type of memory through a bus link. The controller sends a target configuration instruction to the processor, wherein the target configuration instruction is used to instruct the processor to configure a bus link between the processor and the target memory to be accessed using an initial parameter value to obtain an initial bus link, wherein the initial parameter value is a parameter value corresponding to the type of the target memory; The controller obtains the current communication rate of the initial bus link reported by the processor; When the current communication rate does not fall within the communication rate range, a target control mode for the processor is entered, wherein the target control mode is used to control the processor to adjust the initial parameter value to obtain a target bus link whose communication rate falls within the communication rate range.

2. The method according to claim 1, characterized in that The entering into the target control mode of the processor comprises: Filtering out a target sub-parameter to be modified from a plurality of sub-parameters, wherein the plurality of sub-parameters are configuration parameters of a plurality of dimensions required for configuring a bus link between the processor and the target memory; Sending a first adjustment instruction to the processor according to the current communication rate and the communication rate range, wherein the first adjustment instruction is used to instruct the processor to adjust the initial parameter value corresponding to the target sub-parameter according to the parameter adjustment method indicated by the first adjustment instruction to obtain a reference bus link; In a case where the reference bus link meets a communication rate condition, the reference bus link is determined as the target bus link.

3. The method according to claim 2, characterized in that The sending a first adjustment instruction to the processor according to the current communication rate and the communication rate range includes: Acquire a target difference between the current communication rate and a reference communication rate in the communication rate range; Filtering out a target adjustment value corresponding to the target difference value and the target sub-parameter from the difference values, sub-parameters and adjustment values ​​having a corresponding relationship; The first adjustment instruction carrying the target adjustment value is sent to the processor, wherein the first adjustment instruction is used to instruct the processor to adjust the initial parameter value corresponding to the target sub-parameter in the initial bus link according to the target adjustment value to obtain the reference bus link.

4. The method according to claim 2, characterized in that: The step of selecting the target sub-parameter to be corrected from the multiple sub-parameters includes: Filter out the initial sub-parameters to be adjusted from the plurality of sub-parameters; The target sub-parameters having a priority greater than or equal to the target priority are screened out from the initial sub-parameters according to the adjustment priorities corresponding to the sub-parameters.

5. The method according to claim 2, characterized in that: The step of selecting the target sub-parameter to be corrected from the multiple sub-parameters includes: Acquire a target difference between the current communication rate and a reference communication rate in the communication rate range; The target sub-parameter corresponding to the target difference is determined from the difference and sub-parameter having a corresponding relationship.

6. The method according to claim 2, characterized in that After sending a first adjustment instruction to the processor according to the current communication rate and the communication rate range, the method further includes: The controller obtains the current target communication rate of the reference bus link reported by the processor; Matching the target communication rate with the communication rate range; In the case where it is determined that the target communication rate falls within the communication rate range, it is determined that the reference bus link satisfies the communication rate condition.

7. The method according to claim 6, characterized in that After matching the target communication rate with the communication rate range, the method further includes: In the case where it is determined that the target communication rate does not fall within the communication rate range, detecting the number of adjustments to the initial parameter value corresponding to the target sub-parameter in the initial bus link; When the number of adjustment times is greater than or equal to the target number of adjustment times, searching for an initial sub-parameter in a state to be adjusted from the plurality of sub-parameters; In a case where the initial sub-parameter does not exist in the plurality of sub-parameters, it is determined that the reference bus link satisfies the communication rate condition.

8. The method according to claim 1, characterized in that Before the controller sends the target configuration instruction to the processor, the method further includes: Acquire target wiring information of the processor and the target storage in the server, wherein the target wiring information is used to indicate a cable connection status between the processor and the target storage; The initial parameter value of the communication parameter required for configuring a bus link between the processor and the target memory is predicted according to the target type to which the target memory belongs and the target wiring information.

9. The method according to claim 8, characterized in that The predicting, according to the target type to which the target memory belongs and the target wiring information, the initial parameter value of the communication parameter required for configuring a bus link between the processor and the target memory comprises: The initial parameter value corresponding to the target type and the current target wiring information is screened out from the types, wiring information and parameter values ​​of the communication parameters that have a corresponding relationship.

10. The method according to claim 8, characterized in that The predicting, according to the target type to which the target memory belongs and the target wiring information, the initial parameter value of the communication parameter required for configuring a bus link between the processor and the target memory comprises: Filtering reference wiring information matching the target wiring information from a parameter configuration set, wherein the parameter configuration set records configuration conditions of parameter values ​​of the communication parameters of the target type of memory under wiring environments corresponding to different wiring information; The initial parameter value is predicted according to the reference parameter value configured for the communication parameter by the processor and the memory of the target type under the reference wiring information recorded in the parameter configuration set.

11. The method according to claim 10, characterized in that The predicting the initial parameter value according to the reference parameter value configured for the communication parameter by the processor and the memory of the target type recorded in the parameter configuration set under the reference wiring information comprises: Obtain a candidate communication rate between the target type of memory recorded in the parameter configuration set and the processor using the reference parameter value in the reference wiring information; matching the candidate communication rate with the communication rate range; In a case where it is determined that the candidate communication rate falls within the communication rate range, the reference parameter value is determined as the initial parameter value.

12. The method according to claim 11, characterized in that After matching the candidate communication rate with the communication rate range, the method further includes: In a case where it is determined that the candidate communication rate does not fall within the communication rate range, obtaining a target difference between the candidate communication rate and a reference communication rate within the communication rate range; Filtering out a target parameter adjustment value corresponding to the target difference value from the difference values ​​and parameter adjustment values ​​having a corresponding relationship; The reference parameter value is adjusted according to the target parameter adjustment value to obtain the initial parameter value.

13. The method according to claim 1, characterized in that The controller sends a target configuration instruction to the processor, including: Sending a first configuration instruction to the processor, wherein the first configuration instruction is used to instruct the processor to set a link training state machine of the bus link to an enabled state, wherein the link training state machine is used to configure a link communication state of the bus link connected between the processor and the memory; A second configuration instruction carrying the initial parameter value is sent to the processor, wherein the second configuration instruction is used to instruct the processor to control the link training state machine to configure the bus link between the processor and the target memory according to the initial parameter value to obtain the initial bus link, and the target configuration instruction includes the first configuration instruction and the second configuration instruction.

14. The method according to claim 13, characterized in that The processor includes a plurality of sub-processors, each of the memories is connected to a corresponding sub-processor, the bus link includes a sub-link connecting each memory to the corresponding sub-processor, and the controller is connected to each sub-processor. The sending a first configuration instruction to the processor includes: Detecting a target sub-link to which the target storage device belongs; Sending the first configuration instruction carrying the link identifier of the target sub-link to the target sub-processor corresponding to the target sub-link, wherein the first configuration instruction is used to instruct the target sub-processor to configure the target link training state machine corresponding to the target sub-link to be in an enabled state; The sending of the second configuration carrying the initial parameter value to the processor includes: The second configuration instruction carrying the link identifier of the target sub-link and the initial parameter value is sent to the target sub-processor, wherein the second configuration instruction is used to instruct the target sub-processor to control the target link training state machine corresponding to the link identifier to configure the target sub-connection chain between the target sub-processor and the target memory according to the initial parameter value.

15. A control system for server link configuration, It is characterized in that The invention comprises: a controller, a processor and multiple types of memories, wherein the controller is connected to the processor, and the processor is connected to each type of the memories through a bus link. The controller is used to send a target configuration instruction to the processor, wherein the target configuration instruction is used to instruct the processor to use an initial parameter value to configure a bus link between the processor and a target memory to be accessed to obtain an initial bus link, wherein the initial parameter value is a parameter value corresponding to the type of the target memory; obtain a current communication rate of the initial bus link reported by the processor; and enter a target control mode for the processor when the current communication rate does not fall within a communication rate range, wherein the target control mode is used to control the processor to adjust the initial parameter value to obtain a target communication bus whose communication rate falls within the communication rate range.

16. The system according to claim 15, characterized in that The processor includes a plurality of sub-processors, each of the memories is connected to a corresponding sub-processor, the bus link includes a sub-link connecting each memory to the corresponding sub-processor, and the controller is connected to each sub-processor. The controller is used to detect the target sub-link to which the target memory belongs; send a first configuration instruction carrying the link identifier of the target sub-link to the target sub-processor corresponding to the target sub-link, wherein the first configuration instruction is used to instruct the target sub-processor to configure the target link training state machine corresponding to the target sub-link to be in an enabled state; send a second configuration instruction carrying the link identifier of the target sub-link and the initial parameter value to the target sub-processor, wherein the second configuration instruction is used to instruct the target sub-processor to control the target link training state machine corresponding to the link identifier to configure the target sub-connection chain between the target sub-processor and the target memory according to the initial parameter value, and the target configuration instruction includes the first configuration instruction and the second configuration instruction.

17. A control device for server link configuration, characterized in that: Multiple types of memories, processors, and controllers are deployed in the server, and the processor is connected to each type of memory through a bus link. a sending module, configured to send a target configuration instruction to the processor through the controller, wherein the target configuration instruction is used to instruct the processor to configure a bus link between the processor and the target memory to be accessed using an initial parameter value to obtain an initial bus link, wherein the initial parameter value is a parameter value corresponding to the type of the target memory; A first acquisition module, configured to acquire, through the controller, a current communication rate of the initial bus link reported by the processor; A processing module is used to enter a target control mode for the processor when the current communication rate does not fall within the communication rate range, wherein the target control mode is used to control the processor to adjust the initial parameter value to obtain a target bus link whose communication rate falls within the communication rate range.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 14 when executed by a processor.

19. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 14 are implemented.

20. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 14 are implemented.

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