A gallium nitride vertical JFET device with multi-layer channel and staggered super-junction

Abstract

The application discloses a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction and a preparation method thereof. The device comprises an N++ GaN substrate, a GaN drift layer on the surface of the N++ GaN substrate, a super junction on the surface of the GaN drift layer, a channel region, a first P+ GaN region and a second P+ GaN region on the surface of the super junction, a first gate, a source and a second gate on the surfaces of the first P+ GaN region, the channel region and the second P+ GaN region respectively, a passivation layer between the first gate and the source and between the second gate and the source, and a drain on the lower surface of the N++ GaN substrate. The doping concentration of the stepped N-type GaN drift region in the super junction decreases from bottom to top, and the doping concentration of the stepped P-type low-doped region increases from bottom to top. The stepped super junction improves the voltage resistance of the device. The introduction of the super low-doped region in the channel region significantly improves the threshold voltage of the device. The doping concentration of the upper layer of the channel region is increased to increase the forward current, so that the GaN vertical JFET satisfying the high threshold voltage, the large forward current and the high voltage resistance is obtained.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and particularly relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super-junction. BACKGROUND

[0002] Nowadays, lateral GaN HEMT devices are rapidly developing and mature in radio frequency and low-voltage power devices, and enhancement-mode GaN HEMTs based on a p-GaN cap layer and enhancement-mode GaN HEMTs based on a cascade structure are gradually gaining applications. Currently, commercially available GaN HEMTs have a voltage resistance level below 650 V, and have an advantage in switching speed in the medium and low voltage application field. However, if the voltage resistance level needs to be further improved, vertical GaN will become a new focus, and in particular, a homoepitaxial GaN vertical power device based on a GaN bulk material substrate will become a development direction of high-voltage and large-current in the future.

[0003] Compared with lateral GaN HEMT, the vertical GaN device has the following advantages: (1) for a certain chip area, it has higher breakdown voltage and current capacity; (2) the electric field peak of the vertical GaN device can be transferred from the surface to the drift region, and the occurrence of surface breakdown can be inhibited; (3) the thermal mismatch ratio of the substrate and the drift region is reduced by using GaN homoepitaxy, which is beneficial to power dissipation; (4) the dynamic on-resistance is relatively stable due to less dependence on surface passivation; (5) the defect density in the homoepitaxial layer is reduced. These advantages make the vertical GaN device particularly suitable for medium voltage (600-10kV) and high power scenarios.

[0004] So far, several 1.2kV-level vertical GaN transistors have been prepared based on a GaN substrate, such as: current aperture vertical electron transistors (CAVFET), junction field effect transistors (JFET), trench MOSFET and fin channel MOSFET. In the conventional structure of the junction field effect transistor, since the threshold voltage and the forward current are related to the channel n-type impurity concentration, when the channel n-type impurity concentration is high, the threshold voltage is low and the forward current is large, and when the channel n-type impurity concentration is low, the threshold voltage is high and the forward current is low, that is, the conventional vertical GaN transistor cannot simultaneously obtain high threshold voltage and large forward current. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the application provides a gallium nitride vertical JFET device with a multi-layer channel and a stepped super-junction. The technical problem to be solved by the application is realized through the following technical scheme:

[0006] In a first aspect, the application provides a gallium nitride vertical JFET device with a multi-layer channel and a stepped super-junction, comprising:

[0007] N++ GaN substrate;

[0008] GaN drift layer located on one side surface of the N++ GaN substrate;

[0009] super junction located on the other side surface of the GaN drift layer away from the N++ GaN substrate; the super junction comprises stepped N-type GaN drift region and stepped P-type low-doped region, the doping concentration of the stepped N-type GaN drift region decreases from bottom to top, and the doping concentration of the stepped P-type low-doped region increases from bottom to top;

[0010] channel region, first P+ GaN region and second P+ GaN region located on the other side surface of the super junction away from the N++ GaN substrate, and the first P+ GaN region and the second P+ GaN region are respectively located on both sides of the channel region;

[0011] first gate, source and second gate respectively located on the other side surface of the first P+ GaN region, the channel region and the second P+ GaN region away from the N++ GaN substrate; the channel region comprises at least one layer of N-- GaN region located on the other side surface of the stepped N-type GaN drift region away from the N++ GaN substrate, and at least one layer of N++ GaN region located on the other side surface of the source close to the N++ GaN substrate;

[0012] passivation layer located between the first gate and the source and between the second gate and the source;

[0013] drain located on the other side surface of the N++ GaN substrate away from the GaN drift layer.

[0014] In an embodiment of the present application, the stepped P-type low-doped region comprises first P-type low-doped region and second P-type low-doped region respectively located on both sides of the stepped N-type GaN drift region; wherein the doping concentration of the first P-type low-doped region and the second P-type low-doped region both increases from bottom to top.

[0015] In an embodiment of the present application, the doping concentration of the stepped N-type GaN drift region and the stepped P-type low-doped region is 0.7×10 16 ~1.1×10 18 cm -3 .

[0016] In an embodiment of the present application, the stepped N-type GaN drift region comprises three layers of N-type GaN drift region, and the first P-type low-doped region and the second P-type low-doped region both comprise three layers of P-type low-doped region, wherein the doping concentration of the same layer of P-type low-doped region in the first P-type low-doped region and the second P-type low-doped region is the same.

[0017] In one embodiment of the present application, the at least one N-GaN region between the N--GaN region and the N++GaN region in the channel region comprises at least one N-GaN region.

[0018] In one embodiment of the present application, the at least one N-GaN region between the N--GaN region and the N++GaN region in the channel region comprises at least one N-GaN region. 15 17 cm -3 , and the at least one N++GaN region on the side surface of the N++GaN substrate close to the source electrode has a doping concentration of 1 x 10 18 19 cm -3 .

[0019] In one embodiment of the present application, the at least one N-GaN region between the N--GaN region and the N++GaN region has a doping concentration of 3 x 10 17 19 cm -3 .

[0020] In a second aspect, the present application provides a method for manufacturing a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction, comprising:

[0021] providing a N++GaN substrate;

[0022] depositing and forming a GaN drift layer on one side surface of the N++GaN substrate;

[0023] growing a super junction composed of a stepped N-type GaN drift region and a stepped P-type low-doped region on the side surface of the GaN drift layer away from the N++GaN substrate, wherein the doping concentration of the stepped N-type GaN drift region decreases from bottom to top, and the doping concentration of the stepped P-type low-doped region increases from bottom to top;

[0024] growing a channel region on the side surface of the super junction away from the N++GaN substrate, etching the first preset regions at both ends of the channel region, and then growing a first P+GaN region and a second P+GaN region in the first preset regions at both ends of the channel region, respectively;

[0025] thinning the N++GaN substrate, and making a drain electrode on the side surface of the N++GaN substrate away from the GaN drift layer;

[0026] ​​​A source electrode is formed on a side surface of the channel region away from the N++ GaN substrate, and a first gate electrode and a second gate electrode are formed on side surfaces of the first P+ GaN region and the second P+ GaN region away from the N++ GaN substrate respectively; wherein the channel region comprises at least one layer of N-- GaN region on a side surface of the stepped N-type GaN drift region away from the N++ GaN substrate, and at least one layer of N++ GaN region on a side surface of the source electrode close to the N++ GaN substrate;

[0027] After a passivation layer is deposited on surfaces of the first P+ GaN region, the second P+ GaN region, the first gate electrode, the second gate electrode and the source electrode, holes are formed in the passivation layer on surfaces of the source electrode, the first gate electrode and the second gate electrode to lead out electrodes.

[0028] In an embodiment of the present application, the step of growing a super junction composed of a stepped N-type GaN drift region and a stepped P-type low-doped region on a surface of the GaN drift layer away from the N++ GaN substrate comprises:

[0029] The multiple layers of N-type GaN drift region are grown on the surface of the GaN drift layer away from the N++ GaN substrate successively, and the doping concentration of the multiple layers of N-type GaN drift region decreases from bottom to top;

[0030] The multiple layers of N-type GaN drift region are etched to remove the multiple layers of N-type GaN drift region in the second preset region at both ends, thereby forming the stepped N-type GaN drift region;

[0031] The multiple layers of P-type low-doped region are grown in the second preset region at both ends successively, thereby forming the stepped P-type low-doped region comprising a first P-type low-doped region and a second P-type low-doped region; the doping concentration of the first P-type low-doped region and the second P-type low-doped region increases from bottom to top, and the doping concentration of the same layer of P-type low-doped region in the first P-type low-doped region and the second P-type low-doped region is the same.

[0032] In an embodiment of the present application, after the channel region is grown on a surface of the super junction away from the N++ GaN substrate and the first preset region at both ends of the channel region is etched, the step of growing a first P+ GaN region and a second P+ GaN region in the first preset region at both ends of the channel region comprises:

[0033] The multiple layers of N-type GaN region are grown on the surface of the super junction away from the N++ GaN substrate successively, thereby forming the channel region;

[0034] After the channel region is etched to remove the multiple layers of N-type GaN region in the second preset region at both ends of the channel region, the first P+ GaN region and the second P+ GaN region are grown in the second preset region at both ends of the channel region respectively.

[0035] The present application has the following advantages compared with the prior art:

[0036] The present application provides a gallium nitride vertical JFET device with multi-layer channel and stepped super-junction and a preparation method thereof. The device comprises: an N++ GaN substrate; a GaN drift layer located on one side surface of the N++ GaN substrate; a super-junction located on the side surface of the GaN drift layer away from the N++ GaN substrate; a channel region, a first P+ GaN region and a second P+ GaN region located on the side surface of the super-junction away from the N++ GaN substrate, the first P+ GaN region and the second P+ GaN region being located on two sides of the channel region respectively; a first gate, a source and a second gate located on the side surface of the first P+ GaN region, the channel region and the second P+ GaN region away from the N++ GaN substrate respectively; a passivation layer located between the first gate and the source and between the second gate and the source; and a drain located on the side surface of the N++ GaN substrate away from the GaN drift layer. On the one hand, in the super-junction, the doping concentration of the stepped N-type GaN drift region decreases from bottom to top, and the doping concentration of the stepped P-type low-doped region increases from bottom to top, so that the stepped super-junction can effectively relieve the peak electric field at the contact position of the P-type region and the N-type drift region, and improve the withstand voltage of the device. Compared with the prior art, by replacing the traditional drift region with a super-junction with high doping concentration, the present application can improve the carrier concentration of the conductive region, reduce the electrical energy loss, and simultaneously improve the forward characteristics (reduced on-resistance) and reverse characteristics (improved breakdown voltage) of the JFET device, and significantly improve the power quality factor. In addition, the stepped super-junction made below the P-type region is beneficial to improve the avalanche capability of the device, making the device safer and more reliable under extreme conditions.

[0037] On the other hand, the device channel region comprises at least one N-- GaN region located on the side surface of the stepped N-type GaN drift region away from the N++ GaN substrate, and at least one N++ GaN region located on the side surface of the source close to the N++ GaN substrate. By introducing a super-low-doped (N-- GaN region) in the channel region, the threshold voltage of the device can be significantly improved, and at the same time, the forward current is increased by increasing the doping concentration of the upper layer of the channel region (N++ GaN region), and the electric field distribution is uniform in the drift region due to the electric field voltage division of the super-junction, which is beneficial to reduce the electric field intensity of the contact area of the P-type region and the N-type drift region, thereby obtaining a GaN vertical JFET that simultaneously satisfies high threshold voltage, large forward current and high withstand voltage.

[0038] The present application will be further described in detail below with reference to the accompanying drawings and examples. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 is a structural schematic diagram of a gallium nitride vertical JFET device with multi-layer channel and stepped super-junction provided by the present application.

[0040] Figure 2 is a flowchart of a preparation method of a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction according to an embodiment of the present application;

[0041] Figures 3a-3j is a preparation process diagram of a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction according to an embodiment of the present application;

[0042] Figure 4 is a transfer curve diagram of a conventional JFET device and a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction;

[0043] Figure 5 is a transfer curve diagram of a conventional JFET device and a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction in semi-logarithmic coordinates;

[0044] Figure 6 is a super junction electric field distribution diagram of a conventional JFET device;

[0045] Figure 7 is a super junction electric field distribution diagram of a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction;

[0046] Figure 8 is a breakdown voltage comparison diagram of a conventional JFET device and a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. DETAILED DESCRIPTION

[0047] The present application will be further described below in conjunction with specific embodiments, but the embodiments of the present application are not limited thereto.

[0048] Figure 1 is a structural diagram of a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction according to an embodiment of the present application. Please refer to Figure 1 The present application provides a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction, comprising:

[0049] a N++ GaN substrate;

[0050] a GaN drift layer located on one side surface of the N++ GaN substrate;

[0051] a super junction located on a side surface of the GaN drift layer away from the N++ GaN substrate; the super junction comprises a stepped N-type GaN drift region and a stepped P-type low-doped region, the doping concentration of the stepped N-type GaN drift region decreases from bottom to top, and the doping concentration of the stepped P-type low-doped region increases from bottom to top;

[0052] a channel region, a first P+ GaN region and a second P+ GaN region located on a surface of the super junction away from the N++ GaN substrate, the first P+ GaN region and the second P+ GaN region are respectively located on two sides of the channel region;

[0053] a first gate, a source and a second gate respectively located on a surface of the first P+ GaN region, the channel region and the second P+ GaN region away from the N++ GaN substrate, the channel region comprises at least one layer of N-- GaN region located on a surface of the stepped N-type GaN drift region away from the N++ GaN substrate, and at least one layer of N++ GaN region located on a surface of the source close to the N++ GaN substrate;

[0054] a passivation layer located between the first gate and the source and between the second gate and the source;

[0055] a drain located on a surface of the N++ GaN substrate away from the GaN drift layer.

[0056] Specifically, in the above-mentioned GaN vertical JFET device, the surface of the N++ GaN substrate away from the drain includes a super junction, the super junction structure is composed of a stepped N-type GaN drift region and a stepped P-type low-doped region, and "stepped" means that the doping concentration presents a change trend from bottom to top, wherein the doping concentration of the stepped N-type GaN drift region decreases from bottom to top, and the doping concentration of the stepped P-type low-doped region increases from bottom to top. The super junction with the stepped structure can effectively alleviate the peak electric field at the contact position of the P-type region and the N-type drift region, and improve the voltage resistance of the device.

[0057] The surface of the super junction away from the N++ GaN substrate includes a channel region, a first P+ GaN region and a second P+ GaN region, and the first P+ GaN region and the second P+ GaN region are respectively located on the left and right sides of the channel region, and the channel region includes at least one layer of N-- GaN region at the bottom and at least one layer of N++ GaN region at the top. Figure 1 It should be understood that for the GaN vertical JFET device, when the gate voltage is zero, the electrons in the N-type region are one order of magnitude lower than the holes in the P-type region, so the electrons in the N-type region are depleted by the holes in the P-type region, a space charge region is generated, and the space charge region of the N-type region is large, the two P-type regions deplete the entire N-type region channel, preventing the drain current from flowing to the source. When the gate voltage of the GaN vertical JFET device is greater than the threshold voltage, the N-type region space charge region decreases, and the drain current flows to the source. Since the threshold voltage and the forward current are related to the N-type doping concentration of the channel, in a conventional JFET device, when the N-type impurity concentration is high, the forward current is large, but the threshold voltage is low; similarly, when the N-type impurity concentration is low, the threshold voltage is high, but the forward current is small.

[0058] The embodiment introduces an ultra-low doped (N--GaN region) in the channel region, so that the threshold voltage of the device is significantly improved, and the doping concentration of the upper layer of the channel region (N++GaN region) is increased to increase the forward current, and the electric field division of the super junction uniformly distributes the electric field in the drift region, which is beneficial to reduce the electric field intensity of the contact area between the P-type region and the N-type drift region, so that the GaN vertical JFET meets the requirements of high threshold voltage, large forward current and high voltage at the same time.

[0059] Optionally, the stepped P-type low-doped region comprises a first P-type low-doped region and a second P-type low-doped region located on the two sides of the stepped N-type GaN drift region respectively; wherein the doping concentrations of the first P-type low-doped region and the second P-type low-doped region both increase from bottom to top. In the embodiment, the doping concentrations of the stepped N-type GaN drift region and the stepped P-type low-doped region are 0.7*10 16 ~1.1*10 18 cm -3 .

[0060] It should be noted that the stepped N-type GaN drift region and the stepped P-type low-doped region in the embodiment are both three-layer structures, please continue to refer to Figure 1 , the stepped N-type GaN drift region comprises three layers of N-type GaN drift regions, the first P-type low-doped region and the second P-type low-doped region each comprise three layers of P-type low-doped regions, wherein the doping concentrations of the same layer of P-type low-doped regions in the first P-type low-doped region and the second P-type low-doped region are the same. Of course, in some other embodiments of the present application, the stepped N-type GaN drift region and the stepped P-type low-doped region can also be four-layer, five-layer or the like structure, as long as the doping concentrations of the layers of N-type GaN drift regions in the stepped N-type GaN drift region decrease from bottom to top, and the doping concentrations of the layers of P-type low-doped regions in the stepped P-type low-doped region increase from bottom to top, which are not limited by the present application.

[0061] Further, in the channel region, at least one N-GaN region is included between the N--GaN region and the N++GaN region.

[0062] Specifically, the channel region comprises a plurality of N-type GaN regions from bottom to top, and as shown in the perspective view, Figure 1 the N-type GaN region at the bottom of the channel region is the N--GaN region, i.e. N-type ultra-low doped, the N-type GaN region at the top of the channel region is the N++GaN region, i.e. N-type heavy doped, and at least one N-type GaN region between them is the N-GaN region, i.e. N-type low doped. Figure 1The diagram only shows the bottommost N-GaN region and the topmost N++GaN region within the channel region. In fact, this embodiment does not limit the number of N-GaN, N-GaN and N++GaN regions. That is to say, the channel region can include several layers of N-GaN, several layers of N-GaN and several layers of N++GaN from bottom to top, as long as it shows a trend of ultra-low doping - low doping - heavy doping from bottom to top.

[0063] For example, the doping concentration of at least one N--GaN region located on the surface of the drop-type N-type GaN drift region away from the N++GaN substrate is 0.5×10⁻⁶. 15 ~1×10 17 cm -3 The doping concentration of at least one N++ GaN region located on the surface of the source electrode near the N++ GaN substrate is 1×10⁻⁶. 18 ~5×10 19 cm -3 The doping concentration of at least one N-GaN region between the N--GaN region and the N++GaN region is 3×10⁻⁶. 17 ~5×10 19 cm -3 .

[0064] Figure 2 This is a schematic flowchart illustrating a method for fabricating a gallium nitride vertical JFET device with multilayer channels and a drop-out superjunction, as provided in an embodiment of the present invention. Figures 3a-3j This is a schematic diagram illustrating the fabrication process of a gallium nitride vertical JFET device with multilayer channels and a drop-out superjunction, as provided in an embodiment of the present invention. Please refer to... Figure 2 and Figures 3a-3j This invention also provides a method for fabricating a gallium nitride vertical JFET device with multilayer channels and a drop-out superjunction, comprising:

[0065] S1. Provide an N++ GaN substrate;

[0066] S2. A GaN drift layer is deposited on one side of the N++GaN substrate.

[0067] S3. A superjunction consisting of a drop-type N-type GaN drift region and a drop-type P-type low-doped region is grown on the surface of the GaN drift layer away from the N++GaN substrate. The doping concentration of the drop-type N-type GaN drift region decreases from bottom to top, and the doping concentration of the drop-type P-type low-doped region increases from bottom to top.

[0068] S4, growing a channel region on the surface of the super junction away from the N++ GaN substrate, and etching the first preset regions at both ends of the channel region, then growing a first P+ GaN region and a second P+ GaN region in the first preset regions at both ends of the channel region respectively;

[0069] S5, thinning the N++ GaN substrate, and making a drain on the surface of the N++ GaN substrate away from the GaN drift layer;

[0070] S6, making a source on the surface of the channel region away from the N++ GaN substrate, and making a first gate and a second gate on the surfaces of the first P+ GaN region and the second P+ GaN region away from the N++ GaN substrate respectively; wherein the channel region comprises at least one layer of N-- GaN region on the surface of the stepped N-type GaN drift region away from the N++ GaN substrate, and at least one layer of N++ GaN region on the surface of the source close to the N++ GaN substrate;

[0071] S7, depositing a passivation layer on the surfaces of the first P+ GaN region, the second P+ GaN region, the first gate, the second gate and the source, then opening holes in the passivation layer on the surfaces of the source, the first gate and the second gate to lead out electrodes.

[0072] Specifically, as shown in the figure, Figures 3a-3b in steps S1-S2, first, the N++ GaN substrate is ultrasonically cleaned to eliminate surface dangling bonds, then blow-dried and heat-treated, and then a GaN drift layer with a thickness of 1-3 μm is deposited and grown on the surface of the N++ GaN substrate by metal organic chemical vapor deposition (MOCVD) process.

[0073] Optionally, in step S3, the step of growing a super junction composed of a stepped N-type GaN drift region and a stepped P-type low-doped region on the surface of the GaN drift layer away from the N++ GaN substrate comprises:

[0074] growing a plurality of layers of N-type GaN drift region on the surface of the GaN drift layer away from the N++ GaN substrate in sequence, the doping concentration of the plurality of layers of N-type GaN drift region decreasing from bottom to top;

[0075] etching the plurality of layers of N-type GaN drift region to remove the plurality of layers of N-type GaN drift region in the second preset regions at both ends, forming a stepped N-type GaN drift region;

[0076] growing a plurality of layers of P-type low-doped region in the second preset regions at both ends in sequence respectively, forming a stepped P-type low-doped region comprising a first P-type low-doped region and a second P-type low-doped region; the doping concentration of the first P-type low-doped region and the second P-type low-doped region increases from bottom to top, and the doping concentration of the same layer of P-type low-doped region in the first P-type low-doped region and the second P-type low-doped region is the same.

[0077] In this step, multiple N-type GaN drift regions with a thickness of 2 μm are sequentially grown on the surface of the GaN drift layer. The doping concentration of the multiple N-type GaN drift regions is 0.7 × 10⁻⁶. 16 ~1.1×10 18 cm -3 And decreasing from bottom to top, resulting in, as Figure 3c The epitaxial wafer shown.

[0078] Furthermore, such as Figures 3d-3e As shown, the obtained epitaxial wafer was ultrasonically cleaned in acetone for 2 minutes to remove residual organic matter on the surface, then ultrasonically cleaned in ethanol for 3 minutes, and rinsed with deionized water to remove residual acetone and ethanol, followed by drying with N2. After resist coating, photolithography was performed using inductively coupled plasma etching (ICP). A Cl2 / N2 / O2 mixed gas was introduced to etch and remove the multilayer N-type GaN drift regions in the second preset regions at both ends of the epitaxial wafer. Then, metal-organic chemical vapor deposition (MOCVD) was used to sequentially grow multiple layers of P-type low-doped regions with a thickness of 2 μm in the second preset regions at both ends, forming a first P-type low-doped region and a second P-type low-doped region. Optionally, the doping concentration in the first and second P-type low-doped regions increases from the bottom layer to the top layer, with a doping concentration of 0.7 × 10⁻⁶. 16 ~1.1×10 18 cm -3 .

[0079] Step S4, which involves growing a channel region on the surface of the superjunction away from the N++GaN substrate, etching the first preset regions at both ends of the channel region, and then growing a first P+GaN region and a second P+GaN region in the first preset regions at both ends of the channel region, includes:

[0080] Multiple N-type GaN regions are sequentially grown on the surface of the superjunction away from the N++GaN substrate to form a channel region;

[0081] After etching the channel region to remove multiple N-type GaN regions in the second preset regions at both ends of the channel region, a first P+GaN region and a second P+GaN region are grown in the second preset regions at both ends of the channel region, respectively.

[0082] Specifically, such as Figure 3f As shown, a channel region with a thickness of 1 μm to 3 μm is grown on the superjunction surface using metal-organic chemical vapor deposition (MOCVD). The channel region includes at least one N-GaN region below, at least one N++GaN region above, and at least one N-GaN region in between. Optionally, the doping concentration of the N-GaN region is 0.5 × 10⁻⁶. 15 ~1×10 17 cm -3, the doping concentration of the N-GaN region is 3x10 17 , the doping concentration of the N-GaN region is 3x10 19 cm -3 , the doping concentration of the N-GaN region is 3x10 18 , the doping concentration of the N-GaN region is 3x10 19 cm -3 .

[0083] Next, as shown in FIG. 4, the ICP (Inductively Coupled Plasma) etching process is adopted to etch and remove the plurality of N-type GaN regions in the second preset regions at both ends of the channel region, and then the MOCVD (Metal Organic Chemical Vapor Deposition) process is used to grow the first P+ GaN region and the second P+ GaN region with the same thickness as the channel region in the second preset regions at both ends. Figures 3g-3h

[0084] Please refer to FIG. 5, in steps S5-S7, the N++ GaN substrate is thinned first, and then the Ti / Al / Ni / Au metal is deposited on the surface of the N++ GaN substrate away from the GaN drift layer by the electron beam evaporation process, and high-temperature annealing is performed in the rapid annealing furnace to form a good ohmic contact with the substrate and form the drain. Similarly, the Ti / Al / Ni / Au metal is deposited on the surface of the channel region away from the N++ GaN substrate by the electron beam evaporation process, and the Ni / Au metal is deposited on the surface of the first P+ GaN region and the second P+ GaN region away from the N++ GaN substrate, and the source, the first gate and the second gate are made after high-temperature annealing. Figure 3i

[0085] Finally, as shown in FIG. 6, the PECVD (Plasma Enhanced Chemical Vapor Deposition) process is adopted to deposit SiNX or SiO2 with a thickness of about 50 nm on the source, the first gate, the second gate, the first P+ GaN region and the second P+ GaN region to form a passivation layer, wherein the N source is provided by ammonia (NH3) and the Si source is provided by silane (SiH4), so that the direct contact of the first gate\second gate and the source can be avoided, and the passivation layer above the source, the first gate and the second gate is opened to lead out the electrodes, so that the gallium nitride vertical JFET transistor with multi-layer channel and stepped super-junction as shown in FIG. 7 is obtained. Figure 3j Figure 1 is the transfer curve diagram of the conventional JFET device and the gallium nitride vertical JFET device with multi-layer channel and stepped super-junction,

[0086] Figure 4 Figure 5 ​​​​This is a graph showing the transfer curves of a conventional JFET device and a gallium nitride vertical JFET device with multilayer channels and a drop-out superjunction in a semi-logarithmic coordinate system. The horizontal axis represents voltage, and the vertical axis represents current. It should be noted that a conventional JFET device, from bottom to top, includes: a drain, a substrate on the drain surface, an N-GaN drift region on the substrate surface, a channel region on the surface of the N-GaN drift region, a first P+GaN region and a second P+GaN region on either side of the channel, a first gate on the surface of the first P+GaN region, a second gate on the surface of the second P+GaN region, and a source on the surface of the channel region.

[0087] like Figure 4 As shown, when the threshold voltage of both a conventional JFET device and a gallium nitride vertical JFET device with multilayer channels and a drop-out superjunction is 2.8V, the electron concentration in the channel region of the conventional JFET device is 0.6 × 10⁻⁶. 16 cm -3 The forward current is less than that of a gallium nitride vertical JFET device with multi-layer channels and a drop-out superjunction. For example... Figure 5 As shown, when the forward current of both a conventional JFET device and a gallium nitride vertical JFET device with multilayer channels and a drop-out superjunction is 0.6A, the channel concentration of the conventional JFET device is 2.5 × 10⁻⁶. 16 cm -3 The threshold voltage is lower than that of gallium nitride vertical JFET devices with multi-layer channels and drop-out superjunctions.

[0088] Figure 6 This is a superjunction electric field distribution diagram of a conventional JFET device. Figure 7 This is a superjunction electric field distribution diagram of a gallium nitride vertical JFET device with multi-layer channels and a drop-out superjunction. (Example:) Figures 6-7 As shown, at a voltage of 2000V, the electric field distribution of the superjunction in the drift region of the gallium nitride vertical JFET device with multi-layer channels and drop-out superjunction is more uniform, reducing the electric field intensity in the contact region between the P-type and N-type drift regions.

[0089] Figure 8 This is a comparison chart of the breakdown voltages of conventional JFET devices and gallium nitride vertical JFET devices with multi-layer channels and drop-out superjunctions. (Example:) Figure 8 As shown, the breakdown voltage of a conventional JFET device is about 1200V, while the breakdown voltage of a gallium nitride vertical JFET device with multi-layer channels and drop-out superjunctions is about 2100V, which significantly improves the breakdown voltage withstand capability.

[0090] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows:

[0091] The application provides a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction and a preparation method thereof, the device comprising: an N++ GaN substrate; a GaN drift layer located on one side surface of the N++ GaN substrate; a super junction located on the side surface of the GaN drift layer away from the N++ GaN substrate; a channel region, a first P+ GaN region and a second P+ GaN region located on the side surface of the super junction away from the N++ GaN substrate, the first P+ GaN region and the second P+ GaN region being located on two sides of the channel region respectively; a first gate, a source and a second gate located on the side surface of the first P+ GaN region, the channel region and the second P+ GaN region away from the N++ GaN substrate respectively; a passivation layer located between the first gate and the source and between the second gate and the source; and a drain located on the side surface of the N++ GaN substrate away from the GaN drift layer. In one aspect, in the super junction, the doping concentration of the stepped N-type GaN drift region decreases from bottom to top, and the doping concentration of the stepped P-type low-doped region increases from bottom to top, so that the stepped super junction can effectively relieve the peak electric field at the contact position of the P-type region and the N-type drift region, and improve the withstand voltage of the device. Compared with the prior art, by replacing the traditional drift region with a super junction with high doping concentration, the carrier concentration of the conductive region can be improved, the electric energy loss can be reduced, the forward characteristics (reduced on-resistance) and the reverse characteristics (improved breakdown voltage) of the JFET device are simultaneously improved, and the power quality factor is significantly improved. In addition, the stepped super junction made below the P-type region is beneficial to improve the avalanche capability of the device, so that the device is safer and more reliable under extreme conditions.

[0092] In another aspect, the device channel region comprises at least one N-- GaN region located on the side surface of the stepped N-type GaN drift region away from the N++ GaN substrate, and at least one N++ GaN region located on the side surface of the source close to the N++ GaN substrate. By introducing a super-low-doped (N-- GaN region) in the channel region, the threshold voltage of the device can be significantly improved, and at the same time, the forward current is increased by increasing the doping concentration (N++ GaN region) of the upper layer of the channel region, and the electric field distribution is uniform in the drift region due to the electric field voltage division of the super junction, which is beneficial to reduce the electric field intensity of the contact area of the P-type region and the N-type drift region, so as to obtain a GaN vertical JFET satisfying high threshold voltage, large forward current and high withstand voltage at the same time. In the description of the application, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0093] Reference to terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc., mean that a particular feature, structure, material or characteristic being described is included in at least one embodiment or example of the present application. The appearances of the above-described terms in various places in the specification are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples. Also, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art will appreciate that the described particular features, structures, materials, or characteristics can be combined in any suitable manner in other combinations of one or more embodiments or examples without necessarily being mutually exclusive.

[0094] The above description is further to the present application in conjunction with specific preferred embodiments, and cannot be deemed to limit the specific implementation of the present application to these descriptions. For those skilled in the art, a number of simple deductions or replacements can be made without departing from the concept of the present application, and all of them shall be deemed to fall within the protection scope of the present application.

Claims

1. A gallium nitride vertical JFET device having a multi-layer channel and staggered super-junctions, characterized in that, The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The doping concentration of at least one N-- GaN region located on the surface of the N-type GaN drift region away from the N++ GaN substrate is 0.5 × 10⁻⁶. 15 ~1×10 17 cm -3 The doping concentration of at least one N++ GaN region located on the surface of the source electrode near the N++ GaN substrate is 1×10⁻⁶. 18 ~5×10 19 cm -3 .

2. The GaN vertical JFET device with multi-layered channel and staggered super-junction of claim 1, wherein, The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction.

3. The GaN vertical JFET device with multi-layered channel and staggered super-junction of claim 2, wherein, The doping concentration of the stepped N-type GaN drift region and the stepped P-type low-doped region is 0.7 x 10 16 1.1 x 10 18 cm -3 .

4. The GaN vertical JFET device with multi-layered channel and staggered super-junction of claim 2, wherein, The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction.

5. The GaN vertical JFET device with multi-layered channel and staggered super-junction of claim 1, wherein, The doping concentration of at least one layer of N- GaN region between the N- GaN region and the N++ GaN region is 3 x 10 17 5 x 10 19 cm -3 .

6. A method for fabricating a gallium nitride vertical JFET device with multi-layered channel and staggered super-junction, comprising: The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super junction. The application relates to a gallium nitride vertical JFET device with a multi-layer channel and a stepped super thinning the N++ GaN substrate and making a drain on the surface of the N++ GaN substrate away from the GaN drift layer; making a source on the surface of the channel region away from the N++ GaN substrate, and making a first gate and a second gate on the surfaces of the first P+ GaN region and the second P+ GaN region away from the N++ GaN substrate respectively; wherein the channel region comprises at least one layer of N-- GaN region on the surface of the stepped N-type GaN drift region away from the N++ GaN substrate, and at least one layer of N++ GaN region on the surface of the source close to the N++ GaN substrate; after depositing a passivation layer on the surfaces of the first P+ GaN region, the second P+ GaN region, the first gate, the second gate and the source, opening holes in the passivation layer on the surfaces of the source, the first gate and the second gate to lead out electrodes.

7. The method of claim 6, wherein the method further comprises: the step of growing a super junction composed of a stepped N-type GaN drift region and a stepped P-type low-doped region on the surface of the GaN drift layer away from the N++ GaN substrate, comprises: growing a plurality of layers of N-type GaN drift region on the surface of the GaN drift layer away from the N++ GaN substrate in sequence, wherein the doping concentration of the plurality of layers of N-type GaN drift region decreases from bottom to top; etching the plurality of layers of N-type GaN drift region to remove the plurality of layers of N-type GaN drift region in the second preset region at both ends, thereby forming a stepped N-type GaN drift region; growing a plurality of layers of P-type low-doped region in the second preset region at both ends in sequence, thereby forming a stepped P-type low-doped region comprising a first P-type low-doped region and a second P-type low-doped region; the doping concentration of the first P-type low-doped region and the second P-type low-doped region increases from bottom to top, and the doping concentration of the same layer of P-type low-doped region in the first P-type low-doped region and the second P-type low-doped region is the same.

8. The method of claim 6, wherein the method further comprises: after growing a channel region on the surface of the super junction away from the N++ GaN substrate and etching the first preset region at both ends of the channel region, the step of growing a first P+ GaN region and a second P+ GaN region in the first preset region at both ends of the channel region, comprises: growing a plurality of layers of N-type GaN region on the surface of the super junction away from the N++ GaN substrate in sequence, thereby forming a channel region; after etching the plurality of layers of N-type GaN region in the second preset region at both ends of the channel region, growing a first P+ GaN region and a second P+ GaN region in the second preset region at both ends of the channel region.

Images