A piezoelectric MEMS accelerometer with integrated temperature detection and preparation method thereof

Abstract

The present application provides a piezoelectric MEMS accelerometer with integrated temperature detection and a preparation method. The piezoelectric MEMS accelerometer integrates in-situ temperature detection, which is a chip-level integration. By integrating a resistor Pt layer as a temperature detection element on the same chip, the in-situ temperature detection function of the accelerometer is realized, which helps to perceive the temperature changes in the working environment of the accelerometer in real time, and then calibrate and compensate the errors caused by temperature in real time through software algorithms or hardware circuits, significantly improving the measurement accuracy. In addition, by graphing the same metal platinum layer, the bottom electrode Pt layer for measuring acceleration and the resistor Pt layer for in-situ temperature detection can be obtained at the same time, which reduces the steps in the manufacturing process, simplifies the process flow, and saves space on the chip.

Description

Technical Field

[0001] The present application relates to the field of MEMS technology, and in particular to a piezoelectric MEMS accelerometer with integrated temperature detection and a preparation method thereof. Background Art

[0002] The high sensitivity of MEMS accelerometers to temperature changes is an important technical challenge. This sensitivity stems from the thermal properties of their internal micromechanical structures and electronic components. When the ambient temperature changes, the material of the MEMS accelerometer will expand and contract, and the piezoelectric coefficient and other properties of the piezoelectric material will change with temperature. At the same time, the performance of components such as resistors and capacitors in the circuit will also be affected. These factors together lead to a decrease in the measurement accuracy of the accelerometer.

[0003] Existing MEMS accelerometers, due to the lack of in-situ temperature detection function, cannot sense and compensate for errors caused by temperature changes in real time. This means that in an environment with large temperature changes, the measured value of the accelerometer will deviate from the true value, affecting the overall performance of the system. The impact of temperature on MEMS accelerometers is not limited to static parameters such as zero offset and sensitivity, but may also affect dynamic parameters such as dynamic response and frequency characteristics. The lack of temperature detection means that these dynamic changes cannot be accurately compensated, thereby limiting the measurement accuracy and application range of the accelerometer. Temperature changes may also aggravate the uneven distribution of stress inside the MEMS accelerometer, leading to structural fatigue and performance degradation. Long-term operation in an environment with large temperature changes may shorten the service life of the accelerometer and reduce its reliability. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a piezoelectric MEMS accelerometer with integrated temperature detection and a preparation method thereof, so as to solve the problem that the existing MEMS accelerometer has no in-situ temperature detection function, resulting in reduced measurement accuracy.

[0005] An embodiment of the present application provides a method for preparing a piezoelectric MEMS accelerometer with integrated temperature detection, wherein the piezoelectric MEMS accelerometer includes a vibration sensitive structure, a frame structure, and a cantilever beam structure. The method includes:

[0006] Growing isolation layers on the front and back of the SOI substrate, depositing a metal platinum layer on the isolation layer on the front of the SOI substrate, and depositing a piezoelectric layer on the metal platinum layer; wherein the front of the SOI substrate is a device layer, the middle layer of the SOI substrate is a buried oxide layer, and the back of the SOI substrate is a support layer;

[0007] patterning the piezoelectric layer;

[0008] The metal platinum layer is patterned to form a bottom electrode Pt layer and a resistor Pt layer; wherein the bottom electrode Pt layer is used to measure acceleration, and the resistor Pt layer is used for in-situ temperature detection;

[0009] preparing a patterned top electrode layer on the piezoelectric layer;

[0010] Patterning the isolation layer and the device layer on the front side of the SOI substrate to form a vibration sensitive structure and a frame structure;

[0011] Etching the isolation layer on the back side of the SOI substrate, and etching the support layer from the back side of the SOI substrate to a set depth to form a mass block structure; wherein the set depth is less than the thickness of the support layer;

[0012] The isolation layer and the support layer on the back side of the SOI substrate are etched to form a cantilever structure.

[0013] In the above technical solution, the piezoelectric MEMS accelerometer integrates in-situ temperature detection, which is a chip-level integration. By integrating the resistor Pt layer as a temperature detection element on the same chip, the in-situ temperature detection function of the accelerometer is realized, which helps to perceive the temperature changes in the working environment of the accelerometer in real time, and then calibrate and compensate the errors caused by temperature in real time through software algorithms or hardware circuits, significantly improving the measurement accuracy. In addition, by graphing the same metal platinum layer, the bottom electrode Pt layer for measuring acceleration and the resistor Pt layer for in-situ temperature detection can be obtained at the same time, which reduces the steps in the manufacturing process, simplifies the process flow, and saves space on the chip. Since the temperature detection resistor is located on the same chip as the other parts of the accelerometer and is very close, it can more accurately reflect the temperature changes in the actual working environment of the accelerometer. Since the bottom electrode and the temperature detection resistor are made of the same material (metal platinum) and are located on the same layer, the thermal stress difference between them is small, which helps to reduce the risk of mechanical failure caused by thermal stress and improve the long-term reliability of the product.

[0014] In some optional embodiments, depositing a metal platinum layer on the isolation layer on the front side of the SOI substrate comprises:

[0015] Growing silicon oxide as an isolation layer on the front and back sides of the SOI substrate by thermal oxidation;

[0016] On the isolation layer on the front side of the SOI substrate, titanium is sputtered, or titanium is sputtered and then annealed with oxygen to form titanium oxide, thereby forming an adhesion layer;

[0017] On the adhesion layer, metal platinum is deposited by sputtering to form a metal platinum layer.

[0018] In the above technical solution, titanium is first sputtered on the silicon oxide isolation layer, or titanium is sputtered and then oxygen-containing annealing is performed to form titanium oxide, thereby forming an adhesion layer. This step significantly enhances the adhesion between the metal platinum layer and the isolation layer below. Good adhesion is the key to ensuring that the metal platinum layer is not easy to fall off or crack during subsequent processing and use. The metal platinum layer deposited by sputtering on the adhesion layer can form a more uniform, dense and firmly attached platinum layer due to the presence of the adhesion layer.

[0019] In some optional embodiments, depositing a piezoelectric layer on the metal platinum layer comprises:

[0020] On the metallic platinum layer, a buffer layer is deposited by sputtering;

[0021] On the buffer layer, PZT is sputter-deposited to form a piezoelectric layer.

[0022] In the above technical solution, the introduction of the buffer layer helps to improve the interface bonding between the metal platinum layer and the piezoelectric layer (PZT), and reduce the interface defects or delamination that may be caused by differences in material properties. The buffer layer can provide a smooth transition interface, enhance the adhesion between the two, and induce the PZT material to grow in a fixed crystal phase, improve the film quality, and ensure the piezoelectric performance, thereby improving the stability and reliability of the overall structure.

[0023] In some optional embodiments, the piezoelectric layer is patterned, including:

[0024] Coating a photoresist on the front side of the substrate and patterning the photoresist;

[0025] Etching away the portions of the piezoelectric layer and the buffer layer that are not shielded by the photoresist;

[0026] Clean off the remaining photoresist.

[0027] In the above technical solution, first ensure that the substrate surface is clean, flat and free of contaminants. This may require processes such as organic cleaning or plasma treatment to optimize the adhesion of the subsequent photoresist. A layer of photoresist is evenly coated on the front of the substrate by spin coating, spray coating or dip coating. After the photoresist is coated, a soft bake is performed. The purpose of this step is to remove the solvent in the photoresist, solidify it and adhere it to the surface of the substrate, and at the same time improve the adhesion of the photoresist to the substrate, in preparation for the subsequent exposure and development process. Using a precision photolithography machine, the designed pattern (usually achieved through a mask) is projected onto the photoresist. During the exposure process, the area of ​​the photoresist exposed to ultraviolet light will undergo a chemical reaction, and its properties (such as solubility) will change. For positive photoresists, the exposed part of the positive photoresist will become more soluble after being exposed to ultraviolet light, while for negative photoresists, the exposed part of the negative photoresist will undergo a cross-linking reaction after being exposed to ultraviolet light, making the part insoluble. After exposure, the substrate is placed in a developer to remove part of the photoresist and form the desired graphic profile. After development, a hard bake may be performed to further solidify the photoresist, enhance its etch resistance and corrosion resistance, and provide better protection for dry etching or wet etching steps. The piezoelectric layer and buffer layer that are not shielded by the photoresist are etched by dry etching or wet etching, such as using ICP dry etching of PZT.

[0028] In some optional embodiments, the metal platinum layer is patterned to form a bottom electrode Pt layer and a resistor Pt layer, including:

[0029] Coating a photoresist on the front side of the substrate and patterning the photoresist;

[0030] Etching away the portion of the metal platinum layer and the adhesion layer not shielded by the photoresist to form a bottom electrode Pt layer and a resistor Pt layer; for example, etching Pt by dry etching IBE;

[0031] Clean off the remaining photoresist.

[0032] In some optional embodiments, a patterned top electrode layer is prepared on the piezoelectric layer, comprising:

[0033] Coating a photoresist on the front side of the substrate and patterning the photoresist;

[0034] evaporating a metal adhesion layer on the piezoelectric layer and the photoresist;

[0035] vapor depositing a metal electrode layer on the metal adhesion layer;

[0036] The photoresist and the metal adhesion layer and the metal electrode layer thereon are stripped off to form a top electrode layer and a PAD.

[0037] In the above technical solution, first, a photoresist compatible with the subsequent metal evaporation process is selected, and a layer of photoresist is evenly coated on the surface of the piezoelectric layer by spin coating, spray coating or dip coating. The thickness and uniformity of the photoresist are controlled to meet the accuracy requirements of the patterning. The substrate coated with the photoresist is placed on a heating plate for pre-baking to remove the solvent in the photoresist, so that it solidifies and adheres closely to the surface of the piezoelectric layer. At the same time, the adhesion between the photoresist and the substrate is improved to lay the foundation for the subsequent steps. Using a precision photolithography machine, the designed top electrode pattern is projected onto the photoresist through a mask. After exposure, the substrate is placed in a developer to remove part of the photoresist to form the desired graphic contour. On the substrate after the photoresist is patterned, a thin metal adhesion layer (such as titanium) is first evaporated. The main function of this layer of metal is to enhance the adhesion between the subsequent metal electrode layer and the piezoelectric layer to prevent the electrode from falling off or stratification. On the metal adhesion layer, the required metal electrode layer (such as gold) is continued to be evaporated. The selection of the metal electrode layer needs to consider its conductivity, corrosion resistance and compatibility with other materials. The temperature, pressure and evaporation rate must be strictly controlled during the evaporation process to ensure the uniformity and density of the metal layer. Use chemical strippers or physical stripping methods (such as ultrasonic stripping) to peel the photoresist and the metal adhesion layer and metal electrode layer on it from the non-patterned area. This step requires careful operation to avoid damage to the metal electrode layer in the patterned area. After stripping, the substrate is thoroughly cleaned with deionized water, organic solvents or special cleaning agents to remove all residues. Then, the substrate is placed in a dryer for drying to remove moisture and ensure a clean and dry surface.

[0038] In some optional implementations, the isolation layer and the device layer on the front side of the SOI substrate are patterned to form a vibration sensitive structure and a frame structure, including:

[0039] Coating a photoresist on the front side of the substrate and patterning the photoresist;

[0040] Etching away the isolation layer and the device layer on the front side of the SOI substrate that are not shielded by the photoresist to form a vibration sensitive structure and a frame structure;

[0041] Clean off the remaining photoresist.

[0042] In the above technical solution, according to the material properties of the isolation layer and the device layer, a suitable etching process is selected, such as wet etching, dry etching (such as reactive ion etching RIE, deep reactive ion etching DRIE) or a combination of the two. The isolation layer and device layer materials on the front side of the SOI substrate that are not shielded by the photoresist are accurately removed by the etching process to form a designed vibration sensitive structure and frame structure.

[0043] In some optional embodiments, etching the isolation layer on the back side of the SOI substrate, and etching the support layer from the back side of the SOI substrate to a set depth to form a mass block structure, comprising:

[0044] A front protection structure is provided on the front side of the substrate;

[0045] Coating a photoresist on the back side of the substrate and patterning the photoresist;

[0046] Etching away the isolation layer on the back side of the SOI substrate that is not shielded by the photoresist and the support layer of a set depth to form a mass block structure;

[0047] Clean off the remaining photoresist.

[0048] In the above technical solution, before processing the back side of the substrate, a front protection structure is first provided on the front side of the substrate to protect the front side structure of the substrate from damage during the subsequent back side processing. The isolation layer on the back side of the SOI substrate not shielded by the photoresist and the support layer of the set depth are removed by using the selected etching process. Specifically, the etching depth can be controlled by controlling the etching rate and etching time.

[0049] In some optional implementations, etching the isolation layer and the support layer on the back side of the SOI substrate to form a cantilever structure includes:

[0050] Coating a photoresist on the back side of the substrate and patterning the photoresist;

[0051] Etching away the isolation layer and the support layer on the back side of the SOI substrate that are not shielded by the photoresist;

[0052] Clean off the remaining photoresist;

[0053] releasing silicon oxide on the back side of the substrate to form a cantilever beam structure;

[0054] Remove the front protection structure.

[0055] In the above technical solution, the isolation layer and buried oxide layer of the SOI substrate are both silicon oxide (SiO2), and the silicon oxide on the back of the substrate is released by wet etching BOE or dry etching RIE or vapor etching VHF. After the back processing is completed and the cantilever structure is formed, it is necessary to remove the front protection structure set up to protect the front of the substrate during the processing.

[0056] An embodiment of the present application provides a piezoelectric MEMS accelerometer with integrated temperature detection, comprising: a vibration sensitive structure, a frame structure and a cantilever structure; the vibration sensitive structure comprises a bottom electrode Pt layer for measuring acceleration, and the frame structure comprises a resistor Pt layer for in-situ temperature detection; the bottom electrode Pt layer and the resistor Pt layer are obtained by patterning the same metal platinum layer.

[0057] In the above technical solution, the accelerometer can not only measure acceleration, but also detect temperature in situ through the resistor Pt layer. By detecting the temperature in real time, the acceleration measurement result can be temperature compensated to eliminate the influence of temperature on the measurement result, thereby improving the measurement accuracy. The bottom electrode Pt layer and the resistor Pt layer of the accelerometer are obtained by patterning the same metal platinum layer. This design reduces the steps in the manufacturing process, simplifies the process flow, saves space on the chip, and achieves miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1 A flowchart of the steps of a method for preparing a piezoelectric MEMS accelerometer with integrated temperature detection provided in an embodiment of the present application;

[0060] Figure 2 Schematic diagram of the SOI substrate provided in the embodiment of the present application;

[0061] Figure 3 A schematic diagram of a substrate after being processed in step 100 provided in an embodiment of the present application;

[0062] Figure 4 A schematic diagram of a substrate after being processed in step 200 provided in an embodiment of the present application;

[0063] Figure 5 A schematic diagram of a substrate after being processed in step 300 provided in an embodiment of the present application;

[0064] Figure 6 A schematic diagram of a substrate after being processed in step 400 provided in an embodiment of the present application;

[0065] Figure 7 A schematic diagram of a substrate after being processed in step 500 provided in an embodiment of the present application;

[0066] Figure 8 A schematic diagram of a substrate after being processed in step 600 provided in an embodiment of the present application;

[0067] Fig. 9 A schematic diagram of a substrate after being processed in step 700 provided in an embodiment of the present application;

[0068] Fig.10A top view of a piezoelectric MEMS accelerometer with integrated temperature detection provided in an embodiment of the present application;

[0069] Fig.11 A bottom view of a piezoelectric MEMS accelerometer with integrated temperature detection provided in an embodiment of the present application;

[0070] Fig.12 A B'-B cross-sectional schematic diagram of a piezoelectric MEMS accelerometer with integrated temperature detection provided in an embodiment of the present application;

[0071] Fig.13 A C'-C cross-sectional schematic diagram of a piezoelectric MEMS accelerometer with integrated temperature detection provided in an embodiment of the present application.

[0072] Icons: 1- vibration sensitive structure, 2- frame structure, 3- cantilever beam structure. DETAILED DESCRIPTION

[0073] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0074] Please refer to Figure 1 , Figure 1 A flowchart of a method for preparing a piezoelectric MEMS accelerometer with integrated temperature detection provided in an embodiment of the present application, wherein the piezoelectric MEMS accelerometer comprises a vibration sensitive structure 1, a frame structure 2 and a cantilever beam structure 3, and the method comprises:

[0075] Step 100, growing isolation layers on the front and back of the SOI substrate, depositing a metal platinum layer on the isolation layer on the front of the SOI substrate, and depositing a piezoelectric layer on the metal platinum layer; wherein the front of the SOI substrate is a device layer, the middle layer of the SOI substrate is a buried oxide layer, and the back of the SOI substrate is a support layer;

[0076] Specifically, high-quality isolation layers are deposited on both sides of the SOI (Silicon-On-Insulator) substrate through precise thin film growth technology. The selection of the front isolation layer needs to consider its compatibility with the subsequent functional layer and its ability to protect the device layer. Usually, insulating materials such as silicon oxide (SiO2) or silicon nitride (Si3N4) are selected to ensure the electrical isolation between the device layer (i.e., the top silicon of SOI) and the subsequent metal and piezoelectric layers. The back isolation layer focuses on the protection of the support layer and the stability during the subsequent processing. Subsequently, a layer of metal platinum (Pt) is uniformly deposited on top of the front isolation layer using advanced processes such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). Platinum is selected as the material for the bottom electrode and resistor layer because of its good conductivity, stability and compatibility with piezoelectric materials. Next, a layer of piezoelectric material, such as lead zirconate titanate (PZT) or scandium-doped aluminum nitride (ScAlN), is deposited on top of the platinum layer by precisely controlling the deposition parameters. These materials generate electric charge when subjected to stress and are the key to achieving acceleration sensing.

[0077] Step 200, patterning the piezoelectric layer;

[0078] Specifically, the piezoelectric layer is finely patterned using photolithography and wet or dry etching techniques to form preset piezoelectric active areas, which will directly participate in the acceleration measurement process.

[0079] Step 300, patterning the metal platinum layer to form a bottom electrode Pt layer and a resistor Pt layer; wherein the bottom electrode Pt layer is used to measure acceleration, and the resistor Pt layer is used for in-situ temperature detection;

[0080] Specifically, the metal platinum layer is further patterned and subdivided into a bottom electrode Pt layer and a resistor Pt layer. The bottom electrode Pt layer is designed with a specific pattern to ensure effective contact with the piezoelectric layer to collect the piezoelectric signal caused by acceleration and realize acceleration measurement. The resistor Pt layer uses a sophisticated resistor network design to utilize the temperature resistance effect of platinum to achieve in-situ temperature detection, thereby improving the environmental adaptability and measurement accuracy of the sensor.

[0081] Step 400: preparing a patterned top electrode layer on the piezoelectric layer;

[0082] Specifically, a patterned top electrode layer is prepared above the piezoelectric layer by evaporation, sputtering or electroplating. The design of the top electrode layer needs to be coordinated with the bottom electrode layer to form a complete capacitor structure for extracting the charge signal generated by the piezoelectric layer.

[0083] Step 500: patterning the isolation layer and the device layer on the front side of the SOI substrate to form a vibration sensitive structure 1 and a frame structure 2;

[0084] Specifically, advanced micromachining techniques, such as deep reactive ion etching (DRIE) or reactive ion etching (RIE), are used to pattern the isolation layer and the device layer on the front side of the SOI substrate to form a vibration sensitive structure 1 having specific vibration characteristics and a frame structure 2 supporting the vibration sensitive structure.

[0085] Step 600, etching the isolation layer on the back side of the SOI substrate, and etching the support layer from the back side of the SOI substrate to a set depth to form a mass block structure; wherein the set depth is less than the thickness of the support layer;

[0086] Specifically, starting from the back side of the SOI substrate, the isolation layer on the back side is first etched away to expose the support layer, and then a groove of a set depth is etched from the support layer using a precisely controlled etching process to form a mass block structure.

[0087] Step 700 : Etch the isolation layer and the support layer on the back side of the SOI substrate to form a cantilever beam structure 3 .

[0088] Specifically, the isolation layer and the remaining support layer on the back side of the SOI substrate are further processed to form a cantilever structure 3 connecting the mass block and the fixed part.

[0089] In the embodiment of the present application, the piezoelectric MEMS accelerometer integrates in-situ temperature detection, which is a chip-level integration. By integrating the resistor Pt layer as a temperature detection element on the same chip, the in-situ temperature detection function of the accelerometer is realized, which helps to perceive the temperature changes in the working environment of the accelerometer in real time, and then calibrate and compensate the errors caused by temperature in real time through software algorithms or hardware circuits, significantly improving the measurement accuracy. In addition, by graphing the same metal platinum layer, the bottom electrode Pt layer for measuring acceleration and the resistor Pt layer for in-situ temperature detection can be obtained at the same time, which reduces the steps in the manufacturing process, simplifies the process flow, and saves space on the chip. Since the temperature detection resistor is located on the same chip as the other parts of the accelerometer and is very close, it can more accurately reflect the temperature changes in the actual working environment of the accelerometer. Since the bottom electrode and the temperature detection resistor are made of the same material (metal platinum) and are located on the same layer, the thermal stress difference between them is small, which helps to reduce the risk of mechanical failure caused by thermal stress and improve the long-term reliability of the product.

[0090] In the actual preparation process, step 700 should also include:

[0091] Step 800: Correct the resistance value of the resistor Pt layer used for in-situ temperature detection through laser trimming.

[0092] In this embodiment, Pt (platinum) resistors are often used as the core components of temperature sensors due to their good stability and accuracy. However, during the preparation process, the resistance value of the Pt layer may deviate slightly from the design value. Through laser trimming technology, the resistance value of the Pt layer can be accurately adjusted to ensure that the temperature detection accuracy of each product meets the design requirements, thereby improving the overall product quality and reliability.

[0093] Please refer to Figure 2 , Figure 2 A schematic diagram of an SOI substrate provided in an embodiment of the present application, wherein the SOI substrate comprises: a Si device layer with a thickness of 1 to 50 um, a SiO2 buried oxide layer with a thickness of 0.3 to 5 um, and a Si support layer with a thickness of 400 to 800 um.

[0094] Please refer to Figure 3 , Figure 3 A schematic diagram of a substrate after post-processing in step 100 provided in an embodiment of the present application, Figure 3 This is the cross-sectional view of the substrate at section A'-A. For section A'-A, please refer to Fig.10 In this embodiment, a metal platinum layer is deposited on the isolation layer on the front side of the SOI substrate, specifically comprising:

[0095] Silicon oxide with a thickness of 50 to 2000 nm is grown on the front and back sides of the SOI substrate by thermal oxidation as an isolation layer;

[0096] On the isolation layer on the front side of the SOI substrate, titanium oxide or titanium with a thickness of 10 to 100 nm is sputtered to form an adhesion layer;

[0097] On the adhesion layer, metal platinum is deposited by sputtering to a thickness of 50 to 400 nm to form a metal platinum layer.

[0098] In the embodiments of the present application, titanium is first sputtered on the silicon oxide isolation layer, or titanium is sputtered and then oxygen-containing annealing is performed to form titanium oxide, thereby forming an adhesion layer. This step significantly enhances the adhesion between the metal platinum layer and the isolation layer below. Good adhesion is the key to ensuring that the metal platinum layer is not easy to fall off or crack during subsequent processing and use. The metal platinum layer deposited by sputtering on the adhesion layer can form a more uniform, dense and firmly attached platinum layer due to the presence of the adhesion layer.

[0099] In this embodiment, a piezoelectric layer is deposited on the metal platinum layer, including: depositing a buffer layer with a thickness of 30-300 nm by sputtering on the metal platinum layer; and sputtering depositing PZT with a thickness of 0.2-5 um on the buffer layer to form a piezoelectric layer.

[0100] In the embodiment of the present application, the introduction of the buffer layer helps to improve the interface bonding between the metal platinum layer and the piezoelectric layer (PZT), and reduce the interface defects or delamination phenomena that may be caused by differences in material properties. The buffer layer can provide a smooth transition interface, enhance the adhesion between the two, and can also induce the PZT material to grow in a fixed crystal phase, improve the film quality, and ensure the piezoelectric performance, thereby improving the stability and reliability of the overall structure.

[0101] Please refer to Figure 4 , Figure 4 A schematic diagram of a substrate after post-processing in step 200 provided in an embodiment of the present application, Figure 4 This is the cross-sectional view of the substrate at section A'-A. For section A'-A, please refer to Fig.10 In this embodiment, the piezoelectric layer is patterned, including: coating a photoresist on the front side of the substrate and patterning the photoresist; etching away the portions of the piezoelectric layer and the buffer layer that are not shielded by the photoresist; and cleaning away the remaining photoresist.

[0102] In the embodiment of the present application, first ensure that the substrate surface is clean, flat and free of pollutants. This may require processes such as organic cleaning or plasma treatment to optimize the adhesion of the subsequent photoresist. A layer of photoresist is evenly coated on the front of the substrate by spin coating, spray coating or dip coating. After the photoresist is coated, soft baking is performed. The purpose of this step is to remove the solvent in the photoresist, solidify it and adhere to the substrate surface, and at the same time improve the adhesion of the photoresist to the substrate, so as to prepare for the subsequent exposure and development process. A precision photolithography machine is used to project the designed pattern (usually realized by a mask) onto the photoresist. During the exposure process, a chemical reaction will occur in the area where the photoresist is irradiated with ultraviolet light, and its properties (such as solubility) will change. For positive photoresist, after being exposed to ultraviolet light, the exposed part of the positive photoresist will become more soluble, while, for negative photoresist, after being exposed to ultraviolet light, the exposed part of the negative photoresist will undergo a cross-linking reaction, making the part insoluble. After exposure, the substrate is placed in a developer to remove part of the photoresist and form the desired graphic profile. After development, a hard bake may be performed to further solidify the photoresist, enhance its etch resistance and corrosion resistance, and provide better protection for dry etching or wet etching steps. The piezoelectric layer and buffer layer that are not shielded by the photoresist are etched by dry etching or wet etching, such as using ICP dry etching of PZT.

[0103] Please refer to Figure 5 , Figure 5 A schematic diagram of a substrate after post-processing in step 300 provided in an embodiment of the present application, Figure 5 This is the cross-sectional view of the substrate at section A'-A. For section A'-A, please refer to Fig.10In this embodiment, the metal platinum layer is patterned to form a bottom electrode Pt layer and a resistor Pt layer, including: coating a photoresist on the front side of the substrate and patterning the photoresist; etching away the portions of the metal platinum layer and the adhesion layer that are not shielded by the photoresist to form a bottom electrode Pt layer and a resistor Pt layer; and cleaning away the remaining photoresist.

[0104] Please refer to Figure 6 , Figure 6 A schematic diagram of a substrate after post-processing in step 400 provided in an embodiment of the present application, Figure 6 This is the cross-sectional view of the substrate at section A'-A. For section A'-A, please refer to Fig.10 In this embodiment, a patterned top electrode layer is prepared on the piezoelectric layer, including: coating a photoresist on the front side of the substrate and patterning the photoresist; evaporating a metal adhesion layer of titanium or chromium with a thickness of 10 to 60 nm on the piezoelectric layer and the photoresist; evaporating a metal electrode layer of Au with a thickness of 100 to 900 nm on the metal adhesion layer; and stripping the photoresist and the metal adhesion layer and the metal electrode layer thereon to form a top electrode layer and a PAD.

[0105] In the embodiment of the present application, first, a photoresist compatible with the subsequent metal evaporation process is selected, and a layer of photoresist is evenly coated on the surface of the piezoelectric layer by spin coating, spray coating or dip coating. The thickness and uniformity of the photoresist are controlled to meet the accuracy requirements of the patterning. The substrate coated with the photoresist is placed on a heating plate for pre-baking treatment to remove the solvent in the photoresist, so that it is solidified and closely attached to the surface of the piezoelectric layer. At the same time, the adhesion between the photoresist and the substrate is improved, laying the foundation for the subsequent steps. Using a precision photolithography machine, the designed top electrode pattern is projected onto the photoresist through a mask. After exposure, the substrate is placed in a developer to remove part of the photoresist to form the desired graphic profile. On the substrate after the photoresist is patterned, a thin metal adhesion layer (such as titanium) is first evaporated. The main function of this layer of metal is to enhance the adhesion between the subsequent metal electrode layer and the piezoelectric layer to prevent the electrode from falling off or stratification. On the metal adhesion layer, the required metal electrode layer (such as gold) is continued to be evaporated. The selection of the metal electrode layer needs to consider its conductivity, corrosion resistance and compatibility with other materials. The temperature, pressure and evaporation rate must be strictly controlled during the evaporation process to ensure the uniformity and density of the metal layer. Use chemical strippers or physical stripping methods (such as ultrasonic stripping) to peel the photoresist and the metal adhesion layer and metal electrode layer on it from the non-patterned area. This step requires careful operation to avoid damage to the metal electrode layer in the patterned area. After stripping, the substrate is thoroughly cleaned with deionized water, organic solvents or special cleaning agents to remove all residues. Then, the substrate is placed in a dryer for drying to remove moisture and ensure a clean and dry surface.

[0106] Please refer to Figure 7 , Figure 7 A schematic diagram of a substrate after post-processing in step 500 provided in an embodiment of the present application, Figure 7 This is the cross-sectional view of the substrate at section A'-A. For section A'-A, please refer to Fig.10 In this embodiment, the isolation layer and the device layer on the front side of the SOI substrate are patterned to form a vibration sensitive structure 1 and a frame structure 2, including: coating a photoresist on the front side of the substrate and patterning the photoresist; etching away the isolation layer and the device layer on the front side of the SOI substrate that are not shielded by the photoresist to form a vibration sensitive structure 1 and a frame structure 2; and cleaning away the remaining photoresist.

[0107] In the embodiment of the present application, according to the material properties of the isolation layer and the device layer, a suitable etching process is selected, such as wet etching, dry etching (such as reactive ion etching RIE, deep reactive ion etching DRIE) or a combination of the two. The isolation layer and the device layer material on the front side of the SOI substrate that are not shielded by the photoresist are precisely removed by the etching process to form the designed vibration sensitive structure 1 and the frame structure 2.

[0108] Please refer to Figure 8 , Figure 8 A schematic diagram of a substrate after post-processing in step 600 provided in an embodiment of the present application, Figure 8 This is the cross-sectional view of the substrate at the B'-B section. Please refer to the B'-B section. Fig.10 In this embodiment, the isolation layer on the back side of the SOI substrate is etched, and the support layer is etched from the back side of the SOI substrate to a set depth to form a mass block structure, including:

[0109] A front protection structure is set on the front side of the substrate; a photoresist is coated on the back side of the substrate and the photoresist is patterned; an isolation layer on the back side of the SOI substrate not shielded by the photoresist and a support layer of a set depth are etched away to form a mass block structure; and the remaining photoresist is cleaned away.

[0110] In the embodiment of the present application, before processing the back side of the substrate, a front side protection structure is first provided on the front side of the substrate to protect the front side structure of the substrate from being damaged during the subsequent back side processing. The isolation layer on the back side of the SOI substrate not shielded by the photoresist and the support layer of the set depth are accurately removed by using the selected etching process. Specifically, the etching depth can be controlled by controlling the etching rate and etching time.

[0111] Please refer to Fig. 9 , Fig. 9 A schematic diagram of a substrate after post-processing in step 700 provided in an embodiment of the present application, Fig. 9 This is the cross-sectional view of the substrate at the B'-B section. Please refer to the B'-B section. Fig.10 In this embodiment, the isolation layer and the support layer on the back of the SOI substrate are etched to form a cantilever structure 3, including:

[0112] Coat photoresist on the back of the substrate and pattern the photoresist; etch away the isolation layer and the support layer on the back of the SOI substrate that are not shielded by the photoresist; clean off the remaining photoresist; release the silicon oxide on the back of the substrate to form a cantilever structure 3; and remove the front protection structure.

[0113] In the embodiment of the present application, the isolation layer and the buried oxide layer of the SOI substrate are both silicon oxide (SiO2), and the silicon oxide on the back side of the substrate is released by wet etching BOE or dry etching RIE or vapor etching VHF. After the back side processing is completed and the cantilever structure 3 is formed, it is necessary to remove the front side protection structure set to protect the front side of the substrate during the processing.

[0114] Please refer to Figure 10-12 , Fig.10 A top view of a piezoelectric MEMS accelerometer with integrated temperature detection provided in an embodiment of the present application. Fig.11 A bottom view of a piezoelectric MEMS accelerometer with integrated temperature detection provided in an embodiment of the present application, Fig.12 The B'-B cross-sectional view of the piezoelectric MEMS accelerometer provided in the embodiment of the present application, Fig.13 This is a C'-C cross-sectional view of the piezoelectric MEMS accelerometer provided in an embodiment of the present application.

[0115] The piezoelectric MEMS accelerometer includes: a vibration sensitive structure 1, a frame structure 2 and a cantilever structure 3; the vibration sensitive structure 1 includes a bottom electrode Pt layer for measuring acceleration, and the frame structure 2 includes a resistor Pt layer for in-situ temperature detection; the bottom electrode Pt layer and the resistor Pt layer are obtained by patterning the same metal platinum layer.

[0116] In the embodiment of the present application, the accelerometer can not only measure acceleration, but also detect temperature in situ through the resistor Pt layer. By detecting the temperature in real time, the acceleration measurement result can be temperature compensated to eliminate the influence of temperature on the measurement result, thereby improving the measurement accuracy. The bottom electrode Pt layer and the resistor Pt layer of the accelerometer are obtained by patterning the same metal platinum layer. This design reduces the steps in the manufacturing process, simplifies the process flow, saves space on the chip, and achieves miniaturization.

[0117] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0118] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0119] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0120] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0121] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a piezoelectric MEMS accelerometer with integrated temperature detection, characterized in that: The piezoelectric MEMS accelerometer includes a vibration sensitive structure, a frame structure and a cantilever beam structure, and the method includes: Growing isolation layers on the front and back sides of an SOI substrate, depositing a metal platinum layer on the isolation layer on the front side of the SOI substrate, and depositing a piezoelectric layer on the metal platinum layer; wherein the front side of the SOI substrate is a device layer, the middle layer of the SOI substrate is a buried oxide layer, and the back side of the SOI substrate is a support layer; Patterning the piezoelectric layer; The metal platinum layer is patterned to form a bottom electrode Pt layer and a resistor Pt layer; wherein the bottom electrode Pt layer is used to measure acceleration, and the resistor Pt layer is used for in-situ temperature detection; preparing a patterned top electrode layer on the piezoelectric layer; Patterning the isolation layer and the device layer on the front side of the SOI substrate to form the vibration sensitive structure and the frame structure; Etching the isolation layer on the back side of the SOI substrate, and etching the support layer from the back side of the SOI substrate to a set depth to form a mass block structure; wherein the set depth is less than the thickness of the support layer; The isolation layer and the support layer on the back side of the SOI substrate are etched to form the cantilever structure.

2. The method according to claim 1, characterized in that The step of depositing a metal platinum layer on the isolation layer on the front side of the SOI substrate comprises: Growing silicon oxide as an isolation layer on the front and back sides of the SOI substrate by thermal oxidation; On the isolation layer on the front side of the SOI substrate, titanium is sputtered, or titanium is sputtered and then annealed with oxygen to form titanium oxide, thereby forming an adhesion layer; The metal platinum layer is formed by depositing metal platinum on the adhesion layer by sputtering.

3. The method according to claim 2, characterized in that The step of depositing a piezoelectric layer on the metal platinum layer comprises: depositing a buffer layer on the metal platinum layer by sputtering; Lead zirconate titanate is sputter-deposited on the buffer layer to form the piezoelectric layer.

4. The method according to claim 3, characterized in that The step of patterning the piezoelectric layer comprises: Coating a photoresist on the front side of the substrate and patterning the photoresist; Etching away the portions of the piezoelectric layer and the buffer layer that are not shielded by the photoresist; Clean off the remaining photoresist.

5. The method according to claim 4, characterized in that The method of patterning the metal platinum layer to form a bottom electrode Pt layer and a resistor Pt layer includes: Coating a photoresist on the front side of the substrate and patterning the photoresist; Etching away the portions of the metal platinum layer and the adhesion layer that are not shielded by the photoresist to form the bottom electrode Pt layer and the resistor Pt layer; Clean off the remaining photoresist.

6. The method according to claim 1, characterized in that The step of preparing a patterned top electrode layer on the piezoelectric layer comprises: Coating a photoresist on the front side of the substrate and patterning the photoresist; Vapor depositing a metal adhesion layer on the piezoelectric layer and the photoresist; Vapor depositing a metal electrode layer on the metal adhesion layer; The photoresist and the metal adhesion layer and the metal electrode layer thereon are stripped off to form the top electrode layer and the PAD.

7. The method according to claim 6, characterized in that The step of patterning the isolation layer and the device layer on the front side of the SOI substrate to form the vibration sensitive structure and the frame structure includes: Coating a photoresist on the front side of the substrate and patterning the photoresist; Etching away the isolation layer and the device layer on the front side of the SOI substrate that are not shielded by the photoresist to form the vibration sensitive structure and the frame structure; Clean off the remaining photoresist.

8. The method according to claim 7, characterized in that The step of etching the isolation layer on the back side of the SOI substrate and etching the support layer to a set depth from the back side of the SOI substrate to form a mass block structure comprises: A front protection structure is provided on the front side of the substrate; Coating a photoresist on the back side of the substrate and patterning the photoresist; Etching away the isolation layer on the back side of the SOI substrate that is not shielded by the photoresist and the support layer of a set depth to form the mass block structure; Clean off the remaining photoresist.

9. The method according to claim 8, characterized in that The etching of the isolation layer and the support layer on the back side of the SOI substrate to form the cantilever structure includes: Coating a photoresist on the back side of the substrate and patterning the photoresist; Etching away the isolation layer and the support layer on the back side of the SOI substrate that are not shielded by the photoresist; Clean off the remaining photoresist; releasing silicon oxide on the back side of the substrate to form the cantilever beam structure; The front protection structure is removed.

10. A piezoelectric MEMS accelerometer with integrated temperature detection, characterized in that: The piezoelectric MEMS accelerometer is manufactured by the method according to any one of claims 1-9.

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