Inverted back pressure sensor and production method thereof

Abstract

The present invention provides an inverted back pressure sensor and a production method thereof. The inverted back pressure sensor comprises a main chip part and a cover plate part. A Wheatstone bridge and a first electrical connection structure are arranged on the main body of the main chip part. The first electrical connection structure is electrically connected to the Wheatstone bridge. The cover plate part comprises a cover plate and a second electrical connection structure. The cover plate is bonded to the main body and realizes electrical connection between the second electrical connection structure and the first electrical connection structure. The second electrical connection structure penetrates the cover plate, and one end of the second electrical connection structure is electrically connected to the first electrical connection structure, and the other end is located on a side surface of the cover plate away from the main body, so that the second electrical connection structure can be directly welded and packaged with an external substrate by SMT, so that packaging is convenient, thereby improving the packaging efficiency and reliability of the inverted back pressure sensor.

Description

Technical Field

[0001] The present invention relates to the technical field of sensors, and in particular to an inverted back-pressure sensor and a production method thereof. Background Art

[0002] At present, there are two common structural forms of pressure sensors used to measure low pressure in the market: one is front-side pressure, and the front-side pressure sensor needs to be bonded and sealed. The bonding wire and glue need to be in contact with the measured medium. The bonding wire is easy to break and fail during use due to the pressure alternation. The sealing glue also needs to be in contact with different detection media, which is not suitable for invasive media. The other is a common back-side pressure sensor. The common back-side pressure sensor uses a packaging method of glue bonding or eutectic welding. The circuit surface and bonding wire of the packaging structure of the common back-side pressure sensor are not in contact with the detection medium, but because glue bonding and eutectic welding are prone to peeling from the substrate, it is especially used in scenes with large vibrations, such as excavators with large vibrations. As a result, the existing common back-side pressure sensors have high risks of use, and require the packaging glue, eutectic materials and eutectic processes to have very high reliability, which also limits the application of common back-side pressure structure sensors. Summary of the invention

[0003] The purpose of the present invention is to solve the problems of reliability, complex packaging process and low packaging efficiency of front pressure sensors and ordinary back pressure sensors.

[0004] In order to solve the above technical problems, the present invention provides an inverted back-loaded pressure sensor, including a main chip part and a cover part, the main chip part includes a main body, a Wheatstone bridge and a first electrical connection structure, a diaphragm is formed on the main body, the Wheatstone bridge is arranged on the diaphragm, one end of the first electrical connection structure is connected to the Wheatstone bridge, and the other end extends to the outside of the diaphragm; the cover part includes a cover plate and a second electrical connection structure, the cover plate is bonded to the main body as a whole, and a vacuum cavity is constructed on the side of the diaphragm close to the cover plate, the second electrical connection structure passes through the cover plate, and one end is electrically connected to the first electrical connection structure, and the other end is located on the side surface of the cover plate away from the main body, so that the second electrical connection structure can be directly welded and packaged with an external substrate through SMT.

[0005] In some schemes of the present application, a through hole is formed on the cover plate, and the through hole connects a side of the cover plate facing the main body and a side away from the main body; the second electrical connection structure includes a conductive filling layer and a welding layer, the conductive filling layer is arranged in the through hole, the welding layer is arranged on the side of the cover plate away from the main body and is electrically connected to the conductive filling layer, and the welding layer is used for SMT patch packaging with an external substrate.

[0006] In some solutions of the present application, the welding layer is formed on a side of the cover plate facing away from the main body through deposition and photolithography processes, and is connected to the conductive filling layer.

[0007] In some embodiments of the present application, the second electrical connection structure also includes a conductive bonding layer, which is arranged on a side of the conductive filling layer away from the welding layer, one end of the conductive bonding layer is electrically connected to the conductive filling layer, and the other end is bonded to the first electrical connection structure.

[0008] In some schemes of the present application, the main chip part also includes a first bonding part, which is arranged on the side of the main body facing the cover plate; the first bonding part is annular and located on the outside of the Wheatstone bridge and the first electrical connection structure; the cover plate part also includes a second bonding part, which is arranged on the side of the cover plate facing the main body and corresponds to the position of the first bonding part, and the second bonding part is bonded to the first bonding part; the second bonding part is annular and located on the outside of the second electrical connection structure; the first bonding part and the second bonding part are metal parts or semiconductor parts.

[0009] In some schemes of the present application, a groove is provided on the side of the cover plate facing the main body, and the main body blocks the open end of the groove to form a closed vacuum chamber; a pressure-inducing chamber is provided on the side of the main body away from the cover plate, and the main body forms the diaphragm between the pressure-inducing chamber and the vacuum chamber; the Wheatstone bridge includes a resistor bar and a conductive wire, the resistor bar is arranged on the side of the diaphragm away from the pressure-inducing chamber, and the conductive wire connects the resistor bar and the first electrical connection structure.

[0010] A method for producing an inverted back-pressure pressure sensor comprises the following steps:

[0011] A10: Take a wafer and set a Wheatstone bridge on one side of the wafer;

[0012] A20: Disposing a first bonding component and a first electrical connection structure connected to a Wheatstone bridge on one side of the wafer processed in step A10;

[0013] A30: Take another wafer and set a through hole penetrating the wafer on the wafer;

[0014] A40: disposing a conductive filling layer in the through hole of the wafer processed in step A30 and disposing a second bonding member and a conductive bonding layer on one side thereof;

[0015] A50: Photolithography a groove on one side of the wafer processed in step A40 with a second bonding element;

[0016] A60: bonding and annealing the wafer processed in step A20 and the wafer processed in step A50 to form a bonded crystal; wherein the second bonding component is bonded to the first bonding component, the conductive filling layer is bonded to the first electrical connection structure, and the opening of the groove is blocked by the wafer formed with the first electrical connection structure to form a vacuum cavity;

[0017] A70: forming a pad connected to the conductive filling layer on the surface of the bonded crystal; the pad is located on a side of the conductive filling layer away from the conductive bonding layer, and the pad, the conductive filling layer and the conductive bonding layer constitute a second electrical connection structure;

[0018] A80: A pressure induction cavity is formed on the side of the bonded crystal away from the pad; a diaphragm is formed between the pressure induction cavity and the vacuum cavity;

[0019] A90: Plant solder balls on the pads of the bonded crystal;

[0020] A100: The bonded crystal with solder balls is cut and sliced ​​to form a flip-chip back-loaded pressure sensor.

[0021] In some solutions of the present application, A10: taking a wafer and setting a Wheatstone bridge on one side of the wafer specifically includes:

[0022] A11: Photolithography a light boron area on one side of the wafer, and forming a resistor strip in the light boron area by ion implantation and annealing diffusion process;

[0023] A12: A boron-concentrated region is photolithographically formed on the wafer with the resistor bars, and a conductive line is formed in the boron-concentrated region by ion implantation and annealing diffusion process; the conductive line is connected to the resistor bars to form a Wheatstone bridge.

[0024] In some solutions of the present application, A20: the step of providing a first bonding component and a first electrical connection structure connected to a Wheatstone bridge on one side of the wafer processed in step A10 specifically includes:

[0025] A21: forming a second oxide layer covering the Wheatstone bridge and the surface of the wafer on the wafer having the Wheatstone bridge formed thereon;

[0026] A22: A passivation layer is formed on the wafer having the second oxide layer by depositing silicon nitride; the passivation layer covers the surface of the side of the wafer where the Wheatstone bridge is set;

[0027] A23: photolithography a first lead hole and a second lead hole on the wafer having the passivation layer formed thereon;

[0028] A24: Form a first electrical connection structure in the first lead hole and a first bonding member in the second lead hole through deposition and photolithography processes on the wafer processed in step A23.

[0029] In some solutions of the present application, A40: the step of providing a conductive filling layer in the through hole of the wafer processed in step A30 and providing a second bonding member and a conductive bonding layer on one side thereof, specifically includes:

[0030] A41: A first oxide layer is formed on the inner wall surface and outer surface of the through hole of the wafer;

[0031] A42: sequentially forming an adhesion layer and a seed layer in a through hole of the wafer having the first oxide layer formed thereon by a deposition process;

[0032] A43: forming a conductive filling layer in a through hole of the wafer having the seed layer formed thereon by an electroplating process;

[0033] A44: depositing an insulating layer on one end surface of the wafer processed in step A43, and photolithography of a third lead hole at a location corresponding to the conductive filling layer and photolithography of a fourth lead hole outside the conductive filling layer;

[0034] A45: forming a conductive bonding layer at the third lead hole by deposition and photolithography on one end surface of the wafer processed in step A44, and forming a second bonding member at the fourth lead hole by deposition and photolithography;

[0035] A46: depositing an insulating layer on an end surface of the wafer that is away from the conductive bonding layer and the second bonding component after being processed in step A45, and photoetching a fifth lead hole at a location corresponding to the conductive filling layer.

[0036] In some solutions of the present application, A70: the step of forming a pad connected to the conductive filling layer on the surface of the bonded crystal specifically includes:

[0037] A pad is formed at the fifth lead hole of the bonding crystal by deposition and photolithography processes.

[0038] A method for producing an inverted back-pressure pressure sensor comprises the following steps:

[0039] B10: Take a wafer and set a Wheatstone bridge on one side of the wafer;

[0040] B20: Disposing a first electrical connection structure connected to a Wheatstone bridge on one side of the wafer processed in step B10;

[0041] B30: Take another wafer and set a through hole penetrating the wafer on the wafer;

[0042] B40: Photolithography a groove on one side of the wafer processed in step B30;

[0043] B50: bonding and annealing the wafer processed in step B20 and the wafer processed in step B40 to form a bonded crystal; wherein the opening of the groove is blocked by the wafer having the first electrical connection structure to form a vacuum cavity;

[0044] B60: Provide a conductive filling layer in the through hole;

[0045] B70: forming an insulating layer on the surface of the bonded crystal, and forming a pad connected to the conductive filling layer; the pad is located on a side of the conductive filling layer away from the conductive bonding layer, and the pad, the conductive filling layer and the conductive bonding layer constitute a second electrical connection structure;

[0046] B80: A pressure induction cavity is formed on the side of the bonded crystal away from the pad; a diaphragm is formed between the pressure induction cavity and the vacuum cavity;

[0047] B90: Plant solder balls on the pads of the bonded crystal;

[0048] B100: Cut and slice the bonded crystal with solder balls to form a flip-chip back-loaded pressure sensor.

[0049] In some solutions of the present application, B10: taking a wafer and setting a Wheatstone bridge on one side of the wafer specifically includes:

[0050] B11: photolithography a light boron area on one side of the wafer, and forming a resistor strip in the light boron area by ion implantation and annealing diffusion process;

[0051] B12: A boron-rich region is photolithographically formed on the wafer with the resistor strip, and a conductive line is formed in the boron-rich region by ion implantation and annealing diffusion process; the conductive line is connected to the resistor strip to form a Wheatstone bridge.

[0052] In some schemes of the present application, between step B10 and step B20, it also includes: forming a second oxide layer covering the Wheatstone bridge and the surface of the wafer on the wafer formed with the Wheatstone bridge; between step B30 and step B40, it also includes: forming an oxide layer on the inner wall surface of the through hole and the outer surface of the wafer.

[0053] In some embodiments of the present application, after the step of forming a second oxide layer covering the Wheatstone bridge and the surface of the wafer on the wafer having the Wheatstone bridge and before step B50, it also includes: forming a silicon nitride layer above the wafer covering the Wheatstone bridge through deposition and photolithography processes.

[0054] In some solutions of the present application, B60: the step of providing a conductive filling layer in the through hole specifically includes:

[0055] B61: forming an adhesion layer and a seed layer in the through hole by a deposition process;

[0056] B62: Forming a conductive filling layer through an electroplating process on the wafer having the adhesion layer and the seed layer.

[0057] In some embodiments of the present application, B70: forming an insulating layer on the surface of the bonded crystal and forming a pad connected to the conductive filling layer, specifically includes:

[0058] B71: forming an insulating layer by oxidation process on one end surface where the bonding crystal is connected to the conductive filling layer;

[0059] B72: photolithography of a fifth lead hole on the insulating layer of the wafer processed in step B71;

[0060] B73: A pad is formed at the fifth lead hole by deposition and photolithography processes.

[0061] It can be seen from the above technical scheme that the beneficial effects of the present invention are as follows: the inverted back-compression pressure sensor of the present application includes a main chip part and a cover part, a Wheatstone bridge and a first electrical connection structure are provided on the main body of the main chip part, the first electrical connection structure is electrically connected to the Wheatstone bridge, the cover part includes a cover and a second electrical connection structure, the cover is bonded to the main body, and an electrical connection between the second electrical connection structure and the first electrical connection structure is realized; the second electrical connection structure passes through the cover, and one end of the second electrical connection structure is electrically connected to the first electrical connection structure, and the other end is located on a side surface of the cover away from the main body, so that the second electrical connection structure can be directly welded and packaged with an external substrate by SMT, making the packaging convenient and simple, thereby improving the packaging efficiency and reliability of the inverted back-compression pressure sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 It is a schematic structural diagram of an inverted back-pressure sensor in one embodiment.

[0063] Figure 2 yes Figure 1 The schematic diagram of the structure of the main chip of the flip-chip back-pressure pressure sensor is shown.

[0064] Figure 3 yes Figure 1 The schematic diagram of the cover structure of the inverted back-loaded pressure sensor is shown.

[0065] Figure 4 It is a process flow diagram of steps A10-A20 of the first production method of the inverted back-pressure pressure sensor.

[0066] Figure 5 It is a process flow diagram of steps A30-A50 of the first production method of the inverted back-pressure pressure sensor.

[0067] Figure 6 It is a process flow diagram of steps A60-A80 of the first production method of the inverted back-pressure pressure sensor.

[0068] Figure 7 It is a schematic diagram of the structure of an inverted back-pressure pressure sensor obtained by using production method 1, wherein the Wheatstone bridge is formed by an SOI structure.

[0069] Figure 8 It is a schematic diagram of the structure of an inverted back-pressure pressure sensor obtained by using production method 1, wherein the Wheatstone bridge is formed by a PN junction and the diaphragm has an island.

[0070] Fig. 9 It is a schematic diagram of the structure of an inverted back-loaded pressure sensor obtained by production method 1, wherein the Wheatstone bridge is formed by an SOI structure and the diaphragm has an island.

[0071] Fig.10 It is a process flow diagram of steps B10-B20 of the second production method of the inverted back-pressure pressure sensor.

[0072] Fig.11 It is a process flow diagram of steps B30-B40 of the second production method of the inverted back-loaded pressure sensor.

[0073] Fig.12 It is a process flow diagram of steps B50-B80 of the second production method of the inverted back-pressure pressure sensor.

[0074] Fig.13 It is a schematic diagram of the structure of an inverted back-loaded pressure sensor obtained by production method 2, wherein the cover plate is formed by processing a silicon wafer.

[0075] Fig.14 It is a schematic structural diagram of an inverted back-loaded pressure sensor obtained by production method 2, wherein the cover plate is formed by processing a glass sheet.

[0076] The reference numerals are explained as follows: 1-main chip part; 11-main body; 12-Wheatstone bridge; 121-resistance bar; 122-conductive wire; 13-first electrical connection structure; 111-diaphragm; 14-first bonding part; 15-pressure chamber; 2-cover plate part; 21-cover plate; 22-second electrical connection structure; 23-vacuum chamber; 221-conductive filling layer; 222-welding layer; 223-conductive bonding layer; 24-second bonding part; 25-groove. DETAILED DESCRIPTION

[0077] Typical embodiments that embody the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various changes in different embodiments without departing from the scope of the present invention, and the descriptions and illustrations therein are essentially used for illustration purposes rather than for limiting the present invention.

[0078] In the description of the present application, it should be understood that in the embodiments shown in the drawings, the indications of directions or positional relationships (such as up, down, left, right, front and back, etc.) are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation. These descriptions are appropriate when these elements are in the positions shown in the drawings. If the descriptions of the positions of these elements change, the indications of these directions also change accordingly.

[0079] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0080] When existing front-side pressure sensors and ordinary back-side pressure sensors are used in scenarios with large vibrations or different measuring media, the pressure sensors have problems with reliability, complex packaging process, and low packaging efficiency. This application designs a flip-chip back-side pressure sensor that can be packaged using the SMT process. The package is directly welded using SMT, eliminating complex processes such as wire bonding, effectively improving the packaging efficiency of the pressure sensor and improving the reliability of the pressure sensor.

[0081] Among them, when packaging ordinary back-pressure pressure sensors, thin metal wires are needed, and heat, pressure, and ultrasonic energy are used to make multi-point welding between the metal leads and the substrate pads. This process is called wire bonding process.

[0082] SMT is called surface mounting or surface mounting technology. It is a circuit assembly technology that mounts pinless or short-lead surface mounting components on the surface of a printed circuit board or other substrate, and assembles them by soldering through reflow soldering or dip soldering. SMT packaging has high reliability, strong vibration resistance, and low solder joint defect rate.

[0083] See also Figure 1 The flip-chip back pressure sensor of the present application includes a main chip part 1 and a cover part 2, and the cover part 2 and the main chip part 1 are fixed as a whole by bonding methods such as eutectic bonding or metal hot pressing bonding. A pressure induction cavity 15 for contacting a fluid to be detected is provided on the side of the main chip part 1 away from the cover part 2, and a pad is provided on the side of the cover part 2 away from the main chip part 1, and the pad can be directly welded and packaged with the substrate by the SMT process to form a flip-chip back pressure sensor.

[0084] See also Figure 2 The main chip part 1 includes a main body 11, a Wheatstone bridge 12 and a first electrical connection structure 13. A diaphragm 111 is formed on the main body 11. The Wheatstone bridge 12 is arranged on the diaphragm 111. One end of the first electrical connection structure 13 is connected to the Wheatstone bridge 12, and the other end extends to the outside of the diaphragm 111.

[0085] A pressure induction cavity 15 for contacting the fluid to be detected is formed on one side of the main body 11 by etching and photolithography processes, so that a diaphragm 111 is formed between the bottom of the pressure induction cavity 15 and the side of the main body 11 away from the pressure induction cavity 15, and the diaphragm 111 is used to sense the pressure of the fluid entering the pressure induction cavity 15. In order to facilitate the description of the structure of the main body 11, this application defines the side of the main body 11 on which the pressure induction cavity 15 is set as the bottom surface of the main body 11, and the side away from the pressure induction cavity 15 is defined as the top surface of the main body 11.

[0086] The top surface of the main body 11 forms a Wheatstone bridge 12 by ion implantation. The Wheatstone bridge 12 includes a resistor bar 121 and a conductive wire 122. There are four resistor bars 121, which are arranged at intervals and located on the side of the diaphragm 111 away from the pressure-inducing chamber 15. Among the four resistor bars 121, two of them correspond to the peak areas of the tensile stress and the compressive stress of the diaphragm 111, and the four resistor bars 121 are connected by conductive connection to form the Wheatstone bridge 12.

[0087] When the diaphragm 111 undergoes elastic deformation under fluid pressure, the Wheatstone bridge 12 can produce a change in resistance value according to the elastic deformation, and can output a corresponding electrical signal according to the degree of elastic deformation, and the pressure of the fluid can be known according to the electrical signal output by the Wheatstone bridge 12.

[0088] Preferably, the four resistor bars 121 are formed by a PN junction or SOI structure. A PN junction is a process of making a P-type semiconductor and an N-type semiconductor on the same semiconductor (usually silicon or germanium) substrate by epitaxy, dopant diffusion or ion implantation. The boundary or interface between the two semiconductor materials is called a PN junction (English: PN junction). SOI stands for Silicon-On-Insulator, which means silicon on an insulating substrate. This technology introduces a buried oxide layer between the top silicon and the back substrate.

[0089] The first electrical connection structure 13 is disposed on the main body 11 through deposition and photolithography processes, and is located on the same side of the main body 11 as the Wheatstone bridge 12. One end of the first electrical connection structure 13 is connected to the conductive wire 122 of the Wheatstone bridge 12, and the other end is connected to the second electrical connection structure 22 on the cover portion 2, so that the Wheatstone bridge 12 is connected to the circuit on the substrate through the first electrical connection structure 13 and the second electrical connection structure 22. There are four first electrical connection structures 13, and the four first electrical connection structures 13 are arranged at intervals.

[0090] In one embodiment, a silicon oxide layer is formed on the surface of the main body 11 by a thermal oxidation process. The silicon oxide layer is an insulating structure and can provide a good insulation effect between the Wheatstone bridge 12 and the outside world.

[0091] Furthermore, silicon nitride is deposited on the top surface of the body 11 to form a silicon nitride layer, and the silicon oxide layer and the silicon nitride layer form a passivation layer. The passivation layer effectively protects the diaphragm 111 and the Wheatstone bridge 12 and forms stress matching for the diaphragm 111.

[0092] The pressure sensing diaphragm 111 is etched according to the range requirement, and the internal stress of the diaphragm 111 is balanced by matching the thickness of the passivation layer. The internal stress includes tensile stress and compressive stress.

[0093] In one embodiment, the main chip portion 1 further includes a first bonding member 14, which is used to bond and connect with the cover portion 2. The first bonding member 14 is annular, and the first bonding member 14 is arranged on the top surface of the main body 11, and is located outside the Wheatstone bridge 12 and the first electrical connection structure 13. The first bonding member 14 is a metal member or a semiconductor member. The first bonding member 14 is formed by photolithography of a lead hole on the top surface of the main body 11, then depositing a metal layer, and then photolithography of the metal layer.

[0094] The cover plate portion 2 includes a cover plate 21 and a second electrical connection structure 22. The cover plate 21 can be formed by processing a silicon wafer or a glass sheet. A groove 25 is formed by photolithography on one side of the cover plate 21, and the side on which the groove 25 is formed is bonded to the top surface of the main body 11, so that the main body 11 blocks the open end of the groove 25 to form a closed vacuum chamber 23. The position of the diaphragm 111 corresponds to the position of the groove 25, so that the vacuum chamber 23 becomes an elastic deformation space when the diaphragm 111 produces elastic deformation. In order to facilitate the description of the structure of the main body 11, this application defines the side of the cover plate 21 on which the groove 25 is set as the bottom surface of the cover plate 21, and the side away from the groove 25 is defined as the top surface of the cover plate 21. The second electrical connection structure 22 runs through the bottom surface of the cover plate 21 and the top surface of the cover plate 21, so that the second electrical connection structure 22 connects the substrate and the first electrical connection structure 13.

[0095] See also Figure 3 The cover plate portion 2 also includes a second bonding member 24, which is arranged on the side of the cover plate 21 facing the main body 11 and corresponds to the position of the first bonding member 14. The second bonding member 24 is bonded to the first bonding member 14 to achieve a bonding connection between the cover plate portion 2 and the main chip portion 1. The second bonding member 24 is annular and is located outside the second electrical connection structure 22. The first bonding member 14 and the second bonding member 24 are metal parts or semiconductor parts. The second bonding member 24 is formed by photolithography of lead holes on the bottom surface of the cover plate 21, then depositing a metal layer, and then photolithography of the metal layer.

[0096] In the embodiment where the second bonding member 24 is bonded to the first bonding member 14, the second electrical connection structure 22 and the first electrical connection structure 13 may be bonded. Specifically, when the bonding process is performed between the second bonding member 24 and the first bonding member 14, the bonding connection between the second electrical connection structure 22 and the first electrical connection structure 13 is completed at the same time. Eutectic bonding is formed between the second bonding member 24 and the first bonding member 14 and between the second electrical connection structure 22 and the first electrical connection structure 13, such as Figure 1 , Figures 7 to 9 An inverted back-loaded pressure sensor is shown.

[0097] When the cover plate 21 is a silicon wafer, a silicon oxide layer may be formed by oxidation on the bottom surface of the cover plate 21 to improve the insulation effect of the cover plate portion 2 .

[0098] In one embodiment, the cover plate 21 is formed by processing a glass sheet. In this embodiment, the cover plate portion 2 is not provided with the second bonding member 24, and the main chip portion 1 is not provided with the first bonding member 14. The cover plate 21 is directly bonded to the main body 11 to form an anodic bond between the glass material and the silicon material. In this embodiment, the surface of the main body 11 may not be provided with a silicon oxide layer and a silicon nitride layer; or a silicon oxide layer and a silicon nitride layer are only provided above the Wheatstone bridge 12, and a silicon oxide layer and a silicon nitride layer are not provided at the position of the main body 11 for bonding with the cover plate 21, such as Fig.14 An inverted back-loaded pressure sensor is shown.

[0099] In one embodiment, the cover plate 21 is formed by processing a silicon wafer. In this embodiment, the cover plate portion 2 is not provided with the second bonding component 24, and the main chip portion 1 is not provided with the first bonding component 14. The cover plate 21 is directly bonded to the main body 11 to form a silicon-silicon bond between silicon materials. In this embodiment, a silicon oxide layer may be provided on the surface of the main body 11 and the surface of the cover plate 21 to improve the insulation effect of the flip-chip back-pressure pressure sensor. In one embodiment, a silicon oxide layer and a silicon nitride layer may be provided only above the Wheatstone bridge 12, and a silicon nitride layer is not provided at the position of the main body 11 for bonding to the cover plate 21, such as Fig.13 An inverted back-loaded pressure sensor is shown.

[0100] A through hole is photoetched on the cover plate 21, and the through hole connects the bottom surface of the cover plate 21 and the top surface of the cover plate 21. The second electrical connection structure 22 is fixedly connected to the cover plate 21 and passes through the through hole, so that one end of the second electrical connection structure 22 is connected to the first electrical connection structure 13, and the other end forms a pad for direct welding and packaging with the substrate through SMT.

[0101] There are four through holes, the positions of which correspond to the positions of the first electrical connection structures 13 , and a second electrical connection structure 22 is provided in each through hole, so that four second electrical connection structures 22 for connecting the substrate and the first electrical connection structure 13 are formed on the cover plate 21 .

[0102] The second electrical connection structure 22 includes a conductive filling layer 221 and a welding layer 222. The conductive filling layer 221 is arranged in the through hole, and the welding layer 222 is arranged on the side of the cover plate 21 away from the main body 11 and is electrically connected to the conductive filling layer 221. The welding layer 222 forms a pad and is used for SMT patch packaging with an external substrate. Among them, the conductive filling layer 221 can be formed in the through hole by depositing or electroplating a metal material. The welding layer 222 is formed on the top surface of the cover plate 21 by deposition and photolithography processes, and is connected to the conductive filling layer 221.

[0103] In one embodiment, the second electrical connection structure 22 further includes a conductive bonding layer 223, which is disposed on a side of the conductive filling layer 221 away from the welding layer 222. One end of the conductive bonding layer 223 is electrically connected to the conductive filling layer 221, and the other end is bonded to the first electrical connection structure 13. The conductive bonding layer 223 can be formed by deposition and photolithography processes.

[0104] When producing an inverted back-loaded pressure sensor, at least the following method can be used for production.

[0105] Method 1: See Figure 4-Figure 6 First, a Wheatstone bridge 12 and a first electrical connection structure 13 are arranged on the main body 11 (see Figure 4 ), and a second electrical connection structure 22 and a groove 25 are provided on the cover plate 21 (see for details). Figure 5 ), and then the two are bonded, and then the pad and the pressure chamber 15 are processed (see Figure 6 ). The specific steps of the production method of the inverted back pressure sensor are as follows:

[0106] A10: Take a wafer and set a Wheatstone bridge 12 on one side of the wafer. In this step, the wafer can be a silicon wafer (such as Figure 1 and Figure 8 ), or a silicon wafer with an internal oxide layer (such as Figure 7 and Fig. 9 As shown). The step of setting the Wheatstone bridge 12 on the wafer includes:

[0107] A11: photolithography a light boron region on the top surface of the wafer, and ion implantation and annealing diffusion process are performed in the light boron region to form the resistor bar 121. Specifically, photolithography is performed on the top surface of the wafer to form a light boron region, and then ion implantation and annealing diffusion process are performed to form the resistor bar 121.

[0108] A12: A boron-rich region is photolithographically formed on the top surface of the wafer with the resistor bar 121, and a conductive line 122 is formed in the boron-rich region by ion implantation and annealing diffusion process. The conductive line 122 is connected to the resistor bar 121 to form a Wheatstone bridge 12. Specifically, a boron-rich region is photolithographically formed on the top surface of the wafer by a photolithography process, and then ion implantation and annealing diffusion process are performed to form the conductive line 122.

[0109] A20: Arranging a first bonding component 14 and a first electrical connection structure 13 connected to the Wheatstone bridge 12 on one side of the wafer processed in step A10. This step specifically includes:

[0110] A21: A second oxide layer is formed on the wafer with the Wheatstone bridge 12 to cover the Wheatstone bridge 12 and the surface of the wafer. The wafer with the Wheatstone bridge 12 is oxidized by a thermal oxidation device to form an oxide layer on the surface of the wafer.

[0111] A22: A passivation layer is formed on the wafer with the second oxide layer by depositing silicon nitride. In this step, silicon nitride is deposited on the top surface of the wafer with the second oxide layer so that the passivation layer covers the surface of the side of the wafer where the Wheatstone bridge 12 is set. The passivation layer protects the Wheatstone bridge 12 and achieves stress matching for the subsequent formation of the diaphragm 111.

[0112] A23: Photolithography of a first lead hole and a second lead hole is performed on the top surface of the wafer on which the passivation layer is formed; the second lead hole is located outside the first lead hole.

[0113] A24: Deposit a metal layer on the top surface of the wafer after the processing of step A23, and then photolithography the metal layer through a photolithography process to form a first electrical connection structure 13 in the first lead hole, and a first bonding part 14 in the second lead hole. That is, during photolithography, the metal layer outside the positions of the first lead hole and the second lead hole is removed, and the remaining part forms the first electrical connection structure 13 and the first bonding part 14. The bottom surface of the first electrical connection structure 13 is connected to the conductive wire 122, and the top surfaces of the first electrical connection structure 13 and the first bonding part 14 are exposed outside the passivation layer. The first electrical connection structure 13 can be a metal material such as aluminum, copper, gold, tin, or a semiconductor material such as germanium and silicon. The first bonding part 14 can be a metal material such as aluminum, copper, gold, tin, or a semiconductor material such as germanium and silicon. Preferably, the material of the first bonding part 14 is the same as that of the first electrical connection structure 13, so that the first bonding part 14 and the first electrical connection structure 13 can be processed and formed at the same time.

[0114] A30: Take another wafer, and set a through hole on the wafer that passes through the wafer. The wafer can be a silicon wafer or a glass sheet. For a wafer original with a larger thickness, the wafer original is first thinned to a set thickness. For example, in a preferred embodiment of the present application, the wafer needs to be thinned to 400um. For a wafer original with an appropriate thickness, this step can be omitted. Then, through holes are photoetched on the wafer, and the through holes are set vertically. That is, the through holes can be formed by TSV or TGV process. TSV refers to silicon through-hole (short for Through Silicon Via, also known as silicon through-hole), which is a vertical interconnection through-hole that penetrates a silicon wafer or chip. TGV refers to the abbreviation of Through Glass Via, which is a vertical interconnection through-hole that passes through a glass substrate.

[0115] A40: Arrange a conductive filling layer 221 in the through hole of the wafer processed in step A30 and arrange a second bonding member 24 and a conductive bonding layer 223 on one side thereof. This step includes:

[0116] A41: A first oxide layer is formed on the inner wall surface and outer surface of the through hole of the wafer. In this step, the wafer with the through hole is oxidized by a thermal oxidation device, so that a first oxide layer is formed on the inner wall surface of the through hole of the wafer and the surface of the wafer.

[0117] A42: An adhesion layer and a seed layer are sequentially formed in the through hole of the wafer having the first oxide layer formed thereon by a deposition process. Before depositing the adhesion layer, an insulating layer may be deposited on the inner wall surface of the through hole by a deposition process, and the material of the insulating layer may be silicon oxide.

[0118] A43: A conductive filling layer 221 is formed in the through hole of the wafer with the seed layer by electroplating. The conductive filling layer 221 and the seed layer are made of the same material. The conductive filling layer 221 can be made of metal materials such as aluminum, copper, gold, tin, or semiconductor materials such as germanium and silicon. In some embodiments, the electroplated conductive filling layer 221 is flattened by CMP, where CMP refers to chemical mechanical polishing.

[0119] A44: depositing an insulating layer on one end surface of the wafer processed in step A43, and photolithography of a third lead hole corresponding to the conductive filling layer and photolithography of a fourth lead hole outside the conductive filling layer. The third lead hole is photolithography onto the conductive filling layer.

[0120] A45: A metal layer is deposited on the bottom surface of the wafer at one end surface of the wafer after being processed in step A44, and then a conductive bonding layer 223 is photoetched at the third lead hole by a photolithography process, and a second bonding part 24 is formed by photoetching the metal layer at the fourth lead hole. The conductive bonding layer 223 is connected to the conductive filling layer 221. The conductive bonding layer 223 can be a metal material such as aluminum, copper, gold, tin, or a semiconductor material such as germanium and silicon. The second bonding part 24 can be a metal material such as aluminum, copper, gold, tin, or a semiconductor material such as germanium and silicon. Preferably, the material of the second bonding part 24 is the same as that of the conductive bonding layer 223, so that the second bonding part 24 and the conductive bonding layer 223 can be processed and formed at the same time.

[0121] A46: After the wafer is processed in step A45, an insulating layer is deposited on an end surface away from the conductive bonding layer 223 and the second bonding element 24, and a fifth lead hole is photoetched at the corresponding conductive filling layer. The insulating layer can be silicon oxide or silicon nitride.

[0122] A50: A groove 25 is photolithographically formed on one side of the wafer processed in step A40 and provided with the second bonding element 24. The groove 25 is located on the bottom surface of the wafer and is spaced apart from the conductive bonding layer 223.

[0123] A60: Bond the wafer processed in step A20 to the wafer processed in step A50, and eliminate the stress at the bonding point through an annealing process, so that the two are fixed as a whole to form a bonded crystal. In the bonding process, the second bonding part 24 is bonded to the first bonding part 14, the conductive filling layer 221 is bonded to the first electrical connection structure 13, and the groove 25 is blocked by the wafer formed with the first electrical connection structure 13 to form a vacuum chamber 23. The first bonding part 14 is bonded to the second bonding part 24, so that eutectic bonding is achieved between the main chip part 1 and the cover plate part 2.

[0124] A70: A pad connected to the conductive filling layer 221 is formed on the surface of the bonded crystal. The pad is located on the side of the conductive filling layer 221 away from the conductive bonding layer 223, that is, located on the top surface of the bonded crystal, and the pad, the conductive filling layer 221 and the conductive bonding layer 223 constitute a second electrical connection structure 22. Among them, a metal layer is first formed at the fifth lead hole on the top surface of the bonded crystal by a deposition process, and a welding layer 222 is formed at the fifth lead hole by photolithography of the metal layer, that is, a pad is formed.

[0125] In other embodiments, the above step A46 can also be arranged between step A60 and step A70. That is, the wafer processed by step A20 is first bonded to the wafer processed by step A45, and then an insulating layer is deposited on the top surface of the bonded crystal and the fifth lead hole is photoetched. Then, a metal layer is deposited on the top surface of the bonded crystal, and the metal layer is photoetched so that a welding layer connected to the conductive filling layer 221 is formed at the fifth lead hole, that is, a pad is formed.

[0126] A80: A pressure induction cavity 15 is formed on the side of the bonded crystal away from the pad, that is, the pressure induction cavity 15 is formed on the bottom surface of the bonded crystal by etching and photolithography, so that a diaphragm 111 for sensing pressure is formed between the pressure induction cavity 15 and the vacuum cavity 23. For a bonded crystal with a larger thickness, before processing the pressure induction cavity 15, the bottom surface of the bonded crystal is first photolithographed or polished to thin the bonded crystal, and then the pressure induction cavity 15 is photolithographed. For example: In a preferred embodiment of the present application, before etching the pressure induction cavity 15 by etching and photolithography, the bottom surface of the bonded crystal is photolithographed or polished to be thinned to a total thickness of 800um, that is, the wafer on which the Wheatstone bridge 12 is set is thinned to 400um. In other embodiments, other sizes are also possible.

[0127] In one embodiment, the diaphragm 111 is in the shape of a thin film, that is, the cross section of the pressure-inducing chamber 15 is in the shape of a C. Figure 1 and Figure 7 In one embodiment, the thickness of the middle portion of the diaphragm 111 is relatively large, that is, an island structure is formed in the pressure-inducing cavity 15, such as Figure 8 and Fig. 9 .

[0128] A90: Solder balls are planted on the pads of the bonded crystal, and the solder balls are used to weld to the substrate.

[0129] A100: The bonded crystal with solder balls is cut and sliced ​​to form a flip-chip back-loaded pressure sensor.

[0130] Method 2: See Figure 10-12 First, a Wheatstone bridge 12 and a first electrical connection structure 13 are arranged on the main body 11 (see Fig.10 ), and a through hole and a groove 25 are provided on the cover plate 21 (see Fig.11 ), and then the two are bonded together, and then the second electrical connection structure 22 and the pressure-inducing cavity 15 are processed (see details). Fig.12 ). The specific steps of the production method of the inverted back pressure sensor are as follows:

[0131] B10: Take a wafer and set a Wheatstone bridge 12 on one side of the wafer. In this step, the wafer can be a silicon wafer (such as Fig.13 ), or a silicon wafer with an internal oxide layer (such as Fig.14 As shown). The step of setting the Wheatstone bridge 12 on the wafer includes:

[0132] B11: photolithography a light boron region on the top surface of the wafer, and ion implantation and annealing diffusion process are performed in the light boron region to form the resistor bar 121. Specifically, the light boron region is photolithography-etched on the top surface of the wafer, and then ion implantation and annealing diffusion process are performed to form the resistor bar 121.

[0133] B12: A boron-rich region is photolithographically formed on the top surface of the wafer with the resistor bar 121, and a conductive line 122 is formed by ion implantation and annealing diffusion. The conductive line 122 is connected to the resistor bar 121 to form a Wheatstone bridge 12. Specifically, a boron-rich region is photolithographically formed on the top surface of the wafer by a photolithography process, and then ion implantation and annealing diffusion process are performed to form the conductive line 122.

[0134] B20: A first electrical connection structure 13 connected to the Wheatstone bridge 12 is provided on one side of the wafer processed in step B10. In this step, a first lead hole is photoetched on the top surface of the wafer forming the Wheatstone bridge 12, and a metal layer is deposited on the top surface of the wafer, and then the metal layer is photoetched by a photolithography process so that the first electrical connection structure 13 is formed in the first lead hole. The bottom surface of the first electrical connection structure 13 is connected to the conductive wire 122. The first electrical connection structure 13 can be made of metal materials such as aluminum, copper, gold, and tin.

[0135] In the embodiment where the cover plate 21 is formed by processing a silicon wafer, between step B10 and step B20, the following step is further included: forming a second oxide layer covering the Wheatstone bridge 12 and the surface of the wafer on the wafer formed with the Wheatstone bridge 12. That is, the wafer formed with the Wheatstone bridge 12 is first oxidized by a thermal oxidation device so that an oxide layer is formed on the surface of the wafer, and then the first electrical connection structure 13 is formed on the top surface of the wafer by deposition and photolithography processes, and the top surface of the first electrical connection structure 13 is exposed outside the oxide layer.

[0136] In one embodiment, after the step of forming a second oxide layer covering the Wheatstone bridge 12 and the surface of the wafer on which the Wheatstone bridge 12 is formed and before bonding with the cover plate portion, the method further includes: forming a silicon nitride layer on the wafer on which the second oxide layer is formed by deposition and photolithography processes, and the silicon nitride layer and the oxide layer form a passivation layer. The passivation layer protects the Wheatstone bridge 12 and achieves stress matching for the subsequent formation of the diaphragm 111. In this embodiment, the silicon nitride layer is not provided at the position on the top surface of the wafer on which the Wheatstone bridge 12 is formed for bonding with the cover plate; or the silicon nitride layer and the oxide layer are not provided at the position on the top surface of the wafer on which the Wheatstone bridge 12 is formed for bonding with the cover plate.

[0137] In the embodiment where the cover plate 21 is formed by processing a glass sheet, no silicon nitride layer and no oxide layer are provided on the top surface of the wafer where the Wheatstone bridge 12 is formed and at a position for bonding with the cover plate.

[0138] B30: Take another wafer and set a through hole that penetrates the wafer on the wafer. The wafer can be a silicon wafer or a glass sheet. For a wafer with a larger thickness, the wafer is first thinned to a set thickness. For example, in a preferred embodiment of the present application, the wafer needs to be thinned to 400um. For a wafer with a suitable thickness, this step can be omitted. Then, a through hole is photoetched on the wafer, and the through hole is set vertically. That is, the through hole can be formed by TSV or TGV process.

[0139] B40: Photolithography a groove 25 on one side of the wafer processed in step B30. The groove 25 is located on the bottom surface of the wafer and is spaced apart from the through hole.

[0140] In the embodiment where the cover plate 21 is formed by processing a silicon wafer, an oxide layer is formed on the inner wall surface of the through hole and the outer surface of the wafer between step B30 and step B40.

[0141] B50: Bond the wafer processed by step B20 to the wafer processed by step B40 and the wafer formed with the groove 25, and eliminate the stress at the bonding point through an annealing process, so that the two are fixed as a whole to form a bonded crystal. Among them, the groove 25 is blocked by a wafer formed with a first electrical connection structure 13 to form a vacuum chamber 23. In this process, when the cover plate 21 is formed by processing a glass sheet, the bottom surface of the cover plate 21 is directly bonded to the top surface of the main body 11 to form an anodic bond between the glass material and the silicon material. When the cover plate 21 is formed by processing a silicon wafer, the bottom surface of the cover plate 21 is bonded to the top surface of the main body to form a silicon-silicon bond between silicon materials and silicon materials, or to form a silicon-silicon bond between silicon oxide materials and silicon oxide materials.

[0142] B60: Arrange a conductive filling layer 221 in the through hole. This step includes:

[0143] B61: An adhesion layer and a seed layer are sequentially formed in the through hole by a deposition process. Before depositing the adhesion layer, an insulating layer may be deposited on the inner wall surface of the through hole by a deposition process, and the material of the insulating layer may be silicon oxide.

[0144] B62: Form a conductive filling layer 221 on the wafer with the seed layer by electroplating. The conductive filling layer 221 and the seed layer are made of the same material, such as aluminum, copper, gold, tin, etc.

[0145] B70: forming an insulating layer on the surface of the bonded crystal and forming a pad connected to the conductive filling layer 221. This step specifically includes:

[0146] B71: An oxide layer is formed by an oxidation process on one end surface where the bonding crystal is connected to the conductive filling layer. The oxide layer is used for insulation between the flip-chip back-loaded pressure sensor and the substrate, that is, as an insulating layer.

[0147] B72: Photolithography a fifth lead hole in the insulating layer of the wafer processed in step B71. The position of the fifth lead hole corresponds to the conductive filling layer 221, and the fifth lead hole completely penetrates the insulating layer formed in step B71.

[0148] B73: Forming a pad at the fifth lead hole by deposition and photolithography. Specifically, a metal layer is first formed on the top surface of the bonded crystal by deposition, and then a welding layer 222 is formed at the fifth lead hole by photolithography.

[0149] B80: A pressure induction cavity 15 is formed on the side of the bonded crystal away from the pad, that is, the pressure induction cavity 15 is formed on the bottom surface of the bonded crystal by etching and photolithography, so that a diaphragm 111 for sensing pressure is formed between the pressure induction cavity 15 and the vacuum cavity 23. For a bonded crystal with a larger thickness, before processing the pressure induction cavity 15, the bottom surface of the bonded crystal is first photolithographed or polished to thin the bonded crystal, and then the pressure induction cavity 15 is photolithographed. For example: In a preferred embodiment of the present application, before etching the pressure induction cavity 15 by etching and photolithography, the bottom surface of the bonded crystal is photolithographed or polished to be thinned to a total thickness of 800um, that is, the wafer on which the Wheatstone bridge 12 is set is thinned to 400um. In other embodiments, other sizes are also possible.

[0150] In one embodiment, the diaphragm 111 is in the shape of a thin film, that is, the cross section of the pressure-inducing chamber 15 is in the shape of a C. Fig.13 and Fig.14 In one embodiment, the thickness of the middle portion of the diaphragm 111 is relatively large, that is, an island structure is formed in the pressure-inducing chamber 15 .

[0151] B90: Solder balls are planted on the pads of the bonded crystal, and the solder balls are used to solder to the substrate.

[0152] B100: Cut and slice the bonded crystal with solder balls to form a flip-chip back-loaded pressure sensor.

[0153] The inverted back-compression pressure sensor of the present application includes a main chip part 1 and a cover part 2. A Wheatstone bridge 12 and a first electrical connection structure 13 are provided on the main body 11 of the main chip part 1. The first electrical connection structure 13 is electrically connected to the Wheatstone bridge 12. The cover part 2 includes a cover 21 and a second electrical connection structure 22. The cover 21 is bonded to the main body 11 and realizes the electrical connection between the second electrical connection structure 22 and the first electrical connection structure 13. The second electrical connection structure 22 passes through the cover 21, and one end of the second electrical connection structure 22 is electrically connected to the first electrical connection structure 13, and the other end is located on the side surface of the cover 21 away from the main body 11, so that the second electrical connection structure 22 can be directly welded and packaged with an external substrate through the SMT method, which makes the packaging convenient, thereby improving the packaging efficiency and reliability of the inverted back-compression pressure sensor.

[0154] Although the present invention has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present invention can be embodied in a variety of forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A method for producing an inverted back-pressure pressure sensor, characterized in that: The inverted back pressure sensor comprises: The main chip part includes a main body, a Wheatstone bridge and a first electrical connection structure, wherein a diaphragm is formed on the main body, the Wheatstone bridge is arranged on the diaphragm, and one end of the first electrical connection structure is connected to the Wheatstone bridge, and the other end extends to the outside of the diaphragm; The cover plate portion includes a cover plate and a second electrical connection structure, wherein the cover plate is bonded to the main body as an integral whole, and a vacuum cavity is constructed on a side of the diaphragm close to the cover plate, and the second electrical connection structure penetrates the cover plate, and one end of the second electrical connection structure is electrically connected to the first electrical connection structure, and the other end is located on a surface of the cover plate away from the main body, so that the second electrical connection structure can be directly welded and packaged with an external substrate by SMT; A groove is provided on one side of the cover plate facing the main body, and the main body blocks the open end of the groove to form a closed vacuum chamber; a pressure-inducing chamber is provided on one side of the main body away from the cover plate, and the main body forms the diaphragm between the pressure-inducing chamber and the vacuum chamber; The production method comprises the following steps: A10: Take a wafer and set a Wheatstone bridge on one side of the wafer; A20: Disposing a first bonding component and a first electrical connection structure connected to a Wheatstone bridge on one side of the wafer processed in step A10; A30: Take another wafer and set a through hole penetrating the wafer on the wafer; A40: disposing a conductive filling layer in the through hole of the wafer processed in step A30 and disposing a second bonding member and a conductive bonding layer on one side thereof; A50: Photolithography a groove on one side of the wafer processed in step A40 with a second bonding element; A60: bonding and annealing the wafer processed in step A20 and the wafer processed in step A50 to form a bonded crystal; wherein the second bonding component is bonded to the first bonding component, the conductive filling layer is bonded to the first electrical connection structure, and the opening of the groove is blocked by the wafer formed with the first electrical connection structure to form a vacuum cavity; A70: forming a pad connected to the conductive filling layer on the surface of the bonded crystal; the pad is located on a side of the conductive filling layer away from the conductive bonding layer, and the pad, the conductive filling layer and the conductive bonding layer constitute a second electrical connection structure; A80: A pressure induction cavity is formed on the side of the bonded crystal away from the pad; a diaphragm is formed between the pressure induction cavity and the vacuum cavity; A90: Plant solder balls on the pads of the bonded crystal; A100: The bonded crystal with solder balls is cut and sliced ​​to form a flip-chip back-loaded pressure sensor.

2. The method for producing a flip-chip back-loaded pressure sensor according to claim 1, characterized in that: A10: Take a wafer and set a Wheatstone bridge on one side of the wafer, specifically including: A11: Photolithography a light boron area on one side of the wafer, and forming a resistor strip in the light boron area by ion implantation and annealing diffusion process; A12: A boron-concentrated area is photolithographically formed on the wafer with the resistor bars, and a conductive line is formed in the boron-concentrated area by ion implantation and annealing diffusion process; the conductive line is connected to the resistor bars to form a Wheatstone bridge.

3. The method for producing a flip-chip back-loaded pressure sensor according to claim 1, characterized in that: A20: The step of providing a first bonding component and a first electrical connection structure connected to a Wheatstone bridge on one side of the wafer processed in step A10, specifically comprising: A21: forming a second oxide layer covering the Wheatstone bridge and the surface of the wafer on the wafer having the Wheatstone bridge formed thereon; A22: A passivation layer is formed on the wafer having the second oxide layer by depositing silicon nitride; the passivation layer covers the surface of the side of the wafer where the Wheatstone bridge is set; A23: photolithography a first lead hole and a second lead hole on the wafer having the passivation layer formed thereon; A24: Form a first electrical connection structure in the first lead hole and a first bonding member in the second lead hole through deposition and photolithography processes on the wafer processed in step A23.

4. The method for producing a flip-chip back-loaded pressure sensor according to claim 1, characterized in that: A40: the step of providing a conductive filling layer in the through hole of the wafer processed in step A30 and providing a second bonding member and a conductive bonding layer on one side thereof, specifically comprising: A41: A first oxide layer is formed on the inner wall surface and outer surface of the through hole of the wafer; A42: sequentially forming an adhesion layer and a seed layer in a through hole of the wafer having the first oxide layer formed thereon by a deposition process; A43: forming a conductive filling layer in a through hole of the wafer having the seed layer formed thereon by an electroplating process; A44: depositing an insulating layer on one end surface of the wafer processed in step A43, and photolithography of a third lead hole at a location corresponding to the conductive filling layer and photolithography of a fourth lead hole outside the conductive filling layer; A45: forming a conductive bonding layer at the third lead hole by deposition and photolithography on one end surface of the wafer processed in step A44, and forming a second bonding member at the fourth lead hole by deposition and photolithography; A46: depositing an insulating layer on an end surface of the wafer that is away from the conductive bonding layer and the second bonding component after being processed in step A45, and photoetching a fifth lead hole at a location corresponding to the conductive filling layer.

5. The method for producing a flip-chip back-loaded pressure sensor according to claim 4, characterized in that: A70: forming a pad connected to the conductive filling layer on the surface of the bonded crystal, specifically comprising: A pad is formed at the fifth lead hole of the bonding crystal by deposition and photolithography processes.

6. A method for producing an inverted back-pressure pressure sensor, characterized in that: The inverted back pressure sensor comprises: The main chip part includes a main body, a Wheatstone bridge and a first electrical connection structure, wherein a diaphragm is formed on the main body, the Wheatstone bridge is arranged on the diaphragm, and one end of the first electrical connection structure is connected to the Wheatstone bridge, and the other end extends to the outside of the diaphragm; The cover plate portion includes a cover plate and a second electrical connection structure, wherein the cover plate is bonded to the main body as an integral whole, and a vacuum cavity is constructed on a side of the diaphragm close to the cover plate, and the second electrical connection structure penetrates the cover plate, and one end of the second electrical connection structure is electrically connected to the first electrical connection structure, and the other end is located on a surface of the cover plate away from the main body, so that the second electrical connection structure can be directly welded and packaged with an external substrate by SMT; A groove is provided on one side of the cover plate facing the main body, and the main body blocks the open end of the groove to form a closed vacuum chamber; a pressure-inducing chamber is provided on one side of the main body away from the cover plate, and the main body forms the diaphragm between the pressure-inducing chamber and the vacuum chamber; The production method comprises the following steps: B10: Take a wafer and set a Wheatstone bridge on one side of the wafer; B20: Disposing a first electrical connection structure connected to a Wheatstone bridge on one side of the wafer processed in step B10; B30: Take another wafer and set a through hole penetrating the wafer on the wafer; B40: Photolithography a groove on one side of the wafer processed in step B30; B50: bonding and annealing the wafer processed in step B20 and the wafer processed in step B40 to form a bonded crystal; wherein the opening of the groove is blocked by the wafer having the first electrical connection structure to form a vacuum cavity; B60: Provide a conductive filling layer in the through hole; B70: forming an insulating layer on the surface of the bonded crystal, and forming a pad connected to the conductive filling layer; the pad is located on a side of the conductive filling layer away from the conductive bonding layer, and the pad, the conductive filling layer and the conductive bonding layer constitute a second electrical connection structure; B80: A pressure induction cavity is formed on the side of the bonded crystal away from the pad; a diaphragm is formed between the pressure induction cavity and the vacuum cavity; B90: Plant solder balls on the pads of the bonded crystal; B100: Cut and slice the bonded crystal with solder balls to form a flip-chip back-loaded pressure sensor.

7. The method for producing a flip-chip back-loaded pressure sensor according to claim 6, characterized in that: B10: Take a wafer and set a Wheatstone bridge on one side of the wafer, specifically including: B11: photolithography a light boron area on one side of the wafer, and forming a resistor strip in the light boron area by ion implantation and annealing diffusion process; B12: A boron-rich region is photolithographically formed on the wafer with the resistor strip, and a conductive line is formed in the boron-rich region by ion implantation and annealing diffusion process; the conductive line is connected to the resistor strip to form a Wheatstone bridge.

8. The method for producing a flip-chip back-loaded pressure sensor according to claim 6, characterized in that: Between step B10 and step B20, the method further includes: forming a second oxide layer covering the Wheatstone bridge and the surface of the wafer on the wafer having the Wheatstone bridge formed thereon; The process between step B30 and step B40 also includes: forming an oxide layer on the inner wall surface of the through hole and the outer surface of the wafer.

9. The method for producing a flip-chip back-loaded pressure sensor according to claim 8, characterized in that: After the step of forming a second oxide layer covering the Wheatstone bridge and the surface of the wafer on the wafer formed with the Wheatstone bridge and before step B50, the method further includes: forming a silicon nitride layer on the wafer covering the Wheatstone bridge by deposition and photolithography processes.

10. The method for producing a flip-chip back-loaded pressure sensor according to claim 6, characterized in that: B60: The step of providing a conductive filling layer in the through hole specifically comprises: B61: forming an adhesion layer and a seed layer in the through hole by a deposition process; B62: Forming a conductive filling layer through an electroplating process on the wafer having the adhesion layer and the seed layer.

11. The method for producing a flip-chip back-loaded pressure sensor according to claim 6, characterized in that: B70: forming an insulating layer on the surface of the bonded crystal and forming a pad connected to the conductive filling layer, specifically comprising: B71: forming an insulating layer by oxidation process on one end surface where the bonding crystal is connected to the conductive filling layer; B72: photolithography of a fifth lead hole on the insulating layer of the wafer processed in step B71; B73: A pad is formed at the fifth lead hole by deposition and photolithography processes.

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