Peak holding circuit of pixel detector with adaptive matching leakage current function

Abstract

The application discloses a peak holding circuit of a pixel detector with adaptive matching leakage current function and relates to the field of semiconductor integrated circuits. The peak holding circuit is used to solve the problem that the voltage signal holding time is affected due to the limitation of the capacitor in the peak holding circuit. The positive input end of a voltage comparator is connected with the signal input end of the peak holding circuit, the reverse input end of the voltage comparator is connected with the voltage output end of a holding core circuit, the output end of the voltage comparator is connected with the current source control end of the holding core circuit, and the voltage output end of the holding core circuit is connected with the voltage input end of an adaptive leakage current matching circuit. When the positive input signal of the voltage comparator is greater than or equal to the reverse input signal, the holding core circuit adjusts the voltage value output from the output end to increase. When the positive input signal of the voltage comparator is less than the reverse input signal, the holding core circuit adjusts the voltage value output from the output end to remain stable, and the adaptive leakage current matching circuit adaptively matches the leakage of the output voltage of the holding core circuit.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor integrated circuit design. BACKGROUND

[0002] In the scene of high-energy physics experiments, space particle detection, etc., it is necessary to detect particles in space to analyze the time information, position information and energy information of the particles. Internationally, single active pixel detectors or hybrid pixel detectors are generally used for particle detection in such application scenarios. The pixel detector can convert particles in space into electrical signals, and then extract and output the time information and energy information through the front-end circuit, and can also output the position information of the pixel at the same time.

[0003] In the pixel detector, in order to obtain the energy information of the particles to analyze the energy spectrum of the particles, a peak holding circuit is generally needed in the front-end circuit to obtain and hold the amplitude of the electrical signal converted by the detector. In order to obtain better spatial resolution, the pixel unit of the pixel detector is generally smaller. Therefore, due to the size limitation of the pixel unit, the holding capacitor in the peak holding circuit cannot be set too large, which results in that the voltage amplitude held by the peak holding circuit will change greatly due to the leakage of the tube, and the time of the voltage signal held will also be greatly affected. SUMMARY

[0004] The present application is to solve the problem that the size of the pixel unit will limit the size of the holding capacitor in the peak holding circuit, which in turn causes the voltage amplitude held by the peak holding circuit to change greatly due to the leakage of the tube, and the time of the voltage signal held will also be greatly affected. The present application provides a peak holding circuit of a pixel detector with adaptive leakage current matching function.

[0005] The peak holding circuit of the pixel detector with adaptive leakage current matching function comprises: a voltage comparator, a holding core circuit and an adaptive leakage current matching circuit.

[0006] The positive input end of the voltage comparator is connected to the signal input end of the peak holding circuit, and the negative input end is connected to the voltage output end of the holding core circuit. The output end of the voltage comparator is connected to the current source control end of the holding core circuit. The voltage output end of the holding core circuit is connected to the voltage input end of the adaptive leakage current matching circuit.

[0007] The voltage comparator is used for comparing two input signals, when the positive input signal of the voltage comparator is greater than or equal to the reverse input signal, the holding core circuit is used for adjusting the voltage value output by the output end to increase, when the positive input signal of the voltage comparator is less than the reverse input signal, the holding core circuit is used for adjusting the voltage value output by the output end to remain stable, and the adaptive leakage current matching circuit is used for adaptively matching the leakage of the holding core circuit output voltage.

[0008] Further, the holding core circuit comprises a PMOS tube PM1a, a PMOS tube PM1b, an NMOS tube NM0 and a holding capacitor C1.

[0009] The source levels of the PMOS tube PM1a and the PMOS tube PM1b are commonly connected to a power supply end, the gates of the PMOS tube PM1a and the PMOS tube PM1b are connected to the drain level of the PMOS tube PM1a and commonly serve as a current source control end of the holding core circuit, the drain of the PMOS tube PM1b, the drain of the NMOS tube NM0 and one end of the holding capacitor C1 are connected and commonly serve as a voltage output end of the holding core circuit, the gate of the NMOS tube NM0 serves as a reset signal input end of the holding core circuit, and the source of the NMOS tube NM0 and the other end of the holding capacitor C1 are both connected to a ground end.

[0010] Further, when the reset signal of the holding core circuit is enabled, the end voltage of the holding capacitor C1 is reset to zero potential.

[0011] Further, the adaptive leakage current matching circuit comprises PMOS tubes PM1-PM6 and NMOS tubes NM1-NM6.

[0012] The gates and source of the PMOS tube PM1, the sources of the PMOS tube PM3 and the PMOS tube PM4 are connected to the power supply end, the drain of the PMOS tube PM1 is connected to the source of the PMOS tube PM2, the drain of the PMOS tube PM2 is connected to the drain and gate of the NMOS tube NM5 and the gate of the NMOS tube NM6, the source of the NMOS tube NM5 is connected to the drain and gate of the NMOS tube NM4 and the gate of the NMOS tube NM3, the gate of the PMOS tube PM3 is connected to the gate and drain of the PMOS tube PM4 and the source of the PMOS tube PM5, the drain of the PMOS tube PM3 is connected to the source of the PMOS tube PM6, the gate of the PMOS tube PM6 is connected to the gate and drain of the PMOS tube PM5 and the drain of the NMOS tube NM2, the source of the NMOS tube NM6 is connected to the drain of the NMOS tube NM3, and the source of the NMOS tube NM2 is connected to the drain of the NMOS tube NM1.

[0013] The gate of the PMOS tube PM2, the gate of the NMOS tube NM2, the drain of the PMOS tube PM6 and the drain of the NMOS tube NM6 are connected to the voltage output end of the holding core circuit.

[0014] The source of the NMOS tube NM4, the source of the NMOS tube NM3 and the gate and source of the NMOS tube NM1 are connected to the power ground end.

[0015] Further, the peak holding circuit of the pixel detector with the adaptive matching leakage current function further comprises an output buffer, and the voltage output end of the holding core circuit is connected to the inverting input end of the voltage comparator through the output buffer.

[0016] The output buffer is used for enhancing the driving force of the voltage output by the holding core circuit and isolating the voltage output by the holding core circuit from an external circuit.

[0017] The technical scheme provided by the present application has the beneficial effects that:

[0018] In order to realize that the smaller holding capacitor can also make the peak holding circuit better hold the voltage amplitude signal in the pixel detector, the peak holding circuit of the pixel detector with the adaptive matching leakage current function can adaptively match the leakage current on the holding capacitor C1, so as to weaken the influence of the leakage current on the voltage signal on the holding capacitor and improve the robustness to process fluctuations. BRIEF DESCRIPTION OF DRAWINGS

[0019] Fig. 1 FIG. 1 is a structural diagram of the peak holding circuit of the pixel detector with the adaptive matching leakage current function;

[0020] Fig. 2 FIG. 2 is a structural diagram of the holding core circuit;

[0021] Fig. 3 FIG. 3 is a structural diagram of the adaptive matching leakage current circuit. DETAILED DESCRIPTION

[0022] The technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0023] DETAILED DESCRIPTION Figs. 1 to 3This embodiment specifically describes the peak hold circuit of the pixel detector with adaptive leakage current matching function, which includes: a voltage comparator, a hold core circuit, an output buffer, and an adaptive leakage current matching circuit.

[0024] like Fig. 1 As shown, the positive input terminal of the voltage comparator serves as the signal input terminal of the peak hold circuit, and the inverting input terminal is connected to the voltage output terminal of the output buffer; the output terminal of the voltage comparator is connected to the current source control terminal of the hold core circuit, and the voltage output terminal of the hold core circuit is connected to the voltage input terminal of the output buffer; the voltage output terminal of the hold core circuit is also connected to the adaptive leakage current matching circuit.

[0025] Specifically, such as Fig. 2 As shown, the holding core circuit includes: PMOS transistors PM1a and PM1b, NMOS transistor NM0, and holding capacitor C1. The sources of PMOS transistors PM1a and PM1b are connected to the power supply terminal. The gates of both PMOS transistors PM1a and PM1b are connected to the drain of PMOS transistor PM1a and together serve as the current source control terminal of the holding core circuit. The drain of PMOS transistor PM1b, the drain of NMOS transistor NM0, and one end of holding capacitor C1 are connected and together serve as the voltage output terminal of the holding core circuit. The gate of NMOS transistor NM0 serves as the reset signal input terminal of the holding core circuit. The source of NMOS transistor NM0 and the other end of holding capacitor C1 are both connected to ground. When the reset signal of the holding core circuit is enabled, the voltage at the terminal of holding capacitor C1 is reset to zero potential.

[0026] like Fig. 3 As shown, the adaptive leakage current matching circuit includes: PMOS transistors PM1 to PM6 and NMOS transistors NM1 to NM6.

[0027] The gate and source of PMOS transistor PM1, as well as the sources of PMOS transistors PM3 and PM4, are all connected to the power supply. The drain of PMOS transistor PM1 is connected to the source of PMOS transistor PM2. The drain of PMOS transistor PM2 is connected to the drain and gate of NMOS transistor NM5 and the gate of NMOS transistor NM6. The source of NMOS transistor NM5 is connected to the drain and gate of NMOS transistor NM4 and the gate of NMOS transistor NM3. The gate of PMOS transistor PM3 is connected to the gate and drain of PMOS transistor PM4 and the source of PMOS transistor PM5. The drain of PMOS transistor PM3 is connected to the source of PMOS transistor PM6. The gate of PMOS transistor PM6 is connected to the gate and drain of PMOS transistor PM5 and the drain of NMOS transistor NM2. The source of NMOS transistor NM6 is connected to the drain of NMOS transistor NM3. The source of NMOS transistor NM2 is connected to the drain of NMOS transistor NM1. The gates of PMOS transistor PM2, NMOS transistor NM2, PMOS transistor PM6, and NMOS transistor NM6 are all connected to the voltage output terminal of the holding core circuit. The sources of NMOS transistor NM4 and NMOS transistor NM3, as well as the gate and source of NMOS transistor NM1, are all connected to the power supply ground.

[0028] The principle of the peak hold circuit of the pixel detector with adaptive leakage current matching function described in this embodiment is as follows:

[0029] The voltage comparator is used to compare two input signals. When the input signal VIN has not reached its peak value, that is, when the positive input signal of the voltage comparator is greater than or equal to the negative input signal, the holding core circuit adjusts the charging of its internal holding capacitor C1 so that the voltage value output at its output terminal increases as the holding capacitor C1 is charged. When the input signal VIN reaches its peak value, that is, when the positive input signal of the voltage comparator is less than the negative input signal, the holding core circuit shuts off its internal current source so that there is no longer a charging current on the holding capacitor C1. At this time, the voltage value output at the output terminal remains stable, and the voltage of VOUT also remains stable, and is the peak voltage of the input signal VIN.

[0030] In the holding core circuit, holding capacitor C1 converts the current of PMOS transistor PM1b into a voltage signal and holds this voltage signal. The voltage on the upper plate of holding capacitor C1 is the VX node voltage, and this voltage signal is input to the voltage input terminal of the output buffer. The gate of NMOS transistor NM0 is connected to the reset signal RST. When the reset signal RST is enabled, the voltage signal held on holding capacitor C1 can be reset to zero potential.

[0031] The input terminal of the output buffer is connected to the output terminal of the holding core circuit. It can enhance the driving capability of the voltage signal obtained by the holding core circuit and output it to the inverting input terminal of the voltage comparator, and serve as the output terminal of the peak hold circuit. At the same time, the output buffer can isolate the voltage signal obtained by the holding core circuit from other circuits, so as to avoid interference from other circuits to the voltage signal obtained by the holding core circuit.

[0032] The adaptive leakage current matching circuit is used to adaptively match the leakage current of the output voltage of the holding core circuit. Specifically, PMOS transistor PM1 only replicates the leakage current Ileakage_p of PMOS transistor PM1b in the off state in the holding core circuit. NMOS transistors NM3 to NM6 form a common-source cascode current mirror, which replicates the leakage current Ileakage_p of PMOS transistor PM1. The gate of PMOS transistor PM2 is connected to the output terminal of the holding core circuit, which can suppress the channel length modulation effect of PMOS transistor PM1 caused by the difference in the output voltage of the holding core circuit. NMOS transistor NM1 only replicates the leakage current Ileakage_n of NMOS transistor NM0 in the off state in the holding core circuit. PMOS transistors PM3 to PM6 form a common-source cascode current mirror, which replicates the leakage current Ileakage_n of PMOS transistor PM1. The gate of NMOS transistor NM2 is connected to the output of the holding core circuit, which can suppress the channel length modulation effect of NMOS transistor NM1 caused by the difference in the output voltage of the holding core circuit. Thus, the total leakage current from the power supply to the upper plate of holding capacitor C1 inside the holding core circuit is Ileakage_p + Ileakage_n, while the total leakage current from the upper plate of holding capacitor C1 to ground is Ileakage_n + Ileakage_p. It can be seen that these two leakage currents are equal, thus achieving leakage current matching of holding capacitor C1. Theoretically, the voltage on holding capacitor C1 will not be affected by the leakage current and can be maintained indefinitely, improving robustness to process fluctuations.

[0033] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A peak hold circuit for a pixel detector with adaptive leakage current matching function, characterized in that, include: Voltage comparator, holding core circuit and adaptive leakage current matching circuit; The positive input terminal of the voltage comparator serves as the signal input terminal of the peak hold circuit, and the negative input terminal is connected to the voltage output terminal of the hold core circuit. The output terminal of the voltage comparator is connected to the current source control terminal of the hold core circuit, and the voltage output terminal of the hold core circuit is connected to the voltage input terminal of the adaptive leakage current matching circuit. The voltage comparator is used to compare two input signals. When the positive input signal of the voltage comparator is greater than or equal to the negative input signal, the holding core circuit is used to increase the voltage value output at its output terminal. When the positive input signal of the voltage comparator is less than the negative input signal, the holding core circuit is used to keep the voltage value output at its output terminal stable. The adaptive leakage current matching circuit is used to adaptively match the leakage current of the output voltage of the holding core circuit. The adaptive leakage current matching circuit includes: PMOS transistors PM1~PM6 and NMOS transistors NM1~NM6; The gate and source of PMOS transistor PM1, as well as the sources of PMOS transistors PM3 and PM4, are all connected to the power supply. The drain of PMOS transistor PM1 is connected to the source of PMOS transistor PM2. The drain of PMOS transistor PM2 is connected to the drain and gate of NMOS transistor NM5 and the gate of NMOS transistor NM6. The source of NMOS transistor NM5 is connected to the drain and gate of NMOS transistor NM4 and the gate of NMOS transistor NM3. The gate of PMOS transistor PM3 is connected to the gate and drain of PMOS transistor PM4 and the source of PMOS transistor PM5. The drain of PMOS transistor PM3 is connected to the source of PMOS transistor PM6. The gate of PMOS transistor PM6 is connected to the gate and drain of PMOS transistor PM5 and the drain of NMOS transistor NM2. The source of NMOS transistor NM6 is connected to the drain of NMOS transistor NM3. The source of NMOS transistor NM2 is connected to the drain of NMOS transistor NM1. The gate of PMOS transistor PM2, the gate of NMOS transistor NM2, the drain of PMOS transistor PM6, and the drain of NMOS transistor NM6 are all connected to the voltage output terminal of the holding core circuit. The source of NMOS transistor NM4, the source of NMOS transistor NM3, and the gate and source of NMOS transistor NM1 are all connected to the power supply ground.

2. The peak hold circuit of the pixel detector with adaptive matching leakage current function according to claim 1, characterized in that, The holding core circuit includes: PMOS transistor PM1a, PMOS transistor PM1b, NMOS transistor NM0, and holding capacitor C1; The sources of PMOS transistors PM1a and PM1b are connected to the power supply terminal. The gates of both PMOS transistors PM1a and PM1b are connected to the drain of PMOS transistor PM1a and together serve as the current source control terminal of the holding core circuit. The drain of PMOS transistor PM1b, the drain of NMOS transistor NM0, and one end of holding capacitor C1 are connected and together serve as the voltage output terminal of the holding core circuit. The gate of NMOS transistor NM0 serves as the reset signal input terminal of the holding core circuit. The source of NMOS transistor NM0 and the other end of holding capacitor C1 are both connected to the ground terminal.

3. The peak hold circuit of the pixel detector with adaptive matching leakage current function according to claim 2, characterized in that, When the reset signal of the holding core circuit is enabled, the terminal voltage of the holding capacitor C1 is reset to zero potential.

4. The peak hold circuit of the pixel detector with adaptive matching leakage current function according to claim 1, characterized in that, It also includes an output buffer, through which the voltage output terminal of the holding core circuit is connected to the inverting input terminal of the voltage comparator; The output buffer is used to enhance the driving force of the voltage output by the holding core circuit and to isolate the voltage output by the holding core circuit from external circuits.

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