Field programmable gate array encryption method, system, device, equipment and medium

Abstract

The present invention provides an encryption method, system, device, equipment and medium of a field programmable gate array, and relates to the field of data security technology. The method is applied to a RISC-V processor in an encryption system of a field programmable gate array. The encryption system of the field programmable gate array includes: an encryption and decryption program, a RISC-V processor and a Flash memory. The processor is implemented based on an FPGA. The method includes: receiving at least one encryption instruction; wherein the encryption instruction is obtained by cross-compiling an original encryption request by an encryption and decryption program through a RISC-V cross-compilation tool, and the original encryption request is used to instruct the field programmable gate array to be encrypted; each encryption instruction is decoded and executed to obtain an encrypted ciphertext of each encryption instruction; each encrypted ciphertext is written into a Flash memory. In the present invention, encryption of FPGA can be realized using fewer resources, which reduces resource occupancy.

Description

Technical Field

[0001] The present invention relates to the field of data security technology, and in particular to an encryption method, system, device, equipment and medium of a field programmable gate array. Background Art

[0002] FPGA (Field-Programmable Gate Array) is a programmable integrated circuit widely used in various fields such as military, finance and medical treatment, some of which have extremely high requirements for data confidentiality and security. Therefore, encrypting FPGA to prevent unauthorized access, copying and modification is an indispensable and important part.

[0003] Among many encryption algorithms, the RSA asymmetric encryption algorithm is one of the more secure public key cryptographic algorithms. The difficulty of cracking the RSA algorithm is positively correlated with the key length. The longer the key length, the greater the difficulty of cracking. At present, the key length used for RSA encryption is generally 1024 bits. However, integrating RSA encryption logic inside the FPGA to encrypt the (Deoxyribonucleic acid, DNA) information of Xilinx FPGA will greatly increase the use of FPGA design resources, resulting in excessive resources occupied by FPGA encryption methods.

[0004] Therefore, how to reduce the resources occupied by field programmable gate array encryption has become a technical problem that urgently needs to be solved in the industry. Summary of the invention

[0005] The present invention provides a field programmable gate array encryption method, system, device, equipment and medium, which are used to solve the defect that the FPGA encryption method in the prior art occupies too many resources, and realizes that FPGA encryption can be realized by using fewer resources, thereby reducing resource occupancy.

[0006] In a first aspect, the present invention provides an encryption method for a field programmable gate array, which is applied to a RISC-V processor in an encryption system of a field programmable gate array, wherein the encryption system of the field programmable gate array comprises: an encryption and decryption program, the RISC-V processor, and a Flash memory, wherein the RISC-V processor is a processor implemented based on a field programmable gate array; the method comprises the following steps:

[0007] Receive at least one encryption instruction; the encryption instruction is obtained by the encryption and decryption program after cross-compiling the original encryption request through the RISC-V cross-compilation tool, and the encryption instruction is a 32-bit RISC-V instruction; the original encryption request is used to instruct to encrypt the field programmable gate array;

[0008] Decoding and executing each of the encrypted instructions to obtain a first instruction execution result of each of the encrypted instructions; the first instruction execution result is a first encrypted ciphertext;

[0009] Writing each of the first encrypted ciphertexts into the Flash memory.

[0010] According to an encryption method for a field programmable gate array provided by the present invention, the external devices of the RISC-V processor include: a read-only memory external device, a random access memory external device, a universal asynchronous receiver or transmitter external device, a DNA external device and a universal input and output external device;

[0011] The step of decoding and executing each of the encrypted instructions to obtain a first instruction execution result of each of the encrypted instructions includes:

[0012] For any of the encrypted instructions, an instruction fetch operation is performed from a read-only memory external device according to an instruction fetch address in the encrypted instruction;

[0013] According to the encrypted instruction, DNA identification information of the field programmable gate array is read from the DNA external device; the DNA identification information includes at least one of the following: device identification, manufacturing information, configuration data, security features, version information, user data, device function, and supply chain information;

[0014] Encrypting the read DNA identification information of the field programmable gate array using a target encryption algorithm to obtain an encrypted ciphertext of the encryption instruction;

[0015] The encrypted ciphertext of each of the encrypted instructions is determined as the execution result of each of the first instructions.

[0016] According to a field programmable gate array encryption method provided by the present invention, the target encryption algorithm is an RSA encryption algorithm; the target encryption algorithm is used to encrypt the read DNA identification information of the field programmable gate array to obtain the encrypted ciphertext of the encryption instruction, including:

[0017] Calculate the corresponding modulus according to two preset prime numbers, and calculate the Euler function corresponding to the modulus;

[0018] Determine public key parameters according to the Euler function;

[0019] Calculating the inverse element of the public key parameter with respect to the Euler function, and determining the inverse element as a private key parameter;

[0020] Determine a public key according to the public key parameter and the modulus, and determine a private key according to the private key parameter and the modulus; the public key and the private key constitute a key pair;

[0021] The DNA identification information is encrypted according to the private key in the key pair to obtain the encrypted ciphertext of the encryption instruction.

[0022] According to an encryption method for a field programmable gate array provided by the present invention, the external device of the RISC-V processor further includes a serial peripheral interface; the step of writing each of the first encrypted ciphertexts into the Flash memory includes:

[0023] Each of the first encrypted ciphertexts is written into the Flash memory through the serial peripheral interface.

[0024] According to a field programmable gate array encryption method provided by the present invention, the method further includes:

[0025] Obtaining a second encrypted ciphertext from the Flash memory via the serial peripheral interface;

[0026] Decrypting the second encrypted ciphertext using a target decryption algorithm to obtain a plaintext corresponding to the second encrypted ciphertext; the target decryption algorithm is a decryption algorithm corresponding to the target encryption algorithm; the target decryption algorithm is an RSA encryption algorithm;

[0027] Comparing the decrypted plaintext with the read DNA identification information of the field programmable gate array to obtain a consistency comparison result;

[0028] According to the consistency comparison result, the service module of the field programmable gate array is controlled.

[0029] According to a field programmable gate array encryption method provided by the present invention, the control of the service module of the field programmable gate array according to the consistency comparison result includes:

[0030] When the consistency comparison result is consistent, controlling the service module of the field programmable gate array to operate normally;

[0031] When the consistency comparison result is inconsistent, the service module of the field programmable gate array is controlled to stop running.

[0032] According to a field programmable gate array encryption method provided by the present invention, the method further includes:

[0033] Performing a data fetch operation from a random access memory according to a first data address in a received memory load instruction;

[0034] The data in the memory storage instruction is written into a corresponding address of the random access memory according to the second data address in the received memory storage instruction.

[0035] In a second aspect, the present invention further provides an encryption system of a field programmable gate array, characterized in that the encryption system of the field programmable gate array comprises: an encryption and decryption program, a RISC-V processor and a Flash memory, wherein the RISC-V processor is a processor implemented based on the field programmable gate array; wherein:

[0036] The encryption and decryption program is used to cross-compile the original encryption request through a RISC-V cross-compilation tool to obtain at least one encryption instruction, and send it to the RISC-V processor; the encryption instruction is a 32-bit RISC-V instruction; the original encryption request is used to instruct to encrypt the field programmable gate array;

[0037] The RISC-V processor is used to decode and execute each of the encrypted instructions to obtain a first instruction execution result of each of the encrypted instructions; the first instruction execution result is a first encrypted ciphertext; and each of the first encrypted ciphertexts is written into the Flash memory;

[0038] The Flash memory is used to store each of the encrypted ciphertexts.

[0039] In a third aspect, the present invention further provides an encryption device for a field programmable gate array, which is applied to a RISC-V processor in an encryption system of a field programmable gate array, wherein the encryption system of the field programmable gate array comprises: an encryption and decryption program, the RISC-V processor, and a Flash memory, wherein the RISC-V processor is a processor implemented based on a field programmable gate array; the device comprises the following modules:

[0040] A receiving module, configured to receive at least one encryption instruction; the encryption instruction is obtained by the encryption / decryption program after cross-compiling the original encryption request through a RISC-V cross-compilation tool, and the encryption instruction is a 32-bit RISC-V instruction; the original encryption request is used to instruct to encrypt a field programmable gate array;

[0041] An encryption module, used for decoding and executing each of the encryption instructions to obtain a first instruction execution result of each of the encryption instructions; the first instruction execution result is a first encrypted ciphertext;

[0042] A writing module is used to write each of the first encrypted ciphertexts into the Flash memory.

[0043] In a fourth aspect, the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, an encryption method of a field programmable gate array as described above is implemented.

[0044] In a fifth aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the encryption method of the field programmable gate array as described in any one of the above.

[0045] In a sixth aspect, the present invention further provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the encryption method of the field programmable gate array as described in any one of the above is implemented.

[0046] The encryption method, system, device, equipment and medium of a field programmable gate array provided by the present invention are applied to a RISC-V processor in an encryption system of a field programmable gate array. The encryption system of the field programmable gate array includes: an encryption and decryption program, a RISC-V processor and a Flash memory. The RISC-V processor is a processor implemented based on a field programmable gate array. The method includes: first, receiving at least one encryption instruction, wherein the encryption instruction is obtained by cross-compiling an original encryption request by the encryption and decryption program through a RISC-V cross-compilation tool, the encryption instruction is a 32-bit RISC-V instruction, and the original encryption request is used to instruct encryption of the field programmable gate array; then, decoding and executing each encryption instruction to obtain a first instruction execution result of each encryption instruction, wherein the first instruction execution result is a first encrypted ciphertext; and writing each encrypted ciphertext into the Flash memory.

[0047] Since RISC-V is an open source instruction set architecture based on the reduced instruction set principle, the present invention is based on the RISC-V processor receiving encryption instructions of the encryption and decryption program, the encryption instructions are obtained after the encryption and decryption program cross-compiles the original encryption request through the RISC-V cross-compilation tool, and the original encryption request is used to instruct to encrypt the field programmable gate array; the RISC-V processor decodes and executes each encryption instruction to obtain the first instruction execution result of each encryption instruction, that is, to realize the encryption of the field programmable gate array, and to realize the encryption of FPGA using fewer resources, thereby reducing resource occupancy. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1 It is a flow chart of the encryption method of the field programmable gate array provided by the present invention.

[0050] Figure 2 It is a structural schematic diagram of the encryption system of the field programmable gate array provided by the present invention.

[0051] Figure 3 It is a schematic diagram of the structure of the RISC-V processor in the encryption system of the field programmable gate array provided by the present invention.

[0052] Figure 4 This is a schematic diagram of peripheral address space allocation of the RISC-V processor provided by the present invention.

[0053] Figure 5 It is a structural schematic diagram of the encryption device of the field programmable gate array provided by the present invention.

[0054] Figure 6 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first" and "second" are generally a class, and the number of objects is not limited. For example, the first node can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally represents that the front and back associated objects are in an "or" relationship.

[0057] Combine the following Figure 1-Figure 6The present invention describes the encryption method, system, device, equipment and medium of the field programmable gate array.

[0058] Figure 1 The present invention is a flowchart of an encryption method for a field programmable gate array, which is applied to a fifth generation reduced instruction set computer (RISC-V) processor in an encryption system of a field programmable gate array. The encryption system of the field programmable gate array includes: an encryption and decryption program, a RISC-V processor, and a flash memory. The RISC-V processor is a processor implemented based on a field programmable gate array, such as Figure 1 As shown, the method includes the following:

[0059] Step 101, receiving at least one encryption instruction; the encryption instruction is obtained by cross-compiling the original encryption request through the RISC-V cross-compilation tool by the encryption and decryption program, and the encryption instruction is a 32-bit RISC-V instruction; the original encryption request is used to instruct to encrypt the field programmable gate array;

[0060] Specifically, the execution subject of this embodiment is a RISC-V processor in the encryption system of the field programmable gate array. Figure 2 FIG. 1 is a schematic diagram of the structure of the encryption system of the field programmable gate array provided by the present invention, such as Figure 2 As shown, the encryption system of the field programmable gate array includes: an encryption and decryption program, a RISC-V processor and a Flash memory. The RISC-V processor is a processor implemented based on the field programmable gate array. The encryption and decryption program is mainly responsible for implementing the specific logic of encryption and decryption, and compiling it into 32-bit RISC-V instructions through the RISC-V cross-compilation tool. The RISC-V processor is mainly responsible for fetching, decoding and executing the RISC-V instructions generated by the encryption and decryption program, thereby realizing the encryption of the FPGA. The Flash memory is used to store encrypted ciphertext.

[0061] Among them, it should be noted that RISC-V is an open source instruction set architecture based on the principle of reduced instruction set, with a simple architecture and modular design. The main features of RISC-V include: 1. Modularity: The design of RISC-V is very modular, allowing different functional extensions to be selected and customized as needed to adapt to specific application requirements. 2. Concise and efficient: Following the RISC principle, the instruction set of RISC-V is simple and easy to implement, which helps to improve the performance and energy efficiency of the processor. 3. Scalability: RISC-V allows developers to add custom extended instruction sets to support specific hardware functions or software requirements. 4. Multi-platform support: RISC-V supports a wide range of applications from small embedded systems to high-performance computing platforms, which makes it have potential application prospects in different market fields. Based on the characteristics of RISC-V being completely open source and easy to port, the FPGA encryption part can be implemented by the RISC-V processor, thereby occupying less resources and better reducing the complexity of the encryption system.

[0062] Flash memory, also known as flash memory, is a non-volatile storage technology that can keep data from being lost in the event of a power outage. It is mainly divided into two categories: NOR Flash and NAND Flash. 1. NOR Flash is usually used to store small-capacity data. It is characterized by fast read speed and can perform operations in memory (eXecute In Place, XIP), but the write and erase speeds are relatively slow and the cost is high. 2. The interface of NOR Flash is usually parallel, which is suitable for the storage of execution code because it can directly read data like random access memory (Random Access Memory, RAM). NAND Flash is mainly used to store large-capacity data, such as in solid-state drives (SSD), USB flash drives, secure digital cards (SD) and embedded multimedia cards eMMC. NAND Flash is characterized by fast write and erase speeds, high storage density, and low cost, but the random read speed is slow and does not support XIP. The interface of NAND Flash is usually serial, and its storage units are connected in series. Each time data is read, address information needs to be sent first, so the read operation is relatively slow. Furthermore, the working principle of Flash memory is based on a floating gate Metal-Oxide-Semiconductor (MOS) tube, which stores data by controlling the charge in the floating gate. When there is a positive charge in the floating gate, it represents data "1", and when there is a negative charge or electron in the floating gate, it represents data "0". When writing data, electrons are injected into the floating gate through a high voltage, and when erasing data, electrons are removed from the floating gate through the Fowler-Nordheim tunneling effect. In this embodiment, the choice of Flash memory depends on the specific usage scenario. For embedded systems that need to read instructions quickly, NOR Flash is mostly selected.

[0063] When the field programmable gate array needs to be encrypted, first, RISC-V receives at least one encryption instruction. It can be understood that the encryption instruction is obtained by the encryption and decryption program after cross-compiling the original encryption request through the RISC-V cross-compilation tool. The original encryption request is used to instruct the field programmable gate array to be encrypted; the encryption instruction is a 32-bit RISC-V instruction. The RISC-V cross-compilation tool is a set of tools for compiling RISC-V architecture programs, which allows programs that can run on RISC-V hardware to be compiled on a host with a non-RISC-V architecture. The RISC-V cross-compilation tools in this embodiment include RISC-V GNU Toolchain, RISC-V LLVM Toolchain, Docker container, pre-compiled toolchain, etc.

[0064] Step 102: Decode and execute each encrypted instruction to obtain a first instruction execution result of each encrypted instruction; the first instruction execution result is an encrypted ciphertext;

[0065] Specifically, after receiving the 32-bit encrypted instruction, the RISC-V processor decodes and executes each encrypted instruction to obtain an execution result. Since RISC-V is an open source instruction set, the RISC-V processor can use FPGA code to decode and execute each encrypted instruction to obtain an encrypted ciphertext, that is, the first instruction execution result. Exemplarily, using FPGA code to implement RISC-V encrypted instructions usually involves the following steps: 1. Select an FPGA development board: for example, Xilinx FPGA, 2. Install development tools: Install FPGA development tools, such as Xilinx Vivado or Intel Quartus, which provide full-process support for designing, simulating, compiling and configuring FPGA. 3. Design processor architecture: Select a suitable processor architecture, such as RV32I or RV64I, according to the RISC-V instruction set architecture, and design registers, instruction pipelines and memory I / O interfaces. 4. Write hardware description language: Use Verilog or VHDL to write the code of the RISC-V processor, including modules such as instruction decoding, execution unit, and register file. 5. Compile the code: compile the written hardware description language code into a bitstream file that the FPGA can recognize. 6. Configure the FPGA: download the compiled bitstream file to the FPGA and perform actual testing.

[0066] Step 103: Write each encrypted ciphertext into the Flash memory.

[0067] Specifically, each encrypted ciphertext is written into the Flash memory, for example, the encrypted data is written into the Flash memory through the Serial Peripheral Interface (SPI) of the RISC-V processor. This may involve writing the data in blocks and handling the page write limit of the Flash memory.

[0068] The method provided in this embodiment is applied to a RISC-V processor in an encryption system of a field programmable gate array. The encryption system of the field programmable gate array includes: an encryption and decryption program, a RISC-V processor and a Flash memory. The RISC-V processor is a processor implemented based on a field programmable gate array. The method includes: first, receiving at least one encryption instruction, wherein the encryption instruction is obtained by cross-compiling an original encryption request through a RISC-V cross-compilation tool by the encryption and decryption program, the encryption instruction is a 32-bit RISC-V instruction, and the original encryption request is used to instruct encryption of the field programmable gate array; then, decoding and executing each encryption instruction to obtain a first instruction execution result of each encryption instruction, wherein the first instruction execution result is a first encrypted ciphertext; and writing each encrypted ciphertext into the Flash memory.

[0069] Since RISC-V is an open source instruction set architecture based on the reduced instruction set principle, the present invention is based on the RISC-V processor receiving encryption instructions of the encryption and decryption program, the encryption instructions are obtained after the encryption and decryption program cross-compiles the original encryption request through the RISC-V cross-compilation tool, and the original encryption request is used to instruct to encrypt the field programmable gate array; the RISC-V processor decodes and executes each encryption instruction to obtain the first instruction execution result of each encryption instruction, that is, to realize the encryption of the field programmable gate array, and to realize the encryption of FPGA using fewer resources, thereby reducing resource occupancy.

[0070] According to an encryption method of a field programmable gate array provided by the present invention, the external devices of the RISC-V processor include: a read-only memory external device, a random access memory external device, a universal asynchronous receiver or transmitter external device, a DNA external device and a universal input and output external device;

[0071] Decoding and executing each encrypted instruction to obtain a first instruction execution result of each encrypted instruction includes:

[0072] For any encrypted instruction, an instruction fetch operation is performed from a read-only memory external device according to an instruction fetch address in the encrypted instruction;

[0073] Reading DNA identification information of the field programmable gate array from the DNA external device according to the encrypted instruction; the DNA identification information includes at least one of the following: device identification, manufacturing information, configuration data, security features, version information, user data, device function, and supply chain information;

[0074] The DNA identification information of the read field programmable gate array is encrypted by using a target encryption algorithm to obtain an encrypted ciphertext of the encryption instruction;

[0075] The encrypted ciphertext of each encrypted instruction is determined as each first instruction execution result.

[0076] Specifically, the external devices of the RISC-V processor in the present invention include: a read-only memory external device, a random access memory external device, a universal asynchronous receiver or transmitter external device, a DNA external device and a universal input and output external device. Figure 3 is a schematic diagram of the structure of the RISC-V processor in the encryption system of the field programmable gate array provided by the present invention, such as Figure 3As shown, RISC-V contains a total of 6 peripherals (external devices), including ROM (Read-Only Memory), RAM (Random Access Memory), UART (Universal Asynchronous Receiver / Transmitter), SPI (Serial Peripheral Interface), Xilinx DNA and GPIO (General Purpose Input / Output). Among them, ROM is a semiconductor memory used to store fixed data and instructions in firmware or software programs, which will not be easily changed or deleted when the system starts or during operation. RAM (Random Access Memory) is a commonly used computer memory used to store data and programs when the computer is running. It is volatile, which means that once the power is off, the data stored in it will be lost. UART is a widely used serial communication interface for asynchronous communication. It allows different devices to transmit data through serial ports. The principle of serial data transmission: UART converts data from parallel form to serial form and transmits it through a pair of lines (TX and RX). The TX line is used to send data and the RX line is used to receive data. SPI is a high-speed, full-duplex, synchronous communication bus for short-distance communication. Xilinx DNA is a unique identification information embedded by Xilinx in its FPGA and SoC products. It contains a variety of data used to identify and verify the integrity of the hardware. GPIO is a set of bidirectional multiplexers used for data exchange in microcontrollers and other electronic systems. GPIO pins can be configured in input mode or output mode, allowing the microcontroller to interact with external devices. In actual operation, ROM stores RISC-V instructions generated by C programs, RAM stores memory data, UART peripherals are responsible for receiving and sending serial port data, SPI peripherals are responsible for RISC-V reading and writing flash through the SPI interface, XilinxDNA peripherals are responsible for reading the DNA information of the FPGA, and GPIO peripherals are responsible for transferring the decrypted plaintext and DNA comparison results between RISC-V and other FPGA logic.

[0077] Figure 4 : is a schematic diagram of peripheral address space allocation of the RISC-V processor provided by the present invention, such as Figure 4 As shown in the figure, the address space size of ROM and RAM peripherals is 0x4000, and the addresses of other peripherals such as UART, SPI, GPIO, Xilinx DNA, etc. are all at 0x80000000.

[0078] Correspondingly, the process of performing field programmable gate array in step 102 can be implemented by the following steps:

[0079] First, for any encrypted instruction, an instruction fetch operation is performed from a read-only memory external device according to the instruction fetch address in the encrypted instruction; further, according to the encrypted instruction, the DNA identification information of the field programmable gate array is read from the DNA external device, and the DNA identification information includes at least one of the following: device identification, manufacturing information, configuration data, security features, version information, user data, device function, and supply chain information; wherein, the DNA identification information generally includes the following information: 1. Device identification: Each Xilinx device has a unique identification code to distinguish different FPGA or SoC devices. 2. Manufacturing information: including manufacturing date, wafer batch number, etc., which helps to track the production history of the product. 3. Configuration data: a hash value of the bitstream or configuration file used to initialize the FPGA to ensure that the correct configuration data is loaded. 4. Security features: may contain encryption keys or other security-related data to protect the design from unauthorized copying or tampering. 5. Version information: the version number of the design or configuration file, which helps to manage and maintain different versions of the design. 6. User data: users can embed custom data, such as serial numbers, product codes, or other identification information. 7. Device capabilities: metadata describing device capabilities, such as supported interface types, performance indicators, etc. 8. Supply chain information: information used for supply chain management and verification to ensure the authenticity and integrity of the device throughout the supply chain.

[0080] Furthermore, the DNA identification information of the read field programmable gate array is encrypted using a target encryption algorithm to obtain an encrypted ciphertext of the encryption instruction.

[0081] Exemplarily, the target encryption algorithm is, for example, the RSA1024 encryption algorithm, where RSA1024 is an asymmetric encryption algorithm, where "1024" refers to the length of the key, i.e., 1024 bits. It is based on a simple number theory fact: it is easy to multiply two large prime numbers, but it is extremely difficult to do the reverse (i.e., prime factorization). The security of RSA is built on this difficulty. The public key can be shared publicly and used to encrypt data, while the private key must be kept secret and used to decrypt data. The public key and the private key are mathematically related, but it is impossible to derive the private key from the public key.

[0082] The encryption process of the RSA1024 encryption algorithm includes the following steps:

[0083] 1. Select two large prime numbers p and q, and calculate their product n (i.e. modulus), where the length of n is 1024 bits.

[0084] 2. Calculate the Euler function of n ,Right now .

[0085] 3. Choose one with A relatively prime small integer e is used as the public key exponent. Usually 65537 is chosen for e because it is more efficient in computer calculations.

[0086] 4. Calculate e about The module inverse element d satisfies d, as the private key exponent.

[0087] 5. The public key is (n, e) and the private key is (n, d).

[0088] During encryption, the plaintext M, such as the DNA identification information of the read field programmable gate array, is converted into an integer m, and then encrypted using the public key through the formula c ≡ m^e (mod n) to obtain the ciphertext c. During decryption, the private key can be used to decrypt and restore the plaintext m through the formula m ≡ c^d (mod n).

[0089] Furthermore, after encryption, the encrypted ciphertext c of each encrypted instruction is determined as the execution result of each first instruction.

[0090] The method provided in this embodiment can realize FPGA encryption by using a RISC-V processor module based on FPGA, using fewer lookup tables LUT and RAM resources, thereby realizing FPGA encryption by using fewer resources and reducing resource occupancy.

[0091] According to a field programmable gate array encryption method provided by the present invention, the target encryption algorithm is an RSA encryption algorithm; the target encryption algorithm is used to encrypt the read DNA identification information of the field programmable gate array to obtain the encrypted ciphertext of the encryption instruction, including:

[0092] Calculate the corresponding modulus according to two preset prime numbers, and calculate the Euler function corresponding to the modulus;

[0093] Determine public key parameters according to the Euler function;

[0094] Calculating the inverse element of the public key parameter with respect to the Euler function, and determining the inverse element as a private key parameter;

[0095] Determine a public key according to the public key parameter and the modulus, and determine a private key according to the private key parameter and the modulus; the public key and the private key constitute a key pair;

[0096] The DNA identification information is encrypted according to the private key in the key pair to obtain the encrypted ciphertext of the encryption instruction.

[0097] Specifically, in some embodiments, the target encryption algorithm is an RSA encryption algorithm. The RSA algorithm is a public key cryptographic algorithm that uses different private keys e and public keys d to encrypt and decrypt data information m. The process of encrypting the read DNA identification information of the field programmable gate array using the target encryption algorithm to obtain the encrypted ciphertext of the encryption instruction can be implemented by the following steps, including:

[0098] First, the corresponding modulus is calculated according to two preset prime numbers, and the Euler function corresponding to the modulus is calculated; then, the public key parameter is determined according to the Euler function; the inverse element of the public key parameter with respect to the Euler function is calculated, and the inverse element is determined as the private key parameter; further, the public key is determined according to the public key parameter and the modulus, and the private key is determined according to the private key parameter and the modulus; the public key and the private key constitute a set of key pairs; and then, the DNA identification information is encrypted according to the private key in the key pair to obtain the encrypted ciphertext of the encryption instruction.

[0099] Exemplarily, the key pair is determined by referring to the following process:

[0100] 1) Choose two sufficiently large prime numbers p and q, and calculate the modulus n and its Euler function , ;

[0101] 2) Randomly select a public key parameter d that satisfies d and The greatest common divisor of is 1;

[0102] 3) The private key parameter e is obtained by calculation, satisfying , that is, e is d with respect to The module anti-element;

[0103] Thus, the public key (d, n) and private key (e, n) can be obtained. After the key is determined, encryption and decryption operations can be performed. The 96-bit DNA is encrypted using the private key. The encryption method is c=m e mod n, where m is the DNA data and c is the encrypted ciphertext;

[0104] Furthermore, the ciphertext is decrypted using the public key, and the decryption method is p=c d mod n, p is the decrypted plaintext data.

[0105] It should be noted that both encryption and decryption operations require modular exponentiation a bMod n, directly exponentiate and then find the remainder. This method is only applicable to the calculation of small numbers. In particular, RSA1024 needs to process large numbers of 1024 bits, so it is necessary to simplify the modular exponentiation operation, usually decomposing it into multiple A The modular multiplication operation of B mod n can then be used to realize the modular exponentiation operation of large numbers.

[0106] For large number modular multiplication, the multipliers and resources required for direct calculation are still very large, so it is necessary to use the Montgomery algorithm for modular multiplication, and at the same time use shift operations to avoid modular operations. The Montgomery modular multiplication algorithm is to introduce the parameter R (R=2 k ) calculate a b R -1 mod n, and then calculate a b mod n. Assume that

[0107]

[0108] in, , then Montgomery modular multiplication Mont(a,b,n)= a b R -1 The calculation method of mod n is as follows:

[0109] 1) Assume d = 0, and perform the following loop operation for i = 0 ~ k:

[0110] 1.1) d = d + a i b;

[0111] 1.2) d = d + d 0 n, when d is an odd number, d 0 is 1, otherwise d 0 is 0;

[0112] 1.3) d = d / 2;

[0113] 2) If, Then d=dn;

[0114] The d obtained from the above steps is the calculation result of Mont(a,b,n). According to the calculation result of Montgomery modular multiplication algorithm, we can get a The modular multiplication result of b mod n, the specific steps are as follows:

[0115] 1) First, perform data preprocessing to map a and b to the Montgomery domain, that is,

[0116] A=Mont(a, (R 2 mod n), n)=a R mod n,

[0117] B=Mont(b, (R 2 mod n), n)=b R mod n;

[0118] 2) Perform modular multiplication calculation:

[0119] t = Mont(A, B, n)=a b R mod n;

[0120] 3) Adjust the calculation result of step 2) to obtain:

[0121] c = Mont(t, 1, n) = a b mod n;

[0122] Therefore, the encryption and decryption of the RSA1024 algorithm can be realized through modular exponentiation.

[0123] In the method provided in this embodiment, the corresponding modulus is calculated according to two preset prime numbers, and the Euler function corresponding to the modulus is calculated; then, the public key parameter is determined according to the Euler function; the inverse element of the public key parameter with respect to the Euler function is calculated, and the inverse element is determined as the private key parameter; further, the public key is determined according to the public key parameter and the modulus, and the private key is determined according to the private key parameter and the modulus; the public key and the private key constitute a set of key pairs; then, the DNA identification information is encrypted according to the private key in the key pair to obtain the encrypted ciphertext of the encryption instruction. Through the RISC-V processor module based on FPGA, the encryption of FPGA can be realized by using fewer lookup tables (LUT) and RAM resources, which realizes that the encryption of FPGA can be realized by using fewer resources, reducing the resource occupancy rate.

[0124] According to an encryption method of a field programmable gate array provided by the present invention, the external device of the RISC-V processor also includes a serial peripheral interface; each encrypted ciphertext is written into a Flash memory, including:

[0125] Each first encrypted ciphertext is written into the Flash memory through the serial peripheral interface.

[0126] Specifically, in some embodiments, step 103 may be implemented by the following steps:

[0127] Each first encrypted ciphertext is written to the Flash memory through the serial peripheral interface, where SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus standard for short-distance communication, mainly used in embedded systems. SPI communication is commonly used for data transmission between microcontrollers and various peripheral devices (such as sensors, memory, displays, etc.). The following are some key features of SPI: 1. Master-slave mode: SPI communication always involves a master device (such as a microcontroller) and one or more slave devices. The master device controls the clock signal of the communication and initializes the communication. 2. Four-wire interface: SPI communication uses four wires: MOSI (Master Out Slave In): master device data output, slave device data input. MISO (Master In Slave Out): master device data input, slave device data output. SCK (Serial Clock): clock signal, provided by the master device. CS (Chip Select): chip select signal, used to activate a specific slave device. 3. Synchronous communication: SPI communication is synchronous, and data transmission is synchronized with the clock signal, which helps to maintain data consistency and accuracy. 4. Full-duplex: SPI allows data to be transmitted in both directions simultaneously, i.e. the master device can receive data while sending data. 5. Data transfer rate: The data transfer rate of SPI can be very high, depending on the clock frequency and the capabilities of the microcontroller. The rate is usually between a few hundred kHz and tens of MHz. 6. Multiplexing: SPI allows multiple slave devices to be connected to the same bus, with chip selection through their respective CS pins. 7. Simple interface: The SPI interface is relatively simple and requires fewer pins, which makes it very popular in PCB design. 8. Data frame format: SPI data transmission is usually carried out in the form of frames.

[0128] Exemplarily, each first encrypted ciphertext is written into the Flash memory through the serial peripheral interface, following the steps below:

[0129] 1. Initialize the SPI interface: Configure the FPGA's SPI interface, including parameters such as clock frequency, number of data bits, CPOL, and CPHA, to match the requirements of the Flash memory.

[0130] 2. Write Enable: Send a Write Enable (WREN) command to the Flash memory to allow write operations.

[0131] 3. Write address: Send the Flash memory address to be written. This usually requires sending three consecutive bytes, indicating the address in the Flash memory.

[0132] 4. Write data: Send the encrypted data through the SPI interface. Data is usually sent in bytes, and each byte is sent within one cycle of the SPI clock.

[0133] 5. End writing: After writing is completed, you can send a Write Disable Instruction (WRDI) instruction to disable the write operation, or simply stop sending the chip select signal to end writing.

[0134] 6. Verify write: To ensure that the data is written correctly, the data can be read from the Flash and compared with the original encrypted data.

[0135] When implementing the above steps, you also need to handle the SPI communication timing to ensure that data is sampled and sent on the correct clock edge.

[0136] The method provided in this embodiment writes each first encrypted ciphertext into a Flash memory through a serial peripheral interface, thereby achieving effective storage of the encrypted ciphertext and facilitating ciphertext acquisition in a subsequent decryption process.

[0137] According to a field programmable gate array encryption method provided by the present invention, the method further includes:

[0138] Obtaining a second encrypted ciphertext from the Flash memory via the serial peripheral interface;

[0139] Decrypting the second encrypted ciphertext using a target decryption algorithm to obtain a plaintext corresponding to the second encrypted ciphertext; the target decryption algorithm is a decryption algorithm corresponding to the target encryption algorithm;

[0140] The decrypted plain text is compared with the DNA identification information of the read field programmable gate array to obtain a consistency comparison result;

[0141] Based on the consistency comparison result, the business module of the field programmable gate array is controlled.

[0142] Specifically, in some embodiments, the method further includes decrypting the ciphertext, and an example of the process is as follows:

[0143] First, the second encrypted ciphertext is obtained from the Flash memory through the serial peripheral interface.

[0144] Further, the second encrypted ciphertext is decrypted using the target decryption algorithm to obtain the plaintext corresponding to the second encrypted ciphertext. It should be noted that the target decryption algorithm is a decryption algorithm corresponding to the target encryption algorithm, such as if the target encryption algorithm is the RSA1024 encryption algorithm, the target decryption algorithm is the RSA1024 decryption algorithm.

[0145] Exemplarily, the process of decrypting the second encrypted ciphertext using the target decryption algorithm is as follows:

[0146] It should be noted that the target decryption algorithm uses the private key to restore the encrypted ciphertext to the original plaintext. The following are the basic steps of the RSA1024 decryption algorithm:

[0147] 1. Key pair: First, make sure you have the correct private key, which consists of two parts: modulus n and private key exponent d. Modulus n is the product of two large prime numbers p and q, while d is the public key exponent e. The modular inverse of Euler's function, computed as (p-1)(q-1).

[0148] 2. Ciphertext reception: The encrypted second ciphertext c is received, which is obtained through public key encryption.

[0149] 3. Decryption process: Use the private key to decrypt the ciphertext. The decryption formula is:

[0150] m≡c d mod n,

[0151] Where m is the integer representing the original plaintext, c is the ciphertext, d is the private key exponent, and n is the modulus.

[0152] 4. Plaintext recovery: The calculated m is usually a digital representation of the ciphertext. Depending on the data format used during encryption, it may be necessary to convert m back to the original data format, such as text or binary data.

[0153] The decryption process example is as follows:

[0154] Assume the following private key and ciphertext:

[0155] Private key: (n,d)=(3233,2753)

[0156] Ciphertext: c=2201

[0157] The decryption process is as follows:

[0158] m=c d mod n=2201 2753 mod 3233

[0159] In practical applications, since the numbers involved are very large, this modular exponentiation operation usually requires the use of specific algorithms (such as the modular repeated squaring algorithm) to be calculated efficiently.

[0160] In practical applications, RSA decryption is usually implemented by specialized libraries or tools, which optimize these calculation processes to ensure security and efficiency.

[0161] Furthermore, the decrypted plaintext is compared with the DNA identification information of the read field programmable gate array to obtain a consistency comparison result, and the business module of the field programmable gate array is controlled according to the consistency comparison result. For example, the plaintext and DNA data are compared. If the results are consistent, the FPGA business works normally, otherwise the FPGA will stop working. The GPIO peripheral is responsible for transmitting the consistency comparison results of the decrypted plaintext and DNA between RISC-V and other FPGA logic.

[0162] The method provided in this embodiment first obtains the second encrypted ciphertext from the Flash memory through the serial peripheral interface; then, the second encrypted ciphertext is decrypted by using the target decryption algorithm to obtain the plaintext corresponding to the second encrypted ciphertext; wherein the target decryption algorithm is a decryption algorithm corresponding to the target encryption algorithm; further, the plaintext obtained by decryption is compared with the DNA identification information of the read field programmable gate array to obtain a consistency comparison result; according to the consistency comparison result, the business module of the field programmable gate array is controlled. The present invention can ensure the reliability and security of the operation of the field programmable gate array.

[0163] According to a field programmable gate array encryption method provided by the present invention, a service module of the field programmable gate array is controlled according to a consistency comparison result, including:

[0164] When the consistency comparison result is consistent, the business module of the field programmable gate array is controlled to operate normally;

[0165] When the consistency comparison result is inconsistent, the service module of the control field programmable gate array stops running.

[0166] Specifically, in some embodiments, according to the consistency comparison result, the specific implementation process of controlling the service module of the field programmable gate array includes the following steps:

[0167] When the decrypted plaintext and the read DNA identification information of the field programmable gate array are consistent, it indicates that the ciphertext is the data corresponding to the field programmable gate array, and further, the business module of the field programmable gate array can be controlled to operate normally, where the business module mainly refers to other businesses of the field programmable gate array. For example, if the device identification in the plaintext is consistent with the device identification in the DNA identification information of the field programmable gate array and the version number is consistent, it can be considered that the verification is successful.

[0168] On the contrary, if the decrypted plain text and the read DNA identification information of the field programmable gate array are inconsistent, that is, the decrypted plain text is not the relevant data of the field programmable gate array, it indicates a decryption error, and then the business module of the field programmable gate array can be controlled to stop running. Similarly, the business module here mainly refers to other businesses of the field programmable gate array.

[0169] The method provided in this embodiment controls the business module of the field programmable gate array to run normally when the consistency comparison result is consistent, and controls the business module of the field programmable gate array to stop running when the consistency comparison result is inconsistent. The present invention can ensure the reliability and security of the operation of the field programmable gate array.

[0170] According to a field programmable gate array encryption method provided by the present invention, the method further comprises:

[0171] Performing a data fetch operation from a random access memory according to a first data address in a received memory load instruction;

[0172] The data in the memory storage instruction is written into a corresponding address of the random access memory according to the second data address in the received memory storage instruction.

[0173] Specifically, in some embodiments, the method further includes executing a memory load or memory store instruction. An example of a process of executing a memory load instruction is as follows:

[0174] A data fetch operation is performed from a random access memory RAM according to a first data address DADDR in a received memory load instruction. Exemplarily, the process of fetching data from a RAM (random access memory) according to a data address (DADDR) generally involves the following steps:

[0175] 1. Address decoding: First, the data address (DADDR) needs to be decoded into the row and column addresses of the RAM. In a simple RAM configuration, the address may be directly mapped to the memory cell.

[0176] 2. Enable chip: If the RAM is an external device, you may need to enable the RAM through a chip enable signal (such as OE, OutputEnable) so that data can be read from the RAM.

[0177] 3. Activate the row: For multi-bank memory, the row address is needed to activate the corresponding storage row. This usually involves sending the row address to the address pin of the RAM and activating the row enable signal (such as RAS, Row Address Strobe).

[0178] 4. Reading data: Once the row is activated, the data can be read through the column address. This usually involves sending the column address to the address pin of the RAM and activating the column enable signal (such as CAS, Column Address Strobe).

[0179] 5. Data output: Data will be output through the data pin of the RAM. In SRAM, this usually happens at some point after the enable signal is activated.

[0180] 6. Data buffering: In some cases, it may be necessary to buffer the data read from RAM to ensure that the data is stable and ready to be used by subsequent circuits.

[0181] 7. Disable: After the read operation is completed, the chip needs to be disabled to save power and prepare for the next access.

[0182] An example of the process of executing a memory storage instruction is as follows:

[0183] According to the second data address (Destination Address, DADDR) in the received memory storage instruction, the data in the memory storage instruction is written into the corresponding address of the random access memory. Exemplarily, the process of writing into the memory is implemented as follows:

[0184] The process of writing data to random access memory (RAM) is similar to the reading process, but involves a write operation. The following are the general steps to implement the write process:

[0185] 1. Address decoding: As in the reading process, the data address (DADDR) first needs to be decoded into the row and column addresses of the RAM.

[0186] 2. Enable chip: If the RAM is an external device, you may need to enable the RAM write mode through the chip enable signal (such as WE, WriteEnable).

[0187] 3. Activate row: As in the reading process, the corresponding storage row needs to be activated through the row address.

[0188] 4. Write data: After the row is activated, data can be written to the RAM through the column address. This usually involves placing the data on the data pins of the RAM and activating the write enable signal.

[0189] 5. Data stability: Ensure that data remains stable during the write cycle until the write operation is completed.

[0190] 6. Write confirmation: In some systems, it may be necessary to confirm that the data has been correctly written to RAM.

[0191] 7. Disable: After the write operation is completed, the chip needs to be disabled to save power and prepare for the next access.

[0192] Implementing the write process in an FPGA usually requires writing hardware description language (such as Verilog or VHDL) code to control the RAM interface.

[0193] According to the method provided in this embodiment, the RISC-V processor can also fetch data from the random access memory according to the first data address in the received memory loading instruction; write the data in the memory storage instruction into the corresponding address of the random access memory according to the second data address in the received memory storage instruction, thereby realizing memory writing and loading.

[0194] Figure 2 FIG. 1 is a schematic diagram of the structure of the encryption system of the field programmable gate array provided by the present invention, such as Figure 2 As shown, the encryption system of the field programmable gate array includes: an encryption and decryption program, a RISC-V processor and a Flash memory, wherein the RISC-V processor is a processor implemented based on the field programmable gate array; wherein:

[0195] The encryption and decryption program is used to cross-compile the original encryption request through a RISC-V cross-compilation tool to obtain at least one encryption instruction, and send it to the RISC-V processor; the encryption instruction is a 32-bit RISC-V instruction; the original encryption request is used to instruct to encrypt the field programmable gate array;

[0196] The RISC-V processor is used to decode and execute each of the encrypted instructions to obtain a first instruction execution result of each of the encrypted instructions; the first instruction execution result is a first encrypted ciphertext; and each of the first encrypted ciphertexts is written into the Flash memory;

[0197] The Flash memory is used to store each of the encrypted ciphertexts.

[0198] Specifically, this embodiment is applied to an encryption system of a field programmable gate array, such as Figure 2 As shown, the encryption system of the field programmable gate array includes: an encryption and decryption program, a RISC-V processor and a Flash memory. The RISC-V processor is a processor implemented based on the field programmable gate array. The encryption and decryption program is mainly responsible for implementing the specific logic of encryption and decryption, and compiling it into 32-bit RISC-V instructions through the RISC-V cross-compilation tool. The RISC-V processor is mainly responsible for fetching, decoding and executing the RISC-V instructions generated by the encryption and decryption program, thereby realizing the encryption of the FPGA. The Flash memory is used to store encrypted ciphertext.

[0199] When the field programmable gate array needs to be encrypted, the encryption and decryption program cross-compiles the original encryption request through the RISC-V cross-compilation tool to obtain the encryption instruction, and the original encryption request is used to instruct the field programmable gate array to be encrypted; the encryption instruction is a 32-bit RISC-V instruction. The RISC-V cross-compilation tool is a set of tools for compiling RISC-V architecture programs, which allows programs that can run on RISC-V hardware to be compiled on a host with a non-RISC-V architecture. The RISC-V cross-compilation tools in this embodiment include RISC-V GNU Toolchain, RISC-V LLVM Toolchain, Docker container, pre-compiled tool chain, etc. Further, the encryption and decryption program sends at least one encryption instruction obtained after compilation to the RISC-V processor.

[0200] The RISC-V processor is used to decode and execute each of the encrypted instructions to obtain a first instruction execution result of each of the encrypted instructions, and the first instruction execution result is a first encrypted ciphertext; The RISC-V processor decodes and executes each encrypted instruction to obtain an execution result. Since RISC-V is an open source instruction set, the RISC-V processor can use FPGA code to implement instruction decoding and execution of each encrypted instruction to obtain an encrypted ciphertext, that is, the first instruction execution result. Exemplarily, implementing RISC-V encrypted instructions with FPGA code usually involves the following steps: 1. Select an FPGA development board: for example, Xilin FPGA, 2. Install development tools: Install FPGA development tools, such as Xilinx Vivado or Intel Quartus, which provide full-process support for designing, simulating, compiling and configuring FPGA. 3. Design processor architecture: Select a suitable processor architecture, such as RV32I or RV64I, according to the RISC-V instruction set architecture, and design registers, instruction pipelines and memory / I / O interfaces. 4. Write the hardware description language: Use Verilog or VHDL to write the code of the RISC-V processor, including modules such as instruction decoding, execution unit, and register file. 5. Compile the code: Compile the written hardware description language code into a bitstream file that can be recognized by the FPGA. 6. Configure the FPGA: Download the compiled bitstream file to the FPGA and perform actual testing. Further, write each of the first encrypted ciphertexts into the Flash memory;

[0201] The Flash memory is used to store each of the encrypted ciphertexts.

[0202] In the system provided in this embodiment, the encryption system of the field programmable gate array includes: an encryption and decryption program, a RISC-V processor and a Flash memory, the RISC-V processor is a processor implemented based on the field programmable gate array, the encryption and decryption program is used to cross-compile the original encryption request through the RISC-V cross-compilation tool to obtain at least one encryption instruction, and send it to the RISC-V processor; wherein the encryption instruction is a 32-bit RISC-V instruction, and the original encryption request is used to instruct to encrypt the field programmable gate array; the RISC-V processor is used to decode and execute each of the encryption instructions to obtain a first instruction execution result of each of the encryption instructions; wherein the first instruction execution result is a first encrypted ciphertext; each of the first encrypted ciphertexts is written into the Flash memory; the Flash memory is used to store each of the encrypted ciphertexts.

[0203] Since RISC-V is an open source instruction set architecture based on the reduced instruction set principle, the present invention is based on the RISC-V processor receiving encryption instructions of the encryption and decryption program, the encryption instructions are obtained after the encryption and decryption program cross-compiles the original encryption request through the RISC-V cross-compilation tool, and the original encryption request is used to instruct to encrypt the field programmable gate array; the RISC-V processor decodes and executes each encryption instruction to obtain the first instruction execution result of each encryption instruction, that is, to realize the encryption of the field programmable gate array, and to realize the encryption of FPGA using fewer resources, thereby reducing resource occupancy.

[0204] The encryption device of the field programmable gate array provided by the present invention is described below. The encryption device of the field programmable gate array described below and the encryption method of the field programmable gate array described above can be referred to each other.

[0205] Figure 5 : is a schematic diagram of the structure of the encryption device of the field programmable gate array provided by the present invention, the device is applied to the RISC-V processor in the encryption system of the field programmable gate array, the encryption system of the field programmable gate array includes: an encryption and decryption program, the RISC-V processor and a Flash memory, the RISC-V processor is a processor implemented based on the field programmable gate array; the encryption device 500 of the field programmable gate array includes a receiving module 510, an encryption module 520 and a writing module 530, wherein:

[0206] The receiving module 510 is used to receive at least one encryption instruction; the encryption instruction is obtained by the encryption and decryption program after cross-compiling the original encryption request through the RISC-V cross-compilation tool, and the encryption instruction is a 32-bit RISC-V instruction; the original encryption request is used to instruct to encrypt the field programmable gate array;

[0207] The encryption module 520 is used to decode and execute each of the encryption instructions to obtain a first instruction execution result of each of the encryption instructions; the first instruction execution result is a first encrypted ciphertext;

[0208] The writing module 530 is used to write each of the first encrypted ciphertexts into the Flash memory.

[0209] The device provided in this embodiment is applied to a RISC-V processor in an encryption system of a field programmable gate array. The encryption system of the field programmable gate array includes: an encryption and decryption program, a RISC-V processor and a Flash memory. The RISC-V processor is a processor implemented based on a field programmable gate array. The encryption device 500 of the field programmable gate array includes a receiving module 510, an encryption module 520 and a writing module 530. The receiving module 510 receives at least one encryption instruction, wherein the encryption instruction is obtained by cross-compiling the original encryption request by the encryption and decryption program through a RISC-V cross-compilation tool. The encryption instruction is a 32-bit RISC-V instruction, and the original encryption request is used to instruct to encrypt the field programmable gate array; then, the encryption module 520 decodes and executes each encryption instruction to obtain a first instruction execution result of each encryption instruction, and the first instruction execution result is a first encrypted ciphertext; the writing module 530 writes each encrypted ciphertext into the Flash memory.

[0210] Since RISC-V is an open source instruction set architecture based on the reduced instruction set principle, the present invention is based on the RISC-V processor receiving the encryption instructions of the encryption and decryption program. The encryption instructions are obtained after the encryption and decryption program cross-compiles the original encryption request through the RISC-V cross-compilation tool. The original encryption request is used to instruct the field programmable gate array to encrypt and decode and execute each encryption instruction, and then obtain the first instruction execution result of each encryption instruction, that is, the field programmable gate array is encrypted, and the encryption of the FPGA can be realized by using fewer resources, thereby reducing resource occupancy.

[0211] According to an encryption device 500 of a field programmable gate array provided by the present invention, the external devices of the RISC-V processor include: a read-only memory external device, a random access memory external device, a universal asynchronous receiver or transmitter external device, a DNA external device and a universal input and output external device, and the encryption module 520 is specifically used for:

[0212] For any of the encrypted instructions, an instruction fetch operation is performed from a read-only memory external device according to an instruction fetch address in the encrypted instruction;

[0213] According to the encrypted instruction, DNA identification information of the field programmable gate array is read from the DNA external device; the DNA identification information includes at least one of the following: device identification, manufacturing information, configuration data, security features, version information, user data, device function, and supply chain information;

[0214] Encrypting the read DNA identification information of the field programmable gate array using a target encryption algorithm to obtain an encrypted ciphertext of the encryption instruction;

[0215] The encrypted ciphertext of each of the encrypted instructions is determined as the execution result of each of the first instructions.

[0216] According to the field programmable gate array encryption device 500 provided by the present invention, the encryption module 520 is further used for:

[0217] Calculate the corresponding modulus according to two preset prime numbers, and calculate the Euler function corresponding to the modulus;

[0218] Determine public key parameters according to the Euler function;

[0219] Calculating the inverse element of the public key parameter with respect to the Euler function, and determining the inverse element as a private key parameter;

[0220] Determine a public key according to the public key parameter and the modulus, and determine a private key according to the private key parameter and the modulus; the public key and the private key constitute a key pair;

[0221] The DNA identification information is encrypted according to the private key in the key pair to obtain the encrypted ciphertext of the encryption instruction.

[0222] According to a field programmable gate array encryption device 500 provided by the present invention, the external device of the RISC-V processor further includes a serial peripheral interface; the writing module 530 is specifically used for:

[0223] Each of the first encrypted ciphertexts is written into the Flash memory through the serial peripheral interface.

[0224] According to the field programmable gate array encryption device 500 provided by the present invention, the device further includes: a decryption module;

[0225] The decryption module is used for:

[0226] Obtaining a second encrypted ciphertext from the Flash memory via the serial peripheral interface;

[0227] Decrypting the second encrypted ciphertext using a target decryption algorithm to obtain a plaintext corresponding to the second encrypted ciphertext; the target decryption algorithm is a decryption algorithm corresponding to the target encryption algorithm;

[0228] Comparing the decrypted plaintext with the read DNA identification information of the field programmable gate array to obtain a consistency comparison result;

[0229] According to the consistency comparison result, the service module of the field programmable gate array is controlled.

[0230] According to the field programmable gate array encryption device 500 provided by the present invention, the decryption module is further used for:

[0231] When the consistency comparison result is consistent, controlling the service module of the field programmable gate array to operate normally;

[0232] When the consistency comparison result is inconsistent, the service module of the field programmable gate array is controlled to stop running.

[0233] According to the field programmable gate array encryption device 500 provided by the present invention, the method further comprises: a reading module and a storage module;

[0234] The reading module is used to fetch data from the random access memory according to the first data address in the received memory loading instruction;

[0235] The storage module is used to write the data in the memory storage instruction into the corresponding address of the random access memory according to the second data address in the received memory storage instruction.

[0236] Figure 6 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 6As shown, the electronic device may include: a processor 610, a communications interface 620, a memory 630 and a communication bus 640, wherein the processor 610, the communications interface 620 and the memory 630 communicate with each other through the communication bus 640. The processor 610 may call the logic instructions in the memory 630 to execute the encryption method of the field programmable gate array, which is applied to the RISC-V processor in the encryption system of the field programmable gate array. The encryption system of the field programmable gate array includes: an encryption and decryption program, the RISC-V processor and a Flash memory. The RISC-V processor is a processor implemented based on the field programmable gate array; the method includes:

[0237] Receive at least one encryption instruction; the encryption instruction is obtained by the encryption and decryption program after cross-compiling the original encryption request through the RISC-V cross-compilation tool, and the encryption instruction is a 32-bit RISC-V instruction; the original encryption request is used to instruct to encrypt the field programmable gate array;

[0238] Decoding and executing each of the encrypted instructions to obtain a first instruction execution result of each of the encrypted instructions; the first instruction execution result is a first encrypted ciphertext;

[0239] Writing each of the first encrypted ciphertexts into the Flash memory.

[0240] In addition, the logic instructions in the above-mentioned memory 630 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0241] On the other hand, the present invention further provides a computer program product, the computer program product includes a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the encryption method of the field programmable gate array provided by the above methods, applied to a RISC-V processor in an encryption system of a field programmable gate array, the encryption system of the field programmable gate array includes: an encryption and decryption program, the RISC-V processor and a Flash memory, the RISC-V processor is a processor implemented based on a field programmable gate array; the method includes:

[0242] Receive at least one encryption instruction; the encryption instruction is obtained by the encryption and decryption program after cross-compiling the original encryption request through the RISC-V cross-compilation tool, and the encryption instruction is a 32-bit RISC-V instruction; the original encryption request is used to instruct to encrypt the field programmable gate array;

[0243] Decoding and executing each of the encrypted instructions to obtain a first instruction execution result of each of the encrypted instructions; the first instruction execution result is a first encrypted ciphertext;

[0244] Each of the first encrypted ciphertexts is written into the Flash memory.

[0245] On the other hand, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to execute the encryption method of the field programmable gate array provided by the above methods, and is applied to a RISC-V processor in an encryption system of a field programmable gate array, wherein the encryption system of the field programmable gate array comprises: an encryption and decryption program, the RISC-V processor, and a Flash memory, wherein the RISC-V processor is a processor implemented based on a field programmable gate array; the method comprises:

[0246] Receive at least one encryption instruction; the encryption instruction is obtained by the encryption and decryption program after cross-compiling the original encryption request through the RISC-V cross-compilation tool, and the encryption instruction is a 32-bit RISC-V instruction; the original encryption request is used to instruct to encrypt the field programmable gate array;

[0247] Decoding and executing each of the encrypted instructions to obtain a first instruction execution result of each of the encrypted instructions; the first instruction execution result is a first encrypted ciphertext;

[0248] Each of the first encrypted ciphertexts is written into the Flash memory.

[0249] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0250] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0251] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A field programmable gate array encryption method, characterized in that: A RISC-V processor applied to an encryption system of a field programmable gate array, wherein the encryption system of the field programmable gate array comprises: an encryption and decryption program, the RISC-V processor and a Flash memory, wherein the RISC-V processor is a processor implemented based on a field programmable gate array; and the method comprises: Receive at least one encryption instruction; the encryption instruction is obtained by the encryption and decryption program after cross-compiling the original encryption request through the RISC-V cross-compilation tool, and the encryption instruction is a 32-bit RISC-V instruction; the original encryption request is used to instruct to encrypt the field programmable gate array; Decoding and executing each of the encrypted instructions to obtain a first instruction execution result of each of the encrypted instructions; the first instruction execution result is a first encrypted ciphertext; Writing each of the first encrypted ciphertexts into the Flash memory; The external devices of the RISC-V processor include: a read-only memory external device, a random access memory external device, a universal asynchronous receiver or transmitter external device, a DNA external device and a general input and output external device; The step of decoding and executing each of the encrypted instructions to obtain a first instruction execution result of each of the encrypted instructions includes: For any of the encrypted instructions, an instruction fetch operation is performed from a read-only memory external device according to an instruction fetch address in the encrypted instruction; According to the encrypted instruction, DNA identification information of the field programmable gate array is read from the DNA external device; the DNA identification information includes at least one of the following: device identification, manufacturing information, configuration data, security features, version information, user data, device function, supply chain information; Encrypting the read DNA identification information of the field programmable gate array using a target encryption algorithm to obtain an encrypted ciphertext of the encryption instruction; Determining the encrypted ciphertext of each of the encrypted instructions as the execution result of each of the first instructions; The target encryption algorithm is an RSA encryption algorithm; the target encryption algorithm is used to encrypt the DNA identification information of the field programmable gate array read to obtain the encrypted ciphertext of the encryption instruction, including: Calculate the corresponding modulus according to two preset prime numbers, and calculate the Euler function corresponding to the modulus; Determine public key parameters according to the Euler function; Calculating the inverse element of the public key parameter with respect to the Euler function, and determining the inverse element as a private key parameter; Determine a public key according to the public key parameter and the modulus, and determine a private key according to the private key parameter and the modulus; the public key and the private key constitute a key pair; Encrypting the DNA identification information according to the private key in the key pair to obtain an encrypted ciphertext of the encryption instruction; Obtaining a second encrypted ciphertext from the Flash memory via a serial peripheral interface; Decrypting the second encrypted ciphertext using a target decryption algorithm to obtain a plaintext corresponding to the second encrypted ciphertext; the target decryption algorithm is a decryption algorithm corresponding to a target encryption algorithm; the target encryption algorithm is an RSA encryption algorithm; Comparing the decrypted plaintext with the read DNA identification information of the field programmable gate array to obtain a consistency comparison result; According to the consistency comparison result, the service module of the field programmable gate array is controlled.

2. The encryption method of the field programmable gate array according to claim 1, characterized in that: The external device of the RISC-V processor also includes a serial peripheral interface; the step of writing each of the first encrypted ciphertexts into the Flash memory includes: Each of the first encrypted ciphertexts is written into the Flash memory through the serial peripheral interface.

3. The encryption method of the field programmable gate array according to claim 1, characterized in that: The step of controlling the service module of the field programmable gate array according to the consistency comparison result includes: When the consistency comparison result is consistent, controlling the service module of the field programmable gate array to operate normally; When the consistency comparison result is inconsistent, the service module of the field programmable gate array is controlled to stop running.

4. The encryption method of the field programmable gate array according to claim 1, characterized in that: The method further comprises: Performing a data fetch operation from a random access memory according to a first data address in a received memory load instruction; The data in the memory storage instruction is written into a corresponding address of the random access memory according to the second data address in the received memory storage instruction.

5. A field programmable gate array encryption device, characterized in that: The encryption method of the field programmable gate array according to any one of claims 1 to 4 is performed, and is applied to a RISC-V processor in an encryption system of the field programmable gate array, wherein the encryption system of the field programmable gate array comprises: an encryption and decryption program, the RISC-V processor, and a Flash memory, wherein the RISC-V processor is a processor implemented based on the field programmable gate array; the device comprises: A receiving module, configured to receive at least one encryption instruction; the encryption instruction is obtained by the encryption / decryption program after cross-compiling the original encryption request through a RISC-V cross-compilation tool, and the encryption instruction is a 32-bit RISC-V instruction; the original encryption request is used to instruct to encrypt a field programmable gate array; An encryption module, used for decoding and executing each of the encryption instructions to obtain a first instruction execution result of each of the encryption instructions; the first instruction execution result is a first encrypted ciphertext; A writing module is used to write each of the first encrypted ciphertexts into the Flash memory.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the encryption method of the field programmable gate array according to any one of claims 1 to 4 is implemented.

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