Packaging Structure and Packaging Method of Integrated Chips and Miniature Supercapacitors

Abstract

This invention discloses a packaging structure for an integrated chip and a micro supercapacitor, comprising a resin matrix with an internal cavity and openings on its upper and lower surfaces. A substrate is adhered to the bottom surface of the resin matrix via a curable adhesive. Electrodes are disposed on the substrate within the cavity of the resin matrix and extend outwards from the resin matrix as leads. A liquid electrolyte is disposed within the cavity of the resin matrix. An integrated chip is adhered to the top surface of the resin matrix via a curable adhesive, and the integrated chip is connected to the leads via wires. This invention also provides a packaging method for the integrated chip and micro supercapacitor packaging structure. This invention uses a vertical system packaging method to further achieve system miniaturization and integration, solving the problems of difficult liquid electrolyte packaging in micro supercapacitors and the large footprint of separate packaging of micro supercapacitors and integrated chips.

Description

Technical Field

[0001] This invention belongs to the field of electrical component integration, and particularly relates to a packaging structure and packaging method for chips and capacitors. Background Technology

[0002] In recent years, the rapid development of portable, wearable devices and the Internet of Things has placed higher demands on the miniaturization of power systems. Traditional capacitors, due to their large size, are the largest and least integrated components in power modules. Among the many capacitor replacement solutions, micro supercapacitors (MSCs) have attracted much attention due to their advantages, including small size, excellent power density, long lifespan, and ease of integration, and are considered an excellent solution for the next generation of capacitors.

[0003] In terms of manufacturing processes, the encapsulation of the liquid electrolyte in micro supercapacitors has always been one of the challenges in miniaturization. Furthermore, due to process incompatibility, micro supercapacitors and integrated chips are typically packaged separately and then connected in circuitry, which is not conducive to the overall integration and miniaturization of the system. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the deficiencies and defects mentioned in the background art above, and to provide a packaging structure and packaging method for integrated chips and micro supercapacitors that can solve the problems of packaging difficulties of liquid electrolyte in micro supercapacitors and packaging micro supercapacitors and integrated chips separately, which are not conducive to integration and miniaturization.

[0005] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows:

[0006] An integrated chip and micro supercapacitor packaging structure includes a resin matrix with an internal cavity and openings on the top and bottom surfaces. A substrate is adhered to the bottom surface of the resin matrix by a curing adhesive. Electrodes are disposed on the substrate and are located in the cavity inside the resin matrix, with pins extending outward from the resin matrix. A liquid electrolyte is disposed in the cavity inside the resin matrix. An integrated chip is adhered to the top surface of the resin matrix by a curing adhesive, and the integrated chip is connected to the pins by wires.

[0007] In the above-described encapsulation structure, preferably, the cavity inside the resin matrix is ​​divided into an upper chamber and a lower chamber by an inner cavity partition plate. The inner cavity partition plate is funnel-shaped and has a first through-hole in the center. The lower chamber contains a liquid electrolyte, and the upper chamber contains a curing adhesive. By setting the inner cavity partition plate to divide the cavity into an upper and lower chamber, the lower chamber is used to contain the liquid electrolyte, and the upper chamber is used to contain the integrated chip. The inner cavity partition plate can separate the liquid electrolyte from the integrated chip (only the small hole needs to be sealed with curing adhesive), preventing corrosion of the integrated chip and ensuring the sealing of the liquid electrolyte. At the same time, since the liquid electrolyte and the resin matrix are materials of different polarities, the inner cavity partition plate can also prevent the backflow of the injected liquid electrolyte. The liquid electrolyte can be easily injected into the lower chamber through the first through-hole in the center. By setting the inner cavity partition plate to be funnel-shaped, the injection of liquid electrolyte is facilitated.

[0008] In the above-described encapsulation structure, preferably, at least one second through-hole is provided at the junction of the inner cavity partition plate and the resin matrix. The lower chamber has a small volume, and the second through-hole allows for the expulsion of air from inside the lower chamber during liquid electrolyte injection. It should be emphasized that the self-injection channel designed in this invention only requires dripping the liquid electrolyte into the center of the upper chamber.

[0009] In the above packaging structure, preferably, the side edge of the integrated chip is positioned at the top of the cavity inside the resin matrix. This arrangement facilitates more stable installation of the integrated chip.

[0010] As a general technical concept, the present invention also provides a packaging method for the above-mentioned integrated chip and micro supercapacitor packaging structure, comprising the following steps:

[0011] (1) An electrode is disposed on the substrate; the resin matrix is ​​processed;

[0012] (2) The substrate is adhered to the bottom surface of the resin matrix using a curing adhesive, and the electrode is located in the cavity inside the resin matrix, with leads extending outward from the resin matrix.

[0013] (3) Injecting liquid electrolyte into the cavity inside the resin matrix; the specific process is as follows: based on the micro-design of the inner cavity partition plate, the liquid electrolyte dripped into the upper chamber can be self-injected into the lower chamber inside the resin matrix;

[0014] (4) Use curing adhesive to seal the top of the cavity inside the resin matrix, and at the same time adhere the integrated chip to the top surface of the resin matrix.

[0015] (5) The integrated chip and pins are connected by wire bonding, and the electrical interconnection wire bonding between the integrated chip and the micro supercapacitor in the vertical direction is completed.

[0016] In the above encapsulation method, preferably, before injecting the liquid electrolyte, the inner surface of the cavity (lower chamber) inside the resin matrix is ​​first wetted with the liquid electrolyte. The liquid electrolyte of this invention is added via a self-injection method. Since the size of the central first through-hole is at the micrometer level, and since the resin matrix and liquid electrolyte have opposite polarities, the electrolyte cannot be self-injected without wetting. To achieve self-injection of the liquid electrolyte, a pre-wetting treatment of the inner surface of the lower chamber is required. After wetting, the inner surface, due to the mutual attraction between like molecules, guides the liquid electrolyte located outside the injection channel of the upper chamber into the encapsulation interior.

[0017] In the above packaging method, preferably, the substrate is a silicon / silicon oxide substrate, the silicon oxide is disposed on the silicon surface, the electrode is disposed on the silicon oxide surface, and the electrode is an interdigitated porous electrode.

[0018] In the above packaging method, preferably, the electrode is formed on the substrate, including the following steps: a double-layer photoresist is uniformly spin-coated onto the substrate surface, and then irradiated and developed using ultraviolet light to form interdigitated and inverted trapezoidal patterns on the double-layer photoresist; copper / zinc is then deposited on the double-layer photoresist by magnetron sputtering, and then immersed in acetone, and the separation process is completed by ultrasonic waves to form an interdigitated electrode structure on the substrate; finally, zinc is selectively etched in hydrochloric acid to form a porous copper electrode structure, and then ozone oxidation is used to form a porous copper / copper oxide electrode on the substrate. The copper / zinc co-sputtering method proposed in this invention deposits copper / zinc on a double-layer photoresist, then selectively etches zinc in hydrochloric acid to form a porous copper electrode structure, and finally uses ozone oxidation to form a dense copper oxide on the surface of the porous electrode. This method is simple and easy to implement, and it is easy to prepare a porous copper electrode structure. Copper, as a widely used conductor in circuit systems, has good compatibility.

[0019] In the above encapsulation method, preferably, the resin matrix is ​​obtained by 3D printing. High-precision resin matrices can be obtained through 3D printing. The resin matrix of the present invention is made of transparent resin material, which facilitates the curing of the adhesive inside the resin matrix by ultraviolet light.

[0020] In the above encapsulation method, preferably, the curing adhesive is a UV-curable adhesive.

[0021] Existing circuit systems use large-volume, low-capacity electrolytic capacitors. This invention replaces traditional electrolytic capacitors with supermicro capacitors, increasing capacity while reducing footprint. However, due to process incompatibility and difficulties in liquid encapsulation, micro-supercapacitors are generally independently packaged with integrated circuit chips on a plane, which is not conducive to the integration and miniaturization of the entire system. Based on this, this invention proposes a dual-device heterogeneous integration packaging structure and method. Combining the concept of vertical construction, with liquid electrolyte encapsulation as the key, it achieves system encapsulation of the integrated chip and the micro-supercapacitor through wire bonding technology. This solves the difficulties of liquid encapsulation while achieving system encapsulation of the integrated chip and the micro-supercapacitor in the vertical direction. Specifically, this invention uses 3D printing technology to prepare a resin matrix. This resin matrix can use transparent resin material and is rectangular in shape. The upper and lower chambers are used for storing the integrated chip and liquid electrolyte, respectively. The inner cavity partition is funnel-shaped (the inner surface is a triangular slope that curves inward from the periphery to the center), facilitating the concentration and collection of the liquid electrolyte. The center of the inner surface of the upper chamber has a square micropore, which serves as a self-injection channel for the liquid electrolyte. When the substrate, integrated chip, and resin matrix are connected, they can be sealed using UV-curable adhesive. Since the UV-curable adhesive has the same polarity as the encapsulation material and the opposite polarity to the liquid electrolyte, it can effectively complete the encapsulation task. The above-mentioned encapsulation structure and method, while solving the difficulties of liquid encapsulation, achieves vertical encapsulation of the integrated chip and the micro supercapacitor, realizing system miniaturization and integration. Simultaneously, vertical encapsulation halves the total footprint of the micro supercapacitor and chip, shortens the circuit connections between devices, and theoretically infinitely shortens the circuit connections between the integrated chip and the micro supercapacitor, greatly reducing signal transmission time and losses during transmission. The closer fit between the two components results in faster signal exchange; in other words, vertical encapsulation can optimize system performance through circuit connection optimization.

[0022] Compared with the prior art, the advantages of the present invention are as follows:

[0023] The integrated chip and micro supercapacitor packaging structure and packaging method of the present invention utilize a resin matrix and a vertically oriented system packaging method to further achieve system miniaturization and integration, while shortening the circuit connection between devices and thus optimizing system performance.

[0024] The integrated chip and micro supercapacitor packaging structure and packaging method of the present invention solve the problems of difficult packaging of liquid electrolyte in micro supercapacitors and large footprint of micro supercapacitors and integrated chips being packaged separately. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a top view of the resin matrix in the embodiment.

[0027] Figure 2 for Figure 1 A cross-sectional view of plane AA.

[0028] Figure 3 This is an exploded view of the packaging structure of the integrated chip and the micro supercapacitor in the embodiment.

[0029] Figure 4 This is a schematic diagram comparing the packaging structure in the embodiment with the prior art.

[0030] Figure 5 A schematic diagram of the substrate surface electrode structure in the embodiment.

[0031] Figure 6 This is a schematic flowchart illustrating the packaging method of the integrated chip and micro supercapacitor packaging structure in the embodiment.

[0032] Figure 7 This is a schematic diagram of the packaging structure of the integrated chip and the micro supercapacitor in the embodiment.

[0033] Figure 8 The diagram shows the integrated chip and the micro supercapacitor package structure after connection (lower left) and the optical physical image.

[0034] Figure 9 The image shows a comparison of the package structure of the integrated chip and the micro supercapacitor prepared in the example with the actual size of a traditional electrolytic capacitor.

[0035] Figure 10 The circuit diagram shows a specific application scenario of the integrated chip and micro supercapacitor packaging structure prepared for the example.

[0036] Figure 11 for Figure 9 The two types of capacitor products are based on Figure 10 A schematic diagram of charging and discharging in a specific application scenario.

[0037] Legend

[0038] 1. Resin matrix; 2. Substrate; 3. Curing adhesive; 4. Electrode; 5. Liquid electrolyte; 6. Integrated chip; 7. Inner cavity partition plate; 71. Upper chamber; 72. Lower chamber; 73. First through hole; 74. Second through hole; 8. Adhesive layer. Detailed Implementation

[0039] To facilitate understanding of the present invention, the present invention will be described more fully and in detail below with reference to the accompanying drawings and preferred embodiments, but the scope of protection of the present invention is not limited to the following specific embodiments.

[0040] It should be noted that when a component is described as being "fixed to, attached to, connected to or connected to" another component, it can be directly fixed to, attached to, connected to or connected to the other component, or it can be indirectly fixed to, attached to, connected to or connected to the other component through other intermediate connectors.

[0041] Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by those skilled in the art. The technical terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the invention.

[0042] Unless otherwise specified, all raw materials, reagents, instruments and equipment used in this invention can be purchased from the market or prepared by existing methods.

[0043] Example:

[0044] like Figures 1-3 As shown, the integrated chip and micro supercapacitor packaging structure of this embodiment includes a resin substrate 1. The resin substrate 1 has an internal cavity with openings on the upper and lower surfaces. The internal cavity of the resin substrate 1 is divided into an upper chamber 71 and a lower chamber 72 by an inner cavity partition plate 7. The inner cavity partition plate 7 is funnel-shaped and has a first through hole 73 in the center. A substrate 2 (specifically a silicon / silicon oxide substrate, with silicon oxide disposed on the silicon surface) is adhered to the bottom surface of the resin substrate 1 by a curing adhesive 3. Electrodes 4 (specifically interdigitated multi-electrode electrodes) are disposed on the substrate 2. The electrode 4 is disposed on the surface of silicon oxide and extends upward into the cavity inside the resin matrix 1 (extending into the lower chamber 72), and has pins extending outward from the resin matrix 1. Liquid electrolyte 5 is disposed in the cavity inside the resin matrix 1 (liquid electrolyte 5 is disposed in the lower chamber 72). The top surface of the resin matrix 1 is adhered with an integrated chip 6 by a curing adhesive 3. The side edge of the integrated chip 6 is fixed in the upper chamber 71, which is also provided with curing adhesive 3. The integrated chip 6 is connected to the pins by wires.

[0045] like Figure 1 , Figure 2As shown, in this embodiment, four second through holes 74 are provided at the junction of the inner cavity partition plate 7 and the resin matrix 1. In other embodiments, the number of the second through holes 74 can be adjusted, such as 1, 2, 3, 5, etc.

[0046] Taking the integration of power management chips and capacitors as an example, the packaging structure of the integrated chip and miniature supercapacitor in this embodiment differs from the existing integrated structure of power management chips and capacitors as follows: Figure 4 As shown in the figure, from the development trend of traditional discrete power supplies to system-integrated packaged power supplies, traditional electrolytic capacitors have a large footprint and small capacitance; using MSCs to replace traditional capacitors can greatly reduce the capacitor's footprint; and using vertical system packaging can further halve the footprint. That is, the vertical packaging structure in this embodiment has a smaller footprint and higher integration.

[0047] This embodiment also provides a packaging method for an integrated chip and a micro supercapacitor packaging structure, including the following steps:

[0048] (1) Electrode 4 is set on substrate 2; resin matrix 1 is processed by 3D printing;

[0049] (2) Use liquid electrolyte 5 to wet the inner surface of the lower chamber 72; in this process, the entire resin matrix 1 can be immersed in liquid electrolyte 5. After wetting, the liquid electrolyte at the bottom of the resin matrix 1 can be dried by blowing it horizontally with a nitrogen gun without affecting the photocuring.

[0050] (3) The substrate 2 is adhered to the bottom surface of the resin substrate 1 using the curing adhesive 3 (ultraviolet curing adhesive), and the electrode 4 is located in the cavity inside the resin substrate 1 and has leads extending outward from the resin substrate 1.

[0051] (4) Inject liquid electrolyte 5 into the cavity inside the resin matrix 1;

[0052] (5) Use curing adhesive 3 (UV curing adhesive) to seal the top of the cavity inside the resin matrix 1, and at the same time adhere the integrated chip 6 to the top surface of the resin matrix 1.

[0053] (6) The connection between the integrated chip 6 and the pin is realized by wire bonding, and the electrical interconnection wire bonding between the integrated chip 6 and the micro supercapacitor in the vertical direction is completed.

[0054] In this embodiment, the pins are fabricated simultaneously during the manufacturing process of electrode 4, such as... Figure 5 As shown; since the actual thickness of electrode 4 is 20 micrometers (relatively thick), compared to the 1mm thickness of resin matrix 1, no special treatment is required. Once it is covered, the curing adhesive can achieve a good seal.

[0055] In this embodiment, the electrode 4 is formed on the substrate 2 by the following steps: a double layer of photoresist is uniformly spin-coated on the surface of the substrate 2, and ultraviolet light is used for irradiation and development to form interdigitated and inverted trapezoidal patterns on the double layer of photoresist; copper / zinc is then deposited on the double layer of photoresist by magnetron sputtering, and then immersed in acetone and subjected to ultrasonic stripping to form an interdigitated electrode structure on the substrate 2; finally, zinc is selectively etched in hydrochloric acid to form a porous copper electrode structure, and then ozone oxidation is performed to form a porous copper / copper oxide electrode on the substrate 2.

[0056] Specifically, such as Figure 6 As shown, this embodiment also provides a more specific packaging method for an integrated chip and a micro supercapacitor packaging structure, which may include the following steps:

[0057] A double layer of photoresist AZ601 and AR5480 was uniformly spin-coated onto the clean surface of a silicon wafer with an oxide layer. Then, an etching process was performed at a strength of 240 mJ / cm². 2 After being exposed to ultraviolet light for 8 seconds and developed for 22 seconds, the double-layer photoresist formed interdigitated and inverted trapezoidal patterns. Figure 6 As shown in Figure a), a TiW layer is typically deposited as an adhesion layer 8. Subsequently, copper / zinc is co-sputtered using a magnetron sputtering system with a DC power of 150W and an RF AC power of 75W for 10 hours, depositing a copper / zinc layer approximately 20μm thick on the surface of the double-layer photoresist. Figure 6 (As shown in b). It is then immersed in acetone and subjected to ultrasonic exfoliation to form an interdigitated electrode structure. Figure 6 (As shown in c). Then, selective etching was performed in 1 mol / L dilute hydrochloric acid for 12 hours, followed by in-situ oxidation under ozone conditions for 2 hours to form ultra-thick porous Cu@Cu. x O electrode ( Figure 6 (As shown in the middle). Finally, the resin matrix 1 is processed by 3D printing, and the inner surface of the lower chamber 72 is pre-treated by wetting with 1 mol / L sodium sulfate (liquid electrolyte 5). Then, 1 mol / L sodium sulfate is self-injected into the upper chamber 71 (the self-injection principle is shown in the partial enlarged view, i.e.) Figure 6 As shown in g), the MSC and PMIC systems are encapsulated and connected using UV-curable adhesive UV5604. Figure 6 (as shown in f). The final structural diagram after encapsulation is shown in Figure f. Figure 7 As shown (the lower chamber 72 in the figure can be filled with liquid electrolyte 5), the actual picture after wire bonding is as follows. Figure 8 As shown.

[0058] The packaged structures of the integrated chips and micro supercapacitors prepared in the specific embodiments described above are compared in size to those of traditional electrolytic capacitors. Figure 9 As shown, 3mF (3.2×2.7×1mm)3 A miniature supercapacitor (MSC, left image, including power management chip) with 2.2mF (Φ13×20mm) 3 The electrolytic capacitor (right figure) is shown in the comparison of its actual size, with the area reduced by 15 times and the volume reduced by 300 times.

[0059] Figure 10 The circuit schematic diagram shows a specific application scenario of the integrated chip and micro supercapacitor packaging structure prepared in the above embodiments. Figure 9 The two products are used in the energy harvesting system based on the triboelectric nanogenerator (TENG). The part inside the dashed box in the figure is the integrated circuit function, and the part outside the dashed box is the unintegrated part.

[0060] according to Figure 10 An energy harvesting system based on a triboelectric nanogenerator (TENG) was constructed. Since the TENG is a miniature power source with high voltage and high impedance, the AC power it generates needs to be rectified and converted to DC power. Once the integrated chip detects the peak DC voltage, the miniature supercapacitor / electrolytic capacitor is charged according to a "synchronous charge extraction" power management strategy. By harvesting the energy from the TENG (3Hz, 500pF internal capacitance, 220V positive peak voltage, 90V negative peak voltage), the voltage across the miniature supercapacitor increased from 0V to 1.2V within 240s, successfully applied to manage the TENG's output. Figure 11 (Middle red line) The voltage across the electrolytic capacitor increases from 0V to 2V within 240s. The charging speed of MSCs is approximately 60% of that of ACE. This is mainly due to the larger capacitance of the micro supercapacitor (charging speed is inversely proportional to capacitance) and a slightly larger leakage current than ACE (the large leakage current of micro supercapacitors is another major challenge preventing their widespread application). Figure 11 In this embodiment, MSCs represents the package structure of the integrated chip and the micro supercapacitor, while ACE represents a traditional electrolytic capacitor.

Claims

1. A packaging structure for an integrated chip and a micro supercapacitor, characterized in that, The resin matrix (1) includes a cavity inside the resin matrix (1) with openings on the top and bottom surfaces. A substrate (2) is attached to the bottom surface of the resin matrix (1) by a curing adhesive (3). An electrode (4) is provided on the substrate (2), and the electrode (4) is located in the cavity inside the resin matrix (1) and has pins extending outward from the resin matrix (1). A liquid electrolyte (5) is provided in the cavity inside the resin matrix (1). An integrated chip (6) is attached to the top surface of the resin matrix (1) by a curing adhesive (3), and the integrated chip (6) is connected to the pins by wires. The cavity inside the resin matrix (1) is divided into an upper chamber (71) and a lower chamber (72) by an inner cavity partition plate (7). The inner cavity partition plate (7) is funnel-shaped and has a first through hole (73) in the center. The lower chamber (72) contains liquid electrolyte (5) and the upper chamber (71) contains curing adhesive (3).

2. The packaging structure according to claim 1, characterized in that, At least one second through hole (74) is provided at the junction of the inner cavity partition plate (7) and the resin matrix (1).

3. The packaging structure according to claim 1 or 2, characterized in that, The side edge of the integrated chip (6) is fitted onto the top of the cavity inside the resin matrix (1).

4. A packaging method for the integrated chip and micro supercapacitor packaging structure according to any one of claims 1-3, characterized in that, Includes the following steps: (1) An electrode (4) is disposed on the substrate (2); the resin matrix (1) is processed. (2) The substrate (2) is adhered to the bottom surface of the resin matrix (1) using the curing adhesive (3), and the electrode (4) is located in the cavity inside the resin matrix (1) and has pins extending outward from the resin matrix (1); (3) Injecting liquid electrolyte into the cavity inside the resin matrix; (4) Use curing adhesive (3) to seal the top of the cavity inside the resin matrix (1), and at the same time adhere the integrated chip (6) to the top surface of the resin matrix (1). (5) The integrated chip (6) and the pins are connected by wire bonding, and the electrical interconnection wire bonding between the integrated chip (6) and the micro supercapacitor in the vertical direction is completed.

5. The packaging method according to claim 4, characterized in that, Before injecting the liquid electrolyte (5), the cavity inside the resin matrix (1) is first wetted with the liquid electrolyte (5).

6. The packaging method according to claim 4, characterized in that, The substrate (2) is a silicon / silicon oxide substrate, the silicon oxide is disposed on the silicon surface, the electrode (4) is disposed on the silicon oxide surface, and the electrode (4) is an interdigitated porous electrode.

7. The packaging method according to claim 6, characterized in that, The electrode (4) is set on the substrate (2) by the following steps: a double layer of photoresist is uniformly spin-coated on the surface of the substrate (2), and ultraviolet light is used for irradiation and development to form interdigitated and inverted trapezoidal patterns in the double layer of photoresist; copper / zinc is deposited on the double layer of photoresist by magnetron sputtering, and then it is immersed in acetone and the stripping process is completed by ultrasonic waves to form an interdigitated electrode structure on the substrate (2); finally, zinc is selectively etched in hydrochloric acid to form a porous copper electrode structure, and then a porous copper / copper oxide electrode is formed on the substrate (2) by ozone oxidation.

8. The packaging method according to any one of claims 4-7, characterized in that, The resin matrix (1) is obtained by 3D printing.

9. The packaging method according to any one of claims 4-7, characterized in that, The curing adhesive (3) is a UV-curable adhesive.

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