WAT testing method, system and readable storage medium for edge incomplete area

Abstract

The present invention relates to the field of semiconductor technology, and in particular to a WAT ​​test method, system and readable storage medium for edge incomplete areas. The method comprises: obtaining the discriminant coordinates of the pad farthest from the center of the wafer for each testkey in each partial site according to the wafer map of the wafer, and calculating the distance between the discriminant coordinates and the center of the wafer; comparing the calculated distance with the effective radius of the wafer, if the distance is less than the effective radius, it means that the corresponding testkey is complete; otherwise, it means that the corresponding testkey is incomplete; establishing a test program, and performing a WAT ​​test on all complete testkeys on the wafer according to the test program, and automatically skipping the incomplete testkey. The method can simply and quickly determine whether each testkey in the partial site is complete.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a WAT ​​testing method, system and readable storage medium for edge incomplete areas. Background Art

[0002] In the semiconductor manufacturing process, electrical measurement WAT (Wafer Acceptance Testing) is often used to reflect problems on the production line by measuring the electrical parameters of the testkey (test structure) on the wafer (wafer) scribe line (slice groove). The method is to design multiple test structures in the site (area) to be measured on the wafer. These test structures are formed on the scribe groove between the chips, and the probe card is inserted into the pad (metal pad) of the test structure for measurement.

[0003] There are partial sites (incomplete edge areas) of different shapes around the outer edge of the wafer. The WAT parameters of the partial sites can also be used to discover process problems. However, the complete testkeys contained in each partial site are usually inconsistent. For the same testkey, some sites are complete and some are incomplete. Currently, the following two methods are commonly used to test partial sites:

[0004] 1) Manually find the complete testkey in the partial site. This method has great limitations because different partial sites contain different complete testkeys. This method requires building multiple test programs containing complete testkeys. At the same time, engineers need to manually confirm the integrity of the testkeys and test the testkeys of different edge partialsites separately, which is very time-consuming and extremely inconvenient.

[0005] 2) All partial sites use one test program, and perform needle measurement regardless of whether they are complete testkeys. This method wastes test time and has a great risk of needle card damage. At the same time, it will generate abnormal test data that is not conducive to engineer analysis. Summary of the invention

[0006] The object of the present invention is to provide a WAT ​​test method, system and readable storage medium for an edge incomplete area, so as to solve the WAT test problem of each testkey in a partial site.

[0007] In order to achieve the above object, the present invention provides a WAT ​​testing method for an edge incomplete area, comprising the following steps:

[0008] Obtain the discriminant coordinates of the pad of each testkey in each partial site that is farthest from the center of the wafer according to the wafer map of the wafer, and calculate the distance between the discriminant coordinates and the center of the wafer;

[0009] The calculated distance is compared with the effective radius of the wafer. If the distance is smaller than the effective radius, it indicates that the corresponding testkey is complete; otherwise, it indicates that the corresponding testkey is incomplete.

[0010] A test program is established, and WAT test is performed on all complete testkeys on the wafer according to the test program, and incomplete testkeys are automatically skipped and not tested.

[0011] Optionally, a first coordinate system is established with the site located at the center of the wafer as the origin, the coordinates of each partial site in the first coordinate system are marked as (X, Y), and a second coordinate system is established with the center of the wafer as the origin, and a third coordinate system is established with the lower left corner endpoint of the partial site as the origin. The formula for calculating the distance between the discriminant coordinate and the center of the wafer is as follows:

[0012]

[0013] Wherein, STEPX and STEPY are the length of the site on the X axis and the width on the Y axis, respectively; offsetx and offsety represent the offset between the center of the site located at the center of the wafer and the center of the wafer on the X axis and the Y axis in the second coordinate system, respectively; X tk and Y tk respectively represent the coordinates of the first pad on the testkey in the third coordinate system, L tk Indicates the total length of the testkey.

[0014] Optionally, the WAT test method for the incomplete edge area further includes:

[0015] Create a test document to record the integrity of each testkey in each partial site.

[0016] Optionally, all complete testkeys on the wafer share a test program.

[0017] Based on the same inventive concept, the present invention also provides a WAT ​​testing system for an edge incomplete area, comprising:

[0018] A calculation module is configured to obtain the discriminant coordinates of the pad of each testkey in each partial site that is farthest from the center of the wafer according to the wafer map of the wafer, and calculate the distance between the discriminant coordinates and the center of the wafer;

[0019] A determination module is configured to compare the calculated distance with the effective radius of the wafer. If the distance is smaller than the effective radius, it indicates that the corresponding testkey is complete; otherwise, it indicates that the corresponding testkey is incomplete.

[0020] The test module is configured to establish a test program, and perform WAT test on all complete testkeys on the wafer according to the test program, and incomplete testkeys are automatically skipped and not tested.

[0021] Optionally, a first coordinate system is established with the site located at the center of the wafer as the origin, the coordinates of each partial site in the first coordinate system are marked as (X, Y), and a second coordinate system is established with the center of the wafer as the origin, and a third coordinate system is established with the lower left corner endpoint of the partial site as the origin. The formula for calculating the distance between the discriminant coordinate and the center of the wafer is as follows:

[0022]

[0023] Wherein, STEPX and STEPY are the length of the site on the X axis and the width on the Y axis, respectively; offsetx and offsety represent the offset between the center of the site located at the center of the wafer and the center of the wafer on the X axis and the Y axis in the second coordinate system, respectively; X tk and Y tk respectively represent the coordinates of the first pad on the testkey in the third coordinate system, L tk Indicates the total length of the testkey.

[0024] Optionally, the edge incomplete area WAT ​​testing system further includes a filing module, which is configured to create a test document to record the integrity of each testkey in each partial site.

[0025] Optionally, all complete testkeys on the wafer share a test program.

[0026] Based on the same inventive concept, the present invention further provides a readable storage medium having a computer program stored thereon, and when the computer program is executed, the WAT test method for the edge incomplete area as described above can be implemented.

[0027] The WAT test method, system and readable storage medium for edge incomplete areas provided by the present invention have at least one of the following beneficial effects:

[0028] 1) By comparing the calculated coordinates of the pad farthest from the center of each testkey with the distance between the center of the wafer and the effective radius of the wafer, it is possible to quickly and easily determine whether the testkey is complete, so that all testkeys that need to be tested can be put into one test program for testing, and incomplete testkeys will be automatically skipped without being needled, thereby improving the test efficiency, avoiding needle card damage, and reducing production costs;

[0029] 2) You only need to create a test document for a product to determine whether the test key is complete. During the test, you can determine whether the test key is complete by reading the test document, so that you can directly skip the incomplete test key, which makes the test flexible and convenient;

[0030] 3) It is helpful to solve the low yield problem at the edge of the wafer during the process development stage and improve the production output of the machine.

[0031] 4) It is beneficial to collect the electrical properties of a large number of devices on the edge of the wafer and improve the consistency of the chip production process. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0033] Figure 1 A flow chart of a WAT ​​testing method for an edge incomplete area provided by an embodiment of the present invention;

[0034] Figure 2 A schematic diagram of a partial site in a wafer diagram provided by an embodiment of the present invention;

[0035] Figure 3 A structural block diagram of a WAT ​​testing system for edge incomplete areas provided by an embodiment of the present invention.

[0036] in:

[0037] 100- calculation module; 200- identification module; 300- testing module; 400- archiving module. DETAILED DESCRIPTION

[0038] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, please refer to the accompanying drawings. It should be noted that the structure, proportion, size, etc. illustrated in the drawings of this specification are only used to match the content disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Any modification of the structure, change in the proportional relationship or adjustment of the size, under the same or similar conditions as the effects that can be produced by the present invention and the purposes that can be achieved, should still fall within the scope of the technical content disclosed by the present invention.

[0039] As used in the present invention, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0040] Please refer to Figure 1 , this embodiment provides a WAT ​​test method for an edge incomplete area, comprising the following steps:

[0041] S1. Obtain the discriminant coordinates of the pad of each testkey in each partial site that is farthest from the center of the wafer according to the wafer map of the wafer, and calculate the distance between the discriminant coordinates and the center of the wafer;

[0042] S2, comparing the calculated distance with the effective radius of the wafer, if the distance is smaller than the effective radius, it indicates that the corresponding testkey is complete; otherwise, it indicates that the corresponding testkey is incomplete;

[0043] S3. Establish a test program, and perform WAT test on all complete testkeys on the wafer according to the test program. Incomplete testkeys are automatically skipped and not tested.

[0044] By comparing the calculated coordinates of the pad farthest from the center of the wafer with the distance between the center of the wafer and the effective radius of the wafer, it is possible to quickly and easily determine whether the testkey is complete, so that all testkeys that need to be tested can be put into one test program for testing, and incomplete testkeys will be automatically skipped without being needled, thereby improving test efficiency, avoiding needle card damage, and reducing production costs.

[0045] First, execute S1, obtain the discriminant coordinates of the pads of each testkey in each partial site that are farthest from the wafer center according to the wafer map of the wafer, and calculate the distance between the discriminant coordinates and the wafer center. In this embodiment, the wafer map of the wafer can be generated in advance by an existing machine or tool.

[0046] In this embodiment, a first coordinate system is established with the site located at the center of the wafer as the origin, and the coordinates of each partial site in the first coordinate system are marked as (X, Y), and a second coordinate system is established with the center of the wafer as the origin, and a third coordinate system is established with the lower left corner endpoint of the partial site as the origin. The formula for calculating the distance between the discriminant coordinate and the center of the wafer is as follows:

[0047]

[0048] Wherein, STEPX and STEPY are the length of the site on the X axis and the width on the Y axis, respectively; offsetx and offsety represent the offset between the center of the site located at the center of the wafer and the center of the wafer on the X axis and the Y axis in the second coordinate system, respectively; X tk and Y tk respectively represent the coordinates of the first pad on the testkey in the third coordinate system, L tk Indicates the total length of the testkey.

[0049] It should be noted that when the wafer map of the wafer is generated in advance by an existing machine or tool, the coordinate information of each partial site can be directly obtained. Figure 2 As shown, such as FG3 (4, 3) located in the first quadrant, FG17 (-4, 3) located in the second quadrant, FG12 (-4, -3) located in the third quadrant, and FG7 ​​(4, -3) located in the fourth quadrant. At the same time, the length STEPX of the site on the X axis and the width STEPY on the Y axis (the length and width of each site are the same), the offset offsetx and the offset offsety of the site center located at the center of the wafer and the center of the wafer on the X axis in the second coordinate system, and the coordinates of the first pad on the testkey in the third coordinate system (X tk , Y tk ) and the total length of each testkey. Therefore, according to the above formula, the distance A between the determination coordinates of the pad farthest from the wafer center of each testkey and the wafer center can be directly calculated.

[0050] It should be noted that the center of the site located at the center of the wafer may or may not coincide with the center of the wafer in the second coordinate system. Therefore, the offset offsetx on the X-axis and the offset offsety on the Y-axis between the center of the site located at the center of the wafer and the center of the wafer in the second coordinate system are introduced here. If the center of the site located at the center of the wafer coincides with the center of the wafer in the second coordinate system, the values ​​of offsetx and offsety are 0. If they do not coincide, at least one of offsetx and offsety is not 0.

[0051] For example, the determination coordinates of the pad of the testkey in FG3 located in the first quadrant that is farthest from the center of the wafer can be recorded as (X1, Y1), where:

[0052]

[0053] The discriminant coordinates of the pad of the testkey located in the second quadrant FG17 farthest from the center of the wafer can be recorded as (X2, Y2), where:

[0054]

[0055] The discriminant coordinates of the pad of the testkey located in the third quadrant FG12 farthest from the center of the wafer can be recorded as (X3, Y3), where:

[0056]

[0057] The discriminant coordinates of the pad of the testkey located in the fourth quadrant FG7, which is farthest from the center of the wafer, can be recorded as (X4, Y4), where:

[0058]

[0059] Therefore, the distance A between the determination coordinate and the center of the wafer can be calculated using the following formula:

[0060]

[0061] It should be noted that, for each testkey, since the starting point of the pad is usually from left to right, the pad farthest from the center of the wafer may be the last pad of the testkey, such as the testkey in the partial site on the right side of the center of the wafer, or it may be the first pad of the testkey, such as the testkey in the partial site on the left side of the center of the wafer. Therefore, n is introduced in the above formula for representation.

[0062] After calculating the distance between the discrimination coordinate and the center of the wafer, execute S2 to compare the calculated distance with the effective radius of the wafer. If the distance is less than the effective radius, it means that the corresponding testkey is complete; otherwise, it means that the corresponding testkey is incomplete, which is equivalent to that part of the testkey exceeds the effective radius of the wafer.

[0063] Preferably, a test document is established to record the integrity of each testkey in each partial site. Only one test document needs to be established for one product to determine whether the testkey is complete. During the test, the testkey can be determined to be complete by reading the test document, so that incomplete testkeys can be directly skipped, making the test flexible and convenient.

[0064] Finally, S3 is executed to establish a test program, and a WAT ​​test is performed on all complete test keys on the wafer according to the test program.

[0065] In this embodiment, when the wafer is subjected to WAT test, incomplete test keys are automatically skipped to avoid pin card damage, save test time, and reduce production costs.

[0066] In this embodiment, all the complete testkeys on the wafer share a test program, which makes the test flexible and convenient, and is conducive to improving the test efficiency and the production output of the machine.

[0067] Based on the same invention concept, please refer to Figure 3 The embodiment of the present invention further provides a WAT ​​testing system for edge incomplete areas, including:

[0068] The calculation module 100 is configured to obtain the discriminant coordinates of the pad of each testkey in each partial site that is farthest from the center of the wafer according to the wafer map of the wafer, and calculate the distance between the discriminant coordinates and the center of the wafer;

[0069] The determination module 200 is configured to compare the calculated distance with the effective radius of the wafer. If the distance is smaller than the effective radius, it indicates that the corresponding testkey is complete; otherwise, it indicates that the corresponding testkey is incomplete.

[0070] The test module 300 is configured to establish a test program, and perform WAT test on all complete testkeys on the wafer according to the test program, and incomplete testkeys are automatically skipped.

[0071] In this embodiment, a first coordinate system is established with the site located at the center of the wafer as the origin, and the coordinates of each partial site in the first coordinate system are marked as (X, Y), and a second coordinate system is established with the center of the wafer as the origin, and a third coordinate system is established with the lower left corner endpoint of the partial site as the origin. The formula for calculating the distance between the discriminant coordinate and the center of the wafer is as follows:

[0072]

[0073] Wherein, STEPX and STEPY are the length of the site on the X axis and the width on the Y axis, respectively; offsetx and offsety represent the offset between the center of the site located at the center of the wafer and the center of the wafer on the X axis and the Y axis in the second coordinate system, respectively; X tk and Y tk respectively represent the coordinates of the first pad on the testkey in the third coordinate system, L tk Indicates the total length of the testkey.

[0074] In this embodiment, the edge incomplete area WAT ​​testing system further includes a file creation module 400, and the file creation module 400 is configured to create a test document to record the integrity of each testkey in each partial site.

[0075] In this embodiment, all complete test keys on the wafer share a test program.

[0076] Based on the same inventive concept, an embodiment of the present invention further provides a readable storage medium having a computer program stored thereon, and when the computer program is executed, the WAT test method for the edge incomplete area as described above can be implemented.

[0077] The readable storage medium can be a tangible device that can keep and store the instructions used by the instruction execution device, such as but not limited to an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device or any suitable combination thereof. The more specific example (non-exhaustive list) of the readable storage medium includes: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. The computer program described herein can be downloaded from the readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network and / or a wireless network. The network can include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer program from the network and forwards the computer program for storage in the readable storage medium in each computing / processing device. The computer program for performing the operation of the present invention can be an assembly instruction, an instruction set architecture (ISA) instruction, a machine instruction, a machine-related instruction, a microcode, a firmware instruction, a state setting data, or a source code or object code written in any combination of one or more programming languages, including object-oriented programming languages-such as Smalltalk, C++, etc., and conventional procedural programming languages-such as "C" language or similar programming languages. The computer program can be executed completely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on the remote computer, or completely on the remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect through the Internet). In some embodiments, by utilizing the state information of a computer program to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute computer-readable program instructions to implement various aspects of the present invention.

[0078] Here, various aspects of the present invention are described with reference to the flowchart and / or block diagram of the method, system and computer program product according to the embodiment of the present invention. It should be understood that each square frame of the flowchart and / or block diagram and the combination of the square frames in the flowchart and / or block diagram can be realized by a computer program. These computer programs can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device, so as to produce a machine, so that these programs, when executed by the processor of a computer or other programmable data processing device, produce a device for realizing the function / action specified in one or more square frames in the flowchart and / or block diagram. These computer programs can also be stored in a readable storage medium, and these computer programs make the computer, programmable data processing device and / or other equipment work in a specific way, so that the readable storage medium storing the computer program includes a manufactured product, which includes instructions for realizing various aspects of the function / action specified in one or more square frames in the flowchart and / or block diagram.

[0079] The computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are executed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0080] In summary, the embodiments of the present invention provide a WAT ​​test method, system and readable storage medium for incomplete edge areas. By comparing the calculated discrimination coordinates of the pad of each testkey farthest from the center of the wafer with the distance between the center of the wafer and the effective radius of the wafer, it is possible to simply and quickly determine whether the testkey is complete, so that all testkeys that need to be tested can be put into one test program for testing, and incomplete testkeys will automatically jump out without being pierced, thereby improving the test efficiency, while also avoiding damage to the needle card and reducing production costs.

[0081] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for testing electrical properties of an incomplete edge region, characterized in that: The following steps are involved: Obtaining the discriminant coordinates of the pads of each test structure in each edge incomplete region that are farthest from the center of the wafer according to the wafer map of the wafer, and calculating the distance between the discriminant coordinates and the center of the wafer; The calculated distance is compared with the effective radius of the wafer. If the distance is smaller than the effective radius, it indicates that the corresponding test structure is complete; otherwise, it indicates that the corresponding test structure is incomplete. Establishing a test program, and performing electrical tests on all complete test structures on the wafer according to the test program, and automatically skipping incomplete test structures; Among them, a first coordinate system is established with the area located at the center of the wafer as the origin, the coordinates of each edge incomplete area in the first coordinate system are marked as (X, Y), and a second coordinate system is established with the center of the wafer as the origin, and a third coordinate system is established with the lower left corner endpoint of the edge incomplete area as the origin. The formula for calculating the distance between the discriminant coordinate and the center of the wafer is as follows: ； ； Wherein, STEPX and STEPY are the length of the region on the X axis and the width on the Y axis, respectively; offsetx and offsety represent the offset between the center of the region located at the center of the wafer and the center of the wafer on the X axis and the Y axis in the second coordinate system, respectively; X tk and Y tk respectively represent the coordinates of the first pad on the test structure in the third coordinate system, L tk Represents the total length of the test structure.

2. The electrical property testing method for edge incomplete area according to claim 1, characterized in that: The electrical property testing method for the incomplete edge area also includes: Test documentation is established to record the integrity of each test structure in each area of ​​edge imperfections.

3. The electrical property testing method for edge incomplete area according to claim 1, characterized in that: All complete test structures on the wafer share a common test program.

4. An electrical property testing system for edge incomplete areas, characterized in that: include: A calculation module is configured to obtain the discriminant coordinates of the pads of each test structure in each edge incomplete area that are farthest from the center of the wafer according to the wafer map of the wafer, and calculate the distance between the discriminant coordinates and the center of the wafer; A determination module is configured to compare the calculated distance with the effective radius of the wafer, and if the distance is smaller than the effective radius, it indicates that the corresponding test structure is complete; otherwise, it indicates that the corresponding test structure is incomplete; A test module is configured to establish a test program, and to perform electrical tests on all complete test structures on the wafer according to the test program, and incomplete test structures are automatically skipped and not tested; Among them, a first coordinate system is established with the area located at the center of the wafer as the origin, the coordinates of each edge incomplete area in the first coordinate system are marked as (X, Y), and a second coordinate system is established with the center of the wafer as the origin, and a third coordinate system is established with the lower left corner endpoint of the edge incomplete area as the origin. The formula for calculating the distance between the discriminant coordinate and the center of the wafer is as follows: ； ； Wherein, STEPX and STEPY are the length of the region on the X axis and the width on the Y axis, respectively; offsetx and offsety represent the offset between the center of the region located at the center of the wafer and the center of the wafer on the X axis and the Y axis in the second coordinate system, respectively; X tk and Y tk respectively represent the coordinates of the first pad on the test structure in the third coordinate system, L tk Represents the total length of the test structure.

5. The electrical property testing system for edge incomplete area according to claim 4, characterized in that: The electrical property testing system for edge incomplete regions further includes a file building module configured to build a test document to record the integrity of each test structure in each edge incomplete region.

6. The electrical property testing system for edge incomplete area according to claim 4, characterized in that: All complete test structures on the wafer share a common test program.

7. A readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed, the method for testing electrical properties of an edge incomplete area according to any one of claims 1 to 3 can be implemented.

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