Semiconductor device and manufacturing method thereof, and memory system

Abstract

The disclosed embodiment provides a semiconductor device and a manufacturing method thereof, and a memory system; wherein the semiconductor device includes: a first dielectric layer, a second dielectric layer, and a semiconductor structure layer stacked in sequence along a first direction; a first conductive structure, which penetrates the first dielectric layer along the first direction; a contact structure, which penetrates the second dielectric layer along the first direction and extends into the semiconductor structure layer; the contact structure is connected to the first conductive structure; a second conductive structure, which penetrates the first dielectric layer along the first direction and extends into the second dielectric layer; the second conductive structure is electrically isolated from the first conductive structure; a third conductive structure, which penetrates the semiconductor structure layer along the first direction and extends into the second dielectric layer; the third conductive structure is connected to the second conductive structure; the third conductive structure is electrically isolated from the contact structure. In this way, the etching time can be reduced, the etching process difficulty can be reduced, the manufacturing rate can be increased, the manufacturing cost can be reduced, and the reliability of the semiconductor device can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a memory system. Background Art

[0002] With the development of large-scale integrated circuits, the feature size of each structure in the memory is constantly shrinking, and the memory is developing in the three-dimensional direction and entering the post-Moore era to meet the requirements of high integration, fast transmission speed, and low power consumption. Multiple chips stacked in the three-dimensional direction in the memory are mainly connected vertically through silicon via (TSV) technology; and according to different process processes, TSV technology can include TSV-first, TSV-middle, and TSV-last processes.

[0003] However, as the number of stacked layers increases, there are still many problems to be solved in the process of coupling the connection structure with the landing layer using the TSV-last process. Summary of the invention

[0004] In view of this, in order to solve one or more of the existing technical problems, the embodiments of the present disclosure propose a semiconductor device and a manufacturing method thereof, and a memory system; wherein the semiconductor device includes: a first dielectric layer, a second dielectric layer, and a semiconductor structure layer stacked in sequence along a first direction; a first conductive structure, which penetrates the first dielectric layer along the first direction; a contact structure, which penetrates the second dielectric layer along the first direction and extends into the semiconductor structure layer, and the contact structure is connected to the first conductive structure; a second conductive structure, which penetrates the first dielectric layer along the first direction and extends into the second dielectric layer; the second conductive structure is electrically isolated from the first conductive structure; a third conductive structure, which penetrates the semiconductor structure layer along the first direction and extends into the second dielectric layer; the third conductive structure is connected to the second conductive structure; the third conductive structure is electrically isolated from the contact structure.

[0005] In some embodiments, the cross-sectional shape of the second conductive structure on the first plane includes an axisymmetric figure including a hollow area; and the first plane is perpendicular to the first direction.

[0006] In some embodiments, the thickness of the first conductive structure in the first direction ranges from 50 nanometers to 100 nanometers; the thickness of the second conductive structure in the first direction ranges from 300 nanometers to 500 nanometers.

[0007] In some embodiments, the material of the first dielectric layer includes silicon oxide; and the material of the second dielectric layer includes silicon carbon nitride.

[0008] In some embodiments, the semiconductor device further includes: a third dielectric layer, the third dielectric layer being located on one side of the first dielectric layer opposite to the other along the first direction and away from the second dielectric layer; the material of the third dielectric layer includes a dielectric material having a dielectric constant value less than 3.2.

[0009] In some embodiments, the semiconductor device further includes: a first interconnect structure and a second interconnect structure; the first interconnect structure and the second interconnect structure are both located in the third dielectric layer; the first interconnect structure is connected to the first conductive structure, the second interconnect structure is connected to the second conductive structure, and the first interconnect structure and the second interconnect structure are electrically isolated from each other.

[0010] In some embodiments, the third dielectric layer includes a first sub-dielectric layer and at least one second sub-dielectric layer, wherein the at least one second sub-dielectric layer is located between the first sub-dielectric layer and the first dielectric layer; and the material of the second sub-dielectric layer includes a dielectric material having a dielectric constant value less than 3.2.

[0011] In some embodiments, the first interconnect structure includes a first portion and a second portion, the first portion is located in the at least one second sub-dielectric layer, and the second portion is located in the first sub-dielectric layer; the second interconnect structure includes a third portion and a fourth portion, the third portion is located in the at least one second sub-dielectric layer, and the fourth portion is located in the first sub-dielectric layer.

[0012] In some embodiments, the second sub-dielectric layer includes a first layer and a second layer, the first layer is located between the second layer and the first dielectric layer; the material of the first layer includes a dielectric material with a dielectric constant value less than 3.2; and the material of the second layer includes silicon carbon nitride.

[0013] In some embodiments, the semiconductor device further includes: a first pad and a second pad, the first pad and the second pad being electrically isolated from each other and both being located on one side of the third dielectric layer away from the first dielectric layer on two opposite sides along the first direction; the first pad being connected to the first interconnect structure, and the second pad being connected to the second interconnect structure.

[0014] A memory system is further proposed in an embodiment of the present disclosure, comprising a semiconductor device as described in the above embodiment of the present disclosure; and a memory controller coupled to the semiconductor device and used to control the semiconductor device.

[0015] In an embodiment of the present disclosure, a method for manufacturing a semiconductor device is proposed, the method comprising: forming a first dielectric layer, a second dielectric layer, and a semiconductor structure layer stacked in sequence along a first direction; forming a first conductive structure penetrating the first dielectric layer along the first direction, and a second conductive structure penetrating the first dielectric layer and extending into the second dielectric layer; the second conductive structure is electrically isolated from the first conductive structure; forming a contact structure penetrating the second dielectric layer along the first direction and extending into the semiconductor structure layer, the contact structure being connected to the first conductive structure; forming a third conductive structure penetrating the semiconductor structure layer along the first direction and extending into the second dielectric layer; the third conductive structure is connected to the second conductive structure; the third conductive structure is electrically isolated from the contact structure.

[0016] In some embodiments, the forming of a first dielectric layer, a second dielectric layer, and a semiconductor structure layer stacked in sequence along a first direction includes: providing the semiconductor structure layer; forming the second dielectric layer on one side of two opposite sides of the semiconductor structure layer along the first direction; and forming the first dielectric layer on one side of two opposite sides of the second dielectric layer along the first direction that is away from the semiconductor structure layer.

[0017] In some embodiments, the forming of the first conductive structure penetrating the first dielectric layer along the first direction, and the forming of the second conductive structure penetrating the first dielectric layer and extending into the second dielectric layer, includes: forming a first mask layer on one side of the first dielectric layer that is away from the second dielectric layer on two opposite sides along the first direction; forming a second mask layer on one side of the first mask layer that is away from the first dielectric layer on two opposite sides along the first direction; forming a first groove penetrating the first dielectric layer along the first direction using the first mask layer; forming a second groove penetrating the first dielectric layer along the first direction and extending into the second dielectric layer using the first mask layer and the second mask layer; forming the first conductive structure in the first groove, and forming the second conductive structure in the second groove.

[0018] In some embodiments, the method further includes: forming a third dielectric layer on one side of the first dielectric layer that is away from the second dielectric layer, of two opposite sides of the first dielectric layer along the first direction; the material of the third dielectric layer includes a dielectric material with a dielectric constant value less than 3.2.

[0019] In some embodiments, forming a third dielectric layer on one side of the first dielectric layer that is opposite to each other along the first direction and away from the second dielectric layer includes: forming a first sub-dielectric layer on one side of the first dielectric layer that is opposite to each other along the first direction and away from the second dielectric layer; and forming at least one second sub-dielectric layer between the first sub-dielectric layer and the first dielectric layer.

[0020] In some embodiments, forming at least one second sub-dielectric layer between the first sub-dielectric layer and the first dielectric layer includes: forming a first layer between the first sub-dielectric layer and the first dielectric layer; forming a second layer between the first layer and the first sub-dielectric layer; the material of the first layer includes a dielectric material having a dielectric constant value less than 3.2; and the material of the second layer includes silicon carbon nitride.

[0021] In some embodiments, the method further includes: forming a first interconnect structure and a second interconnect structure in the third dielectric layer; the first interconnect structure is connected to the first conductive structure, the second interconnect structure is connected to the second conductive structure, and the first interconnect structure and the second interconnect structure are electrically isolated from each other.

[0022] In some embodiments, the method further includes: forming a first pad and a second pad on one side of the third dielectric layer that is away from the first dielectric layer on two sides opposite to each other along the first direction; the first pad and the second pad are electrically isolated from each other; the first pad is connected to the first interconnect structure, and the second pad is connected to the second interconnect structure.

[0023] In some embodiments, the forming of the third conductive structure that penetrates the semiconductor structure layer along the first direction and extends into the second dielectric layer includes: forming a third groove that penetrates the semiconductor structure layer along the first direction and extends into the second dielectric layer; and forming the third conductive structure in the third groove.

[0024] In the embodiment of the present disclosure, a first conductive structure penetrating the first dielectric layer is formed in the first dielectric layer, and a second conductive structure penetrating the first dielectric layer and extending into the second dielectric layer is formed in the first dielectric layer and the second dielectric layer, so that the thickness of the second conductive structure in the first direction is greater than the thickness of the first conductive structure in the first direction; in this way, on the one hand, in the process of forming the third conductive structure, the etching process can be prevented from etching and breaking down the second conductive structure, thereby improving the anti-breakdown capability of the landing layer, and thus improving the reliability of the semiconductor device. On the other hand, in the process of forming the third conductive structure, the etching process only etches the semiconductor structure layer and part of the second dielectric layer. Compared with the third conductive structure in the related art that needs to etch the first dielectric layer, the second dielectric layer and the semiconductor structure layer, in the embodiment of the present disclosure, the number of dielectric layers to be etched can be reduced, thereby reducing the etching time, reducing the process difficulty of etching, increasing the manufacturing rate, and reducing the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of an electronic device provided by an embodiment of the present disclosure;

[0026] Figure 2 A schematic diagram of a first conductive structure and a second conductive structure provided in an embodiment of the present disclosure;

[0027] Figure 3 Schematic diagram of cross-sectional shapes of five second conductive structures provided in one embodiment of the present disclosure;

[0028] Figure 4 A schematic diagram of a first interconnection structure and a second interconnection structure provided in an embodiment of the present disclosure;

[0029] Figure 5 A schematic diagram of a third conductive structure provided in an embodiment of the present disclosure;

[0030] Figure 6 A schematic diagram of a manufacturing process of a semiconductor device provided by an embodiment of the present disclosure;

[0031] Figure 7 A schematic diagram of a cross-sectional structure of a second mask layer provided in one embodiment of the present disclosure;

[0032] Figure 8 A schematic diagram of a cross-sectional structure of a first mask layer provided in one embodiment of the present disclosure;

[0033] Fig. 9 A schematic diagram of the cross-sectional structure of a bottom anti-reflective coating provided in one embodiment of the present disclosure;

[0034] Fig.10 A schematic diagram of the cross-sectional structure of a photoresist layer provided in one embodiment of the present disclosure;

[0035] Fig.11 A schematic cross-sectional structure diagram of a bottom anti-reflective coating having a second pattern provided in one embodiment of the present disclosure;

[0036] Fig.12 A schematic diagram of the cross-sectional structure of a first dielectric layer provided in one embodiment of the present disclosure;

[0037] Fig.13 A schematic diagram of the cross-sectional structure of a second dielectric layer provided in one embodiment of the present disclosure;

[0038] Fig.14 A schematic diagram of the cross-sectional structure of a conductive material layer provided in one embodiment of the present disclosure;

[0039] Fig.15 A schematic cross-sectional structure diagram of a first conductive structure and a second conductive structure provided in an embodiment of the present disclosure;

[0040] Fig.16 A schematic cross-sectional structure diagram of a first interconnect structure and a second interconnect structure provided in one embodiment of the present disclosure;

[0041] Fig.17A schematic diagram of the cross-sectional structure of a first pad and a second pad provided in an embodiment of the present disclosure;

[0042] Fig.18 A schematic cross-sectional view of a third conductive structure provided in accordance with an embodiment of the present disclosure.

[0043] In the above drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0044] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0045] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0046] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0047] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0048] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0049] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0051] Figure 1 Schematic diagram of an electronic device provided for an embodiment of the present disclosure. The electronic device 1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0052] like Figure 1 As shown, the electronic device 1 may include a memory system 10 and a host 20, and the memory system 10 may include a controller 110 and a memory 120. The host 20 may include a processor of the electronic device 1, such as a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)). The controller 110 is coupled to both the host 20 and the memory 120, and the controller 110 may be configured to communicate with the host 20 and control the memory 120.

[0053] In some embodiments, the controller 110 may be configured to control operations of the memory 120, such as a read operation, an erase operation, a write operation, a refresh operation, etc. In some embodiments, the controller 110 is further configured to process an error correction code (ECC) on data read from or written to the memory 120. In other embodiments, the controller 110 may also be configured to perform any other suitable operations, such as formatting the memory 120.

[0054] In some embodiments, the controller 110 may receive data, commands, and addresses from the host 20, and may send data, commands, and addresses to the memory 120. Specifically, the controller 110 may include a command generator 111, an address generator 112, a device interface 113, and a host interface 114. The controller 110 may receive data, commands, and addresses from the host 20 through the host interface 114, decode the command received from the host 20 through the command generator 111 to generate an access command CMD, and may provide the access command CMD to the memory 120 through the device interface 113. The controller 110 may generate an address ADDR to be accessed in the memory cell array 121 by decoding the address received from the host interface 114 through the address generator 112, and may provide the address ADDR to be accessed to the memory 120 through the device interface 113. The access command may be a signal instructing the memory 120 to write or read data by accessing one or more memory cells in the memory cell array 121 corresponding to the address ADDR. In addition, the controller 110 may also send a refresh command to the memory 120 . The refresh command may be a signal instructing the memory 120 to read out and rewrite data by accessing one or more memory cells in the memory cell array 121 corresponding to the address ADDR.

[0055] In some embodiments, the memory 120 includes a memory cell array 121 and a peripheral circuit 122. The memory cell array 121 includes a plurality of memory cells arranged in an array. The peripheral circuit 122 includes a sense amplifier circuit, a row decoder, a column decoder, a data input / output buffer, etc. The peripheral circuit 122 is used to receive an access command CMD and an address ADDR. Based on the analysis of the access command CMD and the address ADDR, each memory cell in the memory cell array 121 can be independently accessed, and a read operation, a write operation, or a refresh operation, etc., can be performed on the data stored in the accessed memory cell.

[0056] In some specific examples, the memory 120 can be a NAND Flash, a random access memory (RAM), such as a dynamic random access memory, a synchronous dynamic random access memory (SDRAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a double data rate SDRAM (DDR SDRAM), a phase-change random access memory (PRAM), a resistive random access memory (ReRAM), a magnetic random access memory (MRAM), etc.

[0057] With the improvement of memory manufacturing technology, more connection structures (such as metal layers) are needed between the structures in the memory for signal transmission and power distribution. Exemplarily, three types of connection structures (such as M1-M8 metal layers) can be set between the structures in the memory; among them, the first type of connection structure (such as M1, M2, M3 metal layers) is used to interconnect local signals between structures, and the interconnection layout is dense and small. The second type of connection structure (such as M4, M5, M6 metal layers) is used for signal transmission over longer distances between structures and some local power distribution. The third type of connection structure (such as M7, M8 metal layers) is used for long-distance signal transmission between structures and power and ground distribution of the entire chip. It should be understood that as the line width of the connection structure decreases, the corresponding film thickness also decreases. In other words, the depth-to-width ratio of the connection structure decreases and the process window increases.

[0058] In actual operation, when the TSV-last process lands on the front metal layer (i.e., the landing layer), the film thickness of the front metal layer needs to be thicker, so as to prevent the TSV-last process from breaking through the front metal layer. At present, the front metal layer where the TSV-last process lands is mainly in the M4, M5, M6 metal layers, and even the M7 and M8 metal layers. Based on this, the TSV-last process needs to penetrate multiple dielectric layers. In addition, in order to reduce RC delay, the dielectric layer where the front metal layer is located is gradually replaced by a low dielectric constant (Low-K) material, which causes the TSV-Last process to pass through the Low-K material dielectric layer. Water vapor or damage enters the Low-K material dielectric layer, changing the K value of the material. At the same time, in the TSV-Last process, the Through Dielectric Via (TDV) technology is usually used to etch multiple dielectric layers, which takes a long time, increases manufacturing costs, and increases process difficulty.

[0059] Based on this, in order to solve one or more of the above problems, the present disclosure provides a semiconductor device in an embodiment, such as Figure 2 As shown, Figure 2 A schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment of the present disclosure, such as Figure 2 As shown, the semiconductor device includes: a first dielectric layer 201, a second dielectric layer 202 and a semiconductor structure layer 203 stacked in sequence along a first direction; a first conductive structure 204, penetrating the first dielectric layer 201 along the first direction; a contact structure 205, penetrating the second dielectric layer 202 along the first direction and extending into the semiconductor structure layer 203, and the contact structure 205 is connected to the first conductive structure 204; a second conductive structure 206, penetrating the first dielectric layer 201 along the first direction and extending into the second dielectric layer 202; the second conductive structure 206 and the first conductive structure 204 are electrically isolated from each other; a third conductive structure 207, penetrating the semiconductor structure layer 203 along the first direction and extending into the second dielectric layer 202; the third conductive structure 207 is connected to the second conductive structure 206; the third conductive structure 207 and the contact structure 205 are electrically isolated from each other. Here, the third conductive structure 207 and the second conductive structure 206 have an interface at the connection between the two. That is, the third conductive structure 207 and the second conductive structure 206 are formed in different process steps.

[0060] Based on this, by forming a first conductive structure penetrating the first dielectric layer in the first dielectric layer, and forming a second conductive structure penetrating the first dielectric layer and extending into the second dielectric layer in the first dielectric layer and the second dielectric layer, the thickness of the second conductive structure in the first direction is greater than the thickness of the first conductive structure in the first direction; in this way, on the one hand, in the process of forming the third conductive structure, the etching process can be prevented from breaking through the second conductive structure, thereby improving the reliability of the semiconductor device. On the other hand, in the process of forming the third conductive structure, the etching process only needs to etch the semiconductor structure layer and part of the second dielectric layer. Compared with the third conductive structure in the related art that needs to etch the first dielectric layer, the second dielectric layer and the semiconductor structure layer, in the embodiment of the present disclosure, the number of dielectric layers to be etched can be reduced, thereby reducing the difficulty of the etching process, increasing the process window, reducing the etching time, increasing the manufacturing rate, and reducing the manufacturing cost.

[0061] In the detailed introduction Figure 2 Before illustrating the semiconductor device, various directions that may be used in the following description are defined. In the present disclosure, the stacking direction of multiple layers in the semiconductor device is defined as a first direction (i.e., the Z-axis direction). In a plane perpendicular to the Z-direction, an intersecting second direction (i.e., the X-axis direction) and a third direction (i.e., the Y-axis direction) are defined. In some embodiments, the X-axis direction, the Y-axis direction, and the Z-axis direction may be perpendicular to each other.

[0062] refer to Figure 2 The material of the first dielectric layer 201 includes silicon oxide (SiO2); the material of the second dielectric layer 202 includes silicon carbon nitride (SiCN); the thickness of the first dielectric layer 201 and the second dielectric layer 202 along the Z-axis direction can be set according to actual needs, and the present disclosure does not limit it.

[0063] The semiconductor structure layer 203 is provided with a peripheral circuit and / or a memory cell array. The peripheral circuit may include a plurality of CMOS transistors and control circuits related to the CMOS transistors, such as control logic, sensing amplifier circuit, row decoder, column decoder, data input / output buffer, driver and read / write circuit, etc., wherein, when the control logic receives a read / write operation command and address data, under the action of the control logic, the row decoder or column decoder may apply the corresponding voltage generated by the driver to the corresponding bit line and word line based on the decoded address to realize data reading or writing, and perform data interaction with external devices through the data input / output buffer. The memory cell array may include a plurality of memory cells, which may be NAND memory cells, PCM memory cells, DRAM memory cells, etc.

[0064] In some embodiments, the materials of the first conductive structure 204 and the second conductive structure 206 may be the same or different. Exemplarily, the materials of the first conductive structure 204 and / or the second conductive structure 206 include conductive materials, such as gold (Au), silver (Ag), copper (Cu), iron (Fe), nickel (Ni), tin (Sn), aluminum (Al), etc.

[0065] In some embodiments, the thickness of the first conductive structure 204 in the Z-axis direction ranges from 50 nanometers to 100 nanometers; the thickness of the second conductive structure 206 in the Z-axis direction ranges from 300 nanometers to 500 nanometers.

[0066] In some embodiments, the shapes of the first conductive structure 204 and the second conductive structure 206 may be the same or different. Here, the cross-sectional shape of the first conductive structure 204 on the first plane includes a circle, a square, a strip, etc. The cross-sectional shape of the second conductive structure 206 on the first plane includes an axisymmetric figure containing a hollow area. The first plane is a plane formed by the second direction and the third direction, such as an XY plane. For example, refer to Figure 3 , Figure 3 Schematic diagrams of five cross-sectional shapes of the second conductive structure 206 on the XY plane are shown in FIG. In other embodiments, the cross-sectional shape of the second conductive structure 206 on the XY plane may also be other shapes, such as circular, square, strip, non-axisymmetric mesh structure, etc.

[0067] It should be noted that the second conductive structure 206 can serve as a landing layer for the third conductive structure 207. Figure 3 The five cross-sectional shapes shown in the figure are all axisymmetric figures, so that the second conductive structure 206 can be evenly stressed, thereby increasing the reliability of the semiconductor device. In addition, the second conductive structure 206 is set as a hollow structure, which can effectively prevent the device from being delaminated or cracked due to excessive or concentrated stress during the annealing process of the device in the subsequent process.

[0068] Preferably, the third conductive structure 207 is connected to the central region of the second conductive structure 206 , so that the second conductive structure 206 can be further subjected to balanced force, thereby preventing the TDV etching used when forming the third conductive structure 207 from causing breakdown of the second conductive structure 206 .

[0069] In some specific embodiments, the size of the second conductive structure 206 in the X-axis direction is a first size, the size of the third conductive structure 207 in the X-axis direction is a second size, and the first size is greater than the second size. In this way, the contact area between the third conductive structure 207 and the second conductive structure 206 can be increased to increase the process window and reduce the process difficulty.

[0070] It should be noted that in the actual operation process of forming the third conductive structure 207, due to the limitations of the etching process, the formed etched hole is larger at the top and smaller at the bottom along the Z-axis direction, and thus the third conductive structure 207 formed in the etched hole is also larger at the top and smaller at the bottom. Preferably, the third conductive structure 207 has the same size from top to bottom along the Z-axis direction.

[0071] In some embodiments, the semiconductor device further includes a barrier layer 213, which is located between the third conductive structure 207 and the semiconductor structure layer 203, and on a side surface of the semiconductor structure layer 203 away from the second dielectric layer 202 along the Z-axis direction. The barrier layer 213 is used to play a blocking and isolating role. The material of the barrier layer 213 includes but is not limited to silicon oxide.

[0072] In the embodiment of the present disclosure, the material of the contact structure 205 includes but is not limited to conductive materials, such as Au, Ag, Cu, Fe, Ni, Sn, Al, etc. One end of the contact structure 205 along the Z-axis direction is connected to the first conductive structure 204, and the other end along the Z-axis direction is connected to the peripheral circuit or the memory cell array in the semiconductor structure layer 203, so as to realize the electrical signal communication between the peripheral circuit or the memory cell array and the first conductive structure 204.

[0073] In some specific embodiments, a peripheral circuit is disposed in the semiconductor structure layer 203, and the peripheral circuit is connected to the contact structure 205. A storage unit array ( Figure 2 (not shown in the figure), the memory cell array is coupled to the third conductive structure 207, so that the connection between the peripheral circuit and the external device can be achieved through the first conductive structure 204 and the contact structure 205; and the connection between the memory cell array and the external device can be achieved through the second conductive structure 206 and the third conductive structure 207.

[0074] It should be noted that the number of the first conductive structure, the second conductive structure, the third conductive structure and the contact structure in the semiconductor device can be one or more, and their arrangement can be set arbitrarily, but it should be understood that the first conductive structure 204 is electrically isolated from the second conductive structure 206 and the third conductive structure 207, and the contact structure 205 is electrically isolated from the second conductive structure 206 and the third conductive structure 207.

[0075] In some embodiments, reference Figure 4 The semiconductor device further includes: a third dielectric layer 208, which is located on one side of the first dielectric layer 201 that is opposite to each other along the Z-axis direction and is away from the second dielectric layer 202; the material of the third dielectric layer 208 includes a dielectric material having a dielectric constant value less than 3.2.

[0076] In some specific embodiments, the third dielectric layer 208 includes a first sub-dielectric layer 208a and at least one second sub-dielectric layer 208b, wherein the at least one second sub-dielectric layer 208b is located between the first sub-dielectric layer 208a and the first dielectric layer 201; the material of the second sub-dielectric layer 208b includes a dielectric material having a dielectric constant value less than 3.2.

[0077] In some specific embodiments, the second sub-dielectric layer 208 b includes a first layer 2081 and a second layer 2082 , and the first layer 2081 is located between the second layer 2082 and the first dielectric layer 201 .

[0078] In some specific embodiments, the first sub-medium layer 208 a includes a third layer 2083 , a fourth layer 2084 and a fifth layer 2085 . The fourth layer 2084 is located between the third layer 2083 and the fifth layer 2085 ; and the third layer 2083 is located between the fourth layer 2084 and the second layer 2082 .

[0079] In some other specific embodiments, the first sub-dielectric layer 208 a may include only the third layer 2083 .

[0080] refer to Figure 4 The third dielectric layer 208 includes two second sub-dielectric layers 208b, which are adjacent and stacked along the Z-axis direction. In other embodiments, the third dielectric layer 208 may also include other numbers of second sub-dielectric layers 208b, such as 1 layer, 3 layers, 4 layers, 5 layers, etc.

[0081] In the embodiment of the present disclosure, the material of the first layer is a low dielectric constant material (Low-K material), the materials of the second layer and the fourth layer are the same, and the materials of the third layer and the fifth layer are the same. Exemplarily, the material of the first layer 2081 includes a dielectric material with a dielectric constant value less than 3.2; the material of the second layer 2082 includes silicon carbon nitride; the material of the third layer 2083 includes silicon oxide; the material of the fourth layer 2084 includes silicon carbon nitride; and the material of the fifth layer 2085 includes silicon oxide.

[0082] It should be noted that low dielectric constant materials have lower resistivity and loss factor, and are used to reduce signal transmission delay (RC delay), reduce crosstalk, reduce power consumption, and increase the operating speed of semiconductor devices during signal transmission.

[0083] It should be noted that the thicknesses of the first layer 2081, the second layer 2082, the third layer 2083, the fourth layer 2084 and the fifth layer 2085 can be set according to actual needs; in the embodiment of the present disclosure, the thickness of the first layer 2081 along the Z-axis direction is greater than the thickness of the second layer 2082 along the Z-axis direction. The thicknesses of the third layer 2083 and the fifth layer 2085 along the Z-axis direction are both greater than the thickness of the fourth layer 2084 along the Z-axis direction.

[0084] In some embodiments, reference Figure 4 The semiconductor device further includes: a first interconnect structure 209 and a second interconnect structure 210; the first interconnect structure 209 and the second interconnect structure 210 are both located in the third dielectric layer 208; the first interconnect structure 209 is connected to the first conductive structure 204, the second interconnect structure 210 is connected to the second conductive structure 206, and the first interconnect structure 209 and the second interconnect structure 210 are electrically isolated from each other.

[0085] In some specific embodiments, the first interconnect structure 209 includes a first portion 2091 and a second portion 2092, the first portion 2091 is located in at least one second sub-dielectric layer 208b, and the second portion 2092 is located in the first sub-dielectric layer 208a, that is, the first portion 2091 of the first interconnect structure is located between the second portion 2092 of the first interconnect structure and the first conductive structure 204; the second interconnect structure 210 includes a third portion 2101 and a fourth portion 2102, the third portion 2101 is located in at least one second sub-dielectric layer 208b, and the fourth portion 2102 is located in the first sub-dielectric layer 208a, that is, the third portion 2101 of the second interconnect structure is located between the fourth portion 2102 of the second interconnect structure and the second conductive structure 206.

[0086] The materials of the first interconnect structure 209 and the second interconnect structure 210 may be the same or different. Here, the materials of the first interconnect structure 209 and the second interconnect structure 210 both include conductive materials, such as Au, Ag, Cu, Fe, Ni, Sn, Al, etc.

[0087] In some embodiments, reference Figure 5 The semiconductor device also includes: a first pad 211 and a second pad 212, which are electrically isolated from each other and are both located on one side of the third dielectric layer 208 that is opposite to each other along the Z-axis direction and is away from the first dielectric layer 201; the first pad 211 is connected to the first interconnect structure 209, and the second pad 212 is connected to the second interconnect structure 210.

[0088] The materials of the first pad 211 and the second pad 212 are the same or different. Here, the materials of the first pad 211 and the second pad 212 are both conductive materials, such as Au, Ag, Cu, Fe, Ni, Sn, Al, etc.

[0089] In this way, when a peripheral circuit is provided in the semiconductor structure layer 203, the peripheral circuit is connected to the contact structure 205, and a memory cell array is provided on a side of the semiconductor structure layer 203 away from the second dielectric layer 202 along the Z-axis direction, and the memory cell array is connected to the third conductive structure 207, the connection between the peripheral circuit and the external device can be achieved through the first pad 211, the first interconnect structure 209, the first conductive structure 204, and the contact structure 205; and the connection between the memory cell array and the external device can be achieved through the second pad 212, the second interconnect structure 210, the second conductive structure 206, and the third conductive structure 207.

[0090] Based on this, in the embodiment of the present disclosure, by forming a first conductive structure penetrating the first dielectric layer in the first dielectric layer, and forming a second conductive structure penetrating the first dielectric layer and extending into the second dielectric layer in the first dielectric layer and the second dielectric layer, the thickness of the second conductive structure in the Z-axis direction is greater than the thickness of the first conductive structure in the Z-axis direction; in this way, on the one hand, in the process of forming the third conductive structure, the etching process can be prevented from etching and breaking through the second conductive structure, thereby improving the reliability of the semiconductor device. On the other hand, in the process of forming the third conductive structure, the etching process only etches the semiconductor structure layer and part of the second dielectric layer. Compared with the third conductive structure in the related art that needs to etch the first dielectric layer, the second dielectric layer and the semiconductor structure layer, in the embodiment of the present disclosure, the number of dielectric layers to be etched can be reduced, thereby reducing the difficulty of the etching process, reducing the etching time, increasing the manufacturing rate, and reducing the manufacturing cost.

[0091] Based on the above semiconductor device, the present disclosure also provides a method for manufacturing a semiconductor device. Figure 6 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device in an embodiment of the present disclosure; Figure 6 As shown, the manufacturing method comprises the following steps:

[0092] Step S601: forming a first dielectric layer, a second dielectric layer, and a semiconductor structure layer stacked in sequence along a first direction.

[0093] Step S602: forming a first conductive structure penetrating the first dielectric layer along a first direction, and a second conductive structure penetrating the first dielectric layer and extending into the second dielectric layer; the second conductive structure and the first conductive structure are electrically isolated from each other.

[0094] Step S603: forming a contact structure penetrating the second dielectric layer along a first direction and extending into the semiconductor structure layer, wherein the contact structure is connected to the first conductive structure.

[0095] Step S604: forming a third conductive structure penetrating the semiconductor structure layer along the first direction and extending into the second dielectric layer; the third conductive structure is connected to the second conductive structure; and the third conductive structure and the contact structure are electrically isolated from each other.

[0096] It should be understood that Figure 6 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 6 The steps shown in the figure can be adjusted in sequence according to actual needs. Figures 7 to 18 The structure diagram of the manufacturing process of the semiconductor device provided in the embodiment of the present disclosure is as follows. Figures 6 to 18 A method for manufacturing a semiconductor device provided in an embodiment of the present disclosure is introduced.

[0097] In some embodiments, the forming of a first dielectric layer, a second dielectric layer, and a semiconductor structure layer stacked in sequence along a first direction includes: providing a semiconductor structure layer; forming a second dielectric layer on one side of two opposite sides of the semiconductor structure layer along the Z-axis direction; and forming a first dielectric layer on one side of two opposite sides of the second dielectric layer along the Z-axis direction, away from the semiconductor structure layer.

[0098] Here, a peripheral circuit and / or a memory cell array is provided in the semiconductor structure layer. The peripheral circuit may include a plurality of CMOS transistors and control circuits related to the CMOS transistors, such as control logic, sensing amplifier circuit, row decoder, column decoder, data input / output buffer, driver and read / write circuit, etc., wherein, when the control logic receives the read / write operation command and address data, under the action of the control logic, the row decoder or column decoder may apply the corresponding voltage generated by the driver to the corresponding bit line and word line based on the decoded address to realize data reading or writing, and perform data interaction with external devices through the data input / output buffer. The memory cell array may include a plurality of memory cells, which may be NAND memory cells, PCM memory cells, DRAM memory cells, etc. The method of forming a peripheral circuit or a memory cell array is relatively mature and will not be described here.

[0099] Specifically: Reference Figure 7 , a semiconductor structure layer 703 is provided, a second dielectric material layer 801 is formed on one side of the semiconductor structure layer 703 along the Z-axis direction, the second dielectric material layer 801 and the semiconductor structure layer 703 are etched to form a first groove, and a conductive material is filled in the first groove to form a contact structure 705. Here, the first groove penetrates the second dielectric material layer 801 and extends into the semiconductor structure layer 703; the contact structure 705 is connected to the peripheral circuit or the memory cell array in the semiconductor structure layer 703. In some specific embodiments, the length of the contact structure 705 along the Z-axis direction ranges from 700 nanometers to 1000 nanometers.

[0100] The material of the second dielectric material layer 801 includes silicon carbon nitride, and the conductive material includes but is not limited to conductive materials such as W, Au, Ag, Cu, Fe, Ni, Sn, Al, etc. The etching process includes dry etching. The filling process includes but is not limited to electroplating (ECP) process, etc. The method for forming the second dielectric material layer 801 includes but is not limited to deposition process, and the deposition process includes chemical vapor deposition (Chemical Vapor Deposition, CVD), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD) process, etc.

[0101] refer to Figure 7 A first dielectric material layer 802 is formed on one side of the second dielectric material layer 801 that is opposite to each other along the Z-axis direction and is far from the semiconductor structure layer 703, a first mask material layer 803 is formed on one side of the first dielectric material layer 802 that is far from the second dielectric material layer 801, and a second mask layer 804 is formed on one side of the first mask material layer 803 that is opposite to each other along the Z-axis direction and is far from the first dielectric material layer 802. Here, the second mask layer 804 has a first pattern.

[0102] The material of the first dielectric material layer 802 includes silicon carbon nitride, the material of the first mask material layer 803 includes silicon oxide, and the material of the second mask layer 804 includes photoresists (PR). The method of forming the first dielectric material layer 802 and the first mask material layer 803 includes but is not limited to a deposition process, and the deposition process includes CVD, LPCVD, PECVD, PVD, ALD process, etc. The method of forming the second mask layer 804 includes but is not limited to coating / spin coating, etc.

[0103] In actual operation, the specific method of forming the second mask layer 804 may include: coating photoresist on the surface of the side away from the first dielectric material layer 802 on the two opposite sides of the first mask material layer 803 along the Z-axis direction, exposing and developing the photoresist, and removing part of the photoresist by dissolving or ashing to form a second mask layer 804 having a first pattern.

[0104] refer to Figure 8 , the first mask material layer is etched using the second mask layer 804 to form a first mask layer 805. The first mask layer 805 has a first pattern. The etching process includes but is not limited to dry etching.

[0105] refer to Fig. 9 , remove the second mask layer, and deposit a bottom anti-reflective coating (BARC) 806 on the first mask layer 805. The bottom anti-reflective coating 806 is used to reduce reflection and standing waves. The material of the bottom anti-reflective coating 806 includes a cross-linkable resin, a thermal acid generator, a surfactant, and a solvent. The method of forming the bottom anti-reflective coating includes spin coating.

[0106] refer to Fig.10 A layer of photoresist is coated on one side of the bottom anti-reflective coating 806 that is away from the first mask layer 805 on two opposite sides along the Z-axis direction, and a photoresist layer 807 having a second pattern is formed by using processes such as exposure, development, etching, and ashing.

[0107] It should be noted that the first pattern partially overlaps with the second pattern, the first pattern can be used as a preset pattern for forming a first conductive structure, and the first pattern and the second pattern can be used as preset patterns for forming a second conductive structure.

[0108] refer to Fig.11 , using the photoresist layer having the second pattern as a mask, removing part of the bottom anti-reflective coating 806 to form a bottom anti-reflective coating 806 having the second pattern; and removing the photoresist layer 807 having the second pattern; the removal process includes dry etching, etc., and the removal process includes dissolution or ashing, etc.

[0109] refer to Fig.12 , using the bottom anti-reflection coating with the second pattern as a mask, removing part of the first dielectric material layer to form the first dielectric layer 701. At the same time, the bottom anti-reflection coating with the second pattern is removed. The removal process includes but is not limited to dry etching, and the removal process includes dissolution or ashing.

[0110] refer to Fig.13 , using the first mask layer as a mask, removing part of the second dielectric material layer to form the second dielectric layer 702. At the same time, the first mask layer is removed. The removal process includes but is not limited to dry etching.

[0111] It should be noted that after removing part of the first dielectric material layer using the first mask layer, a first groove 809 penetrating the first dielectric layer 701 along the Z-axis direction can be formed; the first groove 809 exposes one end of the contact structure 705. After removing part of the first dielectric material layer and part of the second dielectric material layer using the first mask layer and the second mask layer, a second groove 810 penetrating the first dielectric layer 701 along the Z-axis direction and extending into the second dielectric layer 702 can be formed. It should be understood that the depth of the second groove 810 along the Z-axis direction is greater than the depth of the first groove 809 along the Z-axis direction.

[0112] refer to Fig.14 , a conductive material layer 811 is deposited on the surface of the first groove 809, the second groove 810 and the first dielectric layer 701. The material of the conductive material layer 811 includes but is not limited to Au, Ag, Cu, Fe, Ni, Sn, Al, etc. The method of forming the conductive material layer 811 includes but is not limited to electroplating process, etc.

[0113] refer to Fig.15 , Chemical Mechanical Polishing (CMP) is performed on the conductive material layer 811 to form a first conductive structure 704 in the first groove 809 and a second conductive structure 706 in the second groove 810. The first conductive structure 704 is connected to the exposed surface of the contact structure 705. The surface of the first conductive structure 704 on the side away from the semiconductor structure layer 703 along the Z-axis direction is substantially flush with the surface of the first dielectric layer 701 on the side away from the second dielectric layer 702 along the Z-axis direction; the surface of the second conductive structure 706 on the side away from the semiconductor structure layer 703 along the Z-axis direction is substantially flush with the surface of the first dielectric layer 701 on the side away from the second dielectric layer 702 along the Z-axis direction.

[0114] It should be understood that the “substantially flush” mentioned here can be understood as flush or approximately flush, wherein the non-fluctuation caused by errors in the actual manufacturing process is within the range of substantially flush or approximately flush.

[0115] In this way, a second groove 810 with a deeper depth can be formed by two mask layers, namely, the first mask layer 805 and the second mask layer 804, and a second conductive structure 706 with a thicker thickness can be formed in the second groove 810, that is, the size of the second conductive structure 706 along the Z-axis direction is greater than the size of the first conductive structure 704 along the Z-axis direction. Exemplarily, the thickness of the second conductive structure 706 in the Z-axis direction ranges from 300 nanometers to 500 nanometers. The thickness of the first conductive structure 704 in the Z-axis direction ranges from 50 nanometers to 100 nanometers.

[0116] It should be understood that the thicker the second conductive structure 706 is in the Z-axis direction, the less likely the second conductive structure 706 will be broken down by the etching process during the subsequent process of forming the third conductive structure 707 through the TDV etching process, thereby improving the reliability of the semiconductor device.

[0117] In some embodiments, the cross-sectional shape of the second conductive structure 706 on the XY plane includes an axisymmetric figure including a hollow region, so as to effectively prevent the delamination or cracking of the semiconductor device due to excessive or concentrated stress during the annealing process of the second conductive structure 706 and the third conductive structure 707 in the subsequent process.

[0118] In some embodiments, the method further includes: forming a third dielectric layer 708 on one side of the first dielectric layer 701 that is away from the second dielectric layer 702 in the Z-axis direction; the material of the third dielectric layer 708 includes a dielectric material with a dielectric constant value less than 3.2.

[0119] In some specific embodiments, the third dielectric layer 708 includes a first sub-dielectric layer 708a and at least one second sub-dielectric layer 708b, wherein the at least one second sub-dielectric layer 708b is located between the first sub-dielectric layer 708a and the first dielectric layer 701; the material of the second sub-dielectric layer 708b includes a dielectric material with a dielectric constant value less than 3.2. Based on this, the third dielectric layer is formed on one side of the first dielectric layer that is opposite to each other along the Z-axis direction and is far from the second dielectric layer, including: forming the first sub-dielectric layer 708a on one side of the first dielectric layer 701 that is opposite to each other along the Z-axis direction and is far from the second dielectric layer 702; and forming at least one second sub-dielectric layer 708b between the first sub-dielectric layer 708a and the first dielectric layer 701.

[0120] It should be understood that the third dielectric layer 708 may include one second sub-dielectric layer 708b or multiple second sub-dielectric layers 708b. When the third dielectric layer 708 includes multiple second sub-dielectric layers 708b, the multiple second sub-dielectric layers 708b are stacked along the Z-axis direction. Fig.16 The third dielectric layer 708 shown in FIG. 7 includes two second sub-dielectric layers 708 b . Each second sub-dielectric layer 708 b includes a first layer 7081 and a second layer 7082 . The first layer 7081 is located between the second layer 7082 and the first dielectric layer 701 .

[0121] The method of forming at least one second sub-dielectric layer between the first sub-dielectric layer and the first dielectric layer includes: forming a first layer 7081 between the first sub-dielectric layer 708a and the first dielectric layer 701; forming a second layer 7082 between the first layer 7081 and the first sub-dielectric layer 708a. Here, the material of the first layer 7081 is a low dielectric constant material (Low-K material), and exemplarily, the material of the first layer 7081 includes a dielectric material with a dielectric constant value less than 3.2; the material of the second layer 7082 can be the same as that of the first dielectric layer 701; exemplarily, the material of the second layer 7082 includes silicon carbon nitride. The method of forming the first layer 7081 and the second layer 7082 includes, but is not limited to, a deposition process, and the deposition process includes CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0122] It should be noted that low dielectric constant materials have lower resistivity and loss factor. Therefore, they can be used to reduce signal transmission delay (RC delay), reduce crosstalk, reduce power consumption, and increase the operating speed of memory during signal transmission.

[0123] In some embodiments, the first sub-medium layer 708a may include a third layer 7083, a fourth layer 7084, and a fifth layer 7085, wherein the fourth layer 7084 is located between the third layer 7083 and the fifth layer 7085; and the third layer 7083 is located between the fourth layer 7084 and the second layer 7082. Based on this, the method further includes: forming the third layer 7083 on one side of the second layer 7082 opposite to each other along the Z-axis direction and away from the first layer 7081; forming the fourth layer 7084 on one side of the third layer 7083 opposite to each other along the Z-axis direction and away from the second layer 7082; and forming the fifth layer 7085 on one side of the fourth layer 7084 opposite to each other along the Z-axis direction and away from the third layer 7083.

[0124] In some other specific embodiments, the first sub-dielectric layer 208a may also include only the third layer 2083. Based on this, the method further includes: forming the third layer 7083 on one side of the second layer 7082 that is away from the first layer 7081 in the two opposite sides along the Z-axis direction.

[0125] Here, the fourth layer is made of the same material as the second layer, and the third layer is made of the same material as the fifth layer. Exemplarily, the material of the third layer includes silicon oxide; the material of the fourth layer includes silicon carbon nitride; and the material of the fifth layer includes silicon oxide. Methods for forming the third layer 7083, the fourth layer 7084, and the fifth layer 7085 include, but are not limited to, deposition processes, including CVD, LPCVD, PECVD, PVD, ALD processes, and the like.

[0126] refer to Fig.16 , a second trench and a third trench are formed in the third dielectric layer, a first interconnection structure 709 is formed in the second trench, and a second interconnection structure 710 is formed in the third trench. The second trench and the third trench penetrate the third dielectric layer, the second trench exposes a side surface of the first conductive structure 704 away from the contact structure 705 along the Z-axis direction, the third trench exposes a side surface of the second conductive structure 706 away from the semiconductor structure layer 703 along the Z-axis direction, and the second trench is spaced from the third trench. Based on this, the first interconnection structure 709 is connected to the first conductive structure 704, the second interconnection structure 710 is connected to the second conductive structure 706, and the first interconnection structure 709 and the second interconnection structure 710 are electrically isolated from each other.

[0127] The method for forming the second groove and the third groove can be the same as the method for forming the first groove and the second groove in the aforementioned embodiment. Specifically, when forming each layer in the third dielectric layer, a groove can be formed in the layer using a mask, photolithography, and the like. The aforementioned embodiment has described in detail how to form the groove using a mask, which will not be repeated here.

[0128] In some specific embodiments, the first interconnect structure 709 includes a first portion 7091 and a second portion 7092, wherein the first portion 7091 is located in at least one second sub-dielectric layer 708b, and the second portion 7092 is located in the first sub-dielectric layer 708a; the second interconnect structure 710 includes a third portion 7101 and a fourth portion 7102, wherein the third portion 7101 is located in at least one second sub-dielectric layer 708b, and the fourth portion 7102 is located in the first sub-dielectric layer 708a. That is, the first portion 7091 of the first interconnect structure is located between the second portion 7092 of the first interconnect structure and the first conductive structure 704; and the third portion 7101 of the second interconnect structure is located between the fourth portion 7102 of the second interconnect structure and the second conductive structure 706.

[0129] In some embodiments, reference Fig.17 , a first pad 711 and a second pad 712 are formed on one side of the third dielectric layer 708 that is away from the first dielectric layer 701, on two sides that are opposite to each other along the Z-axis direction. The first pad 711 and the second pad 712 are electrically isolated from each other; the first pad 711 is connected to the second portion 7092 of the first interconnect structure, and the second pad 712 is connected to the fourth portion 7102 of the second interconnect structure. The materials of the first pad 711 and the second pad 712 include conductive materials, such as W, Au, Ag, Cu, Fe, Ni, Sn, Al, etc. The formation of the first pad 711 and the second pad 712 includes but is not limited to etching processes, deposition processes, electroplating processes, etc.

[0130] Next, a third conductive structure 707 is formed.

[0131] In some embodiments, reference Fig.18 The forming of the third conductive structure penetrating the semiconductor structure layer along the first direction and extending into the second dielectric layer comprises: forming a third groove penetrating the semiconductor structure layer along the Z-axis direction and extending into the second dielectric layer; and forming the third conductive structure in the third groove.

[0132] Specifically: the semiconductor device is turned over, and the semiconductor structure layer 703 and the second dielectric layer 702 are etched by TDV technology, and a third groove is formed in the semiconductor structure layer 703 and the second dielectric layer 702, which penetrates the semiconductor structure layer 703 along the Z-axis direction and extends to the second dielectric layer 702. A barrier layer 713 is formed on the side wall of the third groove and the surface of the side of the semiconductor structure layer 703 away from the second dielectric layer 702 along the Z-axis direction, and a conductive material is filled in the third groove by electroplating process to form a third conductive structure 707. The material of the barrier layer 713 includes but is not limited to silicon oxide; the conductive material is, for example, Au, Ag, Cu, Fe, Ni, Sn, Al, etc. Among them, the etching method for forming the third groove includes but is not limited to TDV etching; the method for forming the barrier layer includes but is not limited to deposition process, and the deposition process includes CVD, LPCVD, PECVD, PVD, ALD process, etc.; the method for filling the conductive material includes but is not limited to electroplating process, etc.

[0133] It should be noted that the third conductive structure 707 and the second conductive structure 706 have an interface at their connection.

[0134] It should be understood that in the process of forming the third groove in the above embodiment, the TDV technology only etches the semiconductor structure layer and part of the second dielectric layer, and there is no need to penetrate the second dielectric layer, nor to etch the first dielectric layer, and there is no need to etch the third dielectric layer; therefore, compared with the third groove in the related art that penetrates the semiconductor structure layer, the first dielectric layer, the second dielectric layer and the third dielectric layer, in the embodiment of the present disclosure, fewer dielectric layers are etched during the etching process using the TDV technology, so that the etching time can be reduced, the etching difficulty can be reduced, the etching efficiency can be improved, and the production efficiency of the entire product can be improved. On the other hand, the third dielectric layer includes a low dielectric constant material. In other words, in the embodiment of the present disclosure, it is not necessary to etch the low dielectric constant material in the process of forming the third groove, thereby reducing the damage and injury caused to the low dielectric constant material by the etching process. In this way, the K value of the low dielectric constant material can be protected unchanged, thereby improving the reliability of the semiconductor device, such as improving RC delay and increasing the operating speed of the semiconductor device.

[0135] Based on the above-mentioned semiconductor device and its manufacturing method, the embodiment of the present disclosure also provides a memory system, including the semiconductor device as described in the above-mentioned embodiment of the present disclosure; and a memory controller coupled to the semiconductor device and used to control the semiconductor device.

[0136] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In addition, the technical solutions recorded in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0137] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A first dielectric layer, a second dielectric layer and a semiconductor structure layer are sequentially stacked along a first direction; A first conductive structure, penetrating the first dielectric layer along the first direction; a contact structure, penetrating the second dielectric layer along the first direction and extending into the semiconductor structure layer; the contact structure is connected to the first conductive structure; a second conductive structure, penetrating the first dielectric layer along the first direction and extending into the second dielectric layer; the second conductive structure and the first conductive structure are electrically isolated from each other; The third conductive structure penetrates the semiconductor structure layer along the first direction and extends into the second dielectric layer; the third conductive structure is connected to the second conductive structure; and the third conductive structure and the contact structure are electrically isolated from each other.

2. The semiconductor device according to claim 1, wherein: The cross-sectional shape of the second conductive structure on the first plane includes an axisymmetric figure including a hollow area; and the first plane is perpendicular to the first direction.

3. The semiconductor device according to claim 1, wherein: The thickness of the first conductive structure in the first direction ranges from 50 nanometers to 100 nanometers; the thickness of the second conductive structure in the first direction ranges from 300 nanometers to 500 nanometers.

4. The semiconductor device according to claim 1, wherein: The material of the first dielectric layer includes silicon oxide; the material of the second dielectric layer includes silicon carbon nitride.

5. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: a third dielectric layer, the third dielectric layer being located on one side of the first dielectric layer that is opposite to the first dielectric layer along the first direction and is away from the second dielectric layer; The material of the third dielectric layer includes a dielectric material with a dielectric constant value less than 3.

2.

6. The semiconductor device according to claim 5, characterized in that The semiconductor device further comprises: a first interconnect structure and a second interconnect structure; The first interconnect structure and the second interconnect structure are both located in the third dielectric layer; the first interconnect structure is connected to the first conductive structure, the second interconnect structure is connected to the second conductive structure, and the first interconnect structure and the second interconnect structure are electrically isolated from each other.

7. The semiconductor device according to claim 6, characterized in that The third dielectric layer includes a first sub-dielectric layer and at least one second sub-dielectric layer, and the at least one second sub-dielectric layer is located between the first sub-dielectric layer and the first dielectric layer; The material of the second sub-dielectric layer includes a dielectric material with a dielectric constant value less than 3.

2.

8. The semiconductor device according to claim 7, characterized in that The first interconnect structure comprises a first portion and a second portion, the first portion is located in the at least one second sub-dielectric layer, and the second portion is located in the first sub-dielectric layer; The second interconnect structure includes a third portion and a fourth portion, the third portion is located in the at least one second sub-dielectric layer, and the fourth portion is located in the first sub-dielectric layer.

9. The semiconductor device according to claim 7, characterized in that The second sub-medium layer includes a first layer and a second layer, wherein the first layer is located between the second layer and the first medium layer; The material of the first layer includes a dielectric material with a dielectric constant value less than 3.2; the material of the second layer includes silicon carbon nitride.

10. The semiconductor device according to claim 6, wherein: The semiconductor device also includes: a first pad and a second pad, the first pad and the second pad are electrically isolated from each other and are both located on one side of the third dielectric layer that is away from the first dielectric layer on two opposite sides along the first direction; the first pad is connected to the first interconnect structure, and the second pad is connected to the second interconnect structure.

11. A memory system, characterized in that: A semiconductor device comprising any one of claims 1 to 10; and The memory controller is coupled to the semiconductor device and is used to control the semiconductor device.

12. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Forming a first dielectric layer, a second dielectric layer and a semiconductor structure layer stacked in sequence along a first direction; forming a first conductive structure penetrating the first dielectric layer along the first direction, and a second conductive structure penetrating the first dielectric layer and extending into the second dielectric layer; the second conductive structure and the first conductive structure are electrically isolated from each other; forming a contact structure penetrating through the second dielectric layer and extending into the semiconductor structure layer along the first direction, wherein the contact structure is connected to the first conductive structure; A third conductive structure is formed along the first direction, penetrating the semiconductor structure layer and extending into the second dielectric layer; the third conductive structure is connected to the second conductive structure; and the third conductive structure and the contact structure are electrically isolated from each other.

13. The manufacturing method according to claim 12, characterized in that: The method of forming a first dielectric layer, a second dielectric layer, and a semiconductor structure layer stacked in sequence along a first direction includes: Providing the semiconductor structure layer; forming a second dielectric layer on one side of two opposite sides of the semiconductor structure layer along the first direction; The first dielectric layer is formed on one side of the second dielectric layer that is away from the semiconductor structure layer among two sides of the second dielectric layer that are opposite to each other along the first direction.

14. The manufacturing method according to claim 13, characterized in that: The forming of the first conductive structure penetrating the first dielectric layer along the first direction and the second conductive structure penetrating the first dielectric layer and extending into the second dielectric layer comprises: forming a first mask layer on one side of the first dielectric layer that is away from the second dielectric layer and on two sides of the first dielectric layer that are opposite to each other along the first direction; forming a second mask layer on one side of the first mask layer that is away from the first dielectric layer, of two sides of the first mask layer that are opposite to each other along the first direction; Using the first mask layer to form a first groove penetrating the first dielectric layer along the first direction; Using the first mask layer and the second mask layer, a second groove is formed which penetrates the first dielectric layer along the first direction and extends into the second dielectric layer; A first conductive structure is formed in the first groove, and a second conductive structure is formed in the second groove.

15. The manufacturing method according to claim 14, characterized in that: The method further comprises: forming a third dielectric layer on one side of the first dielectric layer that is away from the second dielectric layer and on two sides of the first dielectric layer that are opposite to each other along the first direction; The material of the third dielectric layer includes a dielectric material with a dielectric constant value less than 3.

2.

16. The manufacturing method according to claim 15, characterized in that: The forming of a third dielectric layer on one side of the first dielectric layer that is away from the second dielectric layer and on two sides of the first dielectric layer that are opposite to each other along the first direction comprises: forming a first sub-dielectric layer on one side of the first dielectric layer that is away from the second dielectric layer and on two sides of the first dielectric layer that are opposite to each other along the first direction; At least one second sub-dielectric layer is formed between the first sub-dielectric layer and the first dielectric layer.

17. The manufacturing method according to claim 16, characterized in that: The forming of at least one second sub-dielectric layer between the first sub-dielectric layer and the first dielectric layer comprises: forming a first layer between the first sub-dielectric layer and the first dielectric layer; forming a second layer between the first layer and the first sub-dielectric layer; The material of the first layer includes a dielectric material with a dielectric constant value less than 3.2; the material of the second layer includes silicon carbon nitride.

18. The manufacturing method according to claim 15, characterized in that: The method further comprises: A first interconnect structure and a second interconnect structure are formed in the third dielectric layer; the first interconnect structure is connected to the first conductive structure, the second interconnect structure is connected to the second conductive structure, and the first interconnect structure and the second interconnect structure are electrically isolated from each other.

19. The manufacturing method according to claim 18, characterized in that: The method further comprises: A first pad and a second pad are formed on one side of the third dielectric layer that is away from the first dielectric layer, on two sides of the third dielectric layer that are opposite to each other along the first direction; the first pad and the second pad are electrically isolated from each other; the first pad is connected to the first interconnect structure, and the second pad is connected to the second interconnect structure.

20. The manufacturing method according to claim 12, characterized in that: The forming of a third conductive structure penetrating through the semiconductor structure layer along the first direction and extending into the second dielectric layer comprises: forming a third groove penetrating the semiconductor structure layer along the first direction and extending into the second dielectric layer; The third conductive structure is formed in the third groove.

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