A trench gate mosfet integrated with positive and negative asymmetric gate-source esd protection

Abstract

The application relates to a trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection, which comprises a drain, a substrate, an epitaxial layer and a source arranged in sequence from the lower right to the upper; a plurality of first grooves and a second groove formed on the surface of the epitaxial layer, all the first grooves are distributed in the source region, and the second groove is located in the gate welding area; the surface of the epitaxial layer is formed with a P well area, a P+ area and an N+ area, the P well area is located below the P+ area and the N+ area, and the P+ area and the N+ area are in contact with the source. The application makes full use of the structural characteristics of the trench gate MOSFET device, constructs the n-polySi / p-SiC heterojunction diode and the p-SiC / n-SiCPN junction diode with asymmetric breakdown voltage between the gate and the source of the device, connects the two voltage stabilizing diodes in series, simply and efficiently realizes the ESD protection structure integrated between the gate and the source, and meets the asymmetric requirement of the SiC MOSFET device opening and closing driving protection voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection. BACKGROUND

[0002] SiC MOSFET devices have the significant advantages of high frequency and low loss, and are widely used in electric vehicles and photovoltaic inverters and other fields. In the application process of SiC MOSFET devices, it is usually desired to increase the gate voltage Vgs to reduce the on-resistance of the device.

[0003] However, increasing the gate voltage not only causes the internal gate oxide of the SiC MOSFET device to bear higher electric field stress, but also causes the allowable voltage overshoot margin during the transient switching process of the SiC MOSFET device to decrease, which threatens the long-term safe and stable operation of the device. Especially for SiC MOSFET, the switching speed is extremely fast, and the gate-source voltage overshoot problem is extremely easy to occur during the turn-on and turn-off processes, causing the SiC MOS gate oxide to bear extremely high voltage stress, and the phenomenon of gate oxide performance degradation or even gate damage is easy to occur during long-term use.

[0004] In order to suppress the gate-source voltage overshoot problem of the MOSFET device, a commonly used method is to introduce a voltage stabilizing diode between the gate and the source. However, in the existing MOSFET technology integrated with ESD protection, a series of forward and reverse PN junction diodes is mainly used. When the gate is subjected to a forward voltage overshoot, the reverse PN junction is broken down and the forward PN junction is turned on, and the transient overshoot energy is discharged through the voltage stabilizing diode composed of the series of forward and reverse PN junctions. Conversely, when the gate is subjected to a negative voltage overshoot, the forward PN junction is broken down and the reverse PN junction is turned on, and the transient overshoot energy is still discharged through the voltage stabilizing diode composed of the series of forward and reverse PN junctions. Therefore, the voltage stabilizing diode composed of the series of forward and reverse PN junctions can realize the functions of clamping voltage and discharging energy, and protect the gate oxide of the MOSFET from being damaged by strong electric field stress. The existing technology has the following disadvantages:

[0005] 1. Under the same preparation process, the forward and reverse PN junctions are symmetrical structures, so the forward and reverse clamping voltages are equal, which cannot meet the requirement of asymmetric drive voltage during the turn-on and turn-off of the SiC MOSFET device;

[0006] 2. The forward and reverse PN junctions are prepared by different preparation processes, which will increase the process complexity, preparation process flow and process cost. SUMMARY

[0007] The technical problem solved by the present application is to provide a trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection.

[0008] To solve the above technical problems, the present application adopts the following technical solutions:

[0009] The trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection comprises a drain, a substrate, an epitaxial layer and a source arranged in sequence from the lower right to the upper left.

[0010] A plurality of first trenches and a second trench are formed on the surface of the epitaxial layer, all the first trenches are distributed in the source region, and the second trench is located in the gate welding area.

[0011] The surface of the epitaxial layer is formed with a P-well region, a P+ region and an N+ region, the P-well region is located below the P+ region and the N+ region, and the P+ region and the N+ region are in contact with the source.

[0012] The bottom of the first trench is provided with a first shielding layer, the first trench is provided with a first polysilicon gate, and the outer side of the first polysilicon gate is coated with a first dielectric layer.

[0013] The bottom of the second trench is provided with a second shielding layer, the second trench is provided with a second polysilicon gate, and the outer side of the second polysilicon gate is coated with a second dielectric layer.

[0014] The bottom end of the second polysilicon gate partially extends through the second dielectric layer and is connected with the second shielding layer, the second shielding layer is provided with an N+ implantation region, the N+ implantation region is isolated from the second polysilicon gate by the second dielectric layer, and the N+ implantation region extends to the source and is in contact with the source.

[0015] The second polysilicon gate is n-type polysilicon, the second shielding layer is p-type SiC, and the N+ implantation region is n-type SiC, the second polysilicon gate and the second shielding layer form a reverse n-polySi / p-SiC heterojunction, and the second shielding layer and the N+ implantation region form a forward p-SiC / n-SiC PN junction.

[0016] Further, the ions implanted in the P-well region, the P+ region and the second shielding layer are Al ions or B ions.

[0017] Further, the concentration of the ions implanted in the P+ region is higher than that in the P-well region and the second shielding layer.

[0018] Further, the doping concentration of the P-well region and the second shielding layer gradually increases from top to bottom.

[0019] Further, the first polysilicon gate is n-type polysilicon, and the first shielding layer is p-type SiC.

[0020] Further, the second shielding layer extends to the source region on both sides.

[0021] Further, the thickness of the first dielectric layer above the first polysilicon gate is greater than the thickness of the first dielectric layer at the side and below the first polysilicon gate,

[0022] The thickness of the second dielectric layer above the second polysilicon gate is greater than the thickness of the second dielectric layer at the side and below the second polysilicon gate.

[0023] Further, the first dielectric layer and the second dielectric layer are both SiO2.

[0024] Further, the first trench and the second trench are both located within the MOSFET terminal structure.

[0025] The present application has the following advantages compared with the prior art after adopting the above technical solutions:

[0026] The present application takes full advantage of the trench gate MOSFET device structure characteristics, and constructs an n-polySi / p-SiC heterojunction diode and a p-SiC / n-SiC PN junction diode with asymmetric breakdown voltage between the gate and the source of the device. By connecting the two voltage stabilizing diodes in series, the ESD protection structure is integrated between the gate and the source simply and efficiently, which meets the asymmetric requirement of the SiC MOSFET device opening and closing drive protection voltage.

[0027] The present application optimizes the ion implantation conditions of the P region without changing the process conditions of the second trench, n-polySi and N+, so as to achieve good positive and negative asymmetric gate-source ESD protection effect. The second trench, n-polySi and N+ process in the ESD structure are fully compatible with the original process, and the ion implantation process of the P region only needs to optimize the process conditions, without adjusting the original process steps. Therefore, the method of integrating the ESD structure is easy to realize, and almost does not increase the process complexity and process cost.

[0028] The ESD structure of the present application is integrated in the gate pressure welding area and the surrounding area, without increasing the additional chip area and electrode, and does not cause performance and reliability loss to the SiC MOSFET itself. The area of the gate pressure welding area is fully utilized, and the ESD structure area is maximized without occupying the chip area of the source region, so as to greatly improve the ESD resistance of the SiC MOSFET device.

[0029] The present application will be described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 Structure diagram of trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection;

[0031] Figure 2 Surface electrode distribution diagram of trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection;

[0032] Figure 3 Structure diagram of first stage product in preparation process of trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection;

[0033] Figure 4 Structure diagram of second stage product in preparation process of trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection;

[0034] Figure 5 Structure diagram of third stage product in preparation process of trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection;

[0035] Figure 6 Structure diagram of fourth stage product in preparation process of trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection.

[0036] Figure 7 Structure diagram of fifth stage product in preparation process of trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection.

[0037] In the drawings, the components represented by the respective reference numerals are listed as follows: DETAILED DESCRIPTION

[0038] 1, drain; 2, substrate; 3, epitaxial layer; 31, first trench; 32, second trench; 4, source; 51, P well region; 52, P+ region; 53, N+ region; 61, first shielding layer; 62, first polysilicon gate; 63, first dielectric layer; 71, second shielding layer; 72, second polysilicon gate; 73, second dielectric layer; 74, N+ implantation region.

[0039] The principles and features of the present application are described below in conjunction with the drawings, and the examples are only used to explain the present application and not to limit the scope of the present application.

[0040] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "clockwise" and "counterclockwise" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0041] As shown in Figure 1 and Figure 2 , a trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection includes a drain 1, a substrate 2, an epitaxial layer 3 and a source 4 arranged in sequence from the lower right to the upper;

[0042] The epitaxial layer 3 is made of silicon carbide, and first and second trenches 31 and 32 are formed on the epitaxial layer 3 by etching. The first trench 31 is located in the source region and is used to construct a trench gate structure. The second trench 32 is located in the gate pressure welding area and is used to construct a voltage stabilizing diode.

[0043] The epitaxial layer 3 also forms P-well region 51, P+ region 52 and N+ region 53 by ion implantation, as well as first and second shielding layers 61 and 72 at the bottom of the first and second trenches 31 and 32. The P+ region 52 and the N+ region 53 on both sides of the first and second trenches 31 and 32 are in contact with the source 4. The first shielding layer 61 (P-type semiconductor region) at the bottom of the first trench 31 is used to shield and protect the bottom of the first trench 31. The second shielding layer 72 (P-type semiconductor region) at the bottom of the second trench 32 is used to protect the bottom of the second trench 32 on the one hand, and to form an n-polySi / p-SiC heterojunction with the polysilicon inside the second trench 32 on the other hand.

[0044] There is also an N+ implantation region 74 in the P-type semiconductor region (second shielding layer 72) at the bottom of the second trench 32. The N+ implantation region 74 is electrically connected to the source 4, but there is a layer of dielectric between the N+ implantation region 74 and the polysilicon gate in the second trench 32, which completely isolates the polysilicon and N+.

[0045] In addition to the bottom structure of the second trench 32, there is a thin dielectric layer on the sidewalls and bottom of the first and second trenches 31 and 32. The dielectric layer is filled with polysilicon used to form the gate of the SiC MOSFET. A thicker dielectric layer is provided on top of the polysilicon gate to completely wrap the polysilicon gate in the first and second trenches 31 and 32 and form good insulation isolation with the source.

[0046] ESD protection structure:

[0047] The second trench 32 is provided with a second polysilicon gate 72 made of n-type polysilicon, the outer side of the second polysilicon gate 72 is covered with a second dielectric layer 73, and the bottom part of the second polysilicon gate 72 is in contact with a second shielding layer 73 made of p-type SiC after penetrating through the second dielectric layer 73, so that the second polysilicon gate 72 and the second shielding layer 73 form a reverse n-polySi / p-SiC heterojunction;

[0048] The second shielding layer 73 is p-type SiC, and n-type SiC is formed in the p-type SiC doped region by ion implantation, that is, an N+ implantation region 73, wherein the p-type SiC and the n-type SiC outside the gate pad area extend to the source region through the gate-source spacing area, and the n-type SiC extending to the source region is directly connected with the source, so that the second shielding layer 73 and the N+ implantation region 73 form a forward p-SiC / n-SiC PN junction;

[0049] In summary, the ESD protection structure of the present application is completely integrated in the gate pad area, and the ESD protection structure is a voltage stabilizing diode composed of a reverse n-polySi / p-SiC heterojunction and a forward p-SiC / n-SiC PN junction in series, without the need to increase additional chip area or electrodes.

[0050] In the embodiment, the ions implanted in the P-type semiconductor are Al ions or B ions, wherein the ion concentration implanted in the P+ region 52 is extremely high, and the P-well region 51 and the second shielding layer 71 adopt an inverted doping structure, that is, the doping concentration of the region gradually increases from top to bottom;

[0051] The ions implanted in the N-type semiconductor are P ions or N ions, and the ion concentration implanted in the N+ region 53 is extremely high.

[0052] Specifically, the first trench 31 has a thin first dielectric layer 63 on the sidewall and the bottom, and a thick first dielectric layer 63 on the top, and the inside of the first trench 31 is filled with n-type polysilicon n-polySi, that is, a first polysilicon gate 62;

[0053] The second trench 32 has a thin second dielectric layer 73 on the sidewall and part of the bottom, and a thick second dielectric layer 73 on the top, and the inside of the second trench 32 is filled with n-type polysilicon n-polySi, that is, a second polysilicon gate 72, and the position of the second trench 32 bottom not covered by the dielectric layer, the n-polySi is directly in contact with the p-SiC to form an n-polySi / p-SiC heterojunction diode;

[0054] The second shielding layer 71 is provided with an N+ implantation region 74, and a thin second dielectric layer 73 is provided above the N+ implantation region 74, which is used to form isolation of the second polysilicon gate 72 and the N+ implantation region 73, and the second shielding layer 71 and the N+ implantation region 73 form a p-SiC / n-SiC PN junction diode, and the N+ implantation region 73 extends to the source region and is electrically connected to the source.

[0055] In the embodiment, the first dielectric layer 63 and the second dielectric layer 73 are both SiO2, and the dielectric layers at other positions can be SiO2, SiN, TEOS, PI and other insulating dielectric and combinations thereof.

[0056] As shown in the figure, a preparation process of a trench gate MOSFET integrated with positive and negative asymmetric gate source ESD protection includes the following steps: Figures 3 to 7

[0057] forming an epitaxial layer on the surface of the substrate;

[0058] etching the surface of the epitaxial layer to form a first trench and a second trench;

[0059] ion implantation on the epitaxial layer to form a first shielding layer, a second shielding layer, a P well region, an N+ region, an N+ implantation region and a P+ region;

[0060] forming a first polysilicon gate structure and a first dielectric layer in the first trench, and forming a second polysilicon gate structure and a second dielectric layer in the second trench;

[0061] forming a source and a drain, and making the N+ region contact and be electrically connected to the source to complete the ESD structure.

[0062] The above describes an example of the best embodiment of the present application, wherein parts not described in detail are common knowledge of ordinary skilled in the art. The protection scope of the present application is subject to the content of the claims, and any equivalent transformation based on the technical inspiration of the present application is also within the protection scope of the present application.​

Claims

1. A trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection, characterized in that, The drain (1), the substrate (2), the epitaxial layer (3) and the source (4) are sequentially arranged from bottom to top. A plurality of first grooves (31) and a second groove (32) are formed on the surface of the epitaxial layer (3), all the first grooves (31) are distributed in the source region, and the second groove (32) is located in the gate press bonding area. The surface of the epitaxial layer (3) is formed with a P-well region (51), a P+ region (52) and an N+ region (53), the P-well region (51) is located below the P+ region (52) and the N+ region (53), and the P+ region (52) and the N+ region (53) are in contact with the source (4). The bottom of the first groove (31) is provided with a first shielding layer (61), the first groove (31) is provided with a first polysilicon gate (62), and the outer side of the first polysilicon gate (62) is coated with a first dielectric layer (63). The bottom of the second groove (32) is provided with a second shielding layer (71), the second groove (32) is provided with a second polysilicon gate (72), and the outer side of the second polysilicon gate (72) is coated with a second dielectric layer (73). The bottom end of the second polysilicon gate (72) is connected with the second shielding layer (71) after penetrating the second dielectric layer (73) in a partial region, and the second shielding layer (71) is provided with an N+ implantation region (74) which is isolated from the second polysilicon gate (72) by the second dielectric layer (73) and extends to and is in contact with the source (4). The second polysilicon gate (72) is n-type polysilicon, the second shielding layer (71) is p-type SiC, the N+ implantation region (74) is n-type SiC, the second polysilicon gate (72) and the second shielding layer (71) form a reverse n-polySi / p-SiC heterojunction, and the second shielding layer (71) and the N+ implantation region (74) form a forward p-SiC / n-SiC PN junction.

2. The integrated positive and negative asymmetric gate-source ESD protected trench gate MOSFET of claim 1, wherein, The ions implanted in the P-well region (51), the P+ region (52) and the second shielding layer (71) are Al ions or B ions.

3. The integrated positive and negative asymmetric gate-source ESD protected trench gate MOSFET of claim 2, wherein, The concentration of the ions implanted in the P+ region (52) is higher than that in the P-well region (51) and the second shielding layer (71).

4. The integrated positive and negative asymmetric gate-source ESD protected trench gate MOSFET of claim 2, wherein, The doping concentration of the P-well region (51) and the second shielding layer (71) gradually increases from top to bottom.

5. The integrated positive and negative asymmetric gate-source ESD protected trench gate MOSFET of claim 1, wherein, The first polysilicon gate (62) is n-type polysilicon, and the first shielding layer (61) is p-type SiC.

6. The integrated positive and negative asymmetric gate-source ESD protected trench gate MOSFET of claim 1, wherein, The second shielding layer (71) extends to the source (4) region on both sides.

7. The integrated positive and negative asymmetric gate-source ESD protected trench gate MOSFET of claim 1, wherein, The thickness of the first dielectric layer (63) above the first polysilicon gate (62) is greater than that of the first dielectric layer (63) on the side and below the first polysilicon gate (62), The thickness of the second dielectric layer (73) above the second polysilicon gate (72) is greater than that of the second dielectric layer (73) on the side and below the second polysilicon gate (72).

8. The integrated positive and negative asymmetric gate-source ESD protected trench gate MOSFET of claim 1, wherein, The first dielectric layer (63) and the second dielectric layer (73) are both SiO2.

9. The integrated positive and negative asymmetric gate-source ESD protected trench gate MOSFET of claim 1, wherein, The first trench (31) and the second trench (32) are both located within a MOSFET termination structure. The first trench (31) and the second trench (32) are both located within a MOSFET termination structure.

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