Control method of arbitrary level output frequency converter with reduced interference and power consumption

Abstract

The invention discloses a control method for an arbitrary level output frequency converter with reduced interference and power consumption, belongs to the field of frequency converter control, and provides six bus voltage control modes for selection by means of software, which can not only realize the traditional mode of equal grid voltage input and equal voltage output; but also realize the high rated voltage output of low grid voltage input, such as 220V grid input and 380V-1140V voltage output; and realize the low rated voltage output of high grid voltage input, such as 480V grid input and 110-460V voltage output, and can output in the traditional mode without bus voltage following, and can also output in the mode of bus voltage following.

Description

Technical Field

[0001] The invention belongs to the field of frequency converter control, and in particular relates to a control method for an arbitrary level output frequency converter capable of reducing interference and power consumption. Background Art

[0002] At present, two-level voltage inverters are mostly used in the field of low-voltage inverters. The disadvantages of two-level voltage inverters are: the higher the input grid voltage, the higher the output PWM amplitude, the more serious the inverter's radiation interference, the greater the inverter's earth leakage current, and the higher the inverter's IGBT switching loss. The three-level voltage inverter used in the field of medium and high voltage inverters uses twice as many IGBT modules, which is more expensive, and the output level is half of the aforementioned two-level voltage inverter, and the radiation interference is still large in the low frequency range.

[0003] The patent application number is 201821607301.0, and the invention name is an existing application for an arbitrary level output frequency converter with reduced interference and power consumption, such as Figure 1As shown, it includes a rectifier circuit, a charging buffer circuit, a filter circuit, a three-phase inverter circuit and a main control circuit, the output end of the rectifier circuit is electrically connected to the input end of the charging buffer circuit, the output end of the filter circuit is electrically connected to the input end of the three-phase inverter circuit, and also includes a first bus voltage regulation circuit and a second bus voltage regulation circuit, the output end of the charging buffer circuit is electrically connected to the input end of the first bus voltage regulation circuit, the output end of the first bus voltage regulation circuit is electrically connected to the input end of the second bus voltage regulation circuit, the output end of the second bus voltage regulation circuit is electrically connected to the input end of the filter circuit, the input end of the first regulating drive circuit and the input end of the second regulating drive circuit are both electrically connected to the output end of the main control circuit, the output end of the first regulating drive circuit is electrically connected to the control end of the first bus voltage regulation circuit, and the output end of the second regulating drive circuit is electrically connected to the control end of the second bus voltage regulation circuit. The main control circuit implements hardware control on the first and second bus voltage regulation circuits through the first regulating drive circuit and the second regulating drive circuit respectively. The first regulating drive circuit is used to drive the single tube SK1 to turn on or off, and the second regulating drive circuit is used to drive the single tube SK2 to turn on or off. The three-phase inverter circuit is used to invert any voltage on the second capacitor C2 into a three-phase adjustable AC voltage of any level. The single tube SK1 in the first IGBT module works in the PWM working mode, and the PWM working frequency and the opening time are determined by the first regulating drive circuit. The working frequency and the opening time of the single tube SK2 in the second IGBT module are determined by the second regulating drive circuit. The first regulating drive circuit includes a reference reference circuit, a constant current source circuit, a closed-loop oscillation circuit, an isolation switch power supply circuit and an isolation IGBT drive circuit; the second regulating drive circuit includes a comparator U7, a PNP transistor T6, an NPN transistor T7, a PNP transistor T8 and a resistor Rn, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25 and a twenty-sixth resistor R26. Summary of the invention

[0004] The purpose of the present invention is to propose a control method for an arbitrary level output inverter that reduces interference and power consumption, and realizes 6 control modes of bus voltage by software. The newly added 5 control modes are used to realize high grid voltage input, low rated voltage output and voltage following and low grid voltage input, high rated voltage output and voltage following.

[0005] The present invention discloses a control method for an arbitrary level output frequency converter with reduced interference and power consumption. The arbitrary level output frequency converter comprises a rectifier unit, a charging buffer unit, a first bus voltage regulating unit, a second bus voltage regulating unit, a three-phase inverter unit, an SK1 gate drive circuit, an SK2 gate drive circuit and a control circuit. The rectifier unit is electrically connected to the charging buffer unit, the first bus voltage regulating unit, the second bus voltage regulating unit and the three-phase inverter circuit in sequence. The input ends of the SK1 gate drive circuit and the SK2 gate drive circuit are both electrically connected to the output end of the control circuit. The output end of the SK1 gate drive circuit is connected to the control end of the first bus voltage regulating unit, and the output end of the SK2 gate drive circuit is connected to the control end of the second bus voltage regulating unit. A control circuit power supply unit is formed by a third resistor R3, a first capacitor C1 and a control circuit. The cathode output end of the rectifier unit is electrically connected to the positive electrode of the first capacitor C1 and the input end of the control circuit through the third resistor R3, and the anode output end of the rectifier circuit is electrically connected to the negative electrode of the first capacitor C1 and the negative electrode N respectively.

[0006] The rectifying unit is used to rectify the AC voltage into a pulsating DC voltage;

[0007] The charging buffer unit includes a first resistor R1 and a contactor MC1, which is used to limit the current buffer charging and boosting of the second capacitor C2 in the first bus voltage regulation unit under corresponding working conditions after the control circuit works normally. After the voltage is boosted to the required voltage, the control circuit in the inverter controls the main contact of the contactor MC1 to close, and the single tube SK1 in the first IGBT module is turned on and coordinated during charging;

[0008] The SK1 gate drive circuit is used to drive the single tube SK1 in the first IGBT module to turn on or off, and determine the PWM operating frequency and turn-on time of the single tube SK1;

[0009] The SK2 gate drive circuit is used to drive the single tube SK2 in the second IGBT module to turn on or off, and determine the PWM operating frequency and turn-on time of the single tube SK2;

[0010] The three-phase inverter circuit is used to invert any voltage on the second capacitor C2 into a three-phase adjustable AC voltage of any level;

[0011] The first bus voltage regulating unit includes a first IGBT module, a DC reactor L1, a first rectifier diode D1 and a second capacitor C2, the collector of the first IGBT module is electrically connected to the output end of the charging buffer unit, the emitter of the first IGBT module is divided into two branches, one branch is electrically connected to the cathode of the first rectifier diode D1, and the other branch is connected to the first pin of the DC reactor L1, the second pin of the DC reactor L1 is divided into two branches, one branch is connected to the anode of the second rectifier diode D2 of the second bus voltage regulating unit, and the other branch is connected to the collector of the second IGBT module of the second bus voltage regulating unit, the cathode of the second rectifier diode D2 is electrically connected to the positive electrode of the second capacitor C2, and the gate of the first IGBT module is electrically connected to the output end of the SK1 gate drive circuit, and the cathode of the second capacitor C2 and the anode of the first rectifier diode D1 are both connected to the negative electrode N;

[0012] The second bus voltage regulating unit includes a second IGBT module and a second rectifier diode D2, the cathode of the second rectifier diode D2 is electrically connected to the positive electrode of the second capacitor C2 of the first bus voltage regulating unit, and the collector of the second IGBT module is divided into two branches, one is connected to the second pin of the DC reactor L1, and the other is connected to the anode of the second rectifier diode D2, the emitter of the second IGBT module is connected to the negative electrode N, and the gate of the second IGBT module is electrically connected to the output end of the SK2 gate drive circuit;

[0013] The control method comprises the following steps:

[0014] Step 101: The user sets the output target AC voltage RMS value Vmac, the stable target value UdcAP and the accuracy X2 of the bus voltage Udc2 of the second bus voltage regulating unit in the non-following control mode, the waveform peak coefficient X1 of the output voltage Vmac, the accuracy X3 of the target bus voltage Udc3 and the power supply voltage Uac in the following control mode, and selects the current bus voltage control mode;

[0015] Step 102: The user inputs an operation instruction;

[0016] Step 103: Start and enter the current bus voltage control module:

[0017] When mode 0 is selected, it is a normal voltage-bus non-following control mode: the bus voltage Udc1 of the first bus voltage regulating unit and the bus voltage Udc2 of the second bus voltage regulating unit follow the power supply voltage change, and the bus does not make any adjustment, and enters step 122;

[0018] When mode 1 is selected, which is a conventional voltage-bus following module mode: the bus voltage Udc1 of the first bus voltage regulating unit follows the change of the power supply voltage, and the bus voltage Udc2 of the second bus voltage regulating unit follows the output voltage Vmac, and the process goes to step 110;

[0019] When mode 2 is selected, it is low voltage boost-bus non-following control mode: the bus voltage Udc2 of the second bus voltage regulation unit is collected in real time, and the current bus voltage Udc2 is calculated and judged whether it has been boosted to the accuracy X2 range of the stable target value UdcAP, that is, whether it satisfies and If the boost is not completed, , then increase the duty cycle of SK2 to continuously increase the voltage until the boost requirement is met; if the boost exceeds , then reduce the SK2 on-duty ratio to continuously reduce the voltage until it is within the precision X2 range of the stable target value UdcAP; if the current bus voltage Udc2 is within the precision X2 range of the stable target value UdcAP, proceed to step 122;

[0020] When mode 3 is selected, which is a low voltage boost-bus following control mode: directly go to step 110;

[0021] When mode 4 is selected, it is high voltage step-down-bus non-following control mode: the bus voltage Udc2 of the second bus voltage regulation unit is collected in real time, and the current bus voltage Udc2 is calculated and judged whether it has been stepped down to the accuracy X2 range of the stable target value UdcAP, that is, whether it satisfies and If the voltage reduction is not completed, , then reduce the SK2 opening duty cycle to continuously reduce the voltage to meet the voltage reduction requirements; if the voltage reduction exceeds , then increase the SK2 opening duty cycle to continuously increase the voltage until the accuracy of the stable target value UdcAP is within the range of X2; if the current bus voltage Udc2 is within the range of X2 of the stable target value UdcAP, proceed to step 122;

[0022] When mode 5 is selected, which is the high voltage step-down-bus following control mode, directly enter step 110;

[0023] Step 110: Read the preset output voltage Vmac, the waveform peak coefficient X1 of the output voltage Vmac in the follower control mode, the accuracy X3 of the target bus voltage Udc3 and the power supply Uac value, and calculate the target bus voltage Udc3:

[0024] Udc3=Vmac*X1*(1±X3);

[0025] If the output voltage Vmac is less than or equal to the power supply voltage Uac, the duty cycle of SK1 is adjusted so that the current bus voltage Udc3 collected in real time is reduced to the accuracy X3 range of the target bus voltage Udc3, that is, If the output voltage Vmac is greater than the power supply voltage Uac, the duty cycle of SK2 is adjusted so that the current bus voltage Udc3 is boosted to within the accuracy X3 range of the target bus voltage Udc3, that is, ;

[0026] Step 122: Output voltage Vmac.

[0027] By adopting the technical solution of the present invention, 6 bus voltage control modes are provided for selection, which can not only realize the traditional mode of equal grid voltage input and equal voltage output; but also realize low grid voltage input and high rated voltage output, such as 220V grid input and 380V~1140V voltage output; and can realize high grid voltage input and low rated voltage output, such as 480V grid input and 110~460V voltage output, which can be output in the traditional mode without bus voltage following or in the bus voltage following mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A circuit diagram of an existing arbitrary level output frequency converter for reducing interference and power consumption;

[0029] Figure 2 The circuit principle block diagram of the arbitrary level output frequency converter for reducing interference and power consumption of the present invention;

[0030] Figure 3 It is the main process control diagram of the present invention;

[0031] Figure 4 This is a sub-flow chart of the following processing in the present invention. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or server that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0034] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or schemes. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0035] The principle of the present invention is described as follows:

[0036] (1) Bus voltage following principle:

[0037] (1-1) Example of traditional output voltage: After the 380V grid voltage of the traditional mode is input, the bus voltage of about 380Vac*1.35=513Vdc is obtained after rectification and filtering. If the AC voltage root mean square value of 220Vac is to be output, 220Vac*1.414=311Vdc is calculated. The coefficient 1.414 is the peak coefficient of the output voltage waveform, which means that if the output voltage is 220Vac, the bus voltage must be at least 311Vdc. The 380Vac input has 513Vdc, which has met the requirement of being greater than 311Vdc. However, in order to achieve a stable output of 220Vac, it is necessary to control the duty cycle to achieve the voltage regulation effect of 220Vac output. It can be simply understood as 311Vdc / 513Vdc=0.606, that is, the output of the inverter is output at a maximum duty cycle of 0.606 to obtain the voltage regulation effect of 220Vac.

[0038] (1-2) Example of bus voltage following function: Taking the required output voltage of 220Vac as an example, since only a bus voltage of 311Vdc is required, the bus voltage is reduced to 311Vdc and appropriately greater than 311Vdc by controlling the duty cycle of SK1 to meet the requirement that the bus voltage follows the required output voltage.

[0039] (2) Low voltage input and high voltage output, the bus voltage does not follow the control mode: For example, if the grid input voltage is 220Vac and the output voltage is 380Vac, it is only necessary to control the duty cycle of SK2 to boost the bus voltage Udc2 of the second bus voltage regulation unit to the set stable target value UdcAP value;

[0040] (3) Low voltage input and high voltage output, bus voltage following control mode, for example, 220Vac grid input voltage, 380Vac output voltage is required, and control needs to be implemented in sections:

[0041] In the 0~220Vac output stage, since the required bus voltage and grid voltage can meet the requirements, there is no need to boost the voltage, so SK2 does not control the action, and only SK1 adjusts the voltage according to the output voltage to meet the low voltage requirements;

[0042] In the 220~380Vac output stage, the output voltage is higher than the grid voltage and a voltage boost must be performed. Therefore, SK2 controls the voltage to boost and adjust the voltage according to the output voltage to meet the high voltage requirement.

[0043] (4) High voltage input and low voltage output, the bus voltage does not follow the control mode: For example, if the grid input voltage is 480Vac and the output voltage is 220Vac, it is only necessary to control the duty cycle of SK1 to reduce the bus voltage to the set stable target value UdcAP value;

[0044] (5) High voltage input and low voltage output, bus voltage following control mode: For example, if the grid input voltage is 480Vac, the output voltage needs to be 220Vac. SK1 can adjust the duty cycle to follow the output voltage.

[0045] The present invention discloses a control method for an arbitrary level output frequency converter with reduced interference and power consumption. The arbitrary level output frequency converter, such as Figure 2 As shown, it includes a rectifier unit, a charging buffer unit, a first bus voltage regulating unit, a second bus voltage regulating unit, a three-phase inverter unit, an SK1 gate drive circuit, an SK2 gate drive circuit and a control circuit, the rectifier unit is electrically connected to the charging buffer unit, the first bus voltage regulating unit, the second bus voltage regulating unit and the three-phase inverter circuit in sequence, the input ends of the SK1 gate drive circuit and the SK2 gate drive circuit are both electrically connected to the output end of the control circuit, the output end of the SK1 gate drive circuit is connected to the control end of the first bus voltage regulating unit, and the output end of the SK2 gate drive circuit is connected to the control end of the second bus voltage regulating unit;

[0046] The control circuit power supply unit is composed of the third resistor R3, the first capacitor C1 and the control circuit, the cathode output end of the rectifier unit is electrically connected to the positive electrode of the first capacitor C1 and the input end of the control circuit through the third resistor R3, and the anode output end of the rectifier circuit is electrically connected to the negative electrode of the first capacitor C1 and the negative electrode N(-) respectively;

[0047] The first bus voltage regulating unit includes a first IGBT module, a DC reactor L1, a first rectifier diode D1 and a second capacitor C2, the collector of the first IGBT module is electrically connected to the output end of the charging buffer unit, the emitter of the first IGBT module is divided into two branches, one branch is electrically connected to the cathode of the first rectifier diode D1, and the other branch is connected to the first pin of the DC reactor L1, the second pin of the DC reactor L1 is divided into two branches, one branch is connected to the anode of the second rectifier diode D2 of the second bus voltage regulating unit, and the other branch is connected to the collector of the second IGBT module of the second bus voltage regulating unit, the cathode of the second rectifier diode D2 is electrically connected to the positive electrode of the second capacitor C2, and the gate of the first IGBT module is electrically connected to the output end of the SK1 gate drive circuit, and the cathode of the second capacitor C2 and the anode of the first rectifier diode D1 are both connected to the negative electrode N(-);

[0048] The second bus voltage regulating unit includes a second IGBT module and a second rectifier diode D2, the cathode of the second rectifier diode D2 is electrically connected to the positive electrode of the second capacitor C2 of the first bus voltage regulating unit, and the collector of the second IGBT module is divided into two branches, one is connected to the second pin of the DC reactor L1, and the other is connected to the anode of the second rectifier diode D2, the emitter of the second IGBT module is connected to the negative electrode N(-), and the gate of the second IGBT module is electrically connected to the output end of the SK2 gate drive circuit;

[0049] The rectifying unit is used to rectify the AC voltage into a pulsating DC voltage;

[0050] The charging buffer unit includes a first resistor R1 and a contactor MC1, which is used to limit the current buffer charging and boosting of the second capacitor C2 in the first bus voltage regulation unit under corresponding working conditions after the control circuit works normally. After the voltage is boosted to the required voltage, the control circuit in the inverter controls the main contact of the contactor MC1 to close, and the single tube SK1 in the first IGBT module is turned on and coordinated during charging;

[0051] The SK1 gate drive circuit is used to drive the single tube SK1 in the first IGBT module to turn on or off, and determine the PWM operating frequency and turn-on time of the single tube SK1;

[0052] The SK2 gate drive circuit is used to drive the single tube SK2 in the second IGBT module to turn on or off, and determine the PWM operating frequency and turn-on time of the single tube SK2;

[0053] The three-phase inverter circuit is used to invert any voltage on the second capacitor C2 into a three-phase adjustable AC voltage of any level;

[0054] The control method, such as Figure 3 As shown, the following steps are included:

[0055] Step 100: Power on and start the program;

[0056] Step 101: The user sets the output target AC voltage RMS value Vmac, the stable target value UdcAP and the accuracy X2 of the bus voltage Udc2 of the second bus voltage regulating unit in the non-following control mode, the waveform peak coefficient X1 of the output voltage Vmac, the accuracy X3 of the target bus voltage Udc3 and the power supply voltage Uac in the following control mode, and selects the current bus voltage control mode;

[0057] Step 102: The user inputs an operation instruction;

[0058] Step 103: Start and enter the current bus voltage control module:

[0059] When mode 0 is selected, it is a conventional voltage-bus non-following control mode: the bus voltage Udc1 of the first bus voltage regulating unit and the bus voltage Udc2 of the second bus voltage regulating unit follow the power supply voltage change, and the bus does not make any adjustment (conventional mode), and enter step 122;

[0060] When mode 1 is selected, which is a conventional voltage-bus following module mode: the bus voltage Udc1 of the first bus voltage regulating unit follows the change of the power supply voltage, and the bus voltage Udc2 of the second bus voltage regulating unit follows the output voltage Vmac, and the process goes to step 110;

[0061] When mode 2 is selected, it is low voltage boost-bus non-following control mode: the bus voltage Udc2 of the second bus voltage regulation unit is collected in real time, and the current bus voltage Udc2 is calculated and judged whether it has been boosted to the accuracy X2 range of the stable target value UdcAP, that is, whether it satisfies and If the boost is not completed, , then increase the duty cycle of SK2 to continuously increase the voltage until the boost requirement is met; if the boost exceeds , then reduce the SK2 on-duty ratio to continuously reduce the voltage until it is within the precision X2 range of the stable target value UdcAP; if the current bus voltage Udc2 is within the precision X2 range of the stable target value UdcAP, proceed to step 122;

[0062] When mode 3 is selected, which is a low voltage boost-bus following control mode: directly go to step 110;

[0063] When mode 4 is selected, it is high voltage step-down-bus non-following control mode: the bus voltage Udc2 of the second bus voltage regulation unit is collected in real time, and the current bus voltage Udc2 is calculated and judged whether it has been stepped down to the accuracy X2 range of the stable target value UdcAP, that is, whether it satisfies and If the voltage reduction is not completed, , then reduce the SK2 opening duty cycle to continuously reduce the voltage to meet the above voltage reduction requirements; if the voltage reduction exceeds , then increase the SK2 opening duty cycle to continuously increase the voltage until the accuracy of the stable target value UdcAP is within the range of X2; if the current bus voltage Udc2 is within the range of X2 of the stable target value UdcAP, proceed to step 122;

[0064] When mode 5 is selected, which is the high voltage step-down-bus following control mode, directly enter step 110;

[0065] Step 110: Figure 4 As shown, the preset output voltage Vmac, the waveform peak coefficient X1 of the output voltage Vmac in the follower control mode, the accuracy X3 of the target bus voltage Udc3 and the power supply Uac value are read to calculate the target bus voltage Udc3:

[0066] Udc3=Vmac*X1*(1±X3);

[0067] If the output voltage Vmac is less than or equal to the power supply voltage Uac, the duty cycle of SK1 is adjusted so that the current bus voltage Udc3 collected in real time is reduced to the accuracy X3 range of the target bus voltage Udc3, that is, If the output voltage Vmac is greater than the power supply voltage Uac, the duty cycle of SK2 is adjusted so that the current bus voltage Udc3 is boosted to within the accuracy X3 range of the target bus voltage Udc3, that is, ;

[0068] Step 122: Output voltage Vmac.

[0069] The professionals should further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the present invention can be implemented by electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0070] Specifically, each step of the method embodiment in the embodiment of the present application can be completed by the hardware integrated logic circuit and / or software instructions in the processor, and the steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor, or a combination of hardware and software modules in the decoding processor. Optionally, the software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps in the above method embodiment in combination with its hardware.

[0071] When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function of the control method according to the present application is generated in whole or in part.

[0072] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A control method for an arbitrary level output frequency converter with reduced interference and power consumption, the arbitrary level output frequency converter comprising a rectifier unit, a charging buffer unit, a first bus voltage regulating unit, a second bus voltage regulating unit, a three-phase inverter unit, an SK1 gate drive circuit, an SK2 gate drive circuit and a control circuit, the rectifier unit being electrically connected to the charging buffer unit, the first bus voltage regulating unit, the second bus voltage regulating unit and the three-phase inverter circuit in sequence, the input ends of the SK1 gate drive circuit and the SK2 gate drive circuit being electrically connected to the output end of the control circuit, the output end of the SK1 gate drive circuit being connected to the control end of the first bus voltage regulating unit, and the output end of the SK2 gate drive circuit being connected to the control end of the second bus voltage regulating unit; a control circuit power supply unit is constituted by a third resistor R3, a first capacitor C1 and a control circuit, the cathode output end of the rectifier unit being electrically connected to the positive electrode of the first capacitor C1 and the input end of the control circuit respectively through the third resistor R3, and the anode output end of the rectifier circuit being electrically connected to the negative electrode of the first capacitor C1 and the negative electrode N respectively; The rectifying unit is used to rectify the AC voltage into a pulsating DC voltage; The charging buffer unit includes a first resistor R1 and a contactor MC1, which is used to limit the current buffer charging and boosting of the second capacitor C2 in the first bus voltage regulation unit under corresponding working conditions after the control circuit works normally. After the voltage is boosted to the required voltage, the control circuit in the inverter controls the main contact of the contactor MC1 to close, and the single tube SK1 in the first IGBT module is turned on and coordinated during charging; The SK1 gate drive circuit is used to drive the single tube SK1 in the first IGBT module to turn on or off, and determine the PWM operating frequency and turn-on time of the single tube SK1; The SK2 gate drive circuit is used to drive the single tube SK2 in the second IGBT module to turn on or off, and determine the PWM operating frequency and turn-on time of the single tube SK2; The three-phase inverter circuit is used to invert any voltage on the second capacitor C2 into a three-phase adjustable AC voltage of any level; Features: The first bus voltage regulating unit includes a first IGBT module, a DC reactor L1, a first rectifier diode D1 and a second capacitor C2, the collector of the first IGBT module is electrically connected to the output end of the charging buffer unit, the emitter of the first IGBT module is divided into two branches, one branch is electrically connected to the cathode of the first rectifier diode D1, and the other branch is connected to the first pin of the DC reactor L1, the second pin of the DC reactor L1 is divided into two branches, one branch is connected to the anode of the second rectifier diode D2 of the second bus voltage regulating unit, and the other branch is connected to the collector of the second IGBT module of the second bus voltage regulating unit, the cathode of the second rectifier diode D2 is electrically connected to the positive electrode of the second capacitor C2, and the gate of the first IGBT module is electrically connected to the output end of the SK1 gate drive circuit, and the cathode of the second capacitor C2 and the anode of the first rectifier diode D1 are both connected to the negative electrode N; The second bus voltage regulating unit includes a second IGBT module and a second rectifier diode D2, the cathode of the second rectifier diode D2 is electrically connected to the positive electrode of the second capacitor C2 of the first bus voltage regulating unit, and the collector of the second IGBT module is divided into two branches, one is connected to the second pin of the DC reactor L1, and the other is connected to the anode of the second rectifier diode D2, the emitter of the second IGBT module is connected to the negative electrode N, and the gate of the second IGBT module is electrically connected to the output end of the SK2 gate drive circuit; The control method comprises the following steps: Step 101: The user sets the output target AC voltage RMS value Vmac, the stable target value UdcAP and the accuracy X2 of the bus voltage Udc2 of the second bus voltage regulating unit in the non-following control mode, the waveform peak coefficient X1 of the output voltage Vmac, the accuracy X3 of the target bus voltage Udc3 and the power supply voltage Uac in the following control mode, and selects the current bus voltage control mode; Step 102: The user inputs an operation instruction; Step 103: Start and enter the current bus voltage control module: When mode 0 is selected, it is a normal voltage-bus non-following control mode: the bus voltage Udc1 of the first bus voltage regulating unit and the bus voltage Udc2 of the second bus voltage regulating unit follow the power supply voltage change, and the bus does not make any adjustment, and enters step 122; When mode 1 is selected, which is a conventional voltage-bus following module mode: the bus voltage Udc1 of the first bus voltage regulating unit follows the change of the power supply voltage, and the bus voltage Udc2 of the second bus voltage regulating unit follows the output voltage Vmac, and the process goes to step 110; When mode 2 is selected, it is low voltage boost-bus non-following control mode: the bus voltage Udc2 of the second bus voltage regulation unit is collected in real time, and the current bus voltage Udc2 is calculated and judged whether it has been boosted to the accuracy X2 range of the stable target value UdcAP, that is, whether it satisfies and If the boost is not completed, , then increase the duty cycle of SK2 to continuously increase the voltage until the boost requirement is met; if the boost exceeds , then reduce the on-duty ratio of SK2 to continuously reduce the voltage until it is within the precision X2 range of the stable target value UdcAP; if the current bus voltage Udc2 is within the precision X2 range of the stable target value UdcAP, proceed to step 122; When mode 3 is selected, which is a low voltage boost-bus following control mode: directly go to step 110; When mode 4 is selected, it is high voltage step-down-bus non-following control mode: the bus voltage Udc2 of the second bus voltage regulation unit is collected in real time, and the current bus voltage Udc2 is calculated and judged whether it has been stepped down to the accuracy X2 range of the stable target value UdcAP, that is, whether it satisfies and If the voltage reduction is not completed, , then reduce the SK2 opening duty cycle to continuously reduce the voltage to meet the voltage reduction requirements; if the voltage reduction exceeds , then increase the SK2 opening duty cycle to continuously increase the voltage until the accuracy of the stable target value UdcAP is within the range of X2; if the current bus voltage Udc2 is within the range of X2 of the stable target value UdcAP, proceed to step 122; When mode 5 is selected, which is the high voltage step-down-bus following control mode, directly enter step 110; Step 110: Read the preset output voltage Vmac, the waveform peak coefficient X1 of the output voltage Vmac in the follower control mode, the accuracy X3 of the target bus voltage Udc3 and the power supply Uac value, and calculate the target bus voltage Udc3: Udc3=Vmac*X1*(1±X3); If the output voltage Vmac is less than or equal to the power supply voltage Uac, the duty cycle of SK1 is adjusted so that the current bus voltage Udc3 collected in real time is reduced to the accuracy X3 range of the target bus voltage Udc3, that is, ; If the output voltage Vmac is greater than the power supply voltage Uac, the duty cycle of SK2 is adjusted so that the current bus voltage Udc3 is boosted to within the accuracy X3 range of the target bus voltage Udc3, that is, ; Step 122: Output voltage Vmac.

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