A dual-ring subsampling phase-locked loop clock system and electronic chip

Abstract

This application relates to the field of integrated circuit technology and discloses a dual-ring subsampling phase-locked loop clock system and electronic chip. The system includes a main loop, a frequency-locked loop, a first lock-in detector, and a second lock-in detector. The frequency-locked loop performs frequency division processing on the oscillation clock signal output by the main loop to obtain a divided clock signal and a reference clock signal, adjusting the oscillation clock signal until the frequency of the oscillation clock signal is locked and the phase difference is stable within a preset range. The main loop includes an adjustable pulse generator. In the second locking stage, the controller outputs a pulse signal with a pulse width to adjust the amplitude of the oscillation clock signal until the phase of the oscillation clock signal is locked. After phase locking, the adjustable pulse generator is controlled to reduce the generation frequency and pulse width of the pulse signal. The dual-ring subsampling phase-locked loop clock system of this application can reduce noise and power consumption.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a dual-ring subsampling phase-locked loop clock system and electronic chip. Background Technology

[0002] With the rise of the Internet of Things, the development of digital circuits is accelerating and expanding in scale. At the same time, the requirements for clock systems are becoming increasingly stringent. Phase-locked loops (PLLs) are widely used in SOCs (System on Chip). Traditional charge pump phase-locked loops (CPPLLs) benefit from high robustness, an infinitely wide frequency tracking range, and a relatively simple circuit structure, making them a commonly used PLL clock system structure in industry.

[0003] However, with ever-increasing demands for power consumption and noise reduction, simple CPPLLs can no longer meet the needs of higher-performance applications, leading to the emergence of various improved frequency lock loop (PLL) structures. Among them, the sub-sampling phase lock loop (SSPLL) modifies the traditional phase frequency detector / charge pump (PFD / CP) structure of the CPPLL by directly sampling the clock signal output by the voltage-controlled oscillator (VCO) using a reference clock signal. Because PLLs often require frequency multiplication of the clock frequency, the frequency of the reference clock signal used as the sampling clock is often lower than the VCO output clock signal used as the sampled clock; hence, this structure is called a sub-sampling PLL system.

[0004] In the implementation of subsampling phase-locked loops (PLLs), the SSPD (Self-Priming Phase-Device) charges and discharges once every reference clock cycle, generating a large current and resulting in high power consumption. Furthermore, the fixed charging and discharging time of the SSPD also leads to unnecessary power consumption. Additionally, the addition of the SSPD creates a dual-loop system, and the noise of the reference clock itself is introduced into the overall loop with each charging and discharging cycle. Therefore, power consumption and noise remain critical issues that urgently need to be addressed in the current implementation of subsampling PLLs. Summary of the Invention

[0005] In view of this, embodiments of this application provide a dual-ring subsampling phase-locked loop clock system and electronic chip, which can effectively solve the problems of high noise and high power consumption in current phase-locked loop clock systems.

[0006] In a first aspect, embodiments of this application provide a dual-ring subsampling phase-locked loop clock system, including: a main loop, a frequency-locked loop, a first lock detector, and a second lock detector;

[0007] The input of the first lock detector is used to connect to an external reference clock signal and a frequency divider clock signal, and its output first detection result is used to regulate the pulse signal in the main loop; the input of the second lock detector is connected to the reference clock signal and the frequency divider clock signal, and its output second detection result is used to control the working state of the frequency lock loop.

[0008] The input of the frequency-locked loop is connected to the reference clock signal and the oscillation clock signal output by the main loop; the frequency-locked loop is used to perform frequency division processing on the oscillation clock signal in the first locking phase to obtain the frequency-divided clock signal, and to adjust the oscillation clock signal based on the frequency-divided clock signal and the reference clock signal until the frequency of the oscillation clock signal is locked and the phase difference is stable within a preset range.

[0009] The main loop includes an adjustable pulse generator. The input of the adjustable pulse generator is connected to the reference clock signal. The adjustable pulse generator is used in the second locking phase to control the pulse width of the pulse signal according to the first detection result, so that the main loop adjusts the amplitude of the oscillating clock signal until the phase of the oscillating clock signal is locked. After the phase is locked, the adjustable pulse generator is controlled to reduce the generation frequency and pulse width of the pulse signal.

[0010] In some embodiments, the adjustable pulse generator is configured to, in a first locking phase, control the pulse width of the pulse signal to be less than or equal to a set pulse width based on the received first detection result, and in a second locking phase, control the pulse width of the pulse signal to be equal to the set pulse width based on the first detection result.

[0011] In some embodiments, during the first locking phase, the first detection result is low; the second detection result is low for a certain period of time and then changes to high; when the second detection result is low, the frequency locking loop is activated; when the second detection result changes to high, the frequency of the oscillation clock signal is locked, and the phase difference between the oscillation clock signal and the reference clock signal is stabilized within a preset range.

[0012] In some embodiments, during the second locking phase, the second detection result is high, controlling the closing of the frequency locking loop; the first detection result is low for a certain period of time and then changes to high; when the first detection result changes to the high level, the phase difference between the oscillation clock signal and the reference clock signal is locked, and after the phase difference is locked, the pulse width of the pulse signal output by the adjustable pulse generator is reduced.

[0013] In some embodiments, the adjustable pulse generator includes a pulse generation module and a pulse output module;

[0014] The pulse generation module is connected to the reference clock signal as input, and the pulse generation module processes the reference clock signal to generate an initial pulse signal;

[0015] The pulse output module includes a frequency division unit and a selection unit;

[0016] The input terminal of the frequency division unit is connected to the output terminal of the pulse generation module, and the output terminal of the frequency division unit is connected to the second input terminal of the selection unit; the frequency division unit divides the initial pulse signal to obtain a frequency-divided pulse signal.

[0017] The first input terminal of the selection unit is connected to the output terminal of the pulse generation module; when the first detection result is low, the selection unit is controlled to use the initial pulse signal as the pulse signal output by the adjustable pulse generator; when the first detection result is high, the selection unit is controlled to use the frequency-divided pulse signal as the pulse signal output by the adjustable pulse generator.

[0018] In some embodiments, the first lock detector and the second lock detector have the same structure; the first lock detector includes a sampling module, a processing module, and an output module;

[0019] The sampling module samples the reference clock signal and the frequency-divided clock signal respectively to obtain the reference edge signal and the frequency-divided edge signal;

[0020] The processing module processes the reference edge signal and the frequency division edge signal, and outputs a result signal and a control signal;

[0021] The output module processes a set number of result signals and control signals to obtain the first detection result.

[0022] In some embodiments, the sampling module includes a first flip-flop, a second flip-flop, and an AND gate;

[0023] The clock terminal of the first flip-flop is connected to the reference clock signal, and the clock terminal of the second flip-flop is connected to the frequency-divided clock signal; the input terminal of the AND gate is connected to the output terminal of the first flip-flop and the output terminal of the second flip-flop, respectively; the output terminal of the AND gate is connected to the control terminal of the first flip-flop and the control terminal of the second flip-flop.

[0024] In some embodiments, the processing module includes an inversion processing unit, a first processing unit, and a second processing unit;

[0025] The input terminal of the inverting processing unit is connected to the output terminal of the sampling module; the inverting processing unit is used to invert the reference edge signal and the frequency division edge signal.

[0026] The first processing unit is connected to the output of the sampling module and the output of the inverting processing unit; the first processing unit processes the inverted reference edge signal and the frequency-divided edge signal, and outputs the control signal;

[0027] The second processing unit is connected to the output of the inverting processing unit. The second processing unit processes the inverted reference edge signal and the frequency-divided edge signal and outputs the result signal.

[0028] In some embodiments, the first processing unit includes a processing subunit and a filtering subunit;

[0029] The processing subunit is connected to the output of the sampling module and the output of the inverting processing unit. The filtering subunit includes a filtering branch and a NAND gate. The input of the filtering branch is connected to the output of the processing subunit, and the output of the filtering branch is connected to the first input of the NAND gate. The second input of the NAND gate is connected to the output of the processing subunit. The NAND gate outputs the result signal.

[0030] Secondly, embodiments of this application provide an electronic chip, the electronic chip including a clock circuit, the clock circuit being the aforementioned dual-ring subsampling phase-locked loop clock system.

[0031] The embodiments of this application have the following beneficial effects:

[0032] When the dual-loop subsampling phase-locked loop system of this application starts working, the frequency-locked loop mainly stabilizes the frequency of the oscillation clock signal output by the main loop and initially locks the phase difference within a preset range, so that the main loop can perform fine phase adjustment in the second locking stage. After the phase adjustment is completed, the adjustable pulse generator is controlled to reduce the frequency of the generated pulse signal, thereby reducing the reference clock signal entering the loop and reducing the power consumption of the main loop. Based on the fact that the adjustable pulse generator reduces both the pulse width and the output frequency after the second locking, power consumption and noise are further reduced. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This paper shows a schematic diagram of a dual-ring subsampling phase-locked loop clock system according to an embodiment of this application;

[0035] Figure 2 A schematic diagram of the control principle of SSPD and CP-M in an embodiment of this application is shown;

[0036] Figure 3 The characteristic curves of the subsampling phase detector in an embodiment of this application are shown.

[0037] Figure 4 A schematic diagram of a circuit structure of an adjustable pulse generator in an embodiment of this application is shown;

[0038] Figure 5 A schematic diagram of a circuit structure for a lock detector according to an embodiment of this application is shown.

[0039] Explanation of key figure labels:

[0040] 10 - Pulse generation module; 20 - Pulse output module; 30 - Sampling module; 40 - Processing module; 50 - Output module; 410 - Inverting processing unit; 420 - First processing unit; 430 - Second processing unit; 421 - Processing subunit; 422 - Filtering subunit. Detailed Implementation

[0041] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0042] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0043] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0044] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0045] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0046] In the implementation of the subsampling phase-locked loop, the reference clock samples the positive-phase clock and the inverted-phase clock output by the VCO, respectively. The two voltage values ​​(V) obtained by the SSPD are... sam V sam-N ) respectively control the current magnitude of the upper / lower current source of CP (I) UP I DN When the reference clock and VCO clock finally reach phase, the current magnitudes of the upper and lower current sources are the same, the control voltage remains unchanged, and the clock frequency g... mLocking. In this case, the SSPD charges and discharges simultaneously with each reference clock cycle, resulting in a large current and high power consumption. Furthermore, the SSPD's charging and discharging time is fixed, unlike the PFD which gradually decreases as the reference clock approaches the VCO output clock, leading to unnecessary power consumption. Additionally, the addition of the SSPD to the sub-sampling PLL creates a dual-loop system, removing the N-divider from the main loop, thus preventing the PFD / CP noise from being multiplied by N^2 and reducing noise. Once the PLL frequency is locked, the SSPD still controls the CP's charging and discharging at the same frequency as the reference clock. The noise from the reference clock itself is carried into the overall loop with each charging and discharging cycle. Therefore, the noise from the clock itself becomes crucial for further noise reduction in the sub-sampling PLL. Therefore, this application proposes a dual-loop sub-sampling PLL clock system to reduce power consumption and noise.

[0047] The following describes the dual-ring subsampling phase-locked loop clock system using some specific embodiments.

[0048] Figure 1 A schematic diagram of a dual-ring subsampling phase-locked loop clock system according to an embodiment of this application is shown. Exemplarily, the dual-ring subsampling phase-locked loop clock system includes a main loop, a frequency-locked loop (FLL), a first lock detector (narrow L-DET), and a second lock detector (L-DET).

[0049] In this embodiment, the main loop includes a subsampling phase detector (SSPD), a main charge pump (CP-M), an adjustable pulse generator (T-Pulser), a low-pass filter (LPF), and a voltage-controlled oscillator (VCO). The first input of the subsampling phase detector (SSPD) is connected to an external reference clock signal (ref), the second input of the subsampling phase detector (SSPD) is connected to the output of the VCO, the output of the subsampling phase detector (SSPD) is connected to the first input of the main charge pump (CP-M), the output of the main charge pump (CP-M) is connected to the input of the low-pass filter (LPF), and the output of the low-pass filter (LPF) is connected to the input of the VCO. The input of the adjustable pulse generator (T-Pulser) is connected to the external reference clock signal (ref) and the first detection result (fiag1) output by the first lock-in detector (narrowL-DET). The output of the adjustable pulse generator (T-Pulser) is connected to the second input of the main charge pump (CP-M).

[0050] In this embodiment, the frequency-locked loop (FLL) includes a frequency and phase detector (PFD), a dead-time generator (DZ), a secondary charge pump (CP-S), and a divider. The input of the divider is connected to the output of the main loop, the output of the divider is connected to the second input of the PFD, the first input of the PFD is connected to an external reference clock signal (ref), the output of the PFD is connected to the input of the dead-time generator (DZ), the output of the DZ is connected to the input of the secondary charge pump (CP-S), and the output of the CP-S is connected to the input of the low-pass filter (LPF).

[0051] In this embodiment, the reference input terminal of the first lock-in detector (narrow L-DET) is connected to the reference clock signal ref, the clock input terminal of the first lock-in detector (narrow L-DET) is connected to the output terminal of the frequency divider (Divider), and the output terminal of the first lock-in detector (narrow L-DET) is connected to the control terminal of the adjustable pulse generator (T-Pulser). The first lock-in detector (narrow L-DET) outputs a first detection result fiag1 to regulate the pulse signal pul output by the adjustable pulse generator (T-Pulser) in the main loop. The reference input terminal of the second lock-in detector (narrow L-DET) is connected to the reference clock signal ref, the clock input terminal of the second lock-in detector (L-DET) is connected to the output terminal of the frequency divider (Divider), and the second detection result fiag2 output by the second lock-in detector (L-DET) is used to control the working state of the frequency lock-in loop (FLL), so that the frequency lock-in loop (FLL) operates before the oscillation clock signal clk output by the main loop completes frequency locking and is turned off after frequency locking is achieved and the phase is stable within ±π. Among them, the frequency divider Divider uses an N-fold frequency divider. The frequency divider Divider divides the oscillation clock signal clk according to the division ratio to obtain the divided signal.

[0052] Specifically, in the first locking phase, the first detection result flag1 is low; the second detection result flag2 is low for a certain period of time and then changes to high. When the second detection result flag2 is low, the frequency locking loop FLL is working. When the second detection result flag2 changes to high, the frequency of the oscillation clock signal clk is locked, and the phase difference between the oscillation clock signal clk and the reference clock signal ref is stable within a preset range.

[0053] Specifically, in the second locking phase, the second detection result flag2 is high, controlling the frequency locking loop FLL to be closed; the first detection result flag1 is low for a certain period of time and then changes to high. When the first detection result flag1 changes to high, the phase difference between the oscillation clock signal clk and the reference clock signal ref is locked, and after the phase difference is locked, the pulse width of the pulse signal pul output by the adjustable pulse generator T-Pulser is reduced.

[0054] In the main loop of this application, the subsampling phase detector (SSPD) samples the oscillation clock signal clk output by the voltage-controlled oscillator (VCO) using an external reference clock signal ref. The sampling method based on a reference clock signal ref whose frequency is less than the frequency of the oscillation clock signal clk is called subsampling. Figure 2 As shown, the oscillation clock signal clk includes the positive phase clock signal F. VCO and the inverted clock signal F VCO-N The subsampling phase detector (SSPD) uses the reference clock signal ref to control the positive phase clock signal F output by the voltage-controlled oscillator (VCO). VCO and the inverted clock signal F VCO-N Sampling is performed, and the subsampling phase detector (SSPD) processes the sampled positive phase clock signal F. VCO The positive phase voltage V is obtained through processing. sam The sampled inverted clock signal F VCO-N The inverting voltage V is obtained through processing. sam-N Positive phase voltage V sam The current I used to control the magnitude of the first current source in the main charge pump CP-M UP Inverting voltage V sam-N The current magnitude I used to control the second current source in the main charge pump CP-M down The pulse signal output by the adjustable pulse generator T-Pulser is used to simultaneously control the on / off state of the first and second current sources in the main charge pump CP-M. The first and second current sources of the main charge pump CP-M are turned on or off according to the pulse signal. Simultaneously, the first current source of the main charge pump CP-M draws current according to the controlled current magnitude, and the second current source injects current according to the controlled current magnitude, so that the main charge pump CP-M outputs the main current i. CP-M .

[0055] In the frequency-locked loop (FLL) of this application, the phase detector (PFD) performs phase difference and frequency discrimination on the reference clock signal ref and the divided clock signal div. When the phase difference between the reference clock signal ref and the divided clock signal div is less than or equal to a preset target, the PFD cannot identify the phase difference signal, and the FLL will enter the dead zone generated by the dead zone generator DZ, so that the frequency-locked loop does not participate in the operation. When the phase difference between the reference clock signal ref and the divided clock signal div is greater than the preset target, the PFD can identify the phase difference signal, the FLL leaves the dead zone, and the signal output by the PFD controls the secondary charge pump CP-S through the dead zone generator DZ, so that the main charge pump CP-M outputs secondary current.

[0056] The low-pass filter LPF in this application affects the main current i CP The input control voltage vc is obtained by processing the auxiliary current; based on the input control voltage vc, the voltage-controlled oscillator (VCO) outputs an oscillation clock signal clk. This application adjusts the frequency of the output oscillation clock signal by changing the control voltage vc of the VCO based on current information. Specifically, the frequency of the oscillation clock signal clk is N times that of the reference clock signal ref. Therefore, when both frequency and phase are expected to be locked simultaneously, the flip edge (passing the midpoint) of the reference clock signal ref must coincide with the flip edge (passing the midpoint) of the oscillation clock signal clk. Therefore, if a secondary lock is performed, the expected sampled positive phase voltage V... sam and the inverting voltage V sam-N They should be the same, and this is used to control the two symmetrical current sources (I) above and below. UP I DN The magnitude of the current flowing through it should also be the same. In this case, the sink current and pump current are equal, and the control voltage vc will not change. If the oscillation clock signal clk is delayed compared to the reference clock signal ref, then... Figure 2 The positive phase voltage V in sam Greater than the inverting voltage V sam-N At this time, the sink current I DN Greater than the pumping current I UP The control voltage vc will increase to increase the frequency of the oscillation clock signal clk; if the oscillation clock signal clk leads the reference clock signal ref, the control voltage vc will decrease to decrease the frequency of the oscillation clock signal clk.

[0057] In the first locking phase, the frequency-locked loop (FLL) dominates, primarily controlling the FLL to lock the frequency of the oscillation clock signal clk, stabilizing the phase difference within a preset range. At this point, the control effect of the main loop is reduced. Because the subsampling phase detector (SSPD) only has phase detection characteristics within ±π, and the phase detection gain is related to the slope of the output signal edge and the transconductance of the two current source transistors in the controlled main charge pump (CP-M), ... Figure 3 As shown, the horizontal axis represents the phase difference between the oscillation clock signal output by the voltage-controlled oscillator and the reference clock signal, and the vertical axis represents the magnitude of the current used for the charge pump output, A. cvo The amplitude of the oscillating clock signal, g m This represents the edge slope of the oscillation clock signal. Therefore, the preset range is ±π. Specifically, based on the low level output of the first detection result flag1, the pulse width of the pulse signal pul output by the adjustable pulse generator T-Pulser is less than or equal to the set pulse width, so as to reduce the control effect of the main loop, thereby making the control of the frequency lock loop (FLL) dominant; the second detection result flag2 first outputs a low level and maintains it for a certain period of time. During this period of time, the frequency lock loop (PLL) processes the output signals of the reference clock signal ref and the oscillation clock signal clk to identify the phase and frequency. When the frequency is locked and the phase difference is stable within the preset range, the second detection result flag2 outputs a high level, completing the entire process of the first locking stage.

[0058] In the second locking phase, after the second detection result flag2 maintains a high level for a certain period of time, the control frequency locking loop FLL is closed. Then, only the main loop regulates the oscillating clock signal clk whose phase difference is stable within ±π, and identifies the phase of the oscillating clock signal clk in real time, so that the main loop adjusts the amplitude of the oscillating clock signal clk until the phase of the oscillating clock signal clk is locked. After the phase is locked, the pulse width of the pulse signal output by the adjustable pulse generator T-Pulser is reduced.

[0059] The adjustable pulse generator T-Pulser in the embodiments of this application is as follows: Figure 4 As shown, the adjustable pulse generator includes a pulse generation module and a pulse output module.

[0060] The pulse generation module 10 is connected to a reference clock signal ref. The pulse generation module 10 processes the reference clock signal ref to generate an initial pulse signal. The reference clock signal ref input to the pulse generation module 10 drives the pulse generation module to start under the action of two inverters. The adjustable delay timer tunabledelay of the pulse generation module adjusts the output delay to adjust the pulse width of the initial pulse signal output by the pulse generation module 10.

[0061] In this application, the subsampling phase detector SSPD and the main charge pump CP-M sample the oscillation clock signal clk output by the voltage-controlled oscillator (VCO) in both forward and reverse directions using the reference clock signal ref. This controls the current magnitudes of the two current sources in the main charge pump CP to achieve phase-locked adjustment. Therefore, the sampling voltage is particularly important. Each switching of the sampling switch introduces transient and thermal noise, so a pulse to control the main charge pump CP-M can only be activated after a certain period of time following the open-loop switching. Therefore, the pulse signal pul generated by the pulse generator T-Pulser needs to be far from the rising and falling edges of the sampling signal. That is, the pulse generation module 10 achieves a short delay by driving the reference clock signal ref through two stages of inverters, ensuring that the pulse signal generated only at the falling edge of the reference clock signal does not coincide with the falling edge, giving the subsampling phase detector sufficient sampling time. This avoids the sampling noise caused by the pulse signal coinciding with the edge of the reference clock signal being directly introduced into the main charge pump and affecting the output frequency, thus ensuring that the pulse signal pul generated by the pulse generator T-Pulser is far from the edge of the sampled oscillation clock signal clk.

[0062] The pulse output module 20 includes a frequency division unit and a selection unit. The input of the frequency division unit is connected to the output of the pulse generation module 10, and the output of the frequency division unit is connected to the second input of the selection unit. The frequency division unit divides the initial pulse signal to obtain a frequency-divided pulse signal. The first input of the selection unit is connected to the output of the pulse generation module 10. When the first detection result flag1 is low, the selection unit is controlled to use the initial pulse signal as the pulse signal pul output by the adjustable pulse generator T-Pulser. When the first detection result flag1 is high, the selection unit is controlled to use the frequency-divided pulse signal as the pulse signal pul output by the adjustable pulse generator T-Pulser.

[0063] In some implementations, the frequency division unit uses a two-divider. As other implementations, a three-divider or a four-divider can also be used. This application does not limit the selection of the frequency division unit, as long as it can meet the actual frequency division needs. The selection unit in this application uses a two-to-one selector.

[0064] The adjustable pulse generator of this application is used in the first locking phase to control the pulse width of the output pulse signal pul to be less than or equal to a set pulse width according to the received first detection result flag1, at which time the first detection result is low level; and in the second locking phase, to control the pulse width of the output pulse signal pul to be equal to the set pulse width according to the low level of the first detection result flag1.

[0065] In a preferred embodiment, during the first locking phase, under the adjustment of the adjustable delay, the pulse width of the pulse signal pul output by the adjustable pulse generator T-Pulser is minimized. At this time, the first detection result fiag1 output by the first locking detector narrow L-DET is low, and the pulse output module 20 uses the initial pulse signal output by the pulse generation module 10 as the pulse signal pul output by the adjustable pulse generator T-Pulser. During the second locking phase, under the adjustment of the adjustable delay, the pulse signal pul output by the adjustable pulse generator T-Pulser recovers to the set pulse width. At this time, the pulse width of the first locking detector narrow L-DET is minimized. The first detection result fiag1 output by L-DET is still low. Furthermore, the pulse output module 20 uses the initial pulse signal output by the pulse generation module 10 as the pulse signal pul output by the adjustable pulse generator T-Pulser. Under the control of the main loop, the oscillation clock signal clk achieves phase locking. After phase locking is completed, the adjustable delay unit tunabledelay is controlled so that the pulse signal pul output by the adjustable pulse generator T-Pulser is reduced from the set pulse width and generates a pulse signal at half the frequency of the reference clock, thereby reducing the power consumption of the dual-ring subsampling phase-locked loop clock system.

[0066] In some implementations, the first locking detector and the second locking detector have the same structure; taking the first locking detector as an example, the structure of the locking detector will be described.

[0067] like Figure 5 As shown, the first lock detector includes a sampling module 30, a processing module 40, and an output module 50. The sampling module 30 samples the reference clock signal ref and the frequency-divided clock signal div to obtain the reference edge signal and the frequency-divided edge signal, respectively. The processing module 40 processes the reference edge signal and the frequency-divided edge signal to output the result signal and the control signal. The output module 50 processes a set number of result signals and control signals to obtain the first detection result.

[0068] In some embodiments, the sampling module 30 includes a first flip-flop, a second flip-flop, and an AND gate Y1. The clock input of the first flip-flop is connected to a reference clock signal ref, and the clock input of the second flip-flop is connected to a frequency-divided clock signal div. The input of the AND gate Y1 is connected to the outputs of the first and second flip-flops, respectively. The output of the AND gate Y1 is connected to the control inputs of the first and second flip-flops. Both the first and second flip-flops are D flip-flops. After the reference clock signal ref and the frequency-divided clock signal div are triggered sequentially at their rising edges, the outputs of the two flip-flops are fed back to the two flip-flops via the AND gate Y1, thereby enabling the sampling of the reference edge signal of the reference clock signal ref and the frequency-divided edge signal of the frequency-divided clock signal div, thus obtaining the phase difference between the reference clock signal ref and the frequency-divided clock signal div. The feedback of the outputs of the two flip-flops to the two flip-flops via the AND gate Y1 resets the two flip-flops, and each reset causes the flip-flops to sample once.

[0069] In some embodiments, the processing module 40 includes an inverting processing unit 410, a first processing unit 420, and a second processing unit 430. The input of the inverting processing unit 410 is connected to the output of the sampling module 30. The inverting processing unit 410 is used to invert the reference edge signal and the frequency division edge signal. The input of the first processing unit 420 is connected to the output of the sampling module 30 and the output of the inverting processing unit 410. The first processing unit 420 processes the inverted reference edge signal and the frequency division edge signal and outputs a control signal. The input of the second processing unit 430 is connected to the output of the inverting processing unit 410. The second processing unit 430 processes the inverted reference edge signal and the frequency division edge signal and outputs a result signal.

[0070] In some embodiments, the first processing unit 420 includes a processing subunit 421 and a filtering subunit 422; the processing subunit 421 is connected to the output of the sampling module 30 and the output of the inverting processing unit 410; the filtering subunit 422 includes a filtering branch and a NAND gate; the input of the filtering branch is connected to the output of the processing subunit 421; the output of the filtering branch is connected to the first input of the NAND gate YN1; the second input of the NAND gate YN1 is connected to the output of the processing subunit 421; and the NAND gate YN1 outputs a result signal.

[0071] In some embodiments, the processing subunit 421 includes three NAND gates. The first input of NAND gate YN2 is connected to the first output of the inverting processing unit 410, the second input of NAND gate YN2 is connected to the first output of the sampling module 30, the first input of NAND gate YN3 is connected to the first output of the sampling module 30, the second input of NAND gate YN3 is connected to the second output of the inverting processing unit 410, the first input of NAND gate YN4 is connected to the output of NAND gate YN2, the second input of NAND gate YN4 is connected to the output of NAND gate YN3, and the output of NAND gate YN4 is the output of the processing subunit 421. After the reference edge signal and the frequency-divided edge signal output by the sampling module 30 are processed by the inverting processing unit and the processing subunit, an intermediate pulse signal with the same phase difference is obtained.

[0072] In some embodiments, the filtering branch of the filtering subunit 422 includes two inverters and an adjustable capacitor to filter out glitches in the intermediate pulse signal output by the processing subunit 421. The glitches filtered by the adjustable capacitor are adjusted to the jitter range of the desired output clock to minimize interference signals or noise in the resulting signal. When glitches smaller than the jitter range are filtered out, the output signal is high.

[0073] Other implementation methods can also be adopted, and other filtering structures can be used. This application does not specifically limit the structure of the filtering subunit, as long as it can filter out the glitch in the intermediate pulse signal output by the processing subunit 421.

[0074] In some embodiments, the second processing unit 430 includes an AND gate, with its first input connected to the first output of the inverting processing unit 410 and its second input connected to the second output of the inverting processing unit 410. Alternatively, other components may be included, as long as they can output a phase difference.

[0075] In some embodiments, the output module 50 includes multiple flip-flops, NAND gates, and inverters; specifically, the outputs of 16 D flip-flops connected in series are all connected to the inputs of the NAND gates, the outputs of the NAND gates are connected in series to one D flip-flop and one inverter, and the inverter outputs the detection result. During the detection process, the lock detector resets the two flip-flops multiple times during a rising edge signal. The sampling module 30 then samples multiple times, resulting in multiple result signals and control signals being generated by the output module. The result signal after glitch filtering is high-level. When the first result signal is output, it goes high through the first D flip-flop connected in series (high level). When the second result signal is output, the first result signal is transmitted to the second D flip-flop connected in series, and the second result signal goes high through the first D flip-flop connected in series. When the third result signal is output, the first result signal is transmitted to the third D flip-flop connected in series, and the second result signal goes high through the second D flip-flop connected in series, and the third result signal goes high through the first D flip-flop connected in series, and so on, until all 16 sequentially connected D flip-flops output high levels and are transmitted to the input of the NAND gate. When the first detection result flag1 output by the output module is high, it indicates that phase locking has occurred in the corresponding main loop.

[0076] The dual-ring subsampling phase-locked loop clock system of this application starts working after power-on, with a reference clock signal ref input before power-on. Since it's just starting, the control voltage vc of the voltage-controlled oscillator (VCO) is at its initial value, so the VCO doesn't output an oscillation clock signal clk. At this time, the phase-frequency detector (PFD) detects that the oscillation clock signal clk lags behind the reference clock signal ref. It then injects current into the control voltage VC through the secondary charge pump CP-S in the frequency-locked loop (FLL). Because the oscillation clock signal clk differs significantly from the reference clock signal ref at this point, and the dead-time generator DZ has little impact on the frequency-locked loop (FLL), and the main loop is also operating simultaneously, the subsampling phase detector SSPD... The phase detection range is limited, so the output signal of the secondary charge pump CP-S is incorrect at this time, which is noise for the system. Therefore, in the first locking stage, by adjusting the adjustable delay of the adjustable pulse generator T-Pulser, the pulse width of the pulse signal pul output by the adjustable pulse generator T-Pulser is set to the minimum, so that the actual current of the main charge pump CP-M (tail current) is much smaller than the current of the secondary charge pump CP-S (tail current). Therefore, the frequency locking loop FLL is dominant, and the other processes in this stage are consistent with the working process of the traditional CPPLL. Once the frequency of the clock signal to be oscillated is basically locked, it enters the ±π phase-locking stage. At this time, the dead zone generator DZ artificially creates a dead zone in the frequency-locking loop FLL. After entering the dead zone, the secondary charge pump CP-S will not inject or extract current into the control voltage VC of the voltage-controlled oscillator VCO. At the same time, the ±π phase has verified the phase detection range of the sub-sampling phase detector SSPD in the main loop. Therefore, at the end of the first locking stage, the frequency-locking loop no longer participates in locking, and the main loop is responsible for the subsequent phase locking.

[0077] After the first locking phase, the frequency-locked loop (FLL) completes frequency locking and phase stabilization within the ±π range. The oscillation clock signal output by the voltage-controlled oscillator (VCO) completes one locking operation. The phase noise of the oscillation clock signal clk is the main noise. Because the locking margin of the second locking detector is greater than that of the first locking detector, the expected phase noise will enter the first-order locking but not the second-order locking. At this time, the first locking detector sends a first-order locking signal, i.e., outputs a high level. Then, the pulse width of the pulse signal pul output by the adjustable pulse generator T-Pulser is controlled to return to positive rubbing. After a certain period of time, the frequency-locked loop (FLL) is controlled to close. At this time, only the pulse generator of the main loop performs phase detection on the oscillation clock signal clk. Figure 3The characteristic curve of the SSPD shown shows that the gain of the subsampling phase detector (SSPD) is proportional to the edge slope of the voltage-controlled oscillator (VCO) output signal, which is much greater than that of the frequency-phase detector (PFD). Therefore, it has a much greater gain than the frequency-phase detector (PFD). Even when the current of the main charge pump (CP-M) is small, it can still significantly suppress the phase noise generated by the main charge pump (CP-M), thereby achieving both low power consumption and low jitter. At the same time, there is no N divider in the main loop, so the phase noise generated by the main charge pump (CP-M) will not be multiplied by N^2, which also greatly reduces the noise of the output clock.

[0078] During the secondary locking process, the phase noise of the output oscillation clock signal clk gradually decreases, eventually triggering the fine second locking detector and triggering the second locking stage. After the secondary locking, the phase noise of the oscillation clock signal clk output by the voltage-controlled oscillator (VCO) is already very small, which will reduce the pulse generation frequency of the pulse generator by half, thereby reducing power consumption and noise introduced by each sampling, and avoiding the introduction of unexpected noise by frequent adjustments.

[0079] It should be noted that, since the possibility of strong transient interference in the environment cannot be ruled out, if the interference enters the control level, it will cause a loss of lock. Therefore, the second lock detector L-DET needs to be turned on at all times when the dual-ring subsampling phase-locked loop clock system is working. If a loss of lock occurs for any reason, the frequency lock loop FLL will be reconnected and replace the main loop as the dominant loop, and the frequency lock loop FLL will be locked again.

[0080] Compared to the traditional CPPLL structure, the clock system of the dual-ring subsampling phase-locked loop in this application can eliminate the noise amplification of the frequency divider and the noise of the loop itself. Compared with the traditional subsampling phase-locked loop structure, it can optimize the over-design in the prior art by reducing the width and frequency of the generated pulse after the fine second locking, thereby further reducing power consumption and noise. At the same time, this application also has the advantages of on-chip integration, no need for additional components, small power consumption and area, making it very suitable for application on existing microcontrollers.

[0081] This application also provides an electronic chip, exemplary of which includes a clock circuit, wherein the clock circuit generates a stable clock signal for the electronic chip; the clock circuit is the aforementioned dual-ring subsampling phase-locked loop clock system.

[0082] It is understood that the clock circuit of this embodiment corresponds to the dual-ring subsampling phase-locked loop clock system of the above embodiment. The options in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0083] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0084] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0085] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A dual-ring subsampling phase-locked loop clock system, characterized in that, include: Main loop, frequency-locked loop, first lockout detector, and second lockout detector; The input of the first lock detector is used to connect to an external reference clock signal and a frequency-divided clock signal, and its output first detection result is used to regulate the pulse signal in the main loop; The input of the second locking detector is connected to the reference clock signal and the frequency division clock signal, and its output second detection result is used to control the working state of the frequency locking loop; The input of the frequency-locked loop is connected to the reference clock signal and the oscillation clock signal output by the main loop; The frequency-locked loop is used to divide the oscillating clock signal to obtain the divided clock signal in the first locking phase, and to adjust the oscillating clock signal based on the divided clock signal and the reference clock signal until the frequency of the oscillating clock signal is locked and the phase difference is stable within a preset range. The main loop includes an adjustable pulse generator. The input of the adjustable pulse generator is connected to the reference clock signal. The adjustable pulse generator is used in the second locking phase to control the pulse width of the pulse signal according to the first detection result, so that the main loop adjusts the amplitude of the oscillating clock signal until the phase of the oscillating clock signal is locked. After the phase is locked, the adjustable pulse generator is controlled to reduce the generation frequency and pulse width of the pulse signal.

2. The dual-ring subsampling phase-locked loop clock system according to claim 1, characterized in that, The adjustable pulse generator is used to control the pulse width of the pulse signal to be less than or equal to a set pulse width according to the received first detection result in a first locking phase, and to control the pulse width of the pulse signal to be equal to the set pulse width according to the first detection result in a second locking phase.

3. The dual-ring subsampling phase-locked loop clock system according to claim 1, characterized in that, In the first locking phase, the first detection result is low level; the second detection result is low level for a certain period of time and then changes to high level. When the second detection result is low level, the frequency locking loop is working. When the second detection result changes to the high level, the frequency of the oscillation clock signal is locked, and the phase difference between the oscillation clock signal and the reference clock signal is stable within a preset range.

4. The dual-ring subsampling phase-locked loop clock system according to claim 1, characterized in that, During the second locking phase, the second detection result is high, controlling the closing of the frequency locking loop; the first detection result is low and then changes to high after a certain period of time. When the first detection result changes to the high level, the phase difference between the oscillation clock signal and the reference clock signal is locked, and after the phase difference is locked, the pulse width of the pulse signal output by the adjustable pulse generator is reduced.

5. The dual-ring subsampling phase-locked loop clock system according to claim 1, characterized in that, The adjustable pulse generator includes a pulse generation module and a pulse output module; The pulse generation module is connected to the reference clock signal as input, and the pulse generation module processes the reference clock signal to generate an initial pulse signal; The pulse output module includes a frequency division unit and a selection unit; The input terminal of the frequency division unit is connected to the output terminal of the pulse generation module, and the output terminal of the frequency division unit is connected to the second input terminal of the selection unit; the frequency division unit divides the initial pulse signal to obtain a frequency-divided pulse signal. The first input terminal of the selection unit is connected to the output terminal of the pulse generation module; When the first detection result is low, the selection unit is controlled to use the initial pulse signal as the pulse signal output by the adjustable pulse generator. When the first detection result is high, the selection unit is controlled to use the frequency division pulse signal as the pulse signal output by the adjustable pulse generator.

6. The dual-ring subsampling phase-locked loop clock system according to claim 5, characterized in that, The first lock detector and the second lock detector have the same structure; the first lock detector includes a sampling module, a processing module, and an output module. The sampling module samples the reference clock signal and the frequency-divided clock signal respectively to obtain the reference edge signal and the frequency-divided edge signal; The processing module processes the reference edge signal and the frequency division edge signal, and outputs a result signal and a control signal. The output module processes a set number of result signals and control signals to obtain the first detection result.

7. The dual-ring subsampling phase-locked loop clock system according to claim 6, characterized in that, The sampling module includes a first flip-flop, a second flip-flop, and an AND gate; The clock terminal of the first flip-flop is connected to the reference clock signal, and the clock terminal of the second flip-flop is connected to the frequency-divided clock signal; the input terminal of the AND gate is connected to the output terminal of the first flip-flop and the output terminal of the second flip-flop, respectively; the output terminal of the AND gate is connected to the control terminal of the first flip-flop and the control terminal of the second flip-flop.

8. The dual-ring subsampling phase-locked loop clock system according to claim 6, characterized in that, The processing module includes an inversion processing unit, a first processing unit, and a second processing unit; The input terminal of the inverting processing unit is connected to the output terminal of the sampling module; the inverting processing unit is used to invert the reference edge signal and the frequency division edge signal. The first processing unit is connected to the output of the sampling module and the output of the inverting processing unit; the first processing unit processes the inverted reference edge signal and the frequency-divided edge signal, and outputs the control signal. The second processing unit is connected to the output of the inverting processing unit. The second processing unit processes the inverted reference edge signal and the frequency-divided edge signal and outputs the result signal.

9. The dual-ring subsampling phase-locked loop clock system according to claim 8, characterized in that, The first processing unit includes a processing subunit and a filtering subunit; The processing subunit is connected to the output of the sampling module and the output of the inverting processing unit. The filtering subunit includes a filtering branch and a NAND gate. The input of the filtering branch is connected to the output of the processing subunit, and the output of the filtering branch is connected to the first input of the NAND gate. The second input of the NAND gate is connected to the output of the processing subunit. The NAND gate outputs the result signal.

10. An electronic chip, characterized in that, The electronic chip includes a clock circuit, which is a dual-ring subsampling phase-locked loop clock system as described in any one of claims 1-9.

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