A semiconductor structure and a preparation method thereof, a memory

Abstract

Provided are a semiconductor structure and a preparation method thereof, and a memory, relating to the technical field of semiconductors, and used to solve the problem of complex column selector wiring. The semiconductor structure comprises: a plurality of active regions arranged in rows and columns, wherein each row of active regions is arranged along a first direction; a gate structure comprising a sub-gate structure, the sub-gate structure being arranged across a column of active regions; the sub-gate structure comprising a gate portion covering an active region and a connecting portion electrically connecting adjacent gate portions; and wherein, in the same sub-gate structure, adjacent gate portions are offset in the first direction. After the gate portions in the gate structure are offset, the layout of the gate structure is changed, so that the spacing between adjacent active regions is increased, thereby providing space for the subsequent setting of the lead-out line.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a preparation method thereof, and a memory. Background Art

[0002] The sense amplifier circuit is a key component in the read and write operations of dynamic random access memory (DRAM). Its function is to amplify the signal stored in the internal memory cell to the external circuit through the sense amplifier circuit. The column selector controls the switch connecting the bit-line sense amplifier (BLSA) and the local sense amplifier input / output (I / O). When the column selector is turned on, the storage signal amplified by the BLSA can be read out to the local input / output line (I / O) output, or the signal from the local I / O can be written to the bit line for storage within the memory cell. It is important to note that as integrated circuits continue to miniaturize, the feature size of the column selector is also decreasing, which in turn leads to the increasing difficulty of its fabrication process. Summary of the Invention

[0003] An embodiment of the present disclosure provides a semiconductor structure, comprising:

[0004] A plurality of active regions arranged in rows and columns, wherein the active regions in each row are arranged along a first direction;

[0005] The gate structure includes a sub-gate structure, wherein the sub-gate structure is arranged across a column of the active areas; the sub-gate structure includes a gate portion covering the active areas and a connecting portion electrically connecting adjacent gate portions; wherein,

[0006] In the same sub-gate structure, adjacent gate portions are offset in the first direction.

[0007] In some embodiments, the gate portion extends along a second direction, an extending direction of the connecting portion intersects with the second direction, and the second direction is perpendicular to the first direction.

[0008] In some embodiments, the sub-gate structure is a straight line, and an extension direction intersects with a second direction, and the second direction is perpendicular to the first direction.

[0009] In some embodiments, the gate structure further includes one or more bridge portions, and the bridge portions electrically connect adjacent sub-gate structures.

[0010] In some embodiments, the bridge portion electrically connects ends of adjacent sub-gate structures.

[0011] In some embodiments, the bridge portion electrically connects middle portions of adjacent sub-gate structures.

[0012] In some embodiments, the gate structure further includes a lead-out portion, one end of which is electrically connected to the sub-gate structure and / or the bridge portion.

[0013] In some embodiments, the active region is in the shape of a rectangle, a trapezoid, or a parallelogram.

[0014] In some embodiments, a line connecting the centers of the four adjacent active regions is in the shape of a trapezoid or a parallelogram.

[0015] In some embodiments, the active region includes a source region and a drain region, and the semiconductor structure further includes a plurality of first conductive lines electrically connecting the source region or the drain region, wherein the first conductive lines are straight lines and parallel to each other.

[0016] In some embodiments, the semiconductor structure further includes a plurality of second conductive lines, wherein the second conductive lines are electrically connected to the gate structure, wherein the second conductive lines are straight lines and parallel to the first conductive lines.

[0017] In some embodiments, the second conductive line is a column selection line, and the column selection line is externally connected to a control signal.

[0018] In some embodiments, the semiconductor structure includes a plurality of the gate structures, and for two adjacent gate structures, one of the gate structures is rotated 160-200 degrees relative to the other.

[0019] In some embodiments, the semiconductor structure includes a plurality of the gate structures, and two adjacent gate structures can overlap with each other by translation.

[0020] An embodiment of the present disclosure further provides a memory, comprising: a semiconductor structure as described in any one of the above items.

[0021] The present disclosure also provides a method for preparing a semiconductor structure, including:

[0022] forming a plurality of active regions arranged in rows and columns, wherein the active regions in each row are arranged along a first direction;

[0023] forming a gate material layer, and etching the gate material layer to form a gate structure, wherein the gate structure includes a sub-gate structure, the sub-gate structure being arranged across a column of the active regions, and the sub-gate structure including a gate portion covering the active regions and a connecting portion electrically connecting adjacent gate portions; wherein,

[0024] In the same sub-gate structure, adjacent gate portions are offset in the first direction.

[0025] In some embodiments, the active region further includes a source region and a drain region, and the method further includes:

[0026] A contact plug is formed, wherein the contact plug is electrically connected to the source region, the drain region or the gate structure.

[0027] In some embodiments, the method further comprises:

[0028] forming a conductive material layer;

[0029] The conductive material layer is etched to form a first conductive line and a second conductive line, wherein the first conductive line is electrically connected to the source region or the drain region, and the second conductive line is connected to the gate structure, wherein the first conductive line and the second conductive line are straight lines and parallel to each other.

[0030] The embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same. By offsetting the gate portion in the gate structure, the layout of the gate structure is changed, and the corresponding spacing between adjacent active areas is increased, thereby providing space for setting up the lead-out lines without the need for complex bending and winding. This effectively overcomes the problem of difficult wiring of traditional column selector circuits and reduces the difficulty of preparing the column selector.

[0031] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] Figure 1-9 A top view of a semiconductor structure provided in an embodiment of the present disclosure;

[0034] Figure 10 A flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0035] Figure 11 A circuit diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0036] Figure 12-16 FIG is a schematic diagram of the structure of a semiconductor structure during the manufacturing process according to an embodiment of the present disclosure, wherein Figure 12 For the Figure 1 Schematic diagram of the vertical cross section of line aa' in the figure. Figure 13-16FIG. 1 is a top view of a semiconductor structure during the manufacturing process according to an embodiment of the present disclosure.

[0037] Active region 100, source region 101, drain region 102, first conductive line 131, column selector 115;

[0038] The second conductive line 132 , the gate structure 110 , the sub-gate structure 111 , the gate portion 112 , and the connecting portion 113 ;

[0039] Bridge portion 121 , lead portion 122 , contact plug 142 , source contact plug 1421 ;

[0040] Drain contact plug 1422 , CSL contact plug 1423 , conductive material layer 143 , first surface 151 ;

[0041] Second surface 152 , third surface 153 , fourth surface 154 , gate dielectric layer 161 , barrier layer 162 ;

[0042] Sidewall spacers 163, second dielectric layer 164, contact hole 165, diffusion barrier layer 166, third dielectric layer 167;

[0043] A first dielectric layer 168 . DETAILED DESCRIPTION

[0044] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0045] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0046] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0047] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0048] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0049] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] The column selector is the main part of the dynamic random access memory (DRAM) read and write operation, which is composed of multiple NMOS transistors, as shown in the attached figure. Figure 11 As shown, during the read operation, the column selector 115 transmits the storage signal amplified by the sense amplifier to the external entity through the input / output line (I / O). During the write operation, the column selector 115 provides the externally received signal to the sense amplifier, and then writes the signal to the bit line BL for storage by the storage unit, and the column select line (CSL) is responsible for transmitting the control signal. However, as integrated circuits continue to develop in the direction of miniaturization, the integration and electrical performance of the column selector must also keep pace with the times. The problem that follows is that the spacing between the active areas is reduced, which reduces the wiring space of the bit lines, I / O lines and column select lines in the column selector, and the mutual influence between the wires increases the difficulty of wiring the bit lines, I / O lines and column select lines, complicates the winding, and increases the difficulty of the column selector manufacturing process. Therefore, there is an urgent need for a solution that can increase the wiring space of the column selector and reduce the difficulty of the column selector manufacturing process.

[0051] Based on this, the present disclosure provides a semiconductor structure, Figure 1-8 Schematic diagrams of semiconductor structures provided by Embodiments 1 to 8 of the present disclosure respectively.

[0052] Specifically, as attached Figure 1-8 As shown, the semiconductor structure includes:

[0053] A plurality of active regions 100 arranged in rows and columns, wherein the active regions 100 in each row are arranged along a first direction;

[0054] The gate structure 110 includes a sub-gate structure 111 , which is arranged across a column of active regions 100 ; the sub-gate structure 111 includes a gate portion 112 covering the active region 100 and a connecting portion 113 electrically connecting adjacent gate portions 112 ;

[0055] In the same sub-gate structure 111 , adjacent gate portions 112 are offset in the first direction.

[0056] In the embodiment of the present disclosure, due to the offset between adjacent gate portions 112 in the same sub-gate structure 111, a special gate structure 110 layout is formed. At the same time, the active area 100 is offset by a certain distance along with the gate portion 112, so that the first conductive wire 131 and the second conductive wire 132 in each column selector can borrow the offset space from each other without the need for complicated winding, thereby effectively increasing the wiring space of the column selector and reducing the difficulty of preparing the column selector.

[0057] Figure 12 For the Figure 1 The vertical cross-section diagram of the aa' line in the figure is shown in the attached figure. Figure 12As shown, the semiconductor structure further includes a substrate (not shown in the figure), and the plurality of active regions 100 are located on the substrate. In order to clearly illustrate the contents of the present invention, the attached Figure 1-9 The substrate is not shown. The substrate includes, but is not limited to, a single semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (e.g., a silicon-germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0058] Each active region 100 includes a source region 101 and a drain region 102. The active region 100 may be doped with P-type ions, while the source region 101 and the drain region 102 may be doped with N-type ions. The active region 100 and the gate portion 112 located on the active region 100 form a complete N-type transistor. In some embodiments, the active region may also be doped with N-type ions, while the source region 101 and the drain region 102 may be doped with P-type ions. The active region 100 and the gate portion 112 located on the active region 100 form a complete P-type transistor. The material of the gate portion 112 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.

[0059] In actual operation, the offset distance D between adjacent gate portions 112 in the same sub-gate structure 111 ranges from 5 to 15 nm, including endpoint values. In some embodiments, it can be 8 nm, 10 nm, 13 nm, etc. Compared with the offset distance of 0 between adjacent gate portions 112 in the sub-gate structure 111 in traditional semiconductor devices, the offset distance between adjacent gate portions 112 in the sub-gate structure 111 in the embodiment of the present disclosure is 5 to 15 nm, and the parasitic capacitance between the gate portions 112 is smaller and the space utilization is higher. The offset distance D here is the component of the distance between the center points of adjacent gate portions 112 in the first direction. It should be understood that the active area 100 covered by the adjacent gate portions 112 in the same sub-gate structure 111 is also offset in the first direction, and the offset of the active area 100 is equal to D.

[0060] Attachment Figure 1-4Schematic diagrams of semiconductor structures provided for Embodiments 1 to 4 of the present disclosure respectively show that, in Embodiments 1 to 4, the gate portion 112 extends along the second direction. Accordingly, since the gate portion 112 extends along the second direction, which is perpendicular to the first direction, adjacent gate portions 112 on the same sub-gate structure 111 are offset, and therefore the extension direction of the connecting portion 113 must intersect with the second direction to achieve connection between adjacent gate portions 112. In short, the extension direction of the connecting portion 113 forms an angle with the second direction, and the magnitude of the angle can vary with the offset distance D of the gate portion 112. Therefore, no specific limitation is imposed on the angle formed between the connecting portion 113 and the second direction, as long as the connection between adjacent gate portions 112 on the same sub-gate structure 111 can be achieved.

[0061] See the attached Figure 1-2 In both the first and second embodiments, the spacing between the gate portions 112 covering the first row of active areas 100 in the same sub-gate structure 110 is denoted as H1, and the spacing between the gate portions 112 covering the second row of active areas 100 is denoted as H2, where H1 is not equal to H2. In this case, the distance between some gate portions 112 is greater, effectively reducing the parasitic capacitance generated between adjacent gate portions 112 and improving the stability of the semiconductor device. Furthermore, the greater distance between some gate portions 112 increases the space for routing the output lines in the column selector, reducing the difficulty in manufacturing the column selector.

[0062] Specifically, in the same gate structure 110, the spacing H1 between the gate portions 112 covering the first row of active regions 100 ranges from 95 to 135 nm, and the spacing H2 between the gate portions 112 covering the second row of active regions 100 ranges from 130 to 170 nm. In some embodiments, H1 is 115 nm and H2 is 150 nm.

[0063] See the attached Figure 3-4 Unlike the first and second embodiments, in the third and fourth embodiments, in the same gate structure 110, the spacing between the gate portions 112 covering the first row of active regions 100 is denoted as H1, and the spacing between the gate portions 112 covering the second row of active regions 100 is denoted as H2, where H1 is equal to H2. By setting the size of H1 equal to H2, space can be more fully utilized, thereby improving the space utilization rate of the semiconductor structure.

[0064] Attachment Figure 5-8Schematic diagrams of semiconductor structures provided for Embodiments 5 to 8 of the present disclosure show that, unlike Embodiments 1 to 4, in Embodiments 5 to 8, the sub-gate structure 111 is a straight line, and its extension direction intersects with the second direction. It should be understood that since the sub-gate structure 111 extends in a direction intersecting with the second direction, adjacent gate portions 112 can still achieve a certain offset D in the first direction. In this solution, since the connecting portion 113 and the gate portion 112 extend in a straight line in the same direction, the sub-gate structure 111 in a straight line form is easier to prepare compared to Embodiments 1 to 4.

[0065] See the attached Figure 1-8 As can be seen, the gate structure 110 further includes one or more bridge portions 121, which are located between two adjacent sub-gate structures 111 and are used to electrically connect the adjacent sub-gate structures 111. The presence of the bridge portion 121 not only facilitates the subsequent extraction of the gate structure 110 and the connection between the gate structure 110 and the extraction circuit, but also enables the gate structure 110 to control multiple transistors, thereby accelerating data transmission.

[0066] In the second to eighth embodiments, as shown in the attached Figure 2-8 As shown, the bridge portion 121 electrically connects the ends of two adjacent sub-gate structures 111. The bridge portion 121 is located at the end of the sub-gate structure 111, which can facilitate the subsequent lead-out of the gate structure 110, facilitate the setting of the lead-out line, reduce the length of the lead-out line, and thus achieve faster data transmission speed while reducing costs. Here, there is no limit on the number of bridge portions 121 in a gate structure 110. For example, as shown in the attached figure, Figure 2 As shown, the bridge portion 121 can be one, or as shown in the attached Figure 3-8 As shown, two or more bridge portions are provided. Compared with one bridge portion 121, multiple bridge portions 121 ensure the connection effect between adjacent sub-gate structures 111, avoid circuit failure caused by damage to a single connector, and thus improve the stability of the semiconductor device. When the number of bridge portions 121 is one, the bridge portions 121 in adjacent gate structures 110 can be provided on the same side of the gate structure 110 (not shown in the figure), or on opposite sides of the gate structure 110 (see the attached figure). Figure 2 The bridging portion 121 may extend along a first direction. Of course, in some other embodiments, the bridging portion 121 may also extend along other directions.

[0067] In the first embodiment, as shown in the attached Figure 1As shown, the bridge portion 121 electrically connects the middle portions of two adjacent sub-gate structures 111. The middle portion here can be any position of the sub-gate structure 111 except the end. The material of the bridge portion 121 can include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy or any combination thereof. In actual operation, the gate portion 112, the bridge portion 121 and the connecting portion 113 can be formed as one piece, or different materials can be used and prepared in different preparation processes.

[0068] In some embodiments, as shown in the attached Figure 3-4 As shown, the gate structure 110 also includes a lead portion 122, one end of which is electrically connected to the sub-gate structure 111 and the bridge portion 121, that is, the lead portion 122 is connected at the connection between the sub-gate structure 111 and the bridge portion 121. In this case, the lead portion 122 can be located in the peripheral area of ​​the active area array to fully utilize the wafer space and improve the space utilization rate of the semiconductor structure. At the same time, it can also facilitate the setting of the lead line in the subsequent column selector and reduce the difficulty of the manufacturing process of the column selection device. The lead portion 122 can be set on either side of the active area array, and adjacent lead portions 122 can be set on the same side or different sides of the active area array.

[0069] Of course, the lead portion 122 can also be directly electrically connected to the sub-gate structure 111 or the bridge portion 121 (not shown in the figure). Here, there is no specific limitation on the position of the lead portion 122, which is based on whether it can achieve the lead-out of the gate structure 110 and increase the wiring space. In actual operation, the material of the lead portion 122 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy or any combination thereof.

[0070] In the above embodiment, as shown in the attached Figure 1-8 As shown, the shape of the active area 100 can be a rectangle, a trapezoid or a parallelogram. It should be understood that since the active area 100 and the gate portion 112 covering the active area 100 constitute a complete transistor, the shape of the active area 100 and the arrangement of the gate portion 112 affect each other, that is, the shape of the active area 100 is related to the layout of the gate structure 110. For example, in the first to fourth embodiments (see Appendix 1), Figure 1-4 As shown), the shape of the active area 100 is rectangular. At this time, the gate portion 112 in the sub-gate structure 111 extends along the second direction, and the connecting portion 113 connecting adjacent gate portions 112 forms a certain angle with the second direction.

[0071] In Examples 5 to 8, Figure 5-8As shown, when the active area 100 is in the shape of a parallelogram, the sub-gate structure 111 can be a straight line, and its extension direction intersects the second direction. In this case, in the second direction, the parallelogram-shaped active area 100 has two surfaces parallel to the first direction, namely a first surface 151 and a second surface 152. In a row of multiple active areas 100, the projection of the first surface 151 of one active area 100 in the second direction can overlap with the projection of the second surface 152 of an adjacent active area 100.

[0072] It should be understood that if the active area 100 is in the shape of a parallelogram, then the corresponding gate portion 112 is in the shape of a parallelogram, and the extension direction of the gate portion 112 forms a certain angle with the second direction, and the size of the angle is equal to the size of the angle formed by the hypotenuse of the parallelogram active area 100 and the second direction.

[0073] Compared with the rectangular active area 100, the parallelogram-shaped active area 100 can, on the one hand, further increase the setting space of the gate structure 110, thereby reducing the mutual influence of the lead-out wires in the column selector, increasing the wiring space of the lead-out wires, and effectively reducing the difficulty of the preparation process of the semiconductor device. On the other hand, it can maximize the space utilization of the active area 100, thereby improving the space utilization rate of the semiconductor structure.

[0074] In another embodiment, as shown in the attached Figure 9 As shown, the active area 100 is trapezoidal in shape and includes a third surface 153 and a fourth surface 154. The third surface 153 and the fourth surface 154 are parallel and extend along the first direction. The length of the third surface 153 is shorter than the length of the fourth surface 154. In a column of active areas 100, the third surfaces 153 or the fourth surfaces 154 of two adjacent active areas 100 are adjacent.

[0075] Unlike the above-described embodiment, the active area 100 has a trapezoidal shape, and the offset D between adjacent gate portions 112 on the sub-gate structure 111 can be zero. In this case, the sub-gate structure 111 is a straight line, further reducing the difficulty of manufacturing the gate structure 110. Furthermore, the trapezoidal shape of the active area 100 increases the space available for disposing the contact plugs 142 on the active area 100, thereby increasing the routing space for the first conductive lines 131 and the second conductive lines 132. This maximizes the spatial utilization of the active area 100 while effectively increasing the routing space of the semiconductor structure, thereby alleviating the complex and difficult manufacturing process of the column selector.

[0076] It is understandable that Figure 1-8 As shown, in the above-mentioned embodiments 1 to 8, the center line connecting the four adjacent active regions 100 is either a trapezoid or a parallelogram. Figure 1-2As shown, when the center lines of the four adjacent active regions 100 are trapezoidal, for two adjacent gate structures 110, one gate structure 110 can be rotated 160-200 degrees relative to the other gate structure 110. In a specific embodiment, the rotation angle of one gate structure 110 relative to the other gate structure 110 is 180 degrees. In the third to eighth embodiments, as shown in the attached Figure 3-8 As shown, the center lines connecting four adjacent active regions 100 form a parallelogram. Among the multiple gate structures 110 in the semiconductor structure, two adjacent gate structures 110 can overlap with each other by translation.

[0077] As attached Figure 1-8 , Attachment Figure 12 As shown, the semiconductor structure further includes a plurality of first conductive lines 131, which extend along the second direction and are electrically connected to the source region 101 or the drain region 102. Figure 11 The first conductive line 131 is divided into a bitline (BL) connected to the transistor source region 101 and an I / O line connected to the transistor drain region 102. Here, the material of the first conductive line 131 may include a conductive material, such as a metal, a carbon-containing material, or a metal nitride, and specifically includes but is not limited to tungsten, copper, graphene, or titanium nitride.

[0078] It should be understood that the Figure 1-2 As shown, the active area 100 also includes a contact plug 142. The above-mentioned first conductive line 131 is connected to the transistor source area 101 and the drain area 102 through the contact plug 142. The contact plug 142 is divided into a source contact plug 1421 and a drain contact plug 1422. Among them, the first conductive line 131 (bit line) is electrically connected to the source area 101 through the source contact plug 1421, and the first conductive line 131 (I / O line) is electrically connected to the drain area 102 through the drain contact plug 1422.

[0079] Since adjacent gate portions 112 in the same sub-gate structure 111 are offset, adjacent first conductive lines 131 can borrow the offset space from each other, thereby allowing the first conductive lines 131 to be straight and parallel to each other without the need for complex bending wiring, thereby effectively reducing the process difficulty of the column selector.

[0080] See the attached Figure 1-8 , Attachment Figure 12, the semiconductor further includes a plurality of second conductive lines 132, which are straight lines and parallel to the first conductive lines 131. The second conductive lines 132 are electrically connected to the gate structure 110 and control the transistors through external control signals. In some embodiments, the second conductive lines 132 are column select lines (CSL). Specifically, the second conductive lines 132 have CSL contact plugs 1423, and the second conductive lines 132 are electrically connected to the gate structure 110 through the CSL contact plugs 1423. The CSL contact plugs 1423 can be located at any position of the gate structure 110. For example, in Embodiments 1 to 2 (Appendix Figure 1-2 ), the CSL contact plug 1423 is located on the bridge portion 121 in the gate structure 110. In the third to sixth embodiments (see Appendix Figure 3-6 ), the CSL contact plug 1423 is located on the lead portion 122, while in the seventh to eighth embodiments (Appendix Figure 7-8 ), and the CSL contact plug 1423 is located on the sub-gate structure 111. The material of the second conductive line 132 may include a conductive material, such as a metal, a carbon-containing material, or a metal nitride, and specifically includes, but is not limited to, tungsten, copper, graphene, or titanium nitride. In some embodiments, the material of the second conductive line 132 may be the same as or different from the material of the first conductive line 131.

[0081] It should be noted that in order to clearly illustrate the contents of this embodiment, the attached Figure 1-9 Parts of the first conductive line 131 and the second conductive line 132 are hidden.

[0082] To sum up, after the gate portion 112 in the sub-gate structure 111 is offset, the layout space of the gate structure 110 becomes larger, but the space occupied by its active area array does not increase significantly. Therefore, this gate structure layout can not only improve the space utilization of the wafer and improve the integration of semiconductor devices, but also enable the first conductive line 131 and the second conductive line 132 to borrow the offset space from each other, thereby reducing the wiring difficulty of the column selector and effectively improving the problem of the difficulty of the preparation process of the column selector.

[0083] The embodiments of the present disclosure also provide a memory, which includes any semiconductor structure as described above. The memory can be a dynamic random access memory device (DRAM), a static random access memory device (SRAM), an application-specific integrated circuit (ASIC), a flash memory device or other memory devices.

[0084] The present disclosure also provides a method for preparing a semiconductor structure. Figure 10 The flow chart of the method for preparing a semiconductor structure is shown in the attached figure. Figure 10 As shown, the method includes:

[0085] Step S101: forming a plurality of active regions 100 arranged in rows and columns, wherein the active regions 100 in each row are arranged along a first direction;

[0086] Step S102: forming a gate material layer, etching the gate material layer to form a gate structure 110, the gate structure 110 including a sub-gate structure 111, the sub-gate structure 111 being arranged across a column of active areas 100, the sub-gate structure 111 including a gate portion 112 covering the active area 100 and a connecting portion 113 electrically connecting adjacent gate portions 112; wherein, in the same sub-gate structure 111, adjacent gate portions 112 are offset in the first direction.

[0087] Attachment Figure 13 To the attached Figure 16 The schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present disclosure during the preparation process is shown in FIG. Figure 13 To the attached Figure 16 The method for preparing the semiconductor structure provided in the embodiment of the present disclosure is further described.

[0088] First, if Figure 13 As shown, step S101 is performed: forming a plurality of active regions 100 arranged in rows and columns, wherein the active regions 100 in each row are arranged along a first direction.

[0089] Figure 12 For the Figure 1 A vertical cross-section diagram of the line a-a' in FIG. Figure 12 To form active region 100, a substrate (not shown) is first provided. A first mask layer (not shown) is formed on the surface of the substrate. An etching process is then used to pattern the first mask layer, forming a second mask layer having a pattern for active region 100. The substrate is then etched using the second mask layer to form active region 100. A P-type doped well is then formed within the substrate within active region 100. In some embodiments, active region 100 may be rectangular, parallelogram, or trapezoidal in shape.

[0090] In some embodiments, the first mask layer can be formed using chemical vapor deposition (CVD), high-density plasma chemical vapor deposition, spin coating, sputtering, or other suitable methods. The first mask layer can be patterned using a dry or wet etching process, such as a plasma etching process or a chemical mechanical polishing (CMP) process. The P-type doped well can be formed using one or more well-known ion implantation processes, a diffusion process, or a combination thereof.

[0091] Then, as attached Figure 12 、 14As shown, step S102 is performed to form a gate material layer (not shown in the figure) on the substrate (active area 100), and the gate material layer is etched to form a gate structure 110. The gate structure 110 includes a sub-gate structure 111. The sub-gate structure 111 is arranged across a column of active areas 100. The sub-gate structure 111 includes a gate portion 112 covering the active area 100 and a connecting portion 113 electrically connecting adjacent gate portions 112. In the same sub-gate structure 111, adjacent gate portions 112 are offset in the first direction.

[0092] Specifically, the method for etching to form the gate structure 110 having the gate portion 112 and the connecting portion 113 includes: forming a third mask layer (not shown) on the gate material layer, patterning the third mask layer to form a fourth mask layer having a pattern of the gate structure 110; and etching the gate material layer using the fourth mask layer to form a plurality of gate structures 110. In some embodiments, the gate structure 110 further includes a plurality of bridge portions 121 and lead portions 122.

[0093] In practice, before etching the gate material layer to form the gate structure 110, the method may further include forming a gate dielectric layer 161. The subsequently formed gate portion 112 overlies the gate dielectric layer 161. The gate dielectric layer 161 may be formed using chemical vapor deposition (CVD) or other suitable methods. In some embodiments, a barrier layer 162 may be formed between the gate dielectric layer 161 and the gate portion 112 to prevent diffusion of the gate portion 112 material. The material of the barrier layer 162 may be, for example, titanium nitride.

[0094] It can be understood that a plurality of gate structures 110 are formed in the semiconductor structure, and the gate structure 110 includes a sub-gate structure 111 and a bridge portion 121. In another embodiment, the gate structure 110 also includes a lead portion 122. The sub-gate structure 111, the bridge portion 121 and the lead portion 122 can be formed in the same process step, that is, when the third mask layer is patterned as described above, the patterns of the sub-gate structure 111, the bridge portion 121 and the lead portion 122 are formed at the same time. Of course, the sub-gate structure 111, the bridge portion 121 and the lead portion 122 can also be formed step by step using processes known to those skilled in the art. The bridge portion 121 can be located in the middle of the sub-gate structure 111, or at the end of the sub-gate structure 111. The lead portion 122 can be located at any position of the sub-gate structure 111. In addition, the sub-gate structure 111 includes a gate portion 112 and a connecting portion 113. The gate portion 112 can extend along two directions or intersect with the second direction. That is, multiple gate portions 112 and multiple connecting portions 113 can be connected to form a broken line or a straight line.

[0095] After forming the gate structure 110, ion implantation can be performed in the substrate (active region 100) on both sides of the gate portion 112 using the gate portion 112 in the gate structure 110 as a mask to form the source region 101 and the drain region 102. Before the ion implantation, sidewall spacers 163 (offset spacers) can be formed on the sidewalls of the gate dielectric layer 161 and the gate portion 112 to protect the gate dielectric layer 161 and the gate portion 112 from the effects of the ion implantation. Of course, the source region 101 and the drain region 102 can also be formed using a known diffusion process or other suitable method.

[0096] In some embodiments, after forming the source region 101 and the drain region 102, as shown in FIG. Figure 15 As shown, contact plugs 142 are formed. Contact plugs 142 are electrically connected to the source region 101, the drain region 102, or the gate structure 110. The purpose of the contact plugs 142 is to lead out the source region 101, the drain region 102, and the gate structure 110 of the transistor. The contact plugs 142 electrically connected to the source region 101 are source contact plugs 1421, the plug electrically connected to the drain region 102 is a drain contact plug 1422, and the plug electrically connected to the gate structure 110 is a CSL contact plug 1423.

[0097] Combined with attachment Figure 12 The specific steps of forming the contact plug 142 may include: forming a first dielectric layer 168, a second dielectric layer 164, and a third dielectric layer 167 on the substrate (active area 100); then, etching the first dielectric layer 168, the second dielectric layer 164, and the third dielectric layer 167 until a contact hole 165 is formed through the above material layers; and then filling the contact hole 165 with a conductive material to form the contact plug 142. The material of the first dielectric layer 168, the second dielectric layer 164, and the third dielectric layer 167 can be one or more of silicon oxide (SiO2), silicon nitride (SiN), or silicon carbonitride (SiCN).

[0098] The contact hole 165 can be filled by physical vapor deposition (PVD) or chemical vapor deposition (CVD), and the conductive material can be selected from aluminum, silver, chromium, nickel, palladium, molybdenum, titanium, tantalum or copper, or an alloy of aluminum, silver, chromium, nickel, palladium, molybdenum, titanium, tantalum or copper.

[0099] In some embodiments, as Figure 12 As shown, before filling contact hole 165 with a conductive material, a diffusion barrier layer 166 is formed on the surface of contact hole 165. Diffusion barrier layer 166 can be made of titanium nitride or tantalum nitride. Diffusion barrier layer 166 can be formed by vacuum sputtering using argon gas. Diffusion barrier layer 166 can improve adhesion between subsequently formed contact plug 142 and the dielectric layer and prevent subsequent reaction between contact plug 142 and the interlayer dielectric layer.

[0100] Next, as attached Figure 12 and attached Figure 16 As shown, a conductive material layer 143 is formed on the third dielectric layer 167; the conductive material layer 143 is etched to form a first conductive line 131 and a second conductive line 132. The first conductive line 131 is electrically connected to the source region 101 and the drain region 102 via a source contact plug 1421 and a drain contact plug 1422, respectively. The second conductive line 132 is connected to the gate structure 110, and the two are electrically connected via a CSL contact plug 1423. In some embodiments, the first conductive line 131 and the second conductive line 132 are straight and parallel to each other. In another embodiment, the first conductive line 131 can also be a curved line. However, compared to the prior art, the embodiments of the present disclosure use an active region 100 in a parallelogram or rectangular shape, which can provide a larger space for the source contact plug 1421 and the drain contact plug 1422, thereby reducing the degree of curvature of the first conductive line 131 and reducing the wiring difficulty of the semiconductor device.

[0101] Here, etching the conductive material layer 143 may adopt dry etching, such as plasma etching, or wet etching process.

[0102] In summary, the semiconductor structure, preparation method thereof, and memory provided by the embodiments of the present disclosure enable the bit lines BL, input / output lines (I / O), and column selection lines CSL in each column selector to borrow the offset space from each other without the need for complex winding, thereby effectively increasing the wiring space of the column selector and reducing the difficulty of preparing the column selector.

[0103] In addition, the semiconductor structure and its preparation method, and memory provided by the embodiments of the present disclosure can also improve product yield while reducing costs.

[0104] It should be noted that the semiconductor device fabrication methods provided in the embodiments of the present disclosure can be applied to DRAM structures or other semiconductor devices, and are not limited here. The embodiments of the semiconductor device fabrication methods provided in the present disclosure and the embodiments of the semiconductor device are based on the same concept; the technical features of the technical solutions described in the embodiments can be combined arbitrarily unless they conflict.

[0105] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: A plurality of active regions arranged in rows and columns, wherein the active regions in each row are arranged along a first direction; The gate structure includes a sub-gate structure, wherein the sub-gate structure is arranged across a column of the active areas; the sub-gate structure includes a gate portion covering the active areas and a connecting portion electrically connecting adjacent gate portions; wherein, In the same sub-gate structure, adjacent gate portions are offset in the first direction; Wherein, in the same sub-gate structure, the distances between the gate portions covering the active regions in different rows are different; The active area includes a source area and a drain area, and the semiconductor structure also includes multiple first conductive lines and multiple second conductive lines. The first conductive lines are electrically connected to the source area or the drain area, and the second conductive lines are electrically connected to the gate structure. The second conductive lines are column selection lines, and the column selection lines are externally connected to control signals.

2. The semiconductor structure according to claim 1, wherein: The gate portion extends along a second direction, an extending direction of the connecting portion intersects with the second direction, and the second direction is perpendicular to the first direction.

3. The semiconductor structure according to claim 1, wherein: The sub-gate structure is a straight line, and an extension direction intersects with a second direction, and the second direction is perpendicular to the first direction.

4. The semiconductor structure according to claim 1, wherein: The gate structure further includes one or more bridge portions, and the bridge portions electrically connect adjacent sub-gate structures.

5. The semiconductor structure according to claim 4, wherein: The bridge portion electrically connects ends of adjacent sub-gate structures. The semiconductor structure according to claim 4 , wherein: The bridge portion electrically connects the middle portions of adjacent sub-gate structures.

7. The semiconductor structure according to claim 4, wherein: The gate structure further includes a lead-out portion, one end of which is electrically connected to the sub-gate structure and / or the bridge portion.

8. The semiconductor structure according to claim 1, wherein: The active area is in the shape of a rectangle, a trapezoid or a parallelogram.

9. The semiconductor structure according to claim 1, wherein: A line connecting the centers of the four adjacent active areas is in the shape of a trapezoid or a parallelogram.

10. The semiconductor structure according to claim 1, wherein: The first conductive lines are straight and parallel to each other.

11. The semiconductor structure according to claim 1, wherein: The second conductive line is a straight line and parallel to the first conductive line.

12. The semiconductor structure according to claim 1, wherein: The semiconductor structure includes a plurality of gate structures. For two adjacent gate structures, one of the gate structures is rotated 160-200 degrees relative to the other.

13. The semiconductor structure according to claim 1, wherein: The semiconductor structure includes a plurality of gate structures, and two adjacent gate structures can overlap with each other through translation.

14. A memory, characterized in that: include: The semiconductor structure according to any one of claims 1 to 13.

15. A method for preparing a semiconductor structure, characterized in that: include: forming a plurality of active regions arranged in rows and columns, wherein the active regions in each row are arranged along a first direction; forming a gate material layer, and etching the gate material layer to form a gate structure, wherein the gate structure includes a sub-gate structure, the sub-gate structure being arranged across a column of the active regions, and the sub-gate structure including a gate portion covering the active regions and a connecting portion electrically connecting adjacent gate portions; wherein, In the same sub-gate structure, adjacent gate portions are offset in the first direction; Wherein, in the same sub-gate structure, the distances between the gate portions covering the active regions in different rows are different; The active region includes a source region and a drain region, and the preparation method further includes: forming a conductive material layer; The conductive material layer is etched to form a first conductive line and a second conductive line, wherein the first conductive line is electrically connected to the source region or the drain region, and the second conductive line is connected to the gate structure. The second conductive line is a column selection line, and the column selection line is externally connected to a control signal.

16. The method according to claim 15, characterized in that The method further comprises: A contact plug is formed, wherein the contact plug is electrically connected to the source region, the drain region or the gate structure.

17. The method according to claim 15, characterized in that The first conductive line and the second conductive line are straight lines and parallel to each other.

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