A processor and memory reading method thereof

Abstract

The present invention proposes a processor and a memory reading method thereof. The processor comprises at least one first-level data cache, a second-level data cache, and a first-level transformation backup buffer linked to the first-level data cache; a second-level transformation backup buffer linked to the second-level data cache, wherein a part of the second-level data cache is permanently reserved for caching the content of a microcode simulation memory. When the content of the microcode simulation memory is to be accessed, the first transformation backup buffer and the second transformation backup buffer are checked at the same time. If the check of the first-level backup cache hits, the check of the second-level backup cache will be terminated or ignored; if the check of the first-level backup cache does not hit, the address of the second-level cache is checked, or data is directly read from the memory, thereby reducing waiting and improving reading efficiency.

Description

Technical Field

[0001] The present invention provides a processor and a memory reading method thereof, and relates to the technical field of data storage, and in particular to the technical field of memory reading of storage devices. Background Art

[0002] The instruction set architectures of current processors mainly include complex instruction set computer (CISC) architecture and reduced instruction set computer (RISC) architecture. In order to make the reduced instruction set architecture compatible with the complex instruction set architecture, the reduced instruction set architecture can use simulation instructions to achieve compatibility with the complex instruction set architecture, thereby improving the performance of the reduced instruction set architecture. Generally speaking, a portion of the system memory (physical memory) can be designated as microcode simulation memory. In order for the processor's microcode to access the contents of the microcode simulation memory as quickly as possible, during the simulation program, the microcode can use scratchpad memory to store intermediate values.

[0003] Typically, a cache access involves specifying a cache line or a portion of a cache line, identifying the target line, and including the address of the data in the cache line to be accessed from the cache line. Since cache access is faster than memory access, many caching techniques are used to increase the likelihood that data will be cached when a core or execution unit needs to access the data.

[0004] In order to allow the cache to quickly load data from the system memory, the microcode emulation memory is usually allocated in the first part of the first-level data cache. However, the capacity of the first-level data cache is small, so the capacity of the first part of the first-level data cache is even smaller. Once the first part is filled, the data of the microcode emulation memory will be moved to the second-level cache.

[0005] It is known that the processor reads data by sequentially accessing the first-level data cache (L1 cache), the second-level cache memory (L2 cache), and the third-level cache memory (L3 cache). In other words, when the predetermined data cannot be accessed in the first-level data cache, the second-level cache memory is accessed. However, the access speed of the second-level cache is much lower than the access speed of the first-level data cache, so the established method of sequentially accessing data from the first-level cache memory and the second-level cache still has room for improvement. Summary of the invention

[0006] The present invention provides a processor and a memory reading method thereof, which are used to solve the problems of low data access efficiency and the like:

[0007] The present invention proposes a processor and a memory reading method thereof, wherein the processor includes at least one first-level data cache module and at least one second-level data cache module, a first-level transformation backup buffer module and a second-level transformation backup buffer module, wherein the first-level data cache module is electrically coupled to the second-level data cache module, the first-level data cache module is electrically coupled to the first-level transformation backup buffer module; and the second-level data cache module is electrically coupled to the second-level transformation backup buffer module.

[0008] Furthermore, the second-level data cache module is electrically coupled to a system memory module having a memory function.

[0009] Furthermore, the system memory module includes a plurality of space blocks, and the space blocks are designated and reserved as microcode emulation memory.

[0010] Furthermore, the second-level data cache module includes a second-level cache microcode emulation memory module.

[0011] Furthermore, the processor also includes a load storage unit; wherein the load storage unit is electrically coupled to the first-level data cache module, and the load storage unit is electrically coupled to the first-level transformation backup buffer module and the second-level transformation backup buffer module.

[0012] Furthermore, the processor also includes an execution unit; wherein the execution unit is electrically coupled to the load storage unit.

[0013] Furthermore, the memory reading method of the processor includes:

[0014] Performing access check on the first-level transformation backup buffer module and the second-level transformation backup buffer module to determine whether the microcode to be accessed exists in the first-level transformation backup buffer module and the second-level transformation backup buffer module, and obtaining a determination result;

[0015] The access execution strategy of the microcode to be accessed is determined according to the judgment result.

[0016] Further, the first-level transformation backup buffer module and the second-level transformation backup buffer module are accessed and checked to determine whether the first-level transformation backup buffer module and the second-level transformation backup buffer module have the microcode to be accessed, and the determination result is obtained, including:

[0017] After the processor starts to access the microcode, the processor performs access check on the first-level conversion backup buffer module and the second-level conversion backup buffer module used for the microcode simulation memory;

[0018] It is determined whether there is a microcode corresponding to the access in the first-level transformation lookaside buffer module and the second-level transformation lookaside buffer module.

[0019] Furthermore, the access execution strategy of the microcode to be accessed is determined according to the judgment result, including:

[0020] If the microcode to be accessed exists in the first-level transform lookaside buffer module, the core of the processor accesses the first-level data cache module according to the location of the corresponding microcode, and the check of the second-level transform lookaside buffer module is terminated or ignored;

[0021] If the microcode to be accessed does not exist in the first-level transformation backup buffer module, according to the result of the second-level transformation backup buffer module check, if the result of the second-level transformation backup buffer module check indicates a hit, the data of the hit microcode to be accessed is copied from the second-level data cache module back to the first-level data cache module, and the first-level transformation backup buffer module is updated; if the result of the second-level transformation backup buffer module check indicates no hit, the microcode to be accessed is accessed from the system memory and then the data is copied back to the first-level data cache module;

[0022] After the data is copied, the core of the processor accesses the first-level data cache module according to the location corresponding to the microcode to be accessed.

[0023] Further, obtaining the data space idle coefficient and data access coefficient of the first-level data cache module, comparing the coefficient with a threshold, and then adjusting the access parameter, including:

[0024] Dividing the cache space of the first-level data cache module to obtain a plurality of divided spaces;

[0025] Acquire access information of the first-level data cache module, and calculate the idle data space coefficient of the first-level data cache module according to the access information;

[0026] The calculation formula of the idle data space coefficient is:

[0027] ;

[0028] Among them, L kj is the idle data space coefficient, C zr is the total cache space, n is the total number of partitioned spaces, D sli is the amount of data space used in the i-th partition, C xli is the storage efficiency of the i-th partition space, D oiis the metadata space of the ith partition, m is the number of independent regions affected by data fragmentation, and W kla is the amount of additional unused space in the ath independent region due to data fragmentation;

[0029] Acquire access check information of the first-level transformation backup buffer module, the second-level transformation backup buffer module and the system memory, and calculate data access coefficients of the system memory, the second-level transformation backup buffer module and the first-level transformation backup buffer module in sequence according to the access check information;

[0030] The calculation formula of the data access coefficient of the system memory is:

[0031] ;

[0032] Among them, N c is the data access coefficient of the system memory, Q c is the number of microcode fetches from system memory, C r The number of times the microcode is stored in the system memory;

[0033] Comparing the data access coefficient of the system memory with a preset data access threshold of the system memory to obtain a system memory comparison result;

[0034] Moving the microcode in the system memory to the second-level transformation lookaside buffer module or the first-level transformation lookaside buffer module according to the system memory comparison result;

[0035] The calculation formula of the data access coefficient of the second-level transformation backup buffer module is:

[0036] ;

[0037] Among them, R c is the data access coefficient of the second-level transform backup buffer module, U c is the number of microcode fetches from the second-level transform backup buffer module, T r is the number of microcode storage times of the second-level transform backup buffer module, N y is the preset data access threshold of the system memory;

[0038] Comparing the data access coefficient of the second-level transform backup buffer module with the preset data access threshold of the second-level transform backup buffer module to obtain a comparison result of the second-level transform backup buffer module;

[0039] According to the comparison result of the second-level transform lookaside buffer module, the microcode in the second-level transform lookaside buffer module is moved to the first-level transform lookaside buffer module;

[0040] The calculation formula of the data access coefficient of the first-level transformation backup buffer module is:

[0041] ;

[0042] Among them, Y c is the data access coefficient of the first-level transform backup buffer module, W c is the number of microcode fetches from the first-level transform lookaside buffer module, M r is the number of microcode storage times of the first-level transformation backup buffer module, N y is the preset data access threshold of the system memory, R y A preset data access threshold for the second-level transformation backup buffer module;

[0043] Comparing the data access coefficient of the first-level transformation backup buffer module with the preset data access threshold of the first-level transformation backup buffer module to obtain a comparison result of the first-level transformation backup buffer module;

[0044] The microcode in the first-level transformation lookaside buffer module is moved to the first-level data cache module according to the comparison result of the first-level transformation lookaside buffer module.

[0045] The beneficial effects of the present invention are as follows: the processor performs L1 TLB and L2 TLB access checks simultaneously. When the required microcode exists in the second-level data cache or system memory, the present invention can move data in advance and improve access efficiency. Through the multi-level cache structure and TLB mechanism, the number of direct accesses of the processor to the system memory is reduced, thereby significantly improving the memory access speed. Fast memory access and efficient address conversion enable the processor to execute instructions faster, improving overall processing power and performance. The introduction of microcode simulation memory enables the processor to expand or modify its functions through software or firmware updates, increasing the flexibility and upgradeability of the system. Access to slow system memory is reduced, and the power consumption of the processor is reduced, especially in application scenarios where small data sets are frequently accessed. The parallel processing mechanism of multi-level cache and TLB helps to maintain efficient memory access in a multi-tasking or multi-threaded environment, thereby improving concurrency performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A flowchart of the processor access execution steps of the present invention;

[0047] Figure 2 A schematic diagram of the configuration of the electrical coupling between the internal components of the processor and the electrical coupling with the system memory of the present invention;

[0048] Figure 3 It is a schematic diagram of the movement of cache columns between different memories of the present invention. DETAILED DESCRIPTION

[0049] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0050] One embodiment of the present invention proposes a processor and a memory reading method thereof, wherein the processor includes at least one first-level data cache module and at least one second-level data cache module, a first-level transformation backup buffer module and a second-level transformation backup buffer module, wherein the first-level data cache module is electrically coupled to the second-level data cache module, the first-level data cache module is electrically coupled to the first-level transformation backup buffer module; and the second-level data cache module is electrically coupled to the second-level transformation backup buffer module.

[0051] The second-level data cache module is electrically coupled to a system memory module having a memory function.

[0052] The system memory module includes a plurality of space blocks, and the space blocks are designated and reserved as microcode emulation memory.

[0053] The second-level data cache module includes a second-level cache microcode emulation memory module.

[0054] The processor further includes a load storage unit, wherein the load storage unit is electrically coupled to the first-level data cache module, and the load storage unit is electrically coupled to the first-level transformation lookaside buffer module and the second-level transformation lookaside buffer module.

[0055] The processor further includes an execution unit, wherein the execution unit is electrically coupled to the load storage unit.

[0056] The working principle of the above technical solution is as follows: Figure 2 As shown, the figure is a generalized block diagram of an embodiment of a computer system. In one embodiment, the processor 10 is shown as being combined with a system memory 20. The processor 10 has at least one core, and includes an execution unit 11, a load / store unit 12, a first-level data cache 13, and a second-level data cache 14. The above-mentioned units can be electrically connected or electrically coupled, and the second-level data cache 14 is electrically connected or electrically connected or electrically coupled with the system memory 20. The system memory 20 can be a physical memory, for example, including but not limited to SDRAM, SRAM, ROM, DRAM and / or other known memory devices.

[0057] The present embodiment further includes a first / second level translation look-aside buffer (L1 / L2 TLB) 15 electrically coupling the first level data cache 13, the second level data cache 14 and the load / store unit 12. Secondly, a portion of the space of the second level data cache 14 can be distinguished and defined as a second level cache microcode emulation memory.

[0058] During operation, the execution unit 11 may receive load data to be executed from the load / store unit 12 via the link, and transfer data to be stored to the load / store unit 12 via the link. The load / store unit 12 may receive load data to be executed from the first-level data cache 13 via the link, and transfer data to be stored to the first-level data cache 13 via the link.

[0059] The first level data cache 13 can receive loaded data from the second level data cache 14 via a link, and can transfer data to be stored to the second level data cache 14 via a link. The second level data cache 14 can receive loaded data from the system memory 20 via a link, and can transfer data to be stored to the system memory 20.

[0060] Next, a first / second level translation lookaside buffer (L1 / L2 TLB) 15 is coupled to the load / store unit 12 via a link, coupled to the first level data cache 13 via a link, and coupled to the second level data cache 14 via a link.

[0061] The first level data cache 13, the second level data cache 14 and the first / second level translation lookaside buffer (L1 / L2 TLB) 15 can perform common address translation and caching functions. For example, the L1 / L2 TLB 15 can cache the mapping of virtual addresses to physical addresses. When a memory access request occurs, the L1 / L2 TLB 15 is checked to see if the mapping of the virtual address required by the physical address has been cached.

[0062] Generally speaking, the mapping of the cache in the first level translation lookaside buffer (L1 TLB) can be used to determine whether the desired cache line exists in the first level data cache 13. If the desired cache line does not exist in the first level data cache 13 (miss), the second level translation lookaside buffer (L2 TLB) is checked to see whether the mapping of the desired virtual address to the physical address is cached. Similarly, the mapping of the cache in the second level translation lookaside buffer (L2 TLB) can be used to determine whether the desired cache line exists in the second level data cache 14.

[0063] When a cache miss occurs in the first level data cache 13, in order to make room for a new entry, the cache line in the first level data cache 13 may be evicted to the second level data cache 14. At the same time, the corresponding entry in the first level translation lookaside buffer (L1 TLB) is moved to the second level translation lookaside buffer (L2 TLB). In order to make room for the new entry in the second level data cache 14, the cache line in the second level data cache 14 may have to be evicted to the system memory 20.

[0064] like Figure 3 As shown, the figure shows an embodiment of the movement of cache columns between different memories. Part of the address space of the system memory 20 is mapped to the address space of the second-level data cache 14, and part of the address space of the second-level data cache 14 is mapped to the address space of the first-level data cache 13. In one embodiment, a space block 21 of the system memory 20 is designated and reserved as a microcode emulation memory. In addition, block 141 of the second-level data cache 14 can be permanently reserved to cache the contents of the microcode emulation memory (block 201). In particular, block 141 can be the first part of the second-level data cache.

[0065] Secondly, other space blocks 202, 203, 204 of the system memory 20 can be relatively mapped to the space blocks 142, 143, 144 of the second-level data cache 14. The space blocks 141, 142, 144 of the second-level data cache 14 can be relatively mapped to the space blocks 131, 132, 133 of the first-level data cache 13.

[0066] Therefore, according to the above description, the microcode emulation routine may be recorded in the second-level data cache 14 or the first-level data cache 13 in addition to being recorded in the microcode emulation memory of the system memory 20. In one embodiment disclosed by the present invention, when the processor 10 is to access the microcode, the first-level data cache 13 and the second-level data cache 14 are checked at the same time during the operation.

[0067] like Figure 1As shown in the figure, an execution flow of an embodiment of the present invention is disclosed. When the processor needs to access the microcode, it will check the L1 / L2 TLB access of the microcode simulation memory at the same time according to step S1. Step S2 is a judgment step, which is to judge whether there is a corresponding microcode to be accessed in the content of L1 TLB based on the check content of the previous step. If there is a corresponding microcode to be accessed in L1 TLB, then according to step S3, the core of the processor can access the first-level data cache according to the corresponding position; because the execution speed of the first-level data cache (L1 cache) is much faster than the execution speed of the second-level cache (L2 cache), when the check of L1 TLB is completed, the check of L2 TLB should not be completed, so the check of L2 TLB should be terminated or ignored.

[0068] If the data (microcode) to be accessed does not correspond to the data (microcode) in the L1 TLB, then according to step S4, the L2TLB is checked to determine whether the data (microcode) exists in the L2 TLB. If the data exists in the L2 TLB, then according to step S5, the data is copied back to the first-level data cache and the content of the L1 TLB is updated; if the data does not exist in the L2 TLB, then according to step S6, the system memory is accessed; after the corresponding data is obtained, the data can be copied to the first cache and the L1 TLB can be updated as shown in step S5. When the data to be accessed is placed in the first-level data cache, the core can access the first cache according to step S7.

[0069] According to the above, the technical means disclosed by the present invention is to simultaneously perform access checks on the L1 TLB and L2 TLB corresponding to the first-level data cache and the second-level data cache, and then perform subsequent actual access actions. Since the execution speed of the first-level data cache is higher than that of the second-level data cache, the access checks of the L1 TLB and the L2TLB are performed simultaneously. When the required microcode exists in the second-level data cache or the system memory, the present invention can move data in advance, thereby improving the access efficiency.

[0070] The first-level data cache module is the data cache closest to the execution unit and is used to store recently accessed data to reduce the number of accesses to the slower second-level cache or system memory. The second-level data cache module has a larger cache than the first-level data cache module and is used to store data that is not frequently used but still needs to be retained. When the first-level data cache module cache misses, it will automatically search for the second-level data cache module cache. The first-level data cache module and the second-level data cache module cache are electrically coupled to ensure that data can be quickly transferred between the two levels of cache. The first-level translation lookaside buffer module quickly maps virtual memory addresses to physical memory addresses to speed up memory access. The second-level translation lookaside buffer module is larger than the first-level translation lookaside buffer module and is used to store more address mapping information to support a wider range of memory accesses. When the processor needs to access memory, it first checks the TLB to determine the physical address corresponding to the virtual address. If the TLB hits, the memory is accessed directly; if it misses, a more time-consuming page table lookup may be required. The system memory module contains multiple blocks of space, some of which are designated and reserved as microcode emulation memory. This memory is used to store processor microcode (i.e., low-level instructions or micro-operations) to simulate or expand the functionality of the processor. The second-level cache microcode emulation memory module sets up a special area in the L2 cache to cache the contents of the microcode emulation memory, further improving the microcode access speed. The load-store unit is responsible for handling memory load (reading data from memory to registers) and store (writing data from registers to memory) operations. It works closely with the L1 cache, L1 TLB, and L2 TLB to optimize memory access performance. The execution unit is responsible for executing processor instructions, connecting to the load-store unit, obtaining the required data, and writing the results back to memory or registers.

[0071] The effects of the above technical solutions are as follows: through the multi-level cache structure and TLB mechanism, the number of direct accesses of the processor to the system memory is reduced, thereby significantly improving the memory access speed. Fast memory access and efficient address translation enable the processor to execute instructions faster, improving overall processing power and performance. The introduction of microcode emulation memory enables the processor to expand or modify its functions through software or firmware updates, increasing the flexibility and upgradeability of the system. Access to slow system memory is reduced, and the power consumption of the processor is reduced, especially in application scenarios where small data sets are frequently accessed. The parallel processing mechanism of multi-level cache and TLB helps to maintain efficient memory access in a multi-tasking or multi-threaded environment, thereby improving concurrent performance.

[0072] In one embodiment of the present invention, the memory reading method of the processor includes:

[0073] Performing access check on the first-level transformation backup buffer module and the second-level transformation backup buffer module to determine whether the microcode to be accessed exists in the first-level transformation backup buffer module and the second-level transformation backup buffer module, and obtaining a determination result;

[0074] The access execution strategy of the microcode to be accessed is determined according to the judgment result.

[0075] The working principle of the above technical solution is as follows: when the execution unit or the load storage unit needs to access the microcode, an access request is initiated, which contains the virtual address of the microcode to be accessed. The system will search in the L1 TLB whether there is an entry that matches the virtual address in the request. The L1 TLB has an extremely fast access speed because it is close to the execution unit. If the L1 TLB misses (i.e., no matching entry is found), the system will automatically turn to the L2 TLB for search. Although the L2 TLB is slightly slower than the L1 TLB, it has a larger capacity and can store more address mapping information. If an entry matching the virtual address in the request is found in the L1 TLB or L2 TLB, it is considered a hit. At this time, the system can directly use the physical address stored in the entry to access the microcode in the memory. If neither the L1 TLB nor the L2 TLB finds a matching entry, it is considered a miss. At this time, the system needs to perform a more time-consuming page table search process to determine the physical address. Based on the judgment result, the system will determine the access execution strategy for the microcode to be accessed. If there is a hit, the physical address in the TLB is directly used for quick access; if there is a miss, a software trap (such as a page fault interrupt) may be required to load the corresponding page into the memory and update the TLB entry.

[0076] The effect of the above technical solution is: by using TLB to quickly convert virtual to physical addresses, the delay caused by page table lookup is significantly reduced, and the access speed of microcode is improved. When the TLB hits, the memory can be accessed directly through the physical address, avoiding the complex page table lookup process, thereby reducing the total delay of memory access. Fast microcode access can speed up the processor's instruction execution speed and improve overall performance, especially in application scenarios that require frequent access to microcode. As a form of cache, the efficient use of TLB helps reduce additional memory accesses caused by cache misses, thereby optimizing overall cache utilization. Through reasonable access execution strategies, such as handling TLB misses, it can be ensured that the system can still maintain stable operation in the face of complex memory access requests.

[0077] In one embodiment of the present invention, the first-level transformation lookaside buffer module and the second-level transformation lookaside buffer module are accessed and checked to determine whether the first-level transformation lookaside buffer module and the second-level transformation lookaside buffer module have microcodes to be accessed, and the determination result is obtained, including:

[0078] After the processor starts to access the microcode, the processor performs access check on the first-level conversion backup buffer module and the second-level conversion backup buffer module used for the microcode simulation memory;

[0079] It is determined whether there is a microcode corresponding to the access in the first-level transformation lookaside buffer module and the second-level transformation lookaside buffer module.

[0080] The working principle of the above technical solution is as follows: when the processor needs to access the microcode (for example, the execution unit needs to execute a special instruction implemented by the microcode), the processor will first start the access check process for the microcode simulation memory. The processor will first check whether there is a mapping from the virtual address to the physical address corresponding to the microcode to be accessed in the L1 TLB. Since the L1 TLB is close to the execution unit, this step is usually very fast. If no matching entry is found in the L1 TLB, the processor will turn to the L2 TLB for further search. Although the L2 TLB has a slightly slower access speed, it can store more mapping information, thereby increasing the possibility of finding a matching entry. If a mapping entry corresponding to the microcode to be accessed is found in the L1 TLB or L2 TLB, the judgment result is "hit". At this time, the processor can directly use the physical address in the entry to access the microcode in the memory. If no matching mapping entry is found in both the L1 TLB and the L2 TLB, the judgment result is "miss". This means that the processor needs to determine the physical address of the microcode through other mechanisms (such as page table search).

[0081] The effect of the above technical solution is: by preferentially searching for the address mapping of the microcode in the TLB, the number of times of directly accessing the memory or performing complex page table searches is reduced, thereby improving the access efficiency of the microcode. When the TLB hits, the access operation of the microcode can be completed almost immediately, significantly reducing the delay introduced by address translation and memory access. As a form of cache, the efficient use of TLB helps to reduce cache pollution and additional memory access caused by cache misses, thereby optimizing the overall cache usage efficiency; the fast microcode access capability enables the processor to execute complex instructions or handle special tasks faster, thereby improving the performance of the entire system. Through a clear access check process and a reasonable miss handling mechanism, the system can handle microcode access requests more stably, avoiding system crashes or instabilities caused by address mapping errors or memory access conflicts.

[0082] In one embodiment of the present invention, the access execution strategy of the microcode to be accessed is determined according to the judgment result, including:

[0083] If the microcode to be accessed exists in the first-level transform lookaside buffer module, the core of the processor accesses the first-level data cache module according to the location of the corresponding microcode, and the check of the second-level transform lookaside buffer module is terminated or ignored;

[0084] If the microcode to be accessed does not exist in the first-level transformation backup buffer module, then according to the result of the second-level transformation backup buffer module check, if the result of the second-level transformation backup buffer module check indicates a hit (i.e., the microcode to be accessed exists in the second-level transformation backup buffer module), the hit microcode to be accessed is copied from the second-level data cache module back to the first-level data cache module, and the first-level transformation backup buffer module is updated; if the result of the second-level transformation backup buffer module check indicates no hit, the microcode to be accessed is accessed from the system memory and then the data is copied back to the first-level data cache module;

[0085] After the data is copied, the core of the processor accesses the first-level data cache module according to the location corresponding to the microcode to be accessed.

[0086] The working principle of the above technical solution is as follows: if the mapping entry corresponding to the microcode to be accessed is found in the L1 TLB, the processor will directly use the physical address to initiate an access request to the first-level data cache module (L1 Data Cache). Since the L1 Data Cache is usually the cache level closest to the processor core, this access method will be the fastest. At the same time, since the required mapping has been found in the L1 TLB, there is no need to check the L2 TLB, thereby saving time and resources. If the corresponding mapping entry is not found in the L1 TLB, but exists in the L2 TLB, the processor will use the physical address in the L2 TLB to retrieve the required microcode from the second-level data cache module (L2 Data Cache). After retrieving the microcode, the processor will copy it back to the L1 Data Cache for subsequent fast access. At the same time, in order to maintain cache consistency, the processor will also update the mapping information in the L1 TLB and add the new microcode address and physical address correspondence thereto. If no corresponding mapping entry is found in either the L1 TLB or the L2 TLB, the processor will have to retrieve the required microcode from system memory. Retrieving microcode from system memory is usually much slower than retrieving it from the cache because the access latency of system memory is higher. Once the microcode is retrieved from system memory, the processor will copy it back to the L1 Data Cache and may update the mapping information in the L1 TLB and L2 TLB as needed. In any of the above cases, once the microcode is loaded into the L1 Data Cache, the core of the processor can access it from the L1 Data Cache according to the location corresponding to the microcode.

[0087] The effect of the above technical solution is: by preferentially searching for the address mapping of the microcode in the L1 TLB and L2 TLB, the number of direct accesses to the system memory is reduced, thereby improving the access efficiency of the microcode. The hits of the L1 TLB and L2 TLB can significantly reduce the latency of memory access because the access speed of the cache is much faster than that of the system memory. Reasonable cache replication and update strategies help maintain the consistency and effectiveness of the cache and reduce cache pollution and misses. The fast microcode access capability enables the processor to execute complex instructions or handle special tasks faster, thereby improving the performance of the entire system. When faced with high loads or complex tasks, this efficient memory access strategy helps to reduce system response time and improve user experience.

[0088] An embodiment of the present invention obtains a data space idle coefficient and a data access coefficient of a first-level data cache module, compares the coefficient with a threshold, and then adjusts the access parameter, including:

[0089] Dividing the cache space of the first-level data cache module to obtain a plurality of divided spaces;

[0090] Acquire access information of the first-level data cache module, and calculate the idle data space coefficient of the first-level data cache module according to the access information;

[0091] The calculation formula of the idle data space coefficient is:

[0092] ;

[0093] Among them, L kj is the idle data space coefficient, C zr is the total cache space, n is the total number of partitioned spaces, D sli is the amount of data space used in the i-th partition, C xli is the storage efficiency of the i-th partition space, D oi is the metadata space of the ith partition, m is the number of independent regions affected by data fragmentation, and W kla is the amount of additional unused space in the ath independent region due to data fragmentation;

[0094] Acquire access check information of the first-level transformation backup buffer module, the second-level transformation backup buffer module and the system memory, and calculate data access coefficients of the system memory, the second-level transformation backup buffer module and the first-level transformation backup buffer module in sequence according to the access check information;

[0095] The calculation formula of the data access coefficient of the system memory is:

[0096] ;

[0097] Among them, N c is the data access coefficient of the system memory, Q c is the number of microcode fetches from system memory, C r The number of times the microcode is stored in the system memory;

[0098] Comparing the data access coefficient of the system memory with a preset data access threshold of the system memory to obtain a system memory comparison result;

[0099] The microcode in the system memory is moved to the second-level transformation backup buffer module or the first-level transformation backup buffer module according to the system memory comparison result; if it is greater, it is moved, otherwise it is not moved.

[0100] The calculation formula of the data access coefficient of the second-level transformation backup buffer module is:

[0101] ;

[0102] Among them, R c is the data access coefficient of the second-level transform backup buffer module, U c is the number of microcode fetches from the second-level transform backup buffer module, T r is the number of microcode storage times of the second-level transform backup buffer module, N y is the preset data access threshold of the system memory;

[0103] Comparing the data access coefficient of the second-level transform backup buffer module with the preset data access threshold of the second-level transform backup buffer module to obtain a comparison result of the second-level transform backup buffer module;

[0104] According to the comparison result of the second-level transformation backup buffer module, the microcode in the second-level transformation backup buffer module is moved to the first-level transformation backup buffer module; if it is greater, it is moved, otherwise it is not moved;

[0105] The calculation formula of the data access coefficient of the first-level transformation backup buffer module is:

[0106] ;

[0107] Among them, Y c is the data access coefficient of the first-level transform backup buffer module, W c is the number of microcode fetches from the first-level transform lookaside buffer module, M r is the number of microcode storage times of the first-level transformation backup buffer module, N y is the preset data access threshold of the system memory, R y A preset data access threshold for the second-level transformation backup buffer module;

[0108] Comparing the data access coefficient of the second-level transform backup buffer module with the preset data access threshold of the second-level transform backup buffer module to obtain a comparison result of the second-level transform backup buffer module;

[0109] Comparing the data access coefficient of the first-level transformation backup buffer module with the preset data access threshold of the first-level transformation backup buffer module to obtain a comparison result of the first-level transformation backup buffer module;

[0110] According to the comparison result of the first-level transformation backup buffer module, the microcode in the first-level transformation backup buffer module is moved to the first-level data cache module. If it is greater, it is moved, otherwise it is not moved.

[0111] The working principle of the above technical solution is: the first-level data cache module is spatially divided into multiple independent partitioned spaces to manage cache resources more accurately. By obtaining the access information of L1 Cache, the idle data space coefficient is calculated, taking into account the total cache space, the used data space of each partitioned space, the storage efficiency (Cxli), the metadata space, and the additional unused space caused by data fragmentation. It is helpful to identify which partitioned spaces have idle or inefficiently used resources. The access check information of the first-level transformation lookaside buffer module (L1 TLB), the second-level transformation lookaside buffer module (L2 TLB) and the system memory is obtained. The data access coefficients of these three components are calculated respectively. The calculation is based on the number of times the microcode is taken out and stored, reflecting the data access frequency and efficiency of each component. The calculated data access coefficient is compared with the preset data access threshold to determine whether the position of the microcode needs to be adjusted. For example, if the data access coefficient of the system memory is higher than the preset threshold, it indicates that the data access of the system memory is more frequent, and some microcodes need to be moved to the L2 TLB or L1 TLB closer to the processor to increase the access speed. According to the comparison results, the microcode is dynamically migrated from the system memory to the L2 TLB or L1 TLB, or from the L2 TLB to the L1 TLB. This migration helps to optimize the data access path, reduce access latency, and improve overall system performance.

[0112] The effect of the above technical solution is: through fine-grained cache space division and calculation of idle data space coefficient, the idle space in the cache can be more accurately identified and utilized, thereby improving the cache utilization and overall performance. By dynamically migrating microcode, the location of data in memory and TLB can be adjusted in real time according to the actual data access pattern, thereby optimizing the data access path and reducing access latency. The improvement in cache utilization and the optimization of data access paths work together to improve the overall performance of the system, especially when processing a large number of data access requests, which can significantly reduce waiting time and increase processing speed. This method allows the system to dynamically adjust resource configuration according to real-time data access conditions, enhances the flexibility and adaptability of the system, and enables it to better cope with different workloads and performance requirements.

[0113] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A processor, characterized in that: The processor includes at least one first-level data cache module and at least one second-level data cache module, a first-level transformation backup buffer module and a second-level transformation backup buffer module, wherein the first-level data cache module is electrically coupled to the second-level data cache module, the first-level data cache module is electrically coupled to the first-level transformation backup buffer module; the second-level data cache module is electrically coupled to the second-level transformation backup buffer module; Obtaining the data space idle coefficient and data access coefficient of the first-level data cache module, comparing the coefficient with a threshold, and then adjusting the access parameter, including: Dividing the cache space of the first-level data cache module to obtain a plurality of divided spaces; Acquire access information of the first-level data cache module, and calculate the idle data space coefficient of the first-level data cache module according to the access information; Acquire access check information of the first-level transformation backup buffer module, the second-level transformation backup buffer module and the system memory, and calculate data access coefficients of the system memory, the second-level transformation backup buffer module and the first-level transformation backup buffer module in sequence according to the access check information; Comparing the data access coefficient of the system memory with a preset data access threshold of the system memory to obtain a system memory comparison result; Moving the microcode in the system memory to the second-level transformation lookaside buffer module or the first-level transformation lookaside buffer module according to the system memory comparison result; Comparing the data access coefficient of the second-level transform backup buffer module with the preset data access threshold of the second-level transform backup buffer module to obtain a comparison result of the second-level transform backup buffer module; According to the comparison result of the second-level transform lookaside buffer module, the microcode in the second-level transform lookaside buffer module is moved to the first-level transform lookaside buffer module; Comparing the data access coefficient of the first-level transformation backup buffer module with the preset data access threshold of the first-level transformation backup buffer module to obtain a comparison result of the first-level transformation backup buffer module; The microcode in the first-level transformation lookaside buffer module is moved to the first-level data cache module according to the comparison result of the first-level transformation lookaside buffer module.

2. The processor according to claim 1, characterized in that: The second-level data cache module is electrically coupled to a system memory module having a memory function.

3. The processor according to claim 2, characterized in that: The system memory module includes a plurality of space blocks, and the space blocks are designated and reserved as microcode emulation memory.

4. The processor according to claim 1 or 2, characterized in that: The second-level data cache module includes a second-level cache microcode emulation memory module.

5. The processor according to claim 1, characterized in that: The processor further includes a load storage unit, wherein the load storage unit is electrically coupled to the first-level data cache module, and the load storage unit is electrically coupled to the first-level transformation lookaside buffer module and the second-level transformation lookaside buffer module.

6. The processor according to claim 5, characterized in that: The processor further includes an execution unit, wherein the execution unit is electrically coupled to the load storage unit.

7. A memory reading method of the processor according to claim 1, characterized in that: The memory reading method of the processor includes: Performing access check on the first-level transformation backup buffer module and the second-level transformation backup buffer module to determine whether the microcode to be accessed exists in the first-level transformation backup buffer module and the second-level transformation backup buffer module, and obtaining a determination result; Determine the access execution strategy of the microcode to be accessed according to the judgment result; Obtaining the data space idle coefficient and data access coefficient of the first-level data cache module, comparing the coefficient with a threshold, and then adjusting the access parameter, including: Dividing the cache space of the first-level data cache module to obtain a plurality of divided spaces; Acquire access information of the first-level data cache module, and calculate the idle data space coefficient of the first-level data cache module according to the access information; Acquire access check information of the first-level transformation backup buffer module, the second-level transformation backup buffer module and the system memory, and calculate data access coefficients of the system memory, the second-level transformation backup buffer module and the first-level transformation backup buffer module in sequence according to the access check information; Comparing the data access coefficient of the system memory with a preset data access threshold of the system memory to obtain a system memory comparison result; Moving the microcode in the system memory to the second-level transformation lookaside buffer module or the first-level transformation lookaside buffer module according to the system memory comparison result; Comparing the data access coefficient of the second-level transform backup buffer module with the preset data access threshold of the second-level transform backup buffer module to obtain a comparison result of the second-level transform backup buffer module; According to the comparison result of the second-level transform lookaside buffer module, the microcode in the second-level transform lookaside buffer module is moved to the first-level transform lookaside buffer module; Comparing the data access coefficient of the first-level transformation backup buffer module with the preset data access threshold of the first-level transformation backup buffer module to obtain a comparison result of the first-level transformation backup buffer module; The microcode in the first-level transformation lookaside buffer module is moved to the first-level data cache module according to the comparison result of the first-level transformation lookaside buffer module.

8. The memory reading method of the processor according to claim 7, characterized in that: Access checking is performed on the first-level transformation backup buffer module and the second-level transformation backup buffer module to determine whether the microcode to be accessed exists in the first-level transformation backup buffer module and the second-level transformation backup buffer module, and obtaining a determination result, including: After the processor starts to access the microcode, the processor performs access check on the first-level conversion backup buffer module and the second-level conversion backup buffer module used for the microcode simulation memory; It is determined whether there is a microcode corresponding to the access in the first-level transformation lookaside buffer module and the second-level transformation lookaside buffer module.

9. The memory reading method of the processor according to claim 7, characterized in that: Determine the access execution strategy of the microcode to be accessed according to the judgment result, including: If the microcode to be accessed exists in the first-level transform lookaside buffer module, the core of the processor accesses the first-level data cache module according to the location of the corresponding microcode, and the check of the second-level transform lookaside buffer module is terminated or ignored; If the microcode to be accessed does not exist in the first-level transformation backup buffer module, according to the result of the second-level transformation backup buffer module check, if the result of the second-level transformation backup buffer module check indicates a hit, the data of the hit microcode to be accessed is copied from the second-level data cache module back to the first-level data cache module, and the first-level transformation backup buffer module is updated; if the result of the second-level transformation backup buffer module check indicates no hit, the microcode to be accessed is accessed from the system memory and then the data is copied back to the first-level data cache module; After the data is copied, the core of the processor accesses the first-level data cache module according to the location corresponding to the microcode to be accessed.

10. The memory reading method of the processor according to claim 7, characterized in that: Obtaining the data space idle coefficient and data access coefficient of the first-level data cache module, comparing the coefficient with a threshold, and then adjusting the access parameter, further comprising: The calculation formula of the idle data space coefficient is: ； Among them, L kj is the idle data space coefficient, C zr is the total cache space, n is the total number of partitioned spaces, D sli is the amount of data space used in the i-th partition, C xli is the storage efficiency of the i-th partition space, D oi is the metadata space of the ith partition, m is the number of independent regions affected by data fragmentation, and W kla is the amount of additional unused space in the ath independent region due to data fragmentation; The calculation formula of the data access coefficient of the system memory is: ； Among them, N c is the data access coefficient of the system memory, Q c is the number of microcode fetches from system memory, C r The number of times the microcode is stored in the system memory; The calculation formula of the data access coefficient of the second-level transformation backup buffer module is: ； Among them, R c is the data access coefficient of the second-level transform backup buffer module, U c is the number of microcode fetches from the second-level transform backup buffer module, T r is the number of microcode storage times of the second-level transform backup buffer module, N y is the preset data access threshold of the system memory; The calculation formula of the data access coefficient of the first-level transformation backup buffer module is: ； Among them, Y c is the data access coefficient of the first-level transform backup buffer module, W c is the number of microcode fetches from the first-level transform lookaside buffer module, M r is the number of microcode storage times of the first-level transformation backup buffer module, N y is the preset data access threshold of the system memory, R y It is the preset data access threshold of the second-level transformation backup buffer module.

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