Chip system-level verification system

Abstract

The present invention relates to the field of chip technology, and in particular to a chip system-level verification system, comprising a python script set in a first verification module and a design under test set in a second verification module; the python script sets the first verification module as a slave device and sets the second verification module as a master device; the first verification module generates a python script main thread and N+1 slave device channels, creates N+1 python script sub-threads in the python script main thread, registers an interrupt service function according to an interrupt number in the first verification module, and registers a read-write request service function according to a slave device channel ID; the python script main thread starts a verification platform simulation thread and establishes a connection; the python script main thread receives a verification request instruction and distributes it to a corresponding python script sub-thread to process the verification request instruction. The present invention improves the efficiency of chip system-level verification.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip system-level verification system. Background Art

[0002] Chip system-level verification refers to the verification of the coordination and cooperation between the design under test (DUT) and the software. When using traditional technology to perform chip system-level verification, it is necessary to attach the IP (Intellectual Property) or model of a specific CPU, write related software, and compile it using a compiler that supports a specific instruction set. In this traditional process, hardware design engineers, model development engineers, and driver software engineers need to work together to complete it. For some special protocols, specific stimulus modules or models need to be written. It can be seen that the traditional chip system-level verification method is difficult, the verification process is complicated, the verification efficiency is low, and the personnel investment cost is high. It can be seen that how to simplify the chip system-level verification process, improve the chip system-level verification efficiency, and reduce the verification cost has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The present invention aims to provide a chip system-level verification system, which simplifies the chip system-level verification process, improves the chip system-level verification efficiency, and reduces the chip system-level verification cost.

[0004] According to one aspect of the present invention, a chip system-level verification system is provided.

[0005] It includes: a first verification module and a second verification module, wherein the first verification module includes a preset python script, and the second verification module includes a design under test;

[0006] The preset python script includes a verification process, in which the first verification module is set as a slave device, and the second verification module is set as a master device;

[0007] The first verification module is used to generate a Python script main thread and N+1 slave device channels {R0, R1, R2, ..., R n ,…,R N}, the python script main thread creates N+1 python script sub-threads {D0, D1, D2, ..., D n ,…,D N}, where R0 is the slave device interrupt channel, R n is the nth slave device read and write service channel, D0 is the python script interrupt subthread, D nThe nth python script read and write service subthread, n ranges from 1 to N, D0 is used to serve R0, D n For serving R n , the python script main thread is also used to register an interrupt service function according to the interrupt number in the first verification module, and to register a read / write request service function according to the slave device channel ID, and to start N+1 python script sub-threads;

[0008] The python script main thread is also used to send a start verification platform simulation thread instruction to the second verification module, start the verification platform simulation thread in the second verification module, and establish a connection between the python script main thread and the verification platform simulation thread, thereby establishing a connection between the first verification module and the second verification module;

[0009] The python script sub-thread is used to receive the verification request instruction sent by the second verification module to the first verification module, process the verification request instruction through the registered interrupt service function or read-write request service function, and send the data required by the verification request instruction back to the first verification module, and the corresponding python script sub-thread feeds back the processing result to the python script main thread.

[0010] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the chip system-level verification system provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0011] The system of the present invention constructs a verification process based on a python script, sets the device to be tested as the master device, sets the preset python script side as the slave device, simulates the slave device behavior based on the preset python script, and implements the chip system-level verification process based on the verification process in the preset python script, thereby simplifying the chip system-level verification process, improving the chip system-level verification efficiency, and reducing the chip system-level verification cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A schematic diagram of a chip system-level verification system provided by an embodiment of the present invention;

[0014] Figure 2 A schematic diagram of the flow of communication between a Python script main thread and a verification platform simulation thread provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0016] The embodiment of the present invention provides a chip system-level verification system, such as Figure 1 As shown, it includes: a first verification module and a second verification module, wherein the first verification module includes a preset python script, and the second verification module includes a design under test. The preset python script includes a verification process, in which the first verification module is set as a slave device, and the second verification module is set as a master device.

[0017] The first verification module is used to generate a Python script main thread and N+1 slave device channels {R0, R1, R2, ..., R n ,…,R N}, the python script main thread creates N+1 python script sub-threads {D0, D1, D2, ..., D n ,…,D N}, where R0 is the slave device interrupt channel, R n is the nth slave device read and write service channel, D0 is the python script interrupt subthread, D n The nth python script read and write service child thread, n ranges from 1 to N, D0 is used to serve R0, D0 is used to serve R0, D n For serving R n , D n For serving R n The python script main thread is also used to register an interrupt service function according to the interrupt number in the first verification module, and to register a read / write request service function according to the slave device channel id, and to start N+1 python script child threads. Subsequently, the corresponding interrupt service function can be called according to the interrupt number in the verification request, and the corresponding read / write request service function can be called according to the slave device channel id in the verification request.

[0018] The python script main thread is also used to send a start verification platform simulation thread instruction to the second verification module, start the verification platform simulation thread in the second verification module, and establish a connection between the python script main thread and the verification platform simulation thread, thereby establishing a connection between the first verification module and the second verification module. The python script sub-thread is used to receive a verification request instruction sent by the second verification module to the first verification module, process the verification request instruction through a registered interrupt service function or a read-write request service function, and send the data required by the verification request instruction back to the first verification module. The corresponding python script sub-thread feeds back the processing result to the python script main thread. The process of communication between the python script main thread and the verification platform simulation thread is as follows: Figure 2 As shown, the verification request instruction includes an interrupt request instruction and / or a read / write register request instruction. Based on the interrupt service function and the read / write request service function registered by the main thread of the python script, the interrupt request and the register read / write request issued by the design under test are received and processed accordingly. When the register read / write request issued by the design under test is received, a corresponding reply is also issued to the design under test.

[0019] It should be noted that the prior art usually requires obtaining a log file to determine whether the simulation platform has successfully completed the simulation. In the present application, the simulation platform is capable of automatically determining the success or failure of the simulation. As an embodiment, when the second verification module completes the simulation process, a simulation completion notification instruction is sent to the first verification module, and the first verification module sets the verification flag to a verification success flag; if the second verification module encounters a verification failure during the execution of the verification process of the preset python script, an abnormal exit process is executed. When the first verification module detects that the second verification module exits abnormally, the verification flag is set to a verification failure flag.

[0020] As an embodiment, the first verification module also includes a storage unit, a first verification control unit and a second verification control unit, wherein the first verification control unit is implemented based on python, and the second verification control unit is implemented based on C++. The second verification control unit is used to receive the instruction parameters sent by the second verification module and store them in the first verification module storage unit; the python script subthread created by the python script main thread controls the first verification control unit to obtain the instruction parameters from the storage unit, and generates a verification request instruction through the interaction between the first verification control unit and the second verification control unit, the python script subthread processes the verification request instruction, and sends the data required by the verification request instruction back to the second verification module through the interaction of the second verification control unit, and the corresponding python script subthread feeds back the processing result to the python script main thread. It can be understood that python and C++ are both existing programming languages, which will not be repeated here.

[0021] As an embodiment, the second verification control unit includes a C++ function, and the first verification control unit encapsulates the C++ function into a python function through C++ and python mixed programming, so as to realize the interaction between the first verification control unit and the second verification control unit. Wherein, the C++ function includes an application programming interface (ApplicationProgramming Interface, referred to as API) function generated based on C++. The first verification module includes a mixed programming library, and the first verification control unit implements C++ and python mixed programming based on the mixed programming library, and the mixed programming library is ctypes or python native C++ library. Wherein, ctypes is an external function library of Python, which provides data types compatible with C language, and allows calling functions in dynamic link library files (Dynamic Link Library, referred to as DLL) or shared libraries, and ctypes can be used to encapsulate these libraries in pure Python form. Python native C++ library is also an existing library, which will not be repeated here.

[0022] As an embodiment, the verification platform simulation thread is used to generate N+1 master device channels {Q0, Q1, Q2, ..., Q n ,…,Q N}, Q0 is the main device interrupt channel, Q n It is the read and write service channel for the nth master device. Q0 corresponds to R0. n and R nIt should be noted that the preset python script can simulate multiple slave devices, each slave device corresponds to a master device channel, and the master device will also set a corresponding number of slave device channels. The number of slave device channels is determined based on the number of master device channels corresponding to the device under test. The interrupt services of the master device and the slave device are implemented through the same channel, so only one interrupt service channel needs to be set.

[0023] As an embodiment, the verification request instruction includes an interrupt request instruction and / or a read-write register request instruction, the interrupt request instruction includes an interrupt number and a slave device interrupt service channel, the read request instruction includes a slave device read-write service channel identifier and a target read address, and the write request instruction includes a slave device read-write service channel identifier, a target write address and a target write data. The verification model is used to obtain the interrupt request instruction sent by the design under test and forward it to the first verification module through the slave device interrupt service channel. The verification model is also used to obtain the read-write register request instruction sent by the design under test and forward it to the first verification module through the corresponding slave device read-write service channel.

[0024] Specifically, for an interrupt request, the first verification module obtains a corresponding interrupt number based on the received interrupt request, and then calls a corresponding interrupt service function based on the interrupt number to perform an interrupt operation.

[0025] For the read register request instruction, the first verification module parses the received read register request instruction to obtain the slave device read / write service channel identifier and the target read address, then reads data from the corresponding target read address through the corresponding slave device channel, and replies to the second verification module.

[0026] For the write register request instruction, the design under test parses the received write register request instruction to obtain the slave device read / write service channel identifier, target write address and target write data, and then writes the target write data to the target write address through the corresponding slave device channel. After the write is successful, the design under test replies to the second verification module to confirm the write success information.

[0027] As an embodiment, when the second verification module sends a simulation completion notification instruction to the first verification module, or exits abnormally, the N+1 master device channels {Q0, Q1, Q2, ..., Q n ,…,Q N}; When the first verification module detects that the second verification module exits abnormally, or receives a simulation notification instruction, it sends a shutdown instruction to the N+1 slave device channels to close the N+1 slave device channels. After the master device channel and the slave device channel are closed, the first verification module and the second verification module are disconnected, and the chip system verification ends.

[0028] As an embodiment, the second verification module also includes a verification model. The system establishes a connection between the second verification control unit and the verification model, and establishes a connection between the python script main thread, the python script sub-thread and the verification platform simulation thread. The verification platform simulation thread controls the verification model to receive the instruction parameters sent by the design under test and forwards them to the second verification control unit. The second verification control unit communicates with the verification model through a communication interface such as TCP / IP, wherein TCP / IP is an existing communication method and will not be described in detail here.

[0029] The design under test can be a design generated based on RTL, or a design model generated based on SystemC. If the design under test is a design generated based on SystemC, the verification model communicates with the design under test through a SystemC interface or a transaction level modeling (TLM) interface. If the design under test is a design model generated based on SystemC, or the design under test is a design model generated based on RTL, the verification model communicates with the design under test through a Direct Programming Interface (DPI) interface or a Device-Kernel Interface (DKI). It should be noted that the SystemC interface, TLM interface, DPI interface and DKI interface are all existing communication interfaces and will not be described in detail here.

[0030] The system described in the embodiment of the present invention constructs a verification process based on a python script, sets the device side to be tested as the master device side, sets the preset python script side as the slave device side, simulates the slave device behavior based on the preset python script, and implements the chip system-level verification process based on the verification process in the preset python script. The chip system-level verification process is simplified, the chip system-level verification efficiency is improved, and the chip system-level verification cost is reduced.

[0031] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A chip system-level verification system, characterized in that: include: A first verification module and a second verification module, wherein the first verification module includes a preset python script, and the second verification module includes a design under test; The preset python script includes a verification process, in which the first verification module is set as a slave device, and the second verification module is set as a master device; The first verification module is used to generate a Python script main thread and N+1 slave device channels {R0, R1, R2, ..., R n ,…,R N }, the python script main thread creates N+1 python script sub-threads {D0, D1, D2, ..., D n ,…,D N }, where R0 is the slave device interrupt channel, R n is the nth slave device read and write service channel, D0 is the python script interrupt subthread, D n The nth python script read and write service subthread, n ranges from 1 to N, D0 is used to serve R0, D n For serving R n , the python script main thread is also used to register an interrupt service function according to the interrupt number in the first verification module, and to register a read / write request service function according to the slave device channel ID, and to start N+1 python script sub-threads; The python script main thread is also used to send a start verification platform simulation thread instruction to the second verification module, start the verification platform simulation thread in the second verification module, and establish a connection between the python script main thread and the verification platform simulation thread, thereby establishing a connection between the first verification module and the second verification module; The python script sub-thread is used to receive the verification request instruction sent by the second verification module to the first verification module, process the verification request instruction through the registered interrupt service function or read-write request service function, and send the data required by the verification request instruction back to the first verification module, and the corresponding python script sub-thread feeds back the processing result to the python script main thread.

2. The system according to claim 1, characterized in that The first verification module further includes a storage unit, a first verification control unit and a second verification control unit, wherein the first verification control unit is implemented based on Python, and the second verification control unit is implemented based on C++; The second verification control unit is used to receive the instruction parameters sent by the second verification module and store them in the first verification module storage unit; The python script sub-thread created by the python script main thread controls the first verification control unit to obtain instruction parameters from the storage unit, and generates a verification request instruction through the interaction between the first verification control unit and the second verification control unit. The python script sub-thread processes the verification request instruction, and sends the data required by the verification request instruction back to the second verification module through the interaction of the second verification control unit. The corresponding python script sub-thread feeds back the processing result to the python script main thread.

3. The system according to claim 2, characterized in that The second verification control unit includes a C++ function, and the first verification control unit encapsulates the C++ function into a python function through C++ and python mixed programming to achieve interaction between the first verification control unit and the second verification control unit.

4. The system according to claim 1, characterized in that The verification platform simulation thread is used to generate N+1 master device channels {Q0, Q1, Q2, ..., Q n ,…,Q N }, Q0 is the main device interrupt channel, Q n It is the read and write service channel for the nth master device. Q0 corresponds to R0. n and R n Corresponding.

5. The system according to claim 4, characterized in that When the second verification module sends a simulation completion notification instruction to the first verification module, or exits abnormally, closes N+1 master device channels {Q0, Q1, Q2, ..., Q n ,…,Q N }; When the first verification module detects that the second verification module exits abnormally, or receives a simulation notification instruction, it sends a closing instruction to the N+1 slave device channels to close the N+1 slave device channels.

6. The system according to claim 2, characterized in that The second verification module also includes a verification model. The system establishes a connection between the python script main thread, the python script sub-thread and the verification platform simulation thread by establishing a connection between the second verification control unit and the verification model. The verification platform simulation thread controls the verification model to receive the instruction parameters sent by the design under test and forward them to the second verification control unit.

7. The system according to claim 6, characterized in that The verification request instruction includes an interrupt request instruction and / or a read / write register request instruction, the interrupt request instruction includes an interrupt number and a slave device interrupt service channel, the read request instruction includes a slave device read / write service channel identifier and a target read address, and the write request instruction includes a slave device read / write service channel identifier, a target write address and a target write data. The verification model is used to obtain the interrupt request instruction sent by the design under test and forward it to the first verification module through the slave device interrupt service channel. The verification model is also used to obtain the read / write register request instruction sent by the design under test and forward it to the first verification module through the corresponding slave device read / write service channel.

8. The system according to claim 1, characterized in that When the second verification module completes the simulation process, it sends a completion simulation notification instruction to the first verification module, and the first verification module sets the verification flag to a verification success flag; If the second verification module fails in the verification process of executing the preset python script, an abnormal exit process is executed. When the first verification module detects that the second verification module exits abnormally, the verification flag is set to a verification failure flag.

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