Temperature adaptive read-write auxiliary circuit and storage chip based on magnetic tunnel junction

Abstract

The present invention belongs to the field of integrated circuits, and specifically relates to a temperature-adaptive read-write assist circuit and a memory chip based on a magnetic tunnel junction. The solution uses FDSOI transistors for all transmission tubes of each memory cell in an SRAM memory array, and when the temperature-adaptive read-write assist circuit performs a read operation or a write operation, it outputs a back-gate bias voltage that rises with the temperature rise to the substrate in the transmission tube of each memory cell in the memory array, wherein the temperature-adaptive read-write assist circuit includes a dynamic voltage source and a read-write assist bias circuit composed of an MTJ and an NMOS; the read-write assist bias circuit divides the output of the dynamic voltage source by using the temperature characteristics of the MTJ in a high-resistance state, thereby obtaining the required back-gate bias voltage. The present invention overcomes the problems of unstable read-write access speed caused by temperature drift in SRAM devices and the influence of leakage current on normal data reading and writing.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and in particular relates to a temperature-adaptive read-write auxiliary circuit and a storage chip based on a magnetic tunnel junction. Background Art

[0002] System on Chip (SOC) has become the main development trend of Very Large Scale Integration (VLSI) because it can integrate microprocessors, analog circuits, interface circuits, etc. on a single chip. At the same time, the chips designed by SOC are more powerful, have lower power consumption, and are smaller in size than traditional integrated circuits. There are many types of memories used in SOC, which can be divided into read-only memory and random access memory according to their functions, and random access memory is widely used due to its random data reading characteristics. According to different storage principles, random access memory can be divided into static random access memory (Static Random Access Memory, SRAM) and dynamic random access memory (Dynamic Random Access Memory, DRAM). SRAM has better stability and lower power consumption due to the high symmetry of its storage unit structure, and has a higher application share due to its high compatibility with standard CMOS processes.

[0003] With the adoption of system-on-chip design, the use of SRAM has greatly increased. At the same time, with the development of process technology, the performance and area density of the system-on-chip have also been significantly improved. The advancement of process technology has also caused the stability of SRAM to become more and more susceptible to environmental influences, and changes in environmental factors have led to functional failures of SRAM units. SRAM failures can be divided into two categories, namely hard failures (failures caused by defects) and soft failures. Among them, the failure of SRAM cells in the process of reading, writing, and retaining data, as well as stability interference during the reading process are all soft failures.

[0004] Technicians have proposed a variety of read-write assist technologies to solve the soft fault problem, such as word line underdrive, negative bit line and lower cell voltage. However, these solutions rarely consider the performance changes caused by temperature drift. Figure 1 As shown in the figure, temperature changes not only cause changes in read and write access time, resulting in performance waste, but in severe cases, may also cause errors in the read and write operations themselves. For example, when the operating temperature of the SRAM changes drastically, it will cause the leakage current to increase, thereby affecting the reliability of the SRAM read and write functions. Summary of the invention

[0005] In order to overcome the problem that the access speed slows down due to temperature drift in SRAM devices and the leakage current affects the normal data reading and writing, the present invention provides a temperature adaptive read-write auxiliary circuit based on a magnetic tunnel junction and a corresponding storage chip.

[0006] The technical solution provided by the present invention is:

[0007] A temperature adaptive read-write auxiliary circuit based on a magnetic tunnel junction is applied to an SRAM circuit in which the transmission tubes of the storage unit all adopt FDSOI type transistors to overcome the leakage current problem of the transmission tubes of the SRAM circuit in the read and write operations.

[0008] The temperature-adaptive read-write assist circuit includes a dynamic voltage source and a read-write assist bias circuit. The dynamic voltage source is connected to the read signal and the write signal of the SRAM circuit, and is used to output a reference voltage signal when receiving a read signal, and to output a boost signal higher than the reference voltage when receiving a write signal. The read-write assist bias circuit is used to synchronously output a back gate bias voltage that rises with the temperature rise to the substrate of the transmission tube of each storage unit in the SRAM circuit during the read-write operation.

[0009] The read-write auxiliary bias circuit includes an NMOS tube N0 and a magnetic tunnel junction MTJ in a high-resistance state. The gate of N0 is connected to the bias voltage Vb, and the source is grounded. The end of the MTJ close to the free layer is connected to the output end of the dynamic voltage source; the end of the MTJ close to the fixed layer is connected to the drain of N0 and serves as the output node of the back gate bias voltage.

[0010] As a further improvement of the present invention, the dynamic voltage source includes a boost circuit and a multi-way selection switch MUX. MUX includes two input terminals IN1 and IN2, two selection terminals Sel1 and Sel2, and an output terminal OUT. The input terminal of the boost circuit and IN1 are connected to VDD. The output terminal of the boost circuit is connected to IN2. Sel1 and Sel2 are respectively connected to the read signal and the write signal of the SRAM circuit. When Sel1 is at a high level, the OUT terminal outputs the input signal of the IN1 terminal, and when Sel2 is at a high level, the OUT terminal outputs the input signal of the IN2 terminal.

[0011] As a further improvement of the present invention, the dynamic voltage source uses the read signal and the write signal as the power supply voltage VDD on the one hand, and uses the read signal and the write signal as the selection signals input to the Sel1 and Sel2 ports of the MUX on the other hand.

[0012] In the dynamic voltage source, MUX is implemented by two transmission gates TG1 and TG2; the input of the boost circuit is connected to the read signal and the write signal as well as the input of TG1. The output of the boost circuit is connected to the input of TG2. The control end of TG1 is connected to the read signal; the control end of TG2 is connected to the write signal. The outputs of TG1 and TG2 are connected and serve as the output of MUX.

[0013] As a further improvement of the present invention, the signal lines of the read signal and the write signal are respectively connected to the dynamic voltage source through the first buffer.

[0014] and / or

[0015] The first buffer is composed of an even number of inverters connected in series.

[0016] As a further improvement of the present invention, the temperature adaptive read / write assist circuit based on the magnetic tunnel junction also includes a step-down circuit, which is used to provide a fixed or adjustable bias voltage Vb lower than the power supply voltage VDD to the read / write assist bias circuit.

[0017] As a further improvement of the present invention, the step-down circuit is composed of a PMOS tube P1 and three NMOS tubes N1 to N3. The drain of N1 and the source of P1 are connected to the gates of P1, N1 and N3 and are connected to the power supply VDD. The source of N1 and the gate of N2 are connected to the drains of N2 and N3. The source of N2 is grounded; the source of N3 is connected to the drain of P1 and serves as the output node of the bias voltage Vb.

[0018] As a further improvement of the present invention, the step-down circuit uses the read signal and the write signal as the gate voltage signals of N1, N3 and P1.

[0019] As a further improvement of the present invention, the read-write assist bias circuit is connected to the substrate of the transmission tube of each storage unit in the SRAM circuit through a second buffer; the second buffer is used to suppress the fluctuation of the output signal of the read-write assist bias circuit.

[0020] As a further improvement of the present invention, when the transistors in the buck circuit and the SRAM circuit are both FDSOI transistors, except for the transmission transistor in the SRAM circuit, the substrates of the remaining NMOS transistors are all grounded, and the substrates of the PMOS transistors are all connected to the power supply voltage.

[0021] A memory chip includes an SRAM memory array using FDSOI transistors as transmission tubes, and is characterized in that it also uses the aforementioned temperature-adaptive read-write auxiliary circuit based on magnetic tunnel junctions.

[0022] The technical solution provided by the present invention has the following beneficial effects:

[0023] The present invention sets the transmission tube in the SRAM circuit as an FDSOI type transistor, and designs a novel read-write auxiliary bias circuit based on a magnetic tunnel junction and an FDSOI type NMOS tube. The read-write auxiliary bias circuit can utilize the temperature characteristics of the MTJ and the FDSOI type NMOS to generate a temperature-adaptive back-gate bias voltage, and output it to the substrate of the transmission tube in the SRAM unit; thereby ensuring that the access speed of the SRAM unit has strong consistency at different temperatures, and overcoming the problems of data read-write errors and performance waste caused by temperature drift.

[0024] The read-write assist circuit in the present invention dynamically adjusts the access speed by applying a substrate bias, which ensures the consistency of the access speed while also reducing the read-write access time to a certain extent, thereby increasing the speed of executing the read-write operation. The read-write assist circuit provided by the present invention also uses a dynamic voltage source and a step-down circuit to expand the voltage swing of the output back gate bias voltage, and enables the circuit to have different outputs during the read-write operation to adapt to the difference in the degree of fluctuation of the temperature effect on the circuit during the read-write operation stage. It is ensured that the SRAM circuit has optimal stability in all operation modes.

[0025] The read-write assist bias circuit provided by the present invention is relatively simple, has small power consumption and area overhead. The temperature-adaptive read-write assist circuit provided by the present invention also uses the read signal and write signal of the SRAM circuit as power supply, so that the read and write operations can be started synchronously, further reducing circuit power consumption and avoiding signal interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram showing the influence of temperature on the read / write access time and quantization accuracy of a 6T SRAM cell introduced in the background technology.

[0027] Figure 2 This is a schematic diagram of a temperature-adaptive read-write assist circuit based on a magnetic tunnel junction provided in Example 1 of the present invention.

[0028] Figure 3 This is a graph showing the relationship between the threshold voltage of the FDSOI type NMOS tube and the back gate bias voltage.

[0029] Figure 4 This is a graph showing the relationship between the threshold voltage of the FDSOI type NMOS tube and temperature.

[0030] Figure 5 This is a graph showing the relationship between the resistance of MTJ and temperature in different resistance states.

[0031] Figure 6 FIG. 4 is a graph showing the relationship between the resistance of the MTJ in the high-resistance state and the bias voltage.

[0032] Figure 74 is an equivalent circuit diagram of the read-write auxiliary bias circuit in Example 1 of the present invention.

[0033] Figure 8 4 is a graph showing the relationship between the output voltage of the read / write auxiliary bias circuit and the temperature in Example 1 of the present invention.

[0034] Fig. 9 This is a circuit schematic diagram of the dynamic voltage source used in Example 1 of the present invention.

[0035] Fig.10 It is a schematic diagram of the circuit connection of the dynamic voltage source used in Example 1 of the present invention.

[0036] Fig.11 is a circuit diagram of the dynamic voltage source used in Example 1 of the present invention.

[0037] Fig.12 This is a schematic diagram of a temperature-adaptive read-write assist circuit based on a magnetic tunnel junction using a first buffer in Embodiment 1 of the present invention.

[0038] Fig.13 4 is a schematic diagram of a temperature-adaptive read-write assist circuit including a voltage-reducing circuit in Embodiment 1 of the present invention.

[0039] Fig.14 4 is a circuit diagram of the step-down circuit used in Example 1 of the present invention.

[0040] Fig.15 4 is a schematic diagram of a temperature adaptive read / write assist circuit including a second buffer in Embodiment 1 of the present invention.

[0041] Fig.16 To verify the read and write access time comparison of the 6T SRAM cell before and after using the auxiliary circuit in the experiment.

[0042] Fig.17 To verify the read and write access time box plot of the SRAM circuit under wide temperature scanning before and after using the auxiliary circuit at different process angles in the experiment.

[0043] Fig.18 To verify the Monte Carlo simulation results of the read and write access time of the SRAM circuit under various temperature conditions after using the auxiliary circuit in the experiment.

[0044] Fig.19 The graph shows the relationship between the write noise tolerance and write margin of a 6T SRAM cell and the temperature before and after using the auxiliary circuit of the present invention. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0046] Example 1

[0047] In view of the problem that the access speed of traditional SRAM circuits is stable under drastic temperature changes, and read and write errors may occur due to leakage current, this embodiment provides a temperature-adaptive read and write auxiliary circuit based on a magnetic tunnel junction, which is applied to an SRAM circuit in which the transmission tubes of the storage unit all use FDSOI type transistors to overcome the leakage current problem of the transmission tubes of the SRAM circuit during read and write operations.

[0048] Specifically, the solution provided by this embodiment includes two parts: Figure 2 As shown, first, all the transmission tubes of each storage unit in the SRAM storage array are FDSOI type transistors. Second, a temperature-adaptive read-write auxiliary circuit is designed, and when the SRAM circuit performs a read operation or a write operation, the temperature-adaptive read-write auxiliary circuit outputs a back gate bias voltage that increases with the temperature rise to the substrate in the transmission tube of each storage unit in the SRAM storage array. The principle that this embodiment can solve the read and write errors caused by the temperature drift of SRAM is as follows:

[0049] In SRAM circuits, the leakage current of the transmission tube changes dramatically with the ambient temperature, which is the main cause of read and write errors. In this embodiment, the transmission tube is set as an FDSOI transistor. According to the electrical characteristics of the FDSOI transistor, the leakage current of the transmission tube I D It can be expressed as:

[0050]

[0051] in, is the mobility, C OX is the gate oxide capacitance; W is the channel width, L is the channel length; V GS is the gate-source voltage, V TH Represents the threshold voltage. By analyzing the temperature characteristics of various factors affecting the leakage current of the transmission tube, it can be seen that the mobility is the main factor affected by temperature. and threshold voltage V TH, while mobility decreases with increasing temperature, and threshold voltage increases with increasing temperature. Among the two, the change in mobility plays a dominant role. Mobility decreases with increasing temperature, so leakage current decreases with increasing temperature, which causes read and write access time to increase with increasing temperature, and read and write errors occur when the threshold of temperature change is exceeded.

[0052] In this embodiment, by applying a back-gate bias voltage that changes with temperature to the substrate of the FDSOI type transmission tube, the sensitivity of the transistor threshold voltage to temperature can be further increased, so that the threshold voltage is further reduced as the temperature increases, thereby resisting the change in leakage current caused by the change in mobility. At the same time, for FDSOI type transistors, applying a back-gate bias voltage will increase the leakage current while reducing the threshold voltage of the transistor, thereby improving the speed of the transmission tube, ultimately shortening the access time of the SRAM circuit and reducing the probability of read and write errors.

[0053] In detail, the temperature-adaptive read-write assist circuit provided in this embodiment includes a dynamic voltage source and a read-write assist bias circuit. The dynamic voltage source is connected to the read signal and the write signal of the SRAM circuit, and is used to output a reference voltage signal when receiving a read signal, and to output a boost signal higher than the reference voltage when receiving a write signal. The read-write assist bias circuit uses the output of the dynamic voltage source as the power supply voltage, and is used to synchronously output a back gate bias voltage that rises with the temperature rise to the substrate of the transmission tube of each storage unit in the SRAM circuit during the read and write operations.

[0054] In this embodiment, the designed read / write auxiliary bias circuit capable of generating a temperature-adaptive back-gate bias voltage is composed of an NMOS tube N0 and a magnetic tunnel junction MTJ. The gate of N0 is connected to the bias voltage Vb, and the source is grounded. The end of the MTJ close to the free layer is connected to the output end of the dynamic voltage source; the end of the MTJ close to the fixed layer is connected to the drain of N0 and serves as the output node of the back-gate bias voltage.

[0055] The magnetic tunnel junction has two resistance states: low resistance state and high resistance state. In the two resistance states, the corresponding resistance value has different change relationships with temperature. Among them, the resistance value of the magnetic tunnel junction in the low resistance state is less affected by temperature, and the resistance value of the magnetic tunnel junction in the high resistance state is more affected by temperature, and the resistance value decreases with the increase of temperature. In the design of this embodiment, the read-write auxiliary bias circuit adopts a circuit connection state that makes the magnetic tunnel junction in a high resistance state, and then cooperates with the FDSOI type NMOS tube whose threshold voltage decreases with the increase of temperature, and utilizes the temperature characteristics of the two to achieve different bias voltages required for adaptive output at different temperatures.

[0056] In detail, the principle that the read / write assist bias circuit provided in this embodiment can output a bias voltage with temperature adaptive characteristics is introduced below:

[0057] Figure 3-6 The electrical characteristics of the magnetic tunnel junction and NMOS tube are shown in Figure 1. Figure 3 As can be seen from the figure, for NMOS transistors, when the temperature is constant, the threshold voltage of the transistor decreases as the back gate bias voltage increases. At the same time, the threshold voltage is also different under different transistor sizes (here the size specifically refers to the gate length of the transistor, and the gate width uses the same fixed value). Figure 4 It can be seen that under the influence of temperature, the threshold voltage of the NMOS tube will decrease as the temperature increases, and the smaller the size of the transistor, the smaller the threshold voltage of the transistor under the same conditions. Figure 5 and Figure 6 The two resistance states of the magnetic tunnel junction are affected by temperature, and the resistance in the high resistance state is affected by temperature and bias voltage. Obviously, the resistance of the magnetic tunnel junction in the high resistance state is more easily affected by temperature, so after the magnetic tunnel junction is adjusted to the high resistance state in the read-write auxiliary bias circuit of this embodiment, its resistance will be affected by both the ambient temperature and the bias voltage at both ends; and the temperature effect can be made greater by adjusting the bias voltage range.

[0058] The equivalent circuit model of the read-write auxiliary bias circuit designed in this embodiment is as follows: Figure 7 As shown, R1 represents the equivalent resistance of MTJ, and R2 represents the equivalent resistance of NMOS tube N0. Further combining the above electrical characteristics of the two components contained therein, the equivalent resistance of FDSOI type NMOS tube N0 in the read-write auxiliary bias circuit is obtained. R eq It can be expressed as:

[0059]

[0060] in, W is the channel width, L is the channel length; V sat is the speed saturation voltage; is the channel length modulation coefficient; V DD is the power supply voltage; V TH is the threshold voltage; K It is a process parameter, which is mainly related to mobility.

[0061] In the above expression, the two parameters K and V_TH in N0 are greatly affected by temperature, and among the two, K is the most affected by temperature, so the change trend of the equivalent resistance is mainly related to K, and K will decrease with the increase of temperature, so the resistance value of the equivalent resistance will increase with the increase of temperature. At the same time, the resistance value of the magnetic tunnel junction in the high resistance state will decrease with the increase of temperature, so the resistance value proportion of R2 in the resistance equivalent model will increase with the increase of temperature, so that more partial pressure is applied to R2, so, if Figure 8 As shown, the bias voltage output by the read / write auxiliary bias circuit in this embodiment increases with the increase of temperature, which just meets the requirement of the back gate bias voltage output to the substrate of the FDSOI type transmission tube in the temperature drift control of the SRAM circuit.

[0062] In addition, considering that the degree of fluctuation of the read and write operations is different when the SRAM unit is affected by temperature, this embodiment provides different power supply voltages for the read-write auxiliary bias circuit through a dynamic voltage source in the read operation stage and the write operation stage, so that the back gate bias voltage change in the two stages matches the nonlinear change of the leakage current; the output voltage of the read-write auxiliary bias circuit under the write operation is increased, so that the write operation obtains better stability.

[0063] The dynamic voltage source in this embodiment needs to be able to provide power supply voltages of different magnitudes during read and write operations, which can be achieved through a variety of different circuit structures. Fig. 9 As shown, in a typical dynamic voltage source provided in this embodiment, a boost circuit and a multi-way selection switch MUX are included. Among them, MUX includes two input terminals IN1 and IN2, two selection terminals Sel1 and Sel2, and an output terminal OUT. The function table of the circuit is as follows:

[0064] Table 1: Logic function table of multiplexer MUX

[0065]

[0066] In this embodiment, the input end of the boost circuit and IN1 are connected to VDD. The output end of the boost circuit is connected to IN2. Sel1 and Sel2 are respectively connected to the read signal and the write signal of the SRAM circuit. The OUT end outputs the input signal of the IN1 end when Sel1 is at a high level, and outputs the input signal of the IN2 end when Sel2 is at a high level. That is, the dynamic voltage source is used to output the low power supply voltage before boosting during the read operation, and output the higher power supply voltage after boosting during the write operation.

[0067] In the more optimized solution of this embodiment, Fig.10As shown, on the one hand, the read signal and the write signal are used as the power supply voltage VDD of the dynamic voltage source, and on the other hand, the read signal and the write signal are used as the selection signals input to the Sel1 and Sel2 ports in the MUX respectively. In this circuit connection state, the dynamic voltage source and the read / write auxiliary bias circuit will only be started when the SRAM circuit performs a read / write operation and generates a read / write signal, and in other stages, the dynamic voltage source and the read / write auxiliary bias circuit are turned off, which can not only reduce the power consumption of the circuit, but also avoid generating interference signals in other stages.

[0068] Specifically, Fig.11 As shown, the MUX in the dynamic voltage source with the above functions can be implemented by two transmission gates TG1 and TG2. Among them, the input end of the boost circuit is connected to the read signal and the write signal and the input end of TG1 at the same time. The output end of the boost circuit is connected to the input end of TG2. The control end of TG1 is connected to the read signal; the control end of TG2 is connected to the write signal. The output ends of TG1 and TG2 are connected and serve as the output of MUX.

[0069] It should be additionally explained that in this embodiment, the function of the boost circuit is only to increase the power supply voltage VDD input to the read-write auxiliary bias circuit, which can be achieved through a variety of different types of boost circuits. This embodiment has no restrictions on the type of boost circuit used.

[0070] To overcome Fig.11 In order to solve the signal quality problems that may exist when the read signal and the write signal are directly used as the power supply voltage in the circuit, in this embodiment, the signal lines of the read signal and the write signal are respectively connected to the dynamic voltage source through the first buffer. Specifically, in this embodiment, if Fig.12 As shown, the first buffer is composed of an even number of inverters connected in series. Of course, in other embodiments, the first buffer can also be implemented by other functional circuits with the same function.

[0071] In a further optimized solution of this embodiment, Fig.13As shown, the temperature-adaptive read-write auxiliary circuit based on the magnetic tunnel junction also includes a step-down circuit, which is used to provide a fixed or adjustable bias voltage Vb lower than the power supply voltage VDD to the read-write auxiliary bias circuit. Combined with the previous content, it can be seen that the back gate bias voltage with temperature-adaptive characteristics output by the read-write auxiliary bias circuit to the SRAM circuit is obtained by dividing the power supply voltage by MTJ and N0. Therefore, the magnitude of the power supply voltage determines the upper limit of the output back gate bias voltage, and the controllable bias voltage Vb provided by the step-down circuit in this embodiment can be used to adjust the lower limit of the back gate bias voltage output by the read-write auxiliary bias circuit. That is, the dynamic voltage source and the step-down circuit are used together to obtain a larger output voltage without reducing the output voltage swing, thereby effectively improving the read and write access speed of the SRAM unit.

[0072] In the solution of this embodiment, the bias voltage Vb can be realized by a fixed output buck circuit, or by a buck circuit that can be autonomously regulated. This embodiment does not limit the specific type of the buck circuit. Fig.14 As shown, in the typical solution provided by this embodiment, the step-down circuit is composed of a PMOS tube P1 and three NMOS tubes N1~N3. The drain of N1 and the source of P1 are connected to the gates of P1, N1 and N3 and connected to the power supply VDD. The source of N1 and the gate of N2 are connected to the drains of N2 and N3. The source of N2 is grounded; the source of N3 is connected to the drain of P1 and serves as the output node of the bias voltage Vb.

[0073] Fig.14 The basic principle of the buck circuit is: when the input signal is high, all NMOS are in the on state and PMOS is in the off state. At this time, the N2 tube will form a path to the ground for discharge, but due to the existence of the power supply voltage and the lossy transmission high-level characteristics of NMOS itself, the output signal will not be discharged to 0, but a stable output voltage after buck processing will be generated.

[0074] In a more optimized solution of this embodiment, the buck circuit can also use the read signal and the write signal as the gate voltage signal of N1, N3 and P1 like the dynamic voltage source, so that the buck circuit is only started when the SRAM circuit performs read and write operations, thereby achieving the technical effect of reducing power consumption and preventing signal interference.

[0075] In addition, if Fig.15 As shown, the read-write assist bias circuit provided in this embodiment is also connected to the substrate of the transmission tube of each storage unit in the SRAM circuit through a second buffer; the second buffer is used to suppress the fluctuation of the output signal of the read-write assist bias circuit.

[0076] Finally, it should be emphasized that the temperature-adaptive read-write assist circuit based on magnetic tunnel junction provided in this embodiment requires that the transmission tube in the SRAM circuit to be applied adopts FDSOI type NMOS tube. In the temperature-adaptive read-write assist circuit based on magnetic tunnel junction provided in this embodiment and the SRAM circuit applied thereto, in addition to the transmission tube, a large number of other transistors are also included. In the manufacturing of integrated circuit products, in order to reduce the process difficulty and improve the product yield, the same type of components usually adopt the same process. Therefore, the SRAM circuit in this embodiment and the MOS tube in the temperature-adaptive read-write assist circuit based on magnetic tunnel junction can all adopt FDSOI type transistors. When all transistors adopt FDSOI type transistors, except for the transmission tube in the SRAM circuit, the substrates of the remaining FDSOI type NMOS tubes are all grounded, and the substrates of the FDSOI type PMOS tubes are all connected to the power supply voltage.

[0077] Of course, all transistors are FDSOI transistors only to meet the requirements of existing integrated circuit manufacturing processes, and do not constitute a further limitation on the circuit solution provided in this embodiment.

[0078] Example 2

[0079] On the basis of the scheme in Example 1, this embodiment further provides a memory chip, which includes an SRAM memory array using FDSOI transistors as transmission tubes, and the memory chip uses a temperature-adaptive read-write auxiliary circuit based on a magnetic tunnel junction as in Example 1. In addition, a back gate bias voltage with temperature-adaptive characteristics is output to the substrate of the transmission tube in the memory array during the read-write operation. This overcomes the problem of slow access speed caused by temperature drift in SRAM devices and leakage current affecting normal data reading and writing.

[0080] Verification experiment

[0081] In order to verify the performance of the technical solution provided by the present invention, the technicians used a 0.8V power supply voltage under a 22nm FDSOI process, took a 6T-SRAM circuit as the application object, and carried out circuit simulation and comparative tests on SRAM circuits using the solution of the present invention and those not using the solution of the present invention, and sorted and analyzed the experimental data:

[0082] 1. Access speed

[0083] This embodiment first tests the read and write access time of the two schemes under different process angles, and the temperature range of the test process is 230 K to 370 K. The selected process angles are: fast NMOS and fast PMOS (Fast NMOSFast PMOS, FF), slow NMOS and slow PMOS (Slow NMOS Slow PMOS, SS), fast NMOS and slow PMOS (Fast NMOS Slow PMOS, FS), slow NMOS and fast PMOS (Slow NMOS Fast PMOS, SF).

[0084] Fig.16 The read and write access time of the 6T SRAM cell before and after using the auxiliary circuit; Fig.17 Shows the box plot of read and write access time for wide temperature scan at different process corners. Fig.16 and Fig.17 It can be found from the data in that the read and write access time of the SRAM circuit is significantly shortened after using the auxiliary circuit of the present invention.

[0085] 2. Stability

[0086] first, Fig.16 and Fig.17 In addition to reflecting the improvement in read and write access speed, it also further reflects the improvement in stability. Especially in the SF and SS process corners, this improvement in stability is more obvious.

[0087] Furthermore, this experiment also tests the Monte Carlo simulation results of the read and write access time of the circuit under various temperature conditions to evaluate the stability of the circuit. The temperature of the experimental process was selected as 230K, 300K and 370K, and the number of Monte Carlo simulations was 5000. The test results are as follows Fig.18 As shown:

[0088] analyze Fig.18 From the data, we can see that the Monte Carlo results under all temperature conditions conform to the standard normal distribution. This distribution result fully shows that after using the read-write assist circuit, the SRAM circuit has better read-write access stability in all test temperature ranges.

[0089] 3. Noise tolerance

[0090] This experiment further analyzes the relationship between the write noise tolerance and write margin of the 6T SRAM cell and the temperature before and after using the present invention. The experimental data obtained are as follows Fig.19 shown.

[0091] It can be seen from the figure that after using the present invention, the write margin and write noise tolerance of the SRAM unit are greatly improved; and stable performance is maintained at different temperatures.

[0092] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A temperature-adaptive read-write assist circuit based on a magnetic tunnel junction, characterized in that: It is applied to an SRAM circuit in which the transmission tubes of the storage unit all adopt FDSOI type transistors, and the temperature adaptive read-write auxiliary circuit includes a dynamic voltage source and a read-write auxiliary bias circuit; Wherein, the dynamic voltage source is connected to the read signal and the write signal of the SRAM circuit, and is used to output a reference voltage signal when receiving a read signal, and output a boost signal higher than the reference voltage when receiving a write signal; The read-write auxiliary bias circuit is used to synchronously output a back gate bias voltage that rises with the temperature to the substrate of the transmission tube of each storage unit in the SRAM circuit during the read-write operation; the read-write auxiliary bias circuit includes an NMOS tube N0 and a magnetic tunnel junction MTJ in a high-resistance state; the gate of N0 is connected to the bias voltage Vb, and the source is grounded; one end of the MTJ close to the free layer is connected to the output end of the dynamic voltage source, and one end of the MTJ close to the fixed layer is connected to the drain of N0 and serves as the output node of the back gate bias voltage.

2. The temperature-adaptive read / write assist circuit based on magnetic tunnel junction according to claim 1, characterized in that: The dynamic voltage source includes a boost circuit and a multi-way selection switch MUX; MUX includes two input terminals IN1 and IN2, two selection terminals Sel1 and Sel2, and an output terminal OUT; the input terminal and IN1 of the boost circuit are connected to VDD; the output terminal of the boost circuit is connected to IN2; Sel1 and Sel2 are respectively connected to the read signal and the write signal of the SRAM circuit; the OUT terminal outputs the input signal of the IN1 terminal when Sel1 is at a high level, and outputs the input signal of the IN2 terminal when Sel2 is at a high level.

3. The temperature-adaptive read / write assist circuit based on magnetic tunnel junction according to claim 2, characterized in that: The dynamic voltage source uses the read signal and the write signal as the power supply voltage VDD on the one hand, and uses the read signal and the write signal as the selection signals input to the Sel1 and Sel2 ports of the MUX respectively on the other hand; In the dynamic voltage source, MUX is implemented using two transmission gates TG1 and TG2; wherein the input end of the boost circuit is simultaneously connected to the read signal and the write signal as well as the input end of TG1; the output end of the boost circuit is connected to the input end of TG2; the control end of TG1 is connected to the read signal; the control end of TG2 is connected to the write signal; the output ends of TG1 and TG2 are connected and serve as the output of MUX.

4. The temperature-adaptive read / write assist circuit based on magnetic tunnel junction according to claim 3, characterized in that: The signal lines of the read signal and the write signal are respectively connected to the dynamic voltage source through a first buffer; and / or The first buffer is composed of an even number of inverters connected in series.

5. The temperature-adaptive read / write assist circuit based on magnetic tunnel junction according to claim 1, characterized in that: It also includes a step-down circuit, which is used to provide a fixed or adjustable bias voltage Vb lower than the power supply voltage VDD to the read-write auxiliary bias circuit.

6. The temperature adaptive read / write assist circuit based on magnetic tunnel junction according to claim 5, characterized in that: The step-down circuit is composed of a PMOS tube P1 and three NMOS tubes N1~N3; the drain of N1 and the source of P1 are connected to the gates of P1, N1 and N3 and connected to the power supply VDD; the source of N1 and the gate of N2 are connected to the drains of N2 and N3; the source of N2 is grounded; the source of N3 is connected to the drain of P1 and serves as the output node of the bias voltage Vb.

7. The temperature-adaptive read / write assist circuit based on magnetic tunnel junction according to claim 6, characterized in that: The step-down circuit uses the read signal and the write signal as gate voltage signals of N1, N3 and P1.

8. The temperature-adaptive read / write assist circuit based on magnetic tunnel junction according to claim 7, characterized in that: The read-write assist bias circuit is connected to the substrate of the transmission tube of each storage unit in the SRAM circuit through a second buffer; the second buffer is used to suppress the fluctuation of the output signal of the read-write assist bias circuit.

9. The temperature-adaptive read / write assist circuit based on magnetic tunnel junction according to claim 6, characterized in that: When the transistors in the step-down circuit and the SRAM circuit are both FDSOI transistors, except for the transmission transistor in the SRAM circuit, the substrates of the remaining NMOS transistors are all grounded, and the substrates of the PMOS transistors are all connected to the power supply voltage.

10. A memory chip comprising an SRAM memory array using FDSOI transistors as transmission transistors, characterized in that: It also adopts a temperature-adaptive read-write assist circuit based on a magnetic tunnel junction as described in any one of claims 1-9.

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