Semiconductor structure and method of forming the same

Abstract

The present disclosure relates to a semiconductor structure and a method of forming the same. The semiconductor structure includes a substrate having a plurality of conductive interconnection layers arranged along a first direction in the substrate, a projection of at least a topmost conductive interconnection layer on a top surface of the substrate is annular, and the first direction is perpendicular to the top surface of the substrate; a dielectric layer on the top surface of the substrate, the dielectric layer having a trench extending through the dielectric layer along the first direction and aligned with the topmost conductive interconnection layer, a projection of the trench on the top surface of the substrate is annular, and a bottom of the trench along the first direction exposes the topmost conductive interconnection layer; and a conductive contact layer continuously covering an inner wall of the trench and a top surface of the dielectric layer, and the conductive contact layer is electrically connected with the topmost conductive interconnection layer. The present disclosure reduces the capacitive coupling effect inside the semiconductor structure, and improves the performance and manufacturing yield of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Throughout IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component that can be produced using a manufacturing process) has continued to decrease. In addition to smaller and more complex IC components, the wafers on which ICs are manufactured have become increasingly larger, making increasing the integration density of semiconductor devices a key development direction.

[0003] As semiconductor structures continue to shrink in size, the distance between conductive components within the semiconductor continues to shrink, leading to an increasing parasitic capacitance effect within the semiconductor structure. This leads to increasingly serious leakage problems within the semiconductor structure, hindering further improvements in semiconductor structure performance and manufacturing yield. For example, in a semiconductor structure, by providing a plurality of through-holes and conductive contact structures located within the through-holes to lead signals from or into the conductive interconnect layer, this results in high parasitic capacitance between the conductive contact structures and the conductive interconnect layer, resulting in poor performance of the semiconductor structure.

[0004] Therefore, how to reduce the parasitic capacitance effect inside the semiconductor structure, thereby improving the performance and manufacturing yield of the semiconductor structure, is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are used to reduce parasitic capacitance effects within the semiconductor structure and improve the performance and manufacturing yield of the semiconductor structure.

[0006] According to some embodiments, the present disclosure provides a semiconductor structure comprising:

[0007] A substrate having a plurality of conductive interconnect layers arranged along a first direction, wherein the first direction is perpendicular to a top surface of the substrate;

[0008] a dielectric layer located on the top surface of the substrate, wherein the dielectric layer comprises a groove penetrating the dielectric layer at least along the first direction and aligned with the topmost conductive interconnect layer, wherein the projection of the groove on the top surface of the substrate is annular, and at least the topmost conductive interconnect layer comprises an extension extending along the bottom of the groove, and the bottom of the groove along the first direction exposes the topmost conductive interconnect layer;

[0009] A conductive contact layer continuously covers the inner wall of the trench and the top surface of the dielectric layer, and the conductive contact layer is electrically connected to the topmost conductive interconnection layer.

[0010] In some embodiments, a projection of the extension portion in at least the topmost conductive interconnect layer on the top surface of the substrate is ring-shaped.

[0011] In some embodiments, the number of the conductive interconnect layers is N, the N conductive interconnect layers are arranged in sequence along a direction from the top surface of the substrate to the bottom surface of the substrate, any two adjacent conductive interconnect layers are electrically connected, and the bottom surface of the substrate is opposite to the top surface of the substrate along the first direction;

[0012] Each of the first to Mth conductive interconnect layers includes the extending portion extending along the bottom of the trench, N and M are both positive integers, and N≥M.

[0013] In some embodiments, a projection of the trench on the top surface of the substrate is located within a projection of the extension in each of the first to Mth conductive interconnect layers on the top surface of the substrate.

[0014] In some embodiments, the dielectric layer includes a plurality of grooves distributed in a direction parallel to the top surface of the substrate, and the extensions in the conductive interconnect layers from the 1st layer to the Mth layer extend along the bottoms of the plurality of grooves, respectively.

[0015] In some embodiments, the conductive contact layer is in direct electrical contact with the extension portion in the topmost conductive interconnect layer.

[0016] In some embodiments, further comprising:

[0017] An air gap is located in the trench, and the conductive contact layer is distributed around the periphery of the air gap.

[0018] In some embodiments, further comprising:

[0019] The identification structure is located in the dielectric layer and outside the groove.

[0020] In some embodiments, the marking structure is located at an edge of the dielectric layer, and the marking structure is a cut that penetrates the dielectric layer at least along the first direction and exposes the topmost conductive interconnect layer.

[0021] In some embodiments, a projection of the groove on the top surface of the substrate is a square ring shape, and the identification structure is located at a corner of the square ring-shaped groove.

[0022] In some embodiments, further comprising:

[0023] An insulating covering layer is located above the conductive contact layer, and the insulating covering layer includes a contact opening, wherein the contact opening exposes the conductive contact layer located on the top surface of the dielectric layer.

[0024] In some embodiments, the substrate includes a device layer, the device layer being located below the bottommost conductive interconnect layer;

[0025] There is no conductive material between the conductive contact layer and the device layer on the top surface of the dielectric layer.

[0026] In some embodiments, the device layer includes a control circuit;

[0027] A projection of the conductive contact layer on the top surface of the dielectric layer on the top surface of the substrate at least partially overlaps with a projection of the control circuit on the top surface of the substrate.

[0028] According to some other embodiments, the present disclosure further provides a method for forming a semiconductor structure, comprising the following steps:

[0029] forming a substrate having a plurality of conductive interconnect layers arranged along a first direction, wherein at least the conductive interconnect layer on the topmost layer includes an extension portion, and the first direction is perpendicular to the top surface of the substrate;

[0030] forming a dielectric layer on the top surface of the substrate, wherein the dielectric layer has a groove penetrating the dielectric layer at least along the first direction and aligned with the topmost conductive interconnect layer, wherein the projection of the groove on the top surface of the substrate is annular, the extension portion extends along the bottom of the groove, and the bottom of the groove along the first direction exposes the topmost conductive interconnect layer;

[0031] A conductive contact layer is formed to continuously cover the inner wall of the trench and the top surface of the dielectric layer, and the conductive contact layer is electrically connected to the topmost conductive interconnection layer.

[0032] In some embodiments, the specific steps of forming the conductive contact layer that continuously covers the inner wall of the trench and the top surface of the dielectric layer include:

[0033] Conductive material is deposited on the dielectric layer to form the conductive contact layer and an air gap in the trench, wherein the conductive contact layer is distributed around the periphery of the air gap.

[0034] Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same. By setting an annular groove in a dielectric layer above a substrate, at least the conductive interconnect layer located at the topmost layer inside the substrate includes an extension portion extending along the bottom of the groove, and a conductive contact layer is filled at least in the annular groove. On the one hand, the facing area between the conductive contact layer and the conductive interconnect layer at the topmost layer is reduced without increasing the resistance, thereby reducing the capacitive coupling effect between the conductive contact layer and the conductive interconnect layer at the topmost layer, thereby achieving improvements in the performance and manufacturing yield of the semiconductor structure. On the other hand, the annular groove and the annular conductive interconnect layer can simplify the manufacturing process of the semiconductor structure and improve the manufacturing efficiency of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Attachment Figure 1 is a schematic top view of a semiconductor structure in a specific embodiment of the present disclosure;

[0036] Attachment Figure 2A It is attached Figure 1 A schematic cross-sectional view of the AA position;

[0037] Attachment Figure 2B It is attached Figure 1 Another cross-sectional schematic diagram of the AA position;

[0038] Attachment Figure 2C It is attached Figure 1 Another cross-sectional diagram at the AA position;

[0039] Attachment Figure 3 is a schematic top view of the topmost conductive interconnect layer in a specific embodiment of the present disclosure;

[0040] Attachment Figure 4 is a schematic top view of a dielectric layer in a specific embodiment of the present disclosure;

[0041] Attachment Figure 5 is a schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure when undergoing a probe test;

[0042] Attachment Figure 6 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] The specific embodiments of the semiconductor structure and the method for forming the same provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0044] This embodiment provides a semiconductor structure. Figure 1 is a top view schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure, Figure 2A It is attached Figure 1A cross-sectional diagram of the AA position in the middle, with Figure 2B It is attached Figure 1 Another cross-sectional diagram of the AA position, attached Figure 2C It is attached Figure 1 Another cross-sectional diagram of the AA position in the middle, attached Figure 3 is a top view schematic diagram of the topmost conductive interconnect layer in a specific embodiment of the present disclosure, Figure 4 Schematic diagram of a top view of the dielectric layer in a specific embodiment of the present disclosure. Figure 1 、 Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 3-Figure 4 As shown, the semiconductor structure includes:

[0045] A substrate 22 having a plurality of conductive interconnect layers 11 arranged along a first direction, wherein the first direction is perpendicular to a top surface of the substrate 22;

[0046] a dielectric layer 21 located on a top surface of the substrate 22, wherein the dielectric layer 21 includes a groove 12 extending through the dielectric layer 21 at least along the first direction and aligned with the topmost conductive interconnect layer 11; the projection of the groove 12 on the top surface of the substrate 22 is annular; at least the topmost conductive interconnect layer includes an extension 111 extending along the bottom of the groove 12, and the bottom of the groove 12 along the first direction exposes the topmost conductive interconnect layer 11;

[0047] The conductive contact layer 10 continuously covers the inner wall of the groove 12 and the top surface of the dielectric layer 21 , and the conductive contact layer 10 is electrically connected to the topmost conductive interconnection layer 11 .

[0048] The semiconductor structure described in this embodiment may be, but is not limited to, a DRAM (Dynamic Random Access Memory). The multiple conductive interconnect layers 11 arranged along the first direction are electrically connected. In one example, the substrate 22 may include a plurality of conductive interconnect layers 11 arranged along the first direction (e.g., Figure 2AThe substrate 22 includes multiple layers of conductive interconnect layers 11 arranged in an interval (in the Z-axis direction) and conductive connecting pillars 23 electrically connecting two adjacent layers of the conductive interconnect layers 11. The conductive interconnect layers 11 and the conductive connecting pillars 23 can be made of the same material, for example, both can be made of a metal material such as copper. The topmost conductive interconnect layer 11 refers to the conductive interconnect layer 11 that is shortest in distance from the dielectric layer 21 along the first direction among the multiple layers of the conductive interconnect layers 11. The dielectric layer 21 is located on the top surface of the substrate 22, and the groove 12 penetrates the dielectric layer 21 along the Z-axis direction and exposes the topmost conductive interconnect layer 11 located below the dielectric layer 21. The alignment of the groove 12 with the topmost conductive interconnect layer 11 means that the projection of the groove 12 on the top surface of the substrate 22 at least partially overlaps with the projection of the topmost conductive interconnect layer 11 on the top surface of the substrate 22. The projection of the groove 12 on the top surface of the substrate 22 is annular, meaning that the projection of the edge line of the groove 12 on the top surface of the substrate 22 is annular. At least the topmost conductive interconnect layer 11 includes an extension 111 extending along the bottom of the groove 12. The conductive contact layer 10 at least covers the inner wall of the groove 12 and is electrically connected to the topmost conductive interconnect layer 11. That is, the conductive contact layer 10 is electrically connected to the topmost conductive interconnect layer 11 through the extension 111, thereby enabling signals from the topmost conductive interconnect layer 11 to be extracted through the conductive contact layer 10, thereby facilitating testing (e.g., WAT (Wafer Acceptable Test) or CP (Chip Probe)) of the topmost conductive interconnect layer 11 or all of the conductive interconnect layers 11, or signal transmission. For example, the conductive contact layer 10 is a redistribution layer, and the groove 12 is a corresponding redistribution trench. In one example, a substrate isolation layer 20 is further disposed between the dielectric layer 21 and the substrate 22. The substrate isolation layer 20 may be made of a nitride material (e.g., silicon nitride). The extension 111 extends along the bottom of the trench 12, which not only ensures a stable electrical connection between the conductive contact layer 10 and the topmost conductive interconnect layer 11, but also increases the contact area between the conductive contact layer 10 and the topmost conductive interconnect layer 11, thereby reducing the contact resistance between the conductive contact layer 10 and the topmost conductive interconnect layer 11.

[0049] In one example, the material of the dielectric layer 21 can be TEOS (Tetraethyl orthosilicate). The material of the conductive contact layer 10 can be a metal material such as aluminum to reduce the contact resistance between the conductive contact layer 10 and the topmost conductive interconnection layer 11. Figure 1 The top surface of the dielectric layer 21 refers to the surface of the dielectric layer 21 away from the substrate 22 along the first direction. The ring shape described in this embodiment can be a circular ring or a square ring.

[0050] In this specific embodiment, the groove 12 in the dielectric layer 21 is configured to have an annular shape, and at least the topmost conductive interconnect layer 11 among the multiple conductive interconnect layers 11 is also configured as a whole to have an annular shape aligned with the annular shape of the groove 12. This reduces the facing area between the conductive contact layer 10 covering the inner wall of the groove 12 and the topmost conductive interconnect layer 11. For example, the projection of the conductive contact layer 10 covering the top surface of the dielectric layer 21 on the top surface of the substrate 22 does not overlap with the projection of the topmost conductive interconnect layer 11 on the top surface of the substrate 22, or overlaps only at the edges. This reduces the capacitive coupling effect between the conductive contact layer 10 and the topmost conductive interconnect layer 11, reduces the leakage current within the semiconductor structure, and improves the performance and manufacturing yield of the semiconductor structure. At the same time, because the annular groove 12 is aligned with the annular topmost conductive interconnect layer 11, a stable electrical connection can be ensured between the conductive contact layer 10 located within the groove 12 and the topmost conductive interconnect layer 11, which helps to further improve the performance of the semiconductor structure. Moreover, the annular groove 12 and the annular topmost conductive interconnect layer can simplify the manufacturing process of the semiconductor structure and improve the manufacturing efficiency of the semiconductor structure.

[0051] In some embodiments, the projection of the extension portion 111 of at least the topmost conductive interconnect layer 11 on the top surface of the substrate 22 is annular. Providing the extension portion 111 with an annular structure that matches the trench 12 helps further simplify the manufacturing process of the semiconductor structure and further increases the contact area between the conductive contact layer 10 and the topmost conductive interconnect layer 11.

[0052] In some embodiments, the number of the conductive interconnect layers 11 is N, and the N conductive interconnect layers 11 are arranged in sequence along a direction from the top surface of the substrate 22 to the bottom surface of the substrate 22, and any two adjacent conductive interconnect layers 11 are electrically connected, and the bottom surface of the substrate 22 is opposite to the top surface of the substrate 22 along the first direction;

[0053] Each of the conductive interconnection layers 11 from the 1st layer to the Mth layer includes the extending portion 111 extending along the trench 12 . N and M are both positive integers, and N≥M.

[0054] In some embodiments, a projection of the groove 12 on the top surface of the substrate 22 is located within a projection of the extension 111 in each of the conductive interconnect layers 11 of the 1st to Mth layers on the top surface of the substrate 22 .

[0055] For example, the semiconductor structure includes a Figure 2A The N layers of conductive interconnect layers 11 are spaced apart (in the Z-axis direction of the substrate 22), and two adjacent layers of conductive interconnect layers 11 along the Z-axis are electrically connected via the conductive connecting pillars 23. The N layers of conductive interconnect layers 11 are arranged sequentially along a direction from the top surface of the substrate 22 toward the bottom surface of the substrate 22 and parallel to the Z-axis. For example, the topmost conductive interconnect layer 11 is the first layer of conductive interconnect layer 11, the conductive interconnect layer 11 located below and adjacent to the topmost conductive interconnect layer 11 is the second layer of conductive interconnect layer 11, the conductive interconnect layer 11 located below and adjacent to the second layer of conductive interconnect layer 11 is the third layer of conductive interconnect layer, and so on. The extension portion 111 in each of the conductive interconnect layers 11 from the 1st layer to the Mth layer extends along the bottom of the groove 12, and the projection of the groove 12 on the top surface of the substrate 22 is located within the projection of the extension portion 111 in each of the conductive interconnect layers 11 from the 1st layer to the Mth layer on the top surface of the substrate 22. Therefore, on the one hand, the facing area between the conductive contact layer 10 located on the top surface of the dielectric layer 21 and the conductive interconnect layers 11 of the M layers inside the substrate 22 (that is, the conductive interconnect layers 11 of the 1st layer to the conductive interconnect layers 11 of the Mth layer) is reduced, thereby further reducing the parasitic capacitance effect inside the semiconductor structure and further improving the performance of the semiconductor structure; on the other hand, a stable electrical connection is ensured between the conductive contact layer 10 located in the groove 12 and the topmost conductive interconnect layer 11, thereby ensuring the performance stability of the semiconductor structure.

[0056] In order to further simplify the manufacturing process of the semiconductor structure, in one example, the projections of the first to Mth conductive interconnect layers 11 on the top surface of the substrate 22 completely overlap.

[0057] In some embodiments, the dielectric layer 21 includes a plurality of grooves 12 distributed along a direction parallel to the top surface of the substrate 22, and the extensions 111 in the conductive interconnect layers 11 of the first to Mth layers extend along the bottoms of the plurality of grooves 12. With this structure, signals from the plurality of conductive interconnect layers can be led out through the conductive contact layers 10 in the plurality of grooves 12, and parasitic capacitance between each conductive interconnect layer and the corresponding conductive contact layer electrically connected thereto can be reduced, thereby further improving the performance of the semiconductor structure.

[0058] For example, if Figure 2C As shown, the dielectric layer 21 includes a first trench H1 and a second trench H2 spaced apart along the X-axis, and both the first trench H1 and the second trench H2 penetrate the dielectric layer 21 along the Z-axis. The substrate 22 includes a first conductive interconnect layer M1 and a second conductive interconnect layer M2 located below the first conductive interconnect layer M1 and electrically connected to the first conductive interconnect layer M1 via the conductive connecting pillars 23. The first trench H1 is aligned with the first conductive interconnect layer M1, and the second trench H2 is aligned with the second conductive interconnect layer M2. The projections of the first trench H1 and the second trench H2 on the top surface of the substrate 22 are both annular. The first conductive interconnect layer M1 includes a first extension extending along the bottom of the first trench H1, and the second conductive interconnect layer M2 includes a second extension extending along the bottom of the second trench H2. The first conductive contact layer C1 covers the inner wall of the first trench H1 and is in contact and electrically connected with the first extension portion in the first conductive interconnect layer M1. The second conductive contact layer C2 covers the inner wall of the second trench H2 and is in contact and electrically connected with the second extension portion M2 in the second conductive interconnect layer M2.

[0059] In some embodiments, the conductive contact layer 10 is in direct electrical contact with the extension 111 in the topmost conductive interconnect layer 11. This structure, on the one hand, avoids the need for additional transition structures within the substrate 22, above the substrate 22, or within the trench 12, thereby simplifying the semiconductor structure and reducing its size, further miniaturizing it. It also helps reduce contact resistance within the semiconductor structure, thereby further improving its performance.

[0060] In some embodiments, the thickness of the conductive contact layer 10 located on the top surface of the dielectric layer 21 is greater than or equal to the width of the groove 12, that is, the thickness of the conductive contact layer 10 located on the top surface of the dielectric layer 21 is greater than the thickness of the conductive contact layer 10 located inside the groove 12. On the one hand, it enables the conductive contact layer 10 on the top surface of the dielectric layer 21 to fully and stably contact the probe during the subsequent WAT test or CP test; on the other hand, it helps to form an air gap inside the groove 12 during the deposition of the conductive contact layer 10, thereby facilitating the release of stress. In one example, the width of the groove 12 can be the inner diameter of the groove 12, the width of the groove 12 along the second direction, or the width of the groove 12 along the third direction. The second direction and the third direction are both parallel to the top surface of the substrate 22, and the second direction intersects with the third direction. In one example, the second direction can be Figure 1 The X-axis direction in the third direction can be Figure 1 The Y-axis direction in .

[0061] In some embodiments, the thickness of the conductive contact layer 10 located on the top surface of the dielectric layer 21 is 5 μm to 7 μm, and the width of the groove 12 is 2 μm to 5 μm. In one example, the thickness of the conductive contact layer 10 located on the top surface of the dielectric layer 21 is 5 μm, 6 μm, or 7 μm, and the width of the groove 12 is 2 μm, 3 μm, 4 μm, or 5 μm.

[0062] In some embodiments, the conductive contact layer 10 continuously covers the sidewalls of the groove 12 and the bottom surface of the groove 12, and the thickness of the conductive contact layer 10 located on the bottom surface of the groove 12 is greater than the thickness of the conductive contact layer 10 located on the sidewalls of the groove 12, so as to ensure a stable electrical connection between the conductive contact layer 10 and the extension portion 111 in the topmost conductive interconnect layer 11.

[0063] In some embodiments, the semiconductor structure further comprises:

[0064] An air gap is located in the groove 12 , and the conductive contact layer 10 is distributed around the periphery of the air gap.

[0065] In some embodiments, along the first direction, a top surface of the air gap is located above a top surface of the dielectric layer 21 .

[0066] Attachment Figure 5Schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure during a probe test. Specifically, by adjusting the width of the groove 12, the deposition parameters when depositing the conductive contact layer 10, the thickness distribution of the conductive contact layer 10, and other factors, the air gap surrounded by the conductive contact layer 10 can be formed inside the groove 12. By providing the air gap surrounded by the conductive contact layer 10 in the annular groove 12, the probe 50 (see FIG. 5 ) can be used to test the semiconductor structure. Figure 5 When performing a CP test or a WAT ​​test on the semiconductor structure, the stress generated when the probe 50 contacts the conductive contact layer 10 located on the top surface of the dielectric layer 21 can be released through the air gap within the annular groove 12, thereby reducing damage to the semiconductor structure during the test. In one example, the projection of the air gap on the top surface of the substrate 22 is also annular.

[0067] In some embodiments, the semiconductor structure further comprises:

[0068] An identification structure 13 is located in the dielectric layer 21 and outside the trench 12. The identification structure 13 is used to identify the semiconductor structure, allowing identification of a specific semiconductor structure during batch testing. In one example, the identification structure 13 can be a pattern identifier, a material identifier, or a combination of two or more. Placing the identification structure 13 outside the trench 12 avoids occupying space within the trench 12 and thus preventing it from affecting the conductive contact layer 10 within the trench 12.

[0069] In some embodiments, the identification structure 13 is located at the edge of the dielectric layer 21 , and the identification structure 13 is a cut that penetrates the dielectric layer 21 at least along the first direction and exposes the topmost conductive interconnect layer 11 , so as to simplify the identification structure 13 .

[0070] In some embodiments, the projection of the groove 12 on the top surface of the substrate 22 is a square ring, and the identification structure 13 is located at the corner of the square ring-shaped groove 12, such as Figure 1 In one example, there are multiple identification structures 13, and the multiple identification structures 13 can be distributed at multiple corners of the square ring-shaped groove 12, so that the multiple identification structures 13 can be used to identify and align the semiconductor structure. In this specific embodiment, the multiple refers to more than two.

[0071] In some embodiments, the semiconductor structure further comprises:

[0072] An insulating covering layer is located above the conductive contact layer 10, and the insulating covering layer includes a contact port, and the contact port exposes the conductive contact layer 10 located on the top surface of the dielectric layer 21. The insulating covering layer is used to protect the conductive contact layer 10 and prevent the external environment from affecting the conductive contact layer 10, for example, to prevent oxygen in the external environment from oxidizing the conductive contact layer 10. In one example, the insulating covering layer may only cover the conductive contact layer 10 on the top surface of the dielectric layer 21, and not fill into the groove 12, so as to ensure that the air gap is formed in the groove 12. The contact port is used for the probe 50 (see Figure 5 ) passes through so that the probe 50 contacts the conductive contact layer 10. The material of the insulating cover layer can be an oxide material (such as silicon dioxide) or a nitride material (such as silicon nitride).

[0073] In some embodiments, the substrate 22 includes a device layer, and the device layer is located below the bottommost conductive interconnect layer 11;

[0074] There is no conductive material between the conductive contact layer 10 located on the top surface of the dielectric layer 21 and the device layer.

[0075] The device layer includes a control circuit;

[0076] The projection of the conductive contact layer 10 on the top surface of the dielectric layer 21 on the top surface of the substrate 22 at least partially overlaps with the projection of the control circuit on the top surface of the substrate 22 .

[0077] The following description uses a DRAM as an example. The semiconductor structure includes a device layer, the device layer includes the control circuit (e.g., a CMOS circuit) and a storage circuit, the storage circuit is used to store information, and the control circuit is used to transmit a control signal to the storage circuit to control the read and write operations of the storage circuit. There is no conductive material between the conductive contact layer 10 located on the top surface of the dielectric layer 21 and the device layer, wherein the conductive material includes the conductive interconnect layer 11, thereby reducing the facing area between the conductive contact layer 10 and the device layer, thereby further reducing the parasitic capacitance within the semiconductor structure.

[0078] This embodiment also provides a method for forming a semiconductor structure. Figure 6 This is a flow chart of the method for forming a semiconductor structure in a specific embodiment of the present disclosure. The schematic diagram of the semiconductor structure formed in this specific embodiment can be found in Figure 1 、 Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 3-Figure 5 .like Figure 1 、 Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 3-Figure 6 As shown, the method for forming the semiconductor structure includes the following steps:

[0079] Step S61: forming a substrate 22, wherein the substrate 22 has a Figure 2A a plurality of conductive interconnect layers 11 arranged along the Z-axis direction in the middle of the substrate 22, wherein at least the conductive interconnect layer 11 on the topmost layer includes an extension portion 111, and the first direction is perpendicular to the top surface of the substrate 22;

[0080] Step S62: forming a dielectric layer 21 on the top surface of the substrate 22, wherein the dielectric layer 21 has a groove 12 extending through the dielectric layer 21 at least along the first direction and aligned with the topmost conductive interconnect layer 11, wherein the projection of the groove 12 on the top surface of the substrate 22 is annular, and the extension portion 111 extends along the bottom of the groove 12, and the bottom of the groove 12 along the first direction exposes the topmost conductive interconnect layer 11;

[0081] Step S63 : forming a conductive contact layer 10 that continuously covers the inner wall of the trench 12 and the top surface of the dielectric layer 21 , and the conductive contact layer 10 is electrically connected to the topmost conductive interconnect layer 11 .

[0082] In some embodiments, the specific steps of forming the substrate 22 include:

[0083] providing a substrate;

[0084] A plurality of first isolation layers stacked in sequence along the first direction and the conductive interconnection layer 11 located inside each of the first isolation layers are formed on the substrate. The conductive interconnection layers 11 in any two adjacent first isolation layers are electrically connected. The substrate, all the first isolation layers and all the conductive interconnection layers 11 together constitute the base 22.

[0085] For example, multiple cycles can be performed to form the first isolation layers and the conductive interconnect layers 11 alternately arranged along the Z-axis, with adjacent conductive interconnect layers 11 along the Z-axis electrically connected via conductive connection pillars 23 penetrating the first isolation layers. The cycles include: forming a layer of the conductive interconnect layer 11 on the top surface of the substrate; forming a layer of the first isolation layer above the conductive interconnect layer 11, wherein the first isolation layer includes conductive connection pillars 23 penetrating the first isolation layer along the Z-axis and electrically connected to the conductive interconnect layer 11 adjacent thereto; and using the first isolation layer formed in the current cycle as the substrate for the next cycle. The conductive interconnect layers 11 and the conductive connection pillars 23 can be made of the same material, for example, both can be made of a metal material such as copper.

[0086] In some embodiments, the specific steps of forming the dielectric layer 21 on the top surface of the substrate 22 include:

[0087] forming a dielectric layer 21 covering the top surface of the substrate 22;

[0088] The dielectric layer 21 is patterned to form the trench 12 that penetrates the dielectric layer 21 along the first direction and exposes the topmost conductive interconnect layer 11 .

[0089] For example, after forming the substrate 22, a nitride material (such as silicon nitride) may be deposited on the top surface of the substrate 22 to form a substrate isolation layer 20 covering the top surface of the substrate 22. Then, TEOS may be deposited on the top surface of the substrate isolation layer 20 to form the dielectric layer 21. Afterwards, a dry etching process may be used to etch the dielectric layer 21 to form a dielectric layer along the substrate 22. Figure 2A The Z-axis direction of the trench 12 passes through the dielectric layer 21. In one example, the width of the trench 12 is 2 μm to 5 μm.

[0090] In some embodiments, the specific steps of forming the conductive contact layer 10 that continuously covers the inner wall of the trench 12 and the top surface of the dielectric layer 21 include:

[0091] Conductive material is deposited on the dielectric layer 21 to form the conductive contact layer 10 that continuously covers the inner wall of the trench 12 and the top surface of the dielectric layer 21 . The conductive contact layer 10 is in direct electrical contact with the topmost conductive interconnect layer 11 .

[0092] Specifically, after forming the trench 12 that exposes the extension 111 in the topmost conductive interconnect layer 11, a conductive material such as metallic aluminum is directly deposited within the trench 12 to form the conductive contact layer 10 that is in direct electrical contact with the extension 111 in the topmost conductive interconnect layer 11. This structure, on the one hand, avoids the need for additional transition structures within the substrate 22, above the substrate 22, or within the trench 12, thereby simplifying the semiconductor structure and reducing its size, promoting further miniaturization. It also helps reduce contact resistance within the semiconductor structure, thereby further improving its performance.

[0093] In some embodiments, the specific steps of forming the conductive contact layer 10 that continuously covers the inner wall of the trench 12 and the top surface of the dielectric layer 21 include:

[0094] Conductive material is deposited on the dielectric layer 21 to form the conductive contact layer 10 and an air gap within the trench 12 . The conductive contact layer 10 is distributed around the periphery of the air gap.

[0095] For example, an atomic layer deposition process can be used to deposit a material such as metallic aluminum on the dielectric layer 21 to form the conductive contact layer 10 that continuously covers the inner wall of the groove 12 (including the sidewalls of the groove 12 and the bottom wall of the groove 12) and the top surface of the dielectric layer 21, and at the same time, the air gap surrounded by the conductive contact layer 10 is formed in the groove 12. By forming the air gap, the stress generated when the probe contacts the conductive contact layer 10 can be released, thereby reducing damage to the semiconductor structure during the test. In one example, by adjusting the parameters of the atomic layer deposition process (such as deposition temperature, pressure, etc.), the air gap can be extended from the inside of the groove 12 to above the groove 12, that is, the top surface of the air gap is located above the top surface of the dielectric layer 21, thereby further improving the stress release effect.

[0096] In some embodiments, after forming the dielectric layer 21 on the top surface of the substrate 22, the following steps are further included:

[0097] The dielectric layer 21 is etched to form a marking structure 13 exposing the topmost conductive interconnect layer 11, see Figure 1 .

[0098] For example, after forming the dielectric layer 21, the dielectric layer 21 can be patterned using an etching process to form an incision at the outer corner of the square ring-shaped groove 12 in the dielectric layer 21, and the incision exposes the topmost conductive interconnect layer 11 in the substrate 22, and the incision is used as the identification structure 13.

[0099] Some embodiments of this specific embodiment provide a semiconductor structure and a method for forming the same. By setting an annular groove in a dielectric layer above a substrate, at least the conductive interconnection layer located at the topmost layer inside the substrate includes an extension portion extending along the bottom of the groove, and the conductive contact layer is at least filled in the annular groove. On the one hand, the facing area between the conductive contact layer and the conductive interconnection layer at the topmost layer is reduced without increasing the resistance, thereby reducing the capacitive coupling effect between the conductive contact layer and the conductive interconnection layer at the topmost layer, thereby achieving improvements in the performance and manufacturing yield of the semiconductor structure. On the other hand, the annular groove and the annular conductive interconnection layer can simplify the manufacturing process of the semiconductor structure and improve the manufacturing efficiency of the semiconductor structure.

[0100] The above is only a preferred embodiment of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: A substrate having N conductive interconnect layers arranged along a first direction, the N conductive interconnect layers being arranged in sequence along a direction pointing from the top surface of the substrate to the bottom surface of the substrate, and any two adjacent conductive interconnect layers being electrically connected, the bottom surface of the substrate being opposite to the top surface of the substrate along the first direction, N being a positive integer, and the first direction being perpendicular to the top surface of the substrate; a dielectric layer located on the top surface of the substrate, the dielectric layer having a groove therein that penetrates the dielectric layer at least along the first direction and is aligned with the topmost conductive interconnect layer, the projection of the groove on the top surface of the substrate being annular, wherein each of the first to Mth conductive interconnect layers includes an extension portion extending along the bottom of the groove, M is a positive integer, N ≥ M, and the bottom of the groove along the first direction exposes the topmost conductive interconnect layer; A conductive contact layer continuously covers the inner wall of the trench and the top surface of the dielectric layer, and the conductive contact layer is electrically connected to the topmost conductive interconnection layer.

2. The semiconductor structure according to claim 1, wherein: The projection of the extension portion in at least the topmost conductive interconnect layer on the top surface of the substrate is ring-shaped.

3. The semiconductor structure according to claim 1, wherein: A projection of the trench on the top surface of the substrate is located within a projection of the extension in each of the first to Mth conductive interconnect layers on the top surface of the substrate.

4. The semiconductor structure according to claim 1, wherein: The dielectric layer includes a plurality of grooves distributed in a direction parallel to the top surface of the substrate, and the extensions in the first to Mth layers of the conductive interconnection layer extend along the bottoms of the plurality of grooves, respectively.

5. The semiconductor structure according to claim 1, wherein: The conductive contact layer is in direct contact and electrically connected to the extension portion in the topmost conductive interconnect layer. The semiconductor structure according to claim 1 , wherein: Also includes: An air gap is located in the trench, and the conductive contact layer is distributed around the periphery of the air gap.

7. The semiconductor structure according to claim 1, wherein: Also includes: The identification structure is located in the dielectric layer and outside the groove.

8. The semiconductor structure according to claim 7, wherein: The marking structure is located at an edge of the dielectric layer, and the marking structure is a cut that penetrates the dielectric layer at least along the first direction and exposes the topmost conductive interconnection layer.

9. The semiconductor structure according to claim 8, wherein: The projection of the groove on the top surface of the substrate is a square ring shape, and the identification structure is located at a corner of the square ring-shaped groove.

10. The semiconductor structure according to claim 5, wherein: Also includes: An insulating covering layer is located above the conductive contact layer, and the insulating covering layer includes a contact opening, wherein the contact opening exposes the conductive contact layer located on the top surface of the dielectric layer.

11. The semiconductor structure according to claim 1, wherein: The substrate includes a device layer, and the device layer is located below the bottommost conductive interconnect layer; There is no conductive material between the conductive contact layer and the device layer on the top surface of the dielectric layer.

12. The semiconductor structure according to claim 11, wherein: The device layer includes a control circuit; A projection of the conductive contact layer on the top surface of the dielectric layer on the top surface of the substrate at least partially overlaps with a projection of the control circuit on the top surface of the substrate.

13. A method for forming a semiconductor structure, characterized in that: The steps include: Forming a substrate, wherein the substrate has N conductive interconnect layers arranged along a first direction, the N conductive interconnect layers being arranged sequentially along a direction pointing from the top surface of the substrate to the bottom surface of the substrate, and any two adjacent conductive interconnect layers being electrically connected, the bottom surface of the substrate being opposite to the top surface of the substrate along the first direction, wherein each of the conductive interconnect layers from the first layer to the Mth layer includes an extension portion, N and M are positive integers, N ≥ M, and the first direction is perpendicular to the top surface of the substrate; forming a dielectric layer on the top surface of the substrate, wherein the dielectric layer has a groove penetrating the dielectric layer at least along the first direction and aligned with the topmost conductive interconnect layer, wherein the projection of the groove on the top surface of the substrate is annular, the extension portion extends along the bottom of the groove, and the bottom of the groove along the first direction exposes the topmost conductive interconnect layer; A conductive contact layer is formed to continuously cover the inner wall of the trench and the top surface of the dielectric layer, and the conductive contact layer is electrically connected to the topmost conductive interconnection layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The specific steps of forming a conductive contact layer that continuously covers the inner wall of the trench and the top surface of the dielectric layer include: Conductive material is deposited on the dielectric layer to form the conductive contact layer and an air gap in the trench, wherein the conductive contact layer is distributed around the periphery of the air gap.

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