Layout structure of semiconductor devices

Abstract

The present invention provides a layout structure of a semiconductor device, wherein a minimum repeating unit pattern is arrayed along a first direction and a second direction, any two adjacent minimum repeating unit patterns are arranged in mirror symmetry, a pull-up transistor pattern is provided in the first region of the minimum repeating unit pattern, a pull-down transistor pattern and a transmission gate transistor pattern are provided in the second region, a first conductive type well region pattern and a second conductive type well region both extend along the second direction and are arranged at intervals along the first direction, the first regions of two adjacent columns of minimum repeating unit patterns in the first direction are both located in the corresponding first conductive type well region pattern, and the second regions of two adjacent columns of minimum repeating unit patterns in the first direction are both located in the corresponding second conductive type well region pattern. The first conductive type well region pattern has first lead-out patterns at both ends along the second direction, and the first lead-out pattern does not need to be provided in each minimum repeating unit pattern, thereby reducing the area of ​​the minimum repeating unit pattern.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a layout structure of a semiconductor device. Background Art

[0002] With the continuous development of digital integrated circuits, on-chip integrated memory has become an important component of digital systems. Static random access memory (SRAM) has become an indispensable component of on-chip memory due to its low power consumption and high speed. SRAM can save data as long as it is powered, without the need to constantly refresh it.

[0003] Single-port SRAM (SP-SRAM) is a SRAM with only one access port. Since it only has one port, it can only provide one memory access operation at a time. Dual-port SRAM (DP-SRAM) has two ports. Compared with SP-SRAM, each port of DP-SRAM can perform read or write operations, thereby providing more memory bandwidth. Therefore, DP-SRAM is widely used in high-speed data exchange systems such as high-speed communication and image processing, and the demand for DP-SRAM is also increasing.

[0004] The minimum repeating unit of a DP-SRAM includes 8 transistors (also called 8T DP-SRAM). The 8 transistors can be divided into two pull-up transistors, two pull-down transistors and four pass gate transistors according to their functions. The two pull-up transistors are usually PMOS transistors, which are made in the N-type conductive well area, while the two pull-down transistors and the four pass gate transistors are usually NMOS transistors, which are made in the P-type conductive well area.

[0005] When designing the layout of DP-SRAM, a lead-out pattern is usually designed in the area corresponding to the N-type conductive type well area and the P-type conductive type well area in the minimum repeating unit pattern, and the N-type conductive type well area and the P-type conductive type well area are led out, so as to facilitate the application of voltage to the N-type conductive type well area and the P-type conductive type well area. At the same time, in order to ensure symmetry, two N-type conductive type well areas are usually set. The lead-out pattern will undoubtedly increase the area of ​​the minimum repeating unit pattern, thereby increasing the area of ​​the entire DP-SRAM layout structure, thereby increasing the leakage power. At the same time, the routing of the back section will also be more complicated, and the device preparation process will be more difficult. Summary of the invention

[0006] The object of the present invention is to provide a layout structure of a semiconductor device to solve the problems of the existing DP-SRAM layout structure, such as large area and complex wiring.

[0007] In order to achieve the above-mentioned object, the present invention provides a layout structure of a semiconductor device, comprising a first conductive type well region pattern, a second conductive type well region pattern and a minimum repeating unit pattern, wherein the minimum repeating unit pattern is arrayed along a first direction and a second direction, and any two adjacent minimum repeating unit patterns are arranged in mirror symmetry, and the number of the minimum repeating unit patterns in the first direction and the second direction is greater than or equal to 2;

[0008] The minimum repeating unit pattern includes a first region and a second region sequentially arranged along the first direction, the first region has a pull-up transistor pattern, and the second region has a pull-down transistor pattern and a transfer gate transistor pattern;

[0009] The first conductive type well region pattern and the second conductive type well region pattern both extend along the second direction and are arranged at intervals along the first direction, the first regions of two adjacent columns of the minimum repeating unit pattern in the first direction are both located in the corresponding first conductive type well region pattern, and the second regions of two adjacent columns of the minimum repeating unit pattern in the first direction are both located in the corresponding second conductive type well region pattern;

[0010] The first conductive type well region pattern has first lead-out patterns at both ends along the second direction.

[0011] Optionally, the first lead-out pattern is symmetrically arranged relative to the center of the first conductive type well region pattern in the second direction.

[0012] Optionally, the pull-up transistor pattern includes a first pull-up transistor pattern and a second pull-up transistor pattern, and the first pull-up transistor pattern and the second pull-up transistor pattern are symmetrically arranged along the second direction;

[0013] The pull-down transistor pattern includes a first pull-down transistor pattern and a second pull-down transistor pattern, the first pull-down transistor pattern and the second pull-down transistor pattern are symmetrically arranged along the second direction; and,

[0014] The transfer gate transistor pattern includes a first transfer gate transistor pattern, a second transfer gate transistor pattern, a third transfer gate transistor pattern and a fourth transfer gate transistor pattern, the first transfer gate transistor pattern and the second transfer gate transistor pattern are symmetrically arranged along the second direction, and the third transfer gate transistor pattern and the fourth transfer gate transistor pattern are symmetrically arranged along the second direction.

[0015] Optionally, the first transfer gate transistor pattern and the second transfer gate transistor pattern are symmetrically arranged on both sides of the pull-down transistor pattern in the second direction, and the third transfer gate transistor pattern and the fourth transfer gate transistor pattern are symmetrically arranged on both sides of the pull-down transistor pattern in the second direction; and

[0016] The first transfer gate transistor pattern and the third transfer gate transistor pattern are located on the same side of the pull-down transistor pattern in the second direction, and the second transfer gate transistor pattern and the fourth transfer gate transistor pattern are located on the same side of the pull-down transistor pattern in the second direction.

[0017] Optionally, the first transfer gate transistor pattern is closer to the pull-down transistor pattern in the first direction than the third transfer gate transistor pattern; the second transfer gate transistor pattern is closer to the pull-down transistor pattern in the first direction than the fourth transfer gate transistor pattern.

[0018] Optionally, a second lead-out pattern is provided in the second area.

[0019] Optionally, the second lead-out pattern is located between the third transfer gate transistor pattern and the fourth transfer gate transistor pattern in the second direction, and the third transfer gate transistor pattern and the fourth transfer gate transistor pattern are symmetrically arranged on both sides of the second lead-out pattern in the second direction.

[0020] Optionally, two ends of the second conductive type well region pattern along the second direction have second lead-out patterns.

[0021] Optionally, the second lead-out pattern is symmetrically arranged relative to the center of the second conductivity type well region pattern in the second direction.

[0022] Optionally, the first pull-up transistor graphic, the second pull-up transistor graphic, the first pull-down transistor graphic, the second pull-down transistor graphic, the first transfer gate transistor graphic, the second transfer gate transistor graphic, the third transfer gate transistor graphic and the fourth transfer gate transistor graphic all include an active area graphic and a gate graphic.

[0023] Optionally, the active area graphics of the first pull-up transistor graphic and the second pull-up transistor graphic are connected as one, the active area graphics of the first pull-down transistor graphic, the second pull-down transistor graphic, the first transfer gate transistor graphic, the second transfer gate transistor graphic, the third transfer gate transistor graphic and the fourth transfer gate transistor graphic are connected as one, the gate graphics of the first pull-up transistor graphic and the first pull-down transistor graphic are connected as one, and the gate graphics of the second pull-up transistor graphic and the second pull-down transistor graphic are connected as one.

[0024] Optionally, in two adjacent minimum repeating unit patterns in the first direction, active area patterns of two first pull-up transistor patterns partially overlap, active area patterns of two second pull-up transistor patterns partially overlap, gate patterns of two third transfer gate transistor patterns partially overlap, and gate patterns of two fourth transfer gate transistor patterns partially overlap; and,

[0025] In two adjacent minimum repeating unit patterns in the second direction, the active area patterns of the two first transfer gate transistor patterns partially overlap, and the active area patterns of the two third transfer gate transistor patterns partially overlap; or, the active area patterns of the two second transfer gate transistor patterns partially overlap, and the active area patterns of the two fourth transfer gate transistor patterns partially overlap.

[0026] Optionally, the pull-up transistor pattern is a pattern of a PMOS transistor, the pull-down transistor pattern and the transfer gate transistor pattern are both patterns of an NMOS transistor, the first conductive type well region pattern is a pattern of an N-type conductive type well region, and the second conductive type well region pattern is a pattern of a P-type conductive type well region.

[0027] In the layout structure of the semiconductor device provided by the present invention, the minimum repeating unit pattern is arrayed along the first direction and the second direction, any two adjacent minimum repeating unit patterns are arranged in mirror symmetry, the number of the minimum repeating unit patterns in the first direction and the second direction is greater than or equal to 2, the minimum repeating unit pattern includes a first region and a second region arranged in sequence along the first direction, the first region has a pull-up transistor pattern, the second region has a pull-down transistor pattern and a transmission gate transistor pattern, the first conductive type well region pattern and the second conductive type well region both extend along the second direction and are arranged at intervals along the first direction, the first regions of the two adjacent columns of the minimum repeating unit pattern in the first direction are both located in the corresponding first conductive type well region pattern, and the second regions of the two adjacent columns of the minimum repeating unit pattern in the first direction are both located in the corresponding second conductive type well region pattern. In the present invention, the first conductive type well region pattern has a first lead-out pattern at both ends along the second direction, and the first lead-out pattern does not need to be set in each of the minimum repeating unit patterns, which reduces the area of ​​the minimum repeating unit pattern, thereby reducing the area of ​​the layout structure, reducing the leakage power of the device, and at the same time, it can also simplify the routing of the back section and reduce the complexity of the device manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of a layout structure of a semiconductor device provided in Embodiment 1 of the present invention;

[0029] Figure 2 A schematic diagram of a minimum repeating unit pattern provided in Example 1 of the present invention;

[0030] Figure 3 A schematic diagram of an 8T DP-SRAM provided in Embodiment 1 of the present invention;

[0031] Figure 4 A schematic diagram of an area of ​​a layout structure of a semiconductor device back-end process corresponding to a minimum repeating unit pattern provided in the first embodiment of the present invention;

[0032] Figure 5 A schematic diagram of the layout structure of a semiconductor device provided in the second embodiment of the present invention;

[0033] Figure 6 A schematic diagram of a minimum repeating unit pattern provided in Embodiment 2 of the present invention;

[0034] Wherein, the accompanying drawings are marked as follows:

[0035] 10-minimum repeating unit pattern; 101-first region; 102-second region; 11-first conductivity type well region pattern; 12-second conductivity type well region pattern. DETAILED DESCRIPTION

[0036] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0037] Embodiment 1

[0038] Figure 1 A schematic diagram of the layout structure of the semiconductor device provided in this embodiment, Figure 2 Schematic diagram of the minimum repeating unit pattern 10 provided in this embodiment. Figure 1 and Figure 2 As shown, the layout structure of the semiconductor device includes a first conductivity type well region pattern 11 , a second conductivity type well region pattern 12 and a minimum repeating unit pattern 10 .

[0039] Specifically, the minimum repeating unit pattern 10 is distributed in an array along a first direction x and a second direction y. In this embodiment, the first direction x and the second direction y are perpendicular to each other, the first direction x is a row direction, and the second direction y is a column direction, but it should not be limited to this, the first direction x and the second direction y are not limited to being perpendicular, and the first direction x and the second direction y are not limited to being a row direction and a column direction respectively.

[0040] The number of the minimum repeating unit patterns 10 in the first direction x and the second direction y is greater than or equal to 2. In this embodiment, the number of the minimum repeating unit patterns 10 in the first direction x and the second direction y is equal to 2, but it should not be limited to this. The number of the minimum repeating unit patterns 10 in the first direction x and the second direction y is not limited to being equal to 2, and the number of the minimum repeating unit patterns 10 in the first direction x and the second direction y may be equal or unequal.

[0041] Furthermore, any two adjacent minimum repeating unit patterns 10 are arranged in mirror symmetry. That is, the two adjacent minimum repeating unit patterns 10 in the first direction x are arranged in mirror symmetry, and the two adjacent minimum repeating unit patterns 10 in the second direction y are also arranged in mirror symmetry.

[0042] Please continue reading Figure 2 The minimum repeating unit pattern 10 includes a first region 101 and a second region 102 arranged along the first direction x, the first region 101 has a pull-up transistor pattern, and the second region 102 has a pull-down transistor pattern and a transfer gate transistor pattern.

[0043] Specifically, the semiconductor device in this embodiment is an 8T DP-SRAM. Figure 3 The schematic diagram of the 8T DP-SRAM provided in this embodiment. Figure 3 As shown, the 8T DP-SRAM includes a first pull-up transistor Pup1, a second pull-up transistor Pup2, a first pull-down transistor Pdown1, a second pull-down transistor Pdown2, a first transmission gate transistor Pgate1, a second transmission gate transistor Pgate2, a third transmission gate transistor Pgate3 and a fourth transmission gate transistor Pgate4. The drain of the first pull-up transistor Pup1 and the drain of the second pull-up transistor Pup2 are connected and then connected to the power line VDD, the source of the first pull-up transistor Pup1 is connected to the drain of the first pull-down transistor Pdown1, the source of the second pull-up transistor Pup2 is connected to the drain of the second pull-down transistor Pdown2, and the source of the first pull-down transistor Pdown1 and the source of the second pull-down transistor Pdown2 are connected and then connected to the ground line GND. The gate of the first pull-up transistor Pup1 is connected to the gate of the first pull-down transistor Pdown1, and then connected to the source of the second pull-up transistor Pup2, the drain of the second pull-down transistor Pdown2, and the drain of the second pass-gate transistor Pgate2. The gate of the second pull-up transistor Pup2 is connected to the gate of the second pull-down transistor Pdown2, and then connected to the source of the first pull-up transistor Pup1, the drain of the first pull-down transistor Pdown1, and the source of the first pass-gate transistor Pgate1. The gate of the first pass-gate transistor Pgate1 and the gate of the second pass-gate transistor Pgate2 are connected to the first word line WL1, the drain of the first pass-gate transistor Pgate1 is connected to the first bit line BL1, and the source of the second pass-gate transistor Pgate2 is connected to the second bit line BLB1. The source of the third transfer gate transistor Pgate3 is connected to the source of the first pull-up transistor Pup1 and the drain of the first pull-down transistor Pdown1, and the drain of the third transfer gate transistor Pgate3 is connected to the third bit line BL2; the source of the fourth transfer gate transistor Pgate4 is connected to the source of the second pull-up transistor Pup2 and the drain of the second pull-down transistor Pdown2, and the drain of the fourth transfer gate transistor Pgate4 is connected to the fourth bit line BLB2; the gate of the third transfer gate transistor Pgate3 and the gate of the fourth transfer gate transistor Pgate4 are connected and then connected to the second word line WL2.

[0044] Combination Figure 2 and Figure 3As shown, the pull-up transistor pattern includes a first pull-up transistor pattern PU1 and a second pull-up transistor pattern PU2, the first pull-up transistor pattern PU1 and the second pull-up transistor pattern PU2 are patterns corresponding to the first pull-up transistor Pup1 and the second pull-up transistor Pup2, respectively, and the first pull-up transistor pattern PU1 and the second pull-up transistor pattern PU2 are symmetrically arranged along the second direction y. The pull-down transistor pattern includes a first pull-down transistor pattern PD1 and a second pull-down transistor pattern PD2, the first pull-down transistor pattern PD1 and the second pull-down transistor pattern PD2 are patterns corresponding to the first pull-down transistor Pdown1 and the second pull-down transistor Pdown2, respectively, and the first pull-down transistor pattern PD1 and the second pull-down transistor pattern PD2 are symmetrically arranged along the second direction y. The transmission gate transistor graphic includes a first transmission gate transistor graphic PG1, a second transmission gate transistor graphic PG2, a third transmission gate transistor graphic PG3 and a fourth transmission gate transistor graphic PG4, wherein the first transmission gate transistor graphic PG1, the second transmission gate transistor graphic PG2, the third transmission gate transistor graphic PG3 and the fourth transmission gate transistor graphic PG4 are graphics corresponding to the first transmission gate transistor Pgate1, the second transmission gate transistor Pgate2, the third transmission gate transistor Pgate3 and the fourth transmission gate transistor Pgate4 respectively, and the first transmission gate transistor graphic PG1 and the second transmission gate transistor graphic PG2 are symmetrically arranged along the second direction y, and the third transmission gate transistor graphic PG3 and the fourth transmission gate transistor graphic PG4 are symmetrically arranged along the second direction y.

[0045] Further, the first transmission gate transistor pattern PG1 and the second transmission gate transistor pattern PG2 are symmetrically arranged on both sides of the pull-down transistor pattern in the second direction y, and the third transmission gate transistor pattern PG3 and the fourth transmission gate transistor pattern PG4 are symmetrically arranged on both sides of the pull-down transistor pattern in the second direction y. In addition, the first transmission gate transistor pattern PG1 and the third transmission gate transistor pattern PG3 are located on the same side of the pull-down transistor pattern in the second direction y (the side close to the first pull-down transistor pattern PD1), and the second transmission gate transistor pattern PG2 and the fourth transmission gate transistor pattern PG4 are located on the same side of the pull-down transistor pattern in the second direction y (the side close to the second pull-down transistor pattern PD2). In this way, the overall layout structure is symmetrically arranged, which meets the layout design requirements of 8T DP-SRAM.

[0046] Please continue reading Figure 2, the first transmission gate transistor pattern PG1 is closer to the pull-down transistor pattern than the third transmission gate transistor pattern PG3 in the first direction x; the second transmission gate transistor pattern PG2 is closer to the pull-down transistor pattern than the fourth transmission gate transistor pattern PG4 in the first direction x. Therefore, the first transmission gate transistor pattern PG1 and the second transmission gate transistor pattern PG2 are physically closer to the pull-down transistor pattern than the third transmission gate transistor pattern PG3 and the fourth transmission gate transistor pattern PG4, thereby facilitating the back-end wiring.

[0047] Combination Figure 2 and Figure 3 As shown, the first pull-up transistor pattern PU1, the second pull-up transistor pattern PU2, the first pull-down transistor pattern PD1, the second pull-down transistor pattern PD2, the first transmission gate transistor pattern PG1, the second transmission gate transistor pattern PG2, the third transmission gate transistor pattern PG3 and the fourth transmission gate transistor pattern PG4 all include an active area pattern AA and a gate pattern Gate. The active area pattern AA is a pattern corresponding to the source, drain and channel between the source and drain of the above transistors, and the gate pattern Gate is a pattern corresponding to the gate of the above transistors.

[0048] Further, the active area graph AA of the first pull-up transistor graph PU1 and the second pull-up transistor graph PU2 are connected as one, and the active area graph AA of the first pull-down transistor graph PD1, the second pull-down transistor graph PD2, the first transmission gate transistor graph PG1, the second transmission gate transistor graph PG2, the third transmission gate transistor graph PG3 and the fourth transmission gate transistor graph PG4 are connected as one. The gate graph Gate of the first pull-up transistor graph PU1 and the first pull-down transistor graph PD1 are connected as one, and the gate graph Gate of the second pull-up transistor graph PU2 and the second pull-down transistor graph PD2 are connected as one. By connecting the active area graph AA or the gate graph Gate as one, electrical connection can be achieved and wiring can be reduced.

[0049] Please continue reading Figure 1Since any two adjacent minimum repeating unit patterns 10 are arranged in mirror symmetry, in two adjacent columns of the minimum repeating unit patterns 10 in the first direction x, either the first regions 101 are close together or the second regions 102 are close together. The first conductive type well region pattern 11 and the second conductive type well region pattern 12 both extend along the second direction y and are arranged at intervals along the first direction x. The first regions 101 of the two adjacent columns of the minimum repeating unit patterns 10 in the first direction x are both located in the corresponding first conductive type well region pattern 11, and the second regions 102 of the two adjacent columns of the minimum repeating unit patterns 10 in the first direction x are both located in the corresponding second conductive type well region pattern 12. It can be seen that all the first regions 101 of the two adjacent columns of the minimum repeating unit graphics 10 in the first direction x are located in the same first conductive type well region graphic 11 (equivalent to all the first pull-up transistors Pup1 and the second pull-down transistors Pdown2 of the two adjacent columns of 8T DP-SRAM in the first direction x are located in the same first conductive type well region); all the second regions 102 of the two adjacent columns of the minimum repeating unit graphics 10 in the first direction x are located in the same second conductive type well region graphic 12 (equivalent to all the first pull-down transistors Pdown1, the second pull-down transistor Pdown2, the first transfer gate transistor Pgate1, the second transfer gate transistor Pgate2, the third transfer gate transistor Pgate3 and the fourth transfer gate transistor Pgate4 of the two adjacent columns of 8T DP-SRAM in the first direction x are located in the same first conductive type well region).

[0050] The first conductive type well region pattern 11 has a first lead-out pattern Pickup1 at both ends along the second direction y, and the first conductive type well region corresponding to the first conductive type well region pattern 11 can be led out through the first lead-out pattern Pickup1. In this way, the first lead-out pattern Pickup1 does not need to be set in each of the minimum repeating unit patterns 10, which reduces the area of ​​the minimum repeating unit pattern 10, thereby reducing the area of ​​the layout structure, reducing the leakage power of the device, and at the same time, it can also simplify the routing of the back section and reduce the complexity of the device manufacturing process.

[0051] In this embodiment, the first lead-out pattern Pickup1 is symmetrically arranged with respect to the center of the first conductive type well region pattern 11 in the second direction y, which meets the layout design requirements of 8T DP-SRAM.

[0052] Please continue reading Figure 1The second region 102 of each of the minimum repeating unit patterns 10 has a second lead-out pattern Pickup2, and the second conductive type well region corresponding to the second conductive type well region pattern 12 can be led out through the second lead-out pattern Pickup2.

[0053] Since there is a vacant area between the third transfer gate transistor graphic PG3 and the fourth transfer gate transistor graphic PG4 in the second direction y, in this embodiment, the second lead-out graphic Pickup2 is located between the third transfer gate transistor graphic PG3 and the fourth transfer gate transistor graphic PG4 in the second direction y, and the third transfer gate transistor graphic PG3 and the fourth transfer gate transistor graphic PG4 are symmetrically arranged on both sides of the second lead-out graphic Pickup2 in the second direction y.

[0054] Further, in this embodiment, in this embodiment, the pull-up transistor pattern is a PMOS transistor pattern, that is, the first pull-up transistor Pup1 and the second pull-up transistor Pup2 are both PMOS transistors; the pull-down transistor pattern and the transmission gate transistor pattern are both NMOS transistor patterns, that is, the first pull-up transistor Pup1, the second pull-up transistor Pup2, the first transmission gate transistor Pgate1, the second transmission gate transistor Pgate2, the third transmission gate transistor Pgate3 and the fourth transmission gate transistor Pgate4 are all NMOS transistors. Based on this, the first conductive type well region is an N-type conductive type well region, and the first conductive type well region pattern 11 is an N-type conductive type well region pattern; the second conductive type well region is a P-type conductive type well region, and the second conductive type well region pattern 12 is a P-type conductive type well region pattern.

[0055] It should be noted that there is also a first plug graphic CT1 in the minimum repeating unit graphic 10. The first plug graphic CT1 is used to lead out the active area graphic AA, the gate graphic Gate, the first lead-out graphic Pickup1 and the second lead-out graphic Pickup2 in the layout structure of the semiconductor device, which will not be repeated here.

[0056] Figure 4 The schematic diagram of the area of ​​the layout structure of the back-end process of the semiconductor device provided in this embodiment corresponding to the minimum repeating unit pattern 10. Figure 4As shown, the layout structure of the back-end process has a first metal wire pattern M1, a second plug pattern CT2, a second metal wire pattern M2, a third plug pattern CT3 and a third metal wire pattern M3. Through the first metal wire pattern M1, the second plug pattern CT2, the second metal wire pattern M2 and the third plug pattern CT3, the active area pattern AA, the gate pattern Gate, the first lead-out pattern Pickup1 and the second lead-out pattern Pickup2 in the layout structure of the semiconductor device can be further led out to complete the routing.

[0057] It can be understood that if the first lead-out pattern Pickup1 is arranged in the minimum repeating unit pattern 10 (usually arranged symmetrically on both sides of the pull-up transistor pattern along the second direction y), then the Figure 4 The area within the dotted circle needs to be set with the first metal wire pattern M1, the second plug pattern CT2, the second metal wire pattern M2 and the third plug pattern CT3. In order to meet the minimum spacing requirement between adjacent metal wire patterns, the area of ​​the minimum repeating unit pattern 10 is larger than that of this embodiment.

[0058] It should be noted that the layout structure of the semiconductor device in this embodiment can be applied not only to the planar gate process, but also to advanced processes such as FinFET.

[0059] Embodiment 2

[0060] Figure 5 A schematic diagram of the layout structure of the semiconductor device provided in this embodiment, Figure 6 Schematic diagram of the minimum repeating unit pattern 10 provided in this embodiment. Figure 5 and Figure 6 As shown, the difference from the first embodiment is that in this embodiment, the second conductive type well region pattern 12 has the second lead-out pattern Pickup2 at both ends along the second direction y, and the second conductive type well region corresponding to the second conductive type well region pattern 12 can be led out through the second lead-out pattern Pickup2. In this way, the second lead-out pattern Pickup2 does not need to be set in each of the minimum repeating unit patterns 10, which can simplify the routing of the subsequent stage and reduce the complexity of the device manufacturing process.

[0061] Optionally, the second lead-out pattern Pickup2 is symmetrically arranged with respect to the center of the second conductive type well region pattern 12 in the second direction y, meeting the layout design requirements of 8T DP-SRAM.

[0062] In summary, in the layout structure of the semiconductor device provided by the embodiment of the present invention, the minimum repeating unit pattern is arrayed along the first direction and the second direction, any two adjacent minimum repeating unit patterns are arranged in mirror symmetry, the number of the minimum repeating unit patterns in the first direction and the second direction is greater than or equal to 2, the minimum repeating unit pattern includes a first area and a second area arranged in sequence along the first direction, the first area has a pull-up transistor pattern, the second area has a pull-down transistor pattern and a transmission gate transistor pattern, the first conductive type well region pattern and the second conductive type well region both extend along the second direction and are arranged at intervals along the first direction, the first areas of the two adjacent columns of the minimum repeating unit patterns in the first direction are both located in the corresponding first conductive type well region pattern, and the second areas of the two adjacent columns of the minimum repeating unit patterns in the first direction are both located in the corresponding second conductive type well region pattern. In the present invention, the first conductive type well region pattern has a first lead-out pattern at both ends along the second direction, and the first lead-out pattern does not need to be set in each of the minimum repeating unit patterns, thereby reducing the area of ​​the minimum repeating unit pattern, thereby reducing the area of ​​the layout structure, reducing the leakage power of the device, and at the same time, simplifying the routing of the later stage and reducing the complexity of the device preparation process.

[0063] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0064] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0065] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0066] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A layout structure of a semiconductor device, characterized in that: It includes a first conductive type well region pattern, a second conductive type well region pattern and a minimum repeating unit pattern, wherein the minimum repeating unit pattern is arrayed along a first direction and a second direction, any two adjacent minimum repeating unit patterns are arranged in mirror symmetry, and the number of the minimum repeating unit patterns in the first direction and the second direction is greater than or equal to 2; The minimum repeating unit pattern includes a first region and a second region sequentially arranged along the first direction, the first region has a pull-up transistor pattern, and the second region has a pull-down transistor pattern and a transfer gate transistor pattern; The first conductive type well region pattern and the second conductive type well region pattern both extend along the second direction and are arranged at intervals along the first direction, the first regions of two adjacent columns of the minimum repeating unit pattern in the first direction are both located in the corresponding first conductive type well region pattern, and the second regions of two adjacent columns of the minimum repeating unit pattern in the first direction are both located in the corresponding second conductive type well region pattern; The first conductive type well region pattern has first lead-out patterns at both ends along the second direction; The pull-up transistor pattern includes a first pull-up transistor pattern and a second pull-up transistor pattern, and the first pull-up transistor pattern and the second pull-up transistor pattern are symmetrically arranged along the second direction; The pull-down transistor pattern includes a first pull-down transistor pattern and a second pull-down transistor pattern, the first pull-down transistor pattern and the second pull-down transistor pattern are symmetrically arranged along the second direction; and, The transfer gate transistor pattern includes a first transfer gate transistor pattern, a second transfer gate transistor pattern, a third transfer gate transistor pattern and a fourth transfer gate transistor pattern, the first transfer gate transistor pattern and the second transfer gate transistor pattern are symmetrically arranged along the second direction, and the third transfer gate transistor pattern and the fourth transfer gate transistor pattern are symmetrically arranged along the second direction; The first transfer gate transistor pattern is closer to the pull-down transistor pattern in the first direction than the third transfer gate transistor pattern; The second pass-gate transistor pattern is closer to the pull-down transistor pattern in the first direction than the fourth pass-gate transistor pattern.

2. The layout structure of the semiconductor device according to claim 1, characterized in that: The first lead-out pattern is symmetrically arranged relative to the center of the first conductive type well region pattern in the second direction.

3. The layout structure of the semiconductor device according to claim 1, characterized in that: The first transfer gate transistor pattern and the second transfer gate transistor pattern are symmetrically arranged on both sides of the pull-down transistor pattern in the second direction, and the third transfer gate transistor pattern and the fourth transfer gate transistor pattern are symmetrically arranged on both sides of the pull-down transistor pattern in the second direction; as well as, The first transfer gate transistor pattern and the third transfer gate transistor pattern are located on the same side of the pull-down transistor pattern in the second direction, and the second transfer gate transistor pattern and the fourth transfer gate transistor pattern are located on the same side of the pull-down transistor pattern in the second direction.

4. The layout structure of the semiconductor device according to claim 1, characterized in that: A second lead-out pattern is provided in the second area.

5. The layout structure of the semiconductor device according to claim 4, characterized in that: The second lead-out pattern is located between the third transfer gate transistor pattern and the fourth transfer gate transistor pattern in the second direction, and the third transfer gate transistor pattern and the fourth transfer gate transistor pattern are symmetrically arranged on both sides of the second lead-out pattern in the second direction.

6. The layout structure of the semiconductor device according to claim 1, characterized in that: The second conductive type well region pattern has second lead-out patterns at both ends along the second direction.

7. The layout structure of the semiconductor device according to claim 6, characterized in that: The second lead-out pattern is symmetrically arranged relative to the center of the second conductive type well region pattern in the second direction.

8. The layout structure of the semiconductor device according to claim 1, characterized in that: The first pull-up transistor pattern, the second pull-up transistor pattern, the first pull-down transistor pattern, the second pull-down transistor pattern, the first transfer gate transistor pattern, the second transfer gate transistor pattern, the third transfer gate transistor pattern and the fourth transfer gate transistor pattern all include active area patterns and gate patterns.

9. The layout structure of the semiconductor device according to claim 8, characterized in that: The active area patterns of the first pull-up transistor pattern and the second pull-up transistor pattern are connected as one, the active area patterns of the first pull-down transistor pattern, the second pull-down transistor pattern, the first transfer gate transistor pattern, the second transfer gate transistor pattern, the third transfer gate transistor pattern and the fourth transfer gate transistor pattern are connected as one, the gate patterns of the first pull-up transistor pattern and the first pull-down transistor pattern are connected as one, and the gate patterns of the second pull-up transistor pattern and the second pull-down transistor pattern are connected as one.

10. The layout structure of the semiconductor device according to claim 8 or 9, characterized in that: In two adjacent minimum repeating unit patterns in the first direction, active area patterns of two first pull-up transistor patterns partially overlap, active area patterns of two second pull-up transistor patterns partially overlap, gate patterns of two third transfer gate transistor patterns partially overlap, and gate patterns of two fourth transfer gate transistor patterns partially overlap; as well as, In two adjacent minimum repeating unit patterns in the second direction, active area patterns of two first transfer gate transistor patterns partially overlap, and active area patterns of two third transfer gate transistor patterns partially overlap; Alternatively, the active region patterns of the two second transfer gate transistor patterns partially overlap, and the active region patterns of the two fourth transfer gate transistor patterns partially overlap.

11. The layout structure of the semiconductor device according to claim 1, characterized in that: The pull-up transistor pattern is a pattern of a PMOS transistor, the pull-down transistor pattern and the transfer gate transistor pattern are both patterns of an NMOS transistor, the first conductive type well region pattern is a pattern of an N-type conductive type well region, and the second conductive type well region pattern is a pattern of a P-type conductive type well region.

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