Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises: a substrate; a semiconductor column located on the substrate, the semiconductor column comprises: a source region, a channel region and a drain region arranged in sequence in a direction away from the surface of the substrate, the average band gap of the source region is a first band gap, the average band gap of the channel region is a second band gap, and the first band gap is smaller than the second band gap. The semiconductor structure provided by the embodiment of the present application can at least reduce the subthreshold swing of the transistor.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] Subthreshold swing is a performance index for measuring the rate of mutual conversion between the on and off states of a transistor, which represents the amount of change in gate voltage required for a ten-fold change in source-drain current, and is also known as SS factor. The smaller the SS factor, the faster the ON / OFF rate, and the lower the power consumption of the transistor.

[0003] There are three types of conventional transistors with low SS: tunneling transistors, negative capacitance transistors (NC-FETs), and cold source transistors. In order to construct a tunneling transistor, the heterojunction usually needs to be doped. However, the heterojunction will cause a mismatch at the interface, which will cause the on-state current of the device to decrease, and thus the switching ratio of the transistor will decrease, resulting in a large subthreshold swing of the transistor. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof, which at least facilitate reducing the subthreshold swing of a transistor.

[0005] Embodiments of the present disclosure provide a semiconductor structure, comprising: a substrate; a semiconductor pillar on the substrate, the semiconductor pillar comprising: a source region, a channel region, and a drain region arranged in sequence along a direction away from a surface of the substrate, an average band gap of the source region being a first band gap, an average band gap of the channel region being a second band gap, the first band gap being smaller than the second band gap.

[0006] In some embodiments, the semiconductor pillar is an integrated structure, and a cross-sectional area of the channel region along a direction parallel to the surface of the substrate is smaller than a cross-sectional area of the source region along the direction parallel to the surface of the substrate, so that the first band gap is smaller than the second band gap.

[0007] In some embodiments, a width dimension of the channel region along a first direction is smaller than a width dimension of the source region along the first direction, the first direction being parallel to the surface of the substrate.

[0008] In some embodiments, along the direction away from the surface of the substrate, a width dimension of the channel region along the first direction is constant, and a width dimension of the source region along the first direction is constant.

[0009] In some embodiments, the channel region includes: a first region and a second region arranged in sequence along a direction away from the substrate surface, the first region is in contact with the source region, at least part of the channel region is the second region, the orthographic projection of the second region on the substrate surface is located within the orthographic projection of the first region on the substrate surface, and the cross-sectional area of ​​the first region in a direction parallel to the substrate surface is not greater than the cross-sectional area of ​​the source region in a direction parallel to the substrate surface.

[0010] In some embodiments, in a direction away from the surface of the substrate, the width of the second region along the first direction remains constant, and the width of the first region along the first direction gradually decreases.

[0011] In some embodiments, along a direction perpendicular to the surface of the substrate, a width dimension of the source region along the first direction is constant.

[0012] In some embodiments, an orthographic projection of the drain region on the substrate surface is located within an orthographic projection of the source region on the substrate surface.

[0013] In some embodiments, the doping ion type of the channel region is the same as the doping ion type of the drain region, and the doping ion type of the source region is different from the doping ion type of the channel region.

[0014] In some embodiments, the source region includes a first sub-source region and a second sub-source region arranged in sequence away from the substrate surface, the second sub-source region is in contact with the channel region, and the doping ion type of the first sub-source region is different from the doping ion type of the second sub-source region.

[0015] In some embodiments, the doping ion type of the drain region is different from the doping ion type of the channel region, the doping ion type of the channel region is the same as the doping type of the first sub-source region, and the doping ion concentration of the channel region is less than the doping ion concentration of the first sub-source region.

[0016] In some embodiments, the system further includes: a word line surrounding a side surface of the semiconductor column corresponding to the channel region; and a bit line located between the substrate and the semiconductor column and electrically contacting the semiconductor column corresponding to the source region.

[0017] In some embodiments, there are multiple semiconductor pillars, and the multiple semiconductor pillars are arranged at intervals along the second direction and the third direction, and the second direction is different from the third direction; wherein, there are multiple word lines, and the multiple word lines are arranged at intervals along the second direction, each word line extends along the third direction, and one word line surrounds the channel region of each of the multiple semiconductor pillars arranged at intervals along the third direction; there are multiple bit lines, and the multiple bit lines are arranged at intervals along the third direction, each word line extends along the second direction, and one bit line is electrically contacted with the source region of each of the multiple semiconductor pillars arranged at intervals along the second direction.

[0018] Correspondingly, an embodiment of the present disclosure also provides a method for preparing a semiconductor structure, comprising: providing a substrate; forming a semiconductor column on the substrate, the semiconductor column comprising: a source region, a channel region, and a drain region arranged in sequence in a direction away from the surface of the substrate, the average band gap of the source region is a first band gap, the average band gap of the channel region is a second band gap, and the first band gap is smaller than the second band gap.

[0019] In some embodiments, a doping process is performed on the same semiconductor material layer to form the semiconductor column. In the formed semiconductor column, the width dimension of the channel region along the first direction is smaller than the width dimension of the source region along the first direction parallel to the first direction, so that the first band gap is smaller than the second band gap, and the first direction is parallel to the substrate surface.

[0020] In some embodiments, the method for forming the semiconductor column includes: providing a semiconductor material layer; etching a portion of the semiconductor material layer to form an initial semiconductor column, and the remaining semiconductor material layer forms the substrate, the width dimension of the initial semiconductor column remains unchanged in the direction away from the surface of the substrate, and the initial semiconductor column has a first part and an initial second part arranged in sequence along the direction away from the surface of the substrate; using a dry etching process to etch the side wall of the initial second part to form a second part, the width dimension of the second part in the first direction is smaller than the width dimension of the first part in the first direction, and the first part and the second part form the semiconductor column.

[0021] In some embodiments, the method for forming the semiconductor column includes: providing a silicon layer; etching the silicon layer to form an initial semiconductor column, and the remaining silicon layer forms the substrate, the width dimension of the initial semiconductor column remains unchanged in the direction away from the substrate surface, and the initial semiconductor column has a first part and an initial second part arranged in sequence along the direction away from the substrate surface; performing an in-situ water vapor oxidation process on the side wall of the initial second part to convert part of the initial second part into a silicon oxide layer; removing the silicon oxide layer, and the remaining part of the initial second part forms a second part, the width dimension of the second part along the first direction is smaller than the width dimension of the first part along the first direction, and the first part and the second part form the semiconductor column.

[0022] In some embodiments, the second part is used to form the channel region and the drain region, and the first part is used to form the source region. The method of forming the first part and the second part includes: providing a first sub-semiconductor material layer, performing a doping process on the top of the first sub-semiconductor material layer to convert part of the first sub-semiconductor material layer into a first semiconductor layer, and the remaining part of the first sub-semiconductor layer forms the substrate; forming a second sub-semiconductor material layer on the surface of the first semiconductor layer; etching part of the second sub-semiconductor material layer to form the initial second part, and etching part of the first semiconductor layer to form the first part.

[0023] In some embodiments, the second portion has a uniform type of dopant ions, and the dopant ion type of the first semiconductor layer is different from the dopant ion type of the second portion.

[0024] In some embodiments, the first semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer arranged in sequence in a direction away from the substrate surface, the second sub-semiconductor layer is in contact with the second portion, and the doping ion type of the first sub-semiconductor layer is different from the doping ion type of the second sub-semiconductor layer.

[0025] In some embodiments, the doping ion type of the second portion corresponding to the drain region is different from the doping ion type of the second portion corresponding to the channel region, the doping ion type of the second portion corresponding to the channel region is the same as the doping ion type of the first sub-semiconductor layer, and the doping ion concentration of the second portion corresponding to the channel region is less than the doping ion concentration of the first sub-semiconductor layer.

[0026] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0027] In the semiconductor structure provided by the embodiment of the present disclosure, the average bandgap width of the channel region is greater than the average bandgap width of the source region. When the transistor is turned on, due to the smaller average bandgap width of the source region, the source region has a smaller barrier height, and a larger number of carriers can be transferred from the source region to the drain region via the channel region, which is beneficial to improving the mobility of the carriers. When the transistor is turned off, due to the larger average bandgap width of the channel region, the channel region has a higher barrier height, making it almost impossible for electrons from the source region to be transferred through the channel region to the drain region, reducing the off-state leakage current of the channel region when the transistor is turned off, and can increase the switching ratio of the transistor and reduce the subthreshold swing of the transistor. It is not difficult to find that due to the increase in the on-state current of the transistor and the reduction in the off-state leakage current of the transistor, the switching ratio of the transistor is increased, thereby reducing the subthreshold swing of the transistor, thereby improving the response rate of the transistor and making the power consumption of the transistor lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 A schematic cross-sectional view of a first semiconductor structure provided in one embodiment of the present disclosure;

[0030] Figure 2 A schematic cross-sectional view of a second semiconductor structure provided in one embodiment of the present disclosure;

[0031] Figure 3 A schematic cross-sectional view of a third semiconductor structure provided in one embodiment of the present disclosure;

[0032] Figure 4 A schematic diagram of an energy band structure of a semiconductor structure provided in one embodiment of the present disclosure;

[0033] Figure 5 A schematic cross-sectional view of a fourth semiconductor structure provided in one embodiment of the present disclosure;

[0034] Figure 6 A schematic cross-sectional view of a fifth semiconductor structure provided in one embodiment of the present disclosure;

[0035] Figure 7A schematic cross-sectional view of a sixth semiconductor structure provided in one embodiment of the present disclosure;

[0036] Figure 8 A schematic cross-sectional view of a seventh semiconductor structure provided in an embodiment of the present disclosure;

[0037] Figure 9 A schematic cross-sectional view of an eighth semiconductor structure provided by an embodiment of the present disclosure;

[0038] Figure 10 A schematic top view of a semiconductor structure provided in one embodiment of the present disclosure;

[0039] Figure 11 A schematic cross-sectional view of a ninth semiconductor structure provided by an embodiment of the present disclosure;

[0040] Figure 12 A schematic cross-sectional structure diagram corresponding to a step of forming a semiconductor material layer in a method for preparing a semiconductor structure provided by another embodiment of the present disclosure;

[0041] Figure 13 A schematic cross-sectional structure diagram along the aa' direction corresponding to the step of forming an initial semiconductor column in a method for preparing a semiconductor structure provided by another embodiment of the present disclosure;

[0042] Figure 14 A schematic cross-sectional structure diagram along the bb' direction corresponding to the step of forming an initial semiconductor column in a method for preparing a semiconductor structure provided by another embodiment of the present disclosure;

[0043] Figure 15 A schematic cross-sectional structure diagram along the aa' direction corresponding to the step of forming the second portion in a method for preparing a semiconductor structure provided by another embodiment of the present disclosure;

[0044] Figure 16 A schematic cross-sectional structure diagram along the bb' direction corresponding to the step of forming the second portion in a method for preparing a semiconductor structure provided by another embodiment of the present disclosure;

[0045] Figure 17 A schematic cross-sectional structure diagram along the aa' direction corresponding to a step of forming a groove in a method for preparing a semiconductor structure provided by another embodiment of the present disclosure;

[0046] Figure 18 A schematic cross-sectional structure diagram along the bb' direction corresponding to the step of forming a groove in a method for preparing a semiconductor structure provided by another embodiment of the present disclosure;

[0047] Figure 19A schematic cross-sectional structure diagram along the aa' direction corresponding to a step of forming a bit line in a method for preparing a semiconductor structure provided by another embodiment of the present disclosure;

[0048] Figure 20 A schematic cross-sectional structure diagram along the bb' direction corresponding to a step of forming a bit line in a method for preparing a semiconductor structure provided by another embodiment of the present disclosure;

[0049] Figure 21 A schematic cross-sectional structure diagram along the aa' direction corresponding to the step of forming a bit line in another semiconductor structure manufacturing method provided by another embodiment of the present disclosure;

[0050] Figure 22 A schematic cross-sectional structure diagram along the bb' direction corresponding to the step of forming a bit line in another semiconductor structure manufacturing method provided by another embodiment of the present disclosure;

[0051] Figure 23 A schematic cross-sectional structure diagram along the aa' direction corresponding to the step of forming a second sacrificial layer in another semiconductor structure preparation method provided by another embodiment of the present disclosure;

[0052] Figure 24 A schematic cross-sectional structure diagram along the bb' direction corresponding to the step of forming a second sacrificial layer in another semiconductor structure preparation method provided by another embodiment of the present disclosure;

[0053] Figure 25 A schematic cross-sectional structure diagram along the aa' direction corresponding to the step of forming a silicon oxide layer in another method for preparing a semiconductor structure provided by another embodiment of the present disclosure;

[0054] Figure 26 A schematic cross-sectional structure diagram along the bb' direction corresponding to the step of forming a silicon oxide layer in another method for preparing a semiconductor structure provided by another embodiment of the present disclosure;

[0055] Figure 27 A schematic cross-sectional structure diagram along the aa' direction corresponding to the step of forming the second portion in another semiconductor structure manufacturing method provided by another embodiment of the present disclosure;

[0056] Figure 28 A schematic cross-sectional structural diagram along the bb' direction corresponding to the step of forming the second portion in another semiconductor structure manufacturing method provided by another embodiment of the present disclosure;

[0057] Figure 29 A schematic cross-sectional structure diagram along the aa' direction corresponding to the step of forming a gate dielectric layer and a word line in another semiconductor structure fabrication method provided by another embodiment of the present disclosure;

[0058] Figure 30A cross-sectional view along the direction of bb' corresponding to the step of forming the gate dielectric layer and the word line in another semiconductor structure preparation method provided by another embodiment of the present disclosure is shown in FIG. 6B.

[0059] Figure 31 A cross-sectional view corresponding to the step of providing the first sub-semiconductor material layer in another semiconductor structure preparation method provided by another embodiment of the present disclosure is shown in FIG. 7B.

[0060] Figure 32 A cross-sectional view corresponding to the step of forming the initial second sub-semiconductor layer in another semiconductor structure preparation method provided by another embodiment of the present disclosure is shown in FIG. 8B.

[0061] Figure 33 A cross-sectional view corresponding to the step of forming the initial first sub-semiconductor layer in another semiconductor structure preparation method provided by another embodiment of the present disclosure is shown in FIG. 9B.

[0062] Figure 34 A cross-sectional view corresponding to the step of forming the first sub-semiconductor layer in another semiconductor structure preparation method provided by another embodiment of the present disclosure is shown in FIG. 10B.

[0063] Figure 35 A cross-sectional view corresponding to the step of forming the bit line and the second sub-semiconductor material layer in another semiconductor structure preparation method provided by another embodiment of the present disclosure is shown in FIG. 11B.

[0064] Figure 36 A cross-sectional view corresponding to the step of forming the initial second part in another semiconductor structure preparation method provided by another embodiment of the present disclosure is shown in FIG. 12B. DETAILED DESCRIPTION

[0065] The semiconductor structure provided by the embodiments of the present disclosure has a channel region with an average band gap width greater than that of the source region. When the transistor is turned on, the average band gap width of the source region is small, so that the source region has a small potential barrier height, and a large number of carriers can be transmitted from the source region to the drain region through the channel region, which is beneficial to improve the mobility of the carriers. When the transistor is turned off, the average band gap width of the channel region is large, so that the channel region has a high potential barrier height, making it difficult for electrons from the source region to transmit to the drain region through the channel region, reducing the off-state leakage current of the channel region when the transistor is turned off, and increasing the on-off ratio of the transistor and reducing the subthreshold swing of the transistor. It is not difficult to find that, due to the increase of the on-state current of the transistor and the decrease of the off-state leakage current of the transistor, the on-off ratio of the transistor is increased, and the response rate of the transistor is improved, and the power consumption of the transistor is low.

[0066] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0067] Figure 1 A schematic cross-sectional view of a first semiconductor structure provided in one embodiment of the present disclosure; Figure 2 A schematic cross-sectional view of a second semiconductor structure provided in one embodiment of the present disclosure; Figure 3 A schematic cross-sectional view of a third semiconductor structure provided in accordance with an embodiment of the present disclosure.

[0068] refer to Figures 1 to 3 The semiconductor structure includes: a substrate 101; a semiconductor column 10 located on the substrate 101, the semiconductor column 10 includes: a source region 12, a channel region 11 and a drain region 13 arranged in sequence along a direction away from the surface of the substrate 101, the average band gap of the source region 12 is a first band gap, the average band gap of the channel region 11 is a second band gap, and the first band gap is smaller than the second band gap.

[0069] In some embodiments, the material of the substrate 101 may be a semiconductor material, in some embodiments, the material of the substrate 101 may be silicon, in some embodiments, the substrate 101 may also be germanium, silicon germanium, or silicon on insulator.

[0070] In solid-state physics, a band gap refers to the energy difference between the top of a semiconductor's valence band and the bottom of its conduction band. In a semiconductor, only electrons with sufficient energy can be excited from the valence band, cross the band gap, and transition to the conduction band. Therefore, when a semiconductor's band gap is small, the potential barrier is small, allowing carriers to easily cross it. When the band gap is large, the potential barrier is large, making it difficult for carriers to cross.

[0071] In the embodiments of the present disclosure, the average band gap of the channel region 11 refers to the average value of the band gaps at different locations of the channel region 11, and the average band gap of the source region 12 refers to the average value of the band gaps at different locations of the source region 12. In some embodiments, multiple locations of the channel region 11 can be arbitrarily specified, and the band gaps of the specified multiple locations of the channel region 11 are measured respectively, and the average value is ultimately obtained as the average band gap of the channel region 11. In some embodiments, multiple locations of the source region 12 can be arbitrarily specified, and the band gaps of the specified multiple locations of the source region 12 are measured respectively, and the average value is ultimately obtained as the average band gap of the source region 12.

[0072] The first band gap being smaller than the second band gap means that the width of the first band gap is smaller than the width of the second band gap.

[0073] In some embodiments, the intercept method can be used to measure the band gap of the semiconductor pillar 10 corresponding to the channel region 11 and the band gap corresponding to the source region 12. The principle of the intercept method is that the absorption threshold λg of the semiconductor is inversely proportional to its band gap width Eg, and the relationship between the two is as follows:

[0074] Eg(eV)=1240 / λg(nm) (1)

[0075] Therefore, Eg can be obtained by calculating λg. The absorption of the material at different wavelengths can be obtained from the UV-vis DRS (ultraviolet visible diffuse reflectance) spectrum. Differentiate the wavelength-absorption curve once, and then make an intercept at the extreme point (the slope is the ordinate value of the extreme point). The intersection of the intercept and the abscissa is λg. Substituting it into the above formula, the bandgap width Eg of the material can be obtained. The bandgap width Eg refers to a bandgap width. Therefore, by calculating the bandgap width Eg, the bandgap width at different positions of the channel region 11 and the bandgap width at different positions of the source region 12 can be obtained.

[0076] The first band gap is set to be smaller than the second band gap. When the transistor is turned on, since the average band gap of the source region 12 is relatively small, the source region 12 has a smaller barrier height, so that a larger number of carriers in the source region 12 can cross the barrier of the source region 12 and be transmitted from the source region 12 to the channel region 11, and then transmitted to the drain region 13 through the channel region 11, which can make the on-state current of the transistor larger when it is turned on. When the transistor is turned off, since the average band gap of the channel region 11 is larger, the carriers from the source region 12 can hardly be transmitted to the drain through the channel region 11, thereby reducing the off-state leakage current when the channel is closed. In other words, while achieving a larger on-state current of the transistor, the off-state current of the transistor is smaller, thereby making the switching ratio of the transistor larger and improving the response rate of the transistor. In addition, since the off-state leakage current of the transistor is reduced, the subthreshold swing of the transistor is smaller, which can also reduce the overall power consumption of the transistor.

[0077] In some embodiments, by setting the first band gap to be smaller than the second band gap, the subthreshold swing of the transistor can be made equal to or smaller than 60 mV / dec.

[0078] For details, please refer to Figure 4 , Figure 4 1 and 2 respectively show the energy band diagrams of the source region 12 and the channel region 11 when the transistor is turned on and the energy band diagrams of the source region 12 and the channel region 11 when the transistor is turned off.

[0079] refer to Figure 4 The energy band of the source region 12 includes a conduction band Ec and a valence band Ev, and the energy band of the channel region 11 includes a conduction band Ec and a valence band Ev, wherein the conduction band Ec is below the valence band Ev. The energy band for carrier injection is above the conduction band Ec.

[0080] When the transistor is turned on, the conduction band of the channel region 11 is lowered compared to the conduction band of the source region 12, the valence band of the channel region 11 is lowered compared to the valence band of the source region 12, and the channel region 11 has an overlapping region 110 between the valence band and the conduction band, forming an energy band for carrier injection at a position as shown in FIG. 1. In the overlapping region, carriers can tunnel from the source region 12 into the channel region 11.

[0081] When the transistor is turned off, the conduction band of the channel region 11 is not changed compared to the conduction band of the source region 12 due to the large band gap width of the channel region 11, and thus the channel region 11 does not have an overlapping region between the valence band and the conduction band, and thus cannot form an energy band for carrier injection, so that when the transistor is turned off, carriers cannot pass through the channel region 11, thereby reducing the off-state current.

[0082] It can be understood that as the size of the semiconductor structure is reduced, the size of the semiconductor pillar 10 reaches the nanometer level. The nanometer material can produce surface effect, which is the change in material properties caused by the sharp increase in the ratio of the number of surface atoms to the total number of atoms of the nanometer ion with the change in particle size. As the size of the nanometer material is reduced, the specific surface area and the proportion of surface atoms will significantly increase, causing changes in material properties, so that the surface of the atoms will break the bond, and then lead to the contraction of the bond length and the enhancement of the bond energy. The contraction of the bond length and the enhancement of the bond energy will cause the local strain and energy pinning of the nanometer material, resulting in an increase in the band gap width of the nanometer material.

[0083] That is, when the size of the semiconductor pillar 10 reaches the nanometer level, the smaller the size of the semiconductor pillar 10, the wider the band gap of the semiconductor pillar 10.

[0084] Reference Figures 1 to 3 In some embodiments, the semiconductor pillar is an integrated structure, the cross-sectional area of the channel region 11 in the direction parallel to the surface of the substrate 101 is smaller than the cross-sectional area of the source region 12 in the direction parallel to the surface of the substrate 101, so that the first band gap is smaller than the second band gap. The integrated structure of the semiconductor pillar 10 means that the materials of the channel region 11, the source region 12 and the drain region 13 are the same, and the channel region 11, the source region 12 and the drain region 13 are obtained by doping the same semiconductor material.

[0085] That is, in the case that the material of the source region 12 is the same as the material of the channel region 11, only the cross-sectional size of the channel region 11 and the cross-sectional size of the source region 12 are changed, so that in the same cross-sectional direction, the cross-sectional size of the channel region 11 is smaller than the cross-sectional size of the source region 12, achieving that the band gap width of the channel region 11 is smaller than the band gap width of the source region 12.

[0086] Because the source region 12 and the channel region 11 are an integrated structure, the source region 12, the channel region 11, and the drain region 13 form a homojunction transistor. The homojunction transistor can increase the on-state current of the transistor, thereby improving the transistor's on-off ratio. In this way, on the basis of increasing the transistor's on-state current by setting the first band gap smaller than the second band gap, the transistor's on-off ratio can be further increased, thereby further reducing the transistor's subthreshold swing.

[0087] In some embodiments, the width of the channel region 11 along a first direction is smaller than the width of the source region 12 along the first direction, where the first direction is parallel to the surface of the substrate 101. That is, along the same direction, the width of at least a portion of the channel region 11 parallel to the surface of the substrate 101 is smaller than the cross-sectional area of ​​the source region 12 in the direction parallel to the surface of the substrate 101.

[0088] It should be noted that the first direction may be any direction parallel to the surface of the substrate 101 .

[0089] Figure 10 A schematic top view of a semiconductor structure provided in one embodiment of the present disclosure; Figure 11 This is a schematic cross-sectional view of a ninth semiconductor structure provided by an embodiment of the present disclosure. Figure 11 for Figure 10 Schematic diagram of the cross-sectional structure along the aa' direction.

[0090] refer to Figure 10 as well as Figure 11 In some embodiments, there are multiple semiconductor pillars 10, and the multiple semiconductor pillars 10 are arranged at intervals along the second direction X and the third direction Y, where the second direction X is different from the third direction Y. In some embodiments, the first direction can be the same as the second direction X. In some embodiments, the first direction can also be the same as the third direction Y. In some embodiments, the first direction can also be any direction different from the second direction X and the third direction Y. It is only necessary that along the same direction, the width dimension of at least a portion of the channel region 11 parallel to the surface of the substrate 101 is smaller than the width dimension of the source region 12 parallel to the surface of the substrate 101, so that the cross-sectional area of ​​at least a portion of the channel region 11 is smaller than the cross-sectional area of ​​the source region 12.

[0091] Continue to refer Figures 1 to 3 In some embodiments, along any direction parallel to the surface of the substrate 101, the width of at least a portion of the channel region 11 is smaller than the width of the source region 12. In other words, the orthographic projection of at least a portion of the channel region 11 on the surface of the substrate 101 is located within the orthographic projection of the source region 12 on the surface of the substrate 101, such that the cross-sectional area of ​​the channel region 11 along the direction parallel to the surface of the substrate 101 is smaller than the cross-sectional area of ​​the source region 12 along the direction parallel to the surface of the substrate 101.

[0092] In some embodiments, the width of at least a portion of the channel region 11 may be smaller than the width of the source region 12 only along one or several directions parallel to the surface of the substrate 101. For example, along the second direction X, the width of at least a portion of the channel region 11 may be smaller than the width of the source region 12, and along the third direction Y, the width of at least a portion of the channel region 11 may be equal to the width of the source region 12.

[0093] refer to Figure 1 In some embodiments, the width of the channel region 11 along the first direction remains constant as it moves away from the surface of the substrate 101, and the width of the source region 12 along the first direction remains constant. In one specific example, the orthographic projection of the channel region 11 on the surface of the substrate 101 may be circular, and the orthographic projection of the source region 12 on the surface of the substrate 101 may be circular. In another specific example, the orthographic projection of the channel region on the surface of the substrate 101 may be rectangular, and the orthographic projection of the source region 12 on the surface of the substrate may also be rectangular.

[0094] refer to Figure 2 、 Figure 3 、 Figure 5 as well as Figure 6 In some embodiments, the channel region 11 includes: a first region 111 and a second region 112 arranged in sequence along a direction away from the surface of the substrate 101. The first region 111 contacts the source region 12. At least a portion of the channel region 11 is the second region 112. The orthographic projection of the second region 112 on the surface of the substrate 101 is located within the orthographic projection of the first region 111 on the surface of the substrate 101. The cross-sectional area of ​​the first region 111 in a direction parallel to the surface of the substrate 101 is no greater than the cross-sectional area of ​​the source region 12 in a direction parallel to the surface of the substrate 101. In other words, in any direction parallel to the surface of the substrate 101, the width of the second region 112 is smaller than the width of the first region 111.

[0095] In some embodiments, the height of the first region 111 in a direction perpendicular to the surface of the substrate 101 is smaller than the height of the second region 112 in a direction perpendicular to the surface of the substrate 101. In this way, the second region 112 with a smaller cross-sectional area occupies the majority of the channel region 11, which is beneficial to ensure that the volume of the overall channel region 11 is small and that the average band gap width of the channel region 11 is smaller than the band gap width of the source region 12.

[0096] In some embodiments, the orthographic projection of the channel region 11 on the surface of the substrate 101 is circular, the orthographic projection of the source region 12 on the surface of the substrate 101 is circular, and the ratio of the minimum diameter of the channel region 11 to the diameter of the source region 12 is 1:3 to 1:12, for example, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, 1:10, 1:11, or 1:12. Within the above range, it can be ensured that the average bandgap width of the channel region 11 is smaller than the bandgap width of the source region 12.

[0097] refer to Figure 2 、 Figure 3 、 Figure 5 as well as Figure 6 In some embodiments, in the direction away from the surface of the substrate 101, the width dimension of the second region 112 along the first direction remains unchanged, the width dimension of the first region 111 along the first direction gradually decreases, and the width dimension of the first region 111 along the first direction is equal to the width dimension of the source region 12 along the first direction.

[0098] In some embodiments, if the channel region 11 includes the first region 111 and the second region 112 , the width of the source region 12 along the first direction perpendicular to the surface of the substrate 101 may remain constant.

[0099] refer to Figure 3 、 Figure 5 as well as Figure 6 In some embodiments, the source region 12 may also include a third region 121 and a fourth region 122 arranged in sequence along a direction away from the surface of the substrate 101. The fourth region 122 is in contact with the channel region 11. Along the direction away from the surface of the substrate 101, the width of the fourth region 122 in the first direction is greater than the width of the channel region 11 along the first direction. The width of the third region 121 in the first direction is greater than the width of the fourth region 122 along the first direction. Along the direction away from the surface of the substrate 101, the width of the fourth region 122 in the first direction gradually decreases, while the width of the third region 121 in the first direction remains unchanged.

[0100] In some embodiments, the orthographic projection of the drain region 13 on the surface of the substrate 101 is located within the orthographic projection of the source region 12 on the surface of the substrate 101. That is, the cross-sectional area of ​​the drain region 13 in a direction parallel to the surface of the substrate 101 is smaller than the cross-sectional area of ​​the source region 12 in a direction parallel to the surface of the substrate 101. The average band gap of the drain region 13 can be the third band gap, so that the third band gap is larger than the first band gap. When the transistor is turned off, due to the small average band gap of the drain region 13, the drain region 13 can form a larger potential barrier, which makes it more difficult for carriers in the drain region 13 to cross the potential barrier of the drain region 13, further reducing the number of carriers injected into the channel region 11, reducing the off-state leakage current, and further improving the switching ratio of the transistor and the response rate of the transistor.

[0101] In some embodiments, the width of the drain region 13 along the first direction remains constant in a direction away from the surface of the substrate 101. In a specific example, the orthographic projection of the drain region 13 on the surface of the substrate 101 can be a circle or a rectangle.

[0102] In some embodiments, the semiconductor pillar 10 may not be an integrated structure, that is, the material of the source region 12 may be different from the material of the drain region 13. In some embodiments, the source region 12 and the channel region 11 may be prepared separately by selecting materials with different band gaps, so that the band gap width of the source region 12 is smaller than the band gap width of the channel region 11.

[0103] In some embodiments, the source region 12 may be made of a narrow bandgap semiconductor material, such as germanium, silicon, silicon carbide, gallium nitride, or any of III-V valence elements. The channel region 11 may be made of a wide bandgap semiconductor material, such as aluminum gallium nitride, aluminum nitride, or boron nitride.

[0104] In some embodiments, the doping ion type of the channel region is the same as the doping ion type of the drain region 13, and the doping ion type of the source region 12 is different from the doping ion type of the channel region 11. In this way, the transistor formed by the channel region 11, the drain region 13, and the source region 12 is a tunneling transistor.

[0105] In some embodiments, the doping ion type of the channel region 11 is the same as the doping ion type of the drain region 13 , the doping ion type of the source region 12 is different from the doping ion type of the channel region 11 , and the doping ion concentration of the channel region 11 is less than the doping ion concentration of the source region 12 .

[0106] In some embodiments, the doping ions of the channel region 11 and the drain region 13 may be P-type doping ions, and the doping ions of the source region 12 may be N-type doping ions.

[0107] In some embodiments, the doping ions of the channel region 11 and the drain region 13 may be N-type doping ions, and the doping ions of the source region 12 may be P-type doping ions.

[0108] In some embodiments, the P-type dopant ions may include any one of boron ions, aluminum ions, gallium ions, or indium ions. In some embodiments, the N-type dopant ions may include any one of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

[0109] The source region 12 includes a third region 121 and a fourth region 122 arranged in a direction away from the surface of the substrate 101. The fourth region 122 contacts the channel region 11. The dopant ion type of the third region 121 is different from the dopant ion type of the fourth region 122. In some embodiments, the dopant ion type of the third region 121 can be either P-type or N-type, and the dopant ion type of the fourth region 122 can be either P-type or N-type. In other words, the third region 121 and the fourth region 122 form a PN junction.

[0110] It is understandable that the off-state leakage current is also related to the transfer characteristics of hot carriers in the transistor. Hot carriers are carriers with high energy, whose kinetic energy is higher than the average thermal motion energy, so their movement speed is also very high. Hot carriers can cause damage to transistor devices. As the degree of damage increases, the current-voltage characteristics of the transistor will change. When the current-voltage parameters of the transistor change beyond a certain limit, the transistor will fail. As the size of the semiconductor structure becomes smaller and smaller, it is difficult to shield the transport of hot carriers in the high-energy area, and thus it is impossible to limit the leakage current in the off state while reducing the voltage supply, resulting in excessive power consumption of the transistor and an excessively large switching ratio of the transistor, which reduces the response rate of the transistor.

[0111] The PN junction formed by the third region 121 and the fourth region 122 can effectively suppress thermally excited hot carriers, reduce the off-state leakage current caused by excessive hot carriers transferred to the channel, further reduce the switching ratio of the transistor, and reduce the power consumption of the transistor.

[0112] refer to Figure 3 In some embodiments, the channel region 11 includes a first region 111 and a second region 112 arranged in sequence along a direction away from the surface of the substrate 101, and the source region 12 includes a third region 121 and a fourth region 122 arranged in sequence along a direction away from the surface of the substrate 101. In the direction away from the surface of the substrate 101, the width of the first region 111 gradually decreases, the width of the second region 112 remains unchanged, the width of the third region 121 remains unchanged, and the width of the fourth region 122 gradually decreases.

[0113] refer to Figure 5 as well as Figure 6In some embodiments, the source region 12 includes, in sequence in a direction away from the surface of the substrate 101, a third region 121 and a fourth region 122, and the third region 121 and the fourth region 122 are configured to form a PN junction. The fourth region 122 is in electrical contact with the channel region 11, and the fourth region 122 can include, in sequence in a direction away from the surface of the substrate 101, a fifth region 1211 and a sixth region 1212, the sixth region 1212 is in electrical contact with the channel region 11, and a projection of the sixth region 1212 on the surface of the substrate 101 is located within a projection of the fifth region 1211 on the surface of the substrate 101.

[0114] Reference is made to Figure 5 In some embodiments, in the direction away from the surface of the substrate 101, the sixth region 1212 has a width in the first direction that is the same as a width of the channel region 11 in the first direction. In other words, the projection of the sixth region 1212 on the surface of the substrate 101 coincides with the projection of the channel region 11 on the surface of the substrate 101. The fifth region 1211 has a width in the first direction that gradually decreases, and the third region 121 has a width in the first direction that is constant.

[0115] Reference is made to Figure 6 In some embodiments, in the direction away from the surface of the substrate 101, the sixth region 1212 has a width in the first direction that gradually decreases, the fifth region 1211 has a width in the first direction that gradually decreases, and the third region 121 has a width in the first direction that is constant.

[0116] In some embodiments, in the direction away from the surface of the substrate 101, the sixth region has a width in the first direction that gradually decreases, the fifth region has a width in the first direction that can also be constant, and the third region 121 has a width in the first direction that is constant.

[0117] In some embodiments, the drain region 13 is configured to form a drain region of a transistor, and the drain region 13 includes, in sequence in a direction perpendicular to the surface of the substrate 101, a third sub-drain region (not shown) and a fourth sub-drain region (not shown), the third sub-drain region and the fourth sub-drain region have different types of doping ions, and the third sub-drain region is in contact with the channel region 11.

[0118] In some embodiments, the third sub-drain region can have either of a P-type or an N-type, and the fourth sub-drain region can have the other of the P-type or the N-type. That is, the third sub-drain region and the fourth sub-drain region form a PN junction, effectively suppresses hot carriers excited by heat, reduces off-state current caused by excessive number of hot carriers transmitted into the channel, and further reduces the sub-threshold swing at room temperature, so that the sub-threshold swing at room temperature can be less than or equal to a preset value.

[0119] In some embodiments, the drain region 13 includes a third sub-drain region and a fourth sub-drain region, and the third sub-drain region and the fourth sub-drain region form a PN junction; the source region 12 includes a third region 121 and a fourth region 122, and the third region 121 and the fourth region 122 form a PN junction, thereby suppressing thermally excited hot carriers in the source region 12 and the drain region 13 of the transistor to a greater extent, reducing the number of hot carriers crossing the channel barrier to reach the channel region 11, reducing the off-state leakage current, further reducing the switching ratio of the transistor, and improving the response rate of the transistor.

[0120] In some embodiments, the doping ion type of the drain region 13 may be different from the doping ion type of the channel region 11. The doping ion type of the channel region 11 is the same as the doping type of the third region 121, and the doping ion concentration of the channel region 11 is lower than the doping ion concentration of the third region 121. In other words, the doping ion type of the fourth region 122 is different from the doping ion type of the channel region 11.

[0121] In some embodiments, the doping ion type of the fourth region 122 is P-type, the doping ion type of the third region 121 is N-type, and the doping ion type of the channel region 11 is P-type.

[0122] In some embodiments, the doping ion type of the fourth region 122 is N-type, the doping ion type of the third region 121 is P-type, and the doping ion type of the channel region 11 is N-type.

[0123] In a specific example, the dopant ion type of the third region 121 is P-type, the dopant ion type of the fourth region 122 is N-type, the dopant ion type of the channel region 11 is P-type, and the dopant ion type of the drain region 13 is N-type. In another specific example, the dopant ion type of the third region 121 may also be N-type, the dopant ion type of the fourth region 122 may also be P-type, the dopant ion type of the channel region 11 may also be N-type, and the dopant ion type of the drain region 13 may also be N-type.

[0124] In some embodiments, the doping ion type of the channel region 11 may be the same as the doping ion type of the fourth region 122, and the doping ion concentration of the channel region 11 is lower than the doping ion concentration of the fourth region 122. For example, the doping ion type of the channel region 11 and the doping ion type of the fourth region 122 are both P-type, or the doping ion type of the channel region 11 and the doping ion type of the fourth region 122 are both N-type.

[0125] refer to Figures 7 to 9 In some embodiments, the semiconductor structure further includes a word line 102 , which surrounds a side surface of the semiconductor pillar 10 corresponding to the channel region 11 .

[0126] In some embodiments, the semiconductor structure further includes a gate dielectric layer 103, which is located on the side of the semiconductor pillar 10 in the channel region 11. The word line 102 is located on the surface of the gate dielectric layer 103. In some embodiments, the gate dielectric layer 103 may be made of silicon oxide. In some embodiments, the word line 102 may be made of a conductive material, such as a metal material, which may be at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or ruthenium.

[0127] In some embodiments, the semiconductor structure further includes a bit line 104 located between the substrate 101 and the semiconductor pillar 10 and electrically contacting the semiconductor pillar 10 corresponding to the source region 12 .

[0128] In some embodiments, the material of the bit line 104 includes a metal material, for example, at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or nail.

[0129] refer to Figure 10 as well as Figure 11 In some embodiments, there are a plurality of semiconductor pillars, and the plurality of semiconductor pillars 10 are arranged at intervals along the second direction X and the third direction Y, where the second direction X is different from the third direction Y. There are a plurality of word lines 102, and the plurality of word lines 102 are arranged at intervals along the second direction X. Each word line 102 extends along the third direction Y, and one word line 102 surrounds the channel region 11 of each semiconductor pillar 10 in the plurality of semiconductor pillars 10 arranged at intervals along the third direction Y. There are a plurality of bit lines 104, and the plurality of bit lines 104 are arranged at intervals along the third direction Y. Each bit line 104 extends along the second direction X, and each bit line 104 is in electrical contact with the source region 12 of each semiconductor pillar 10 in the plurality of semiconductor pillars 10 arranged at intervals along the second direction X.

[0130] In the semiconductor structure provided by the above embodiment, the average bandgap width of the channel region 11 is greater than the average bandgap width of the source region 12. When the transistor is turned on, due to the smaller average bandgap width of the source region 12, the source region 12 has a smaller barrier height, and a larger number of carriers can be transferred from the source region 12 to the drain region 13 via the channel region 11, which is beneficial to improving the mobility of the carriers. When the transistor is turned off, due to the larger average bandgap width of the channel region 11, the channel region 11 has a higher barrier height, making it almost impossible for electrons from the source region 12 to be transferred to the drain region 13 through the channel region 11, thereby reducing the off-state leakage current of the channel region 11 when the transistor is turned off, and increasing the switching ratio of the transistor. It is not difficult to find that due to the increase in the on-state current of the transistor and the reduction in the off-state leakage current of the transistor, the switching ratio of the transistor is increased, thereby improving the response rate of the transistor and making the power consumption of the transistor lower.

[0131] Correspondingly, an embodiment of the present disclosure also provides a method for preparing a semiconductor structure, which can be used to prepare the semiconductor structure provided by the above embodiment. The semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0132] The method for preparing a semiconductor structure includes:

[0133] refer to Figures 12 to 30 , providing a substrate 101; forming a semiconductor column 10 on the substrate 101, the semiconductor column 10 includes: a source region 12, a channel region 11 and a drain region 13 arranged in sequence along a direction away from the surface of the substrate 101, the average band gap of the source region 12 is a first band gap, the average band gap of the channel region 11 is a second band gap, and the first band gap is smaller than the second band gap.

[0134] When the transistor is turned on, since the average band gap of the source region 12 is relatively small, the source region 12 has a smaller barrier height, so that a larger number of carriers in the source region 12 can cross the potential barrier of the source region 12 and be transmitted from the source region 12 to the channel region 11, and then transmitted to the drain region 13 via the channel region 11, which can make the on-state current of the transistor larger when it is turned on. When the transistor is turned off, since the average band gap of the channel region 11 is larger, the carriers from the source region 12 can hardly be transmitted to the drain through the channel region 11, reducing the off-state leakage current when the channel is closed. In other words, while achieving a larger on-state current of the transistor, the off-state current of the transistor is smaller, thereby making the switching ratio of the transistor larger and improving the response rate of the transistor.

[0135] In some embodiments, a doping process is performed on the same semiconductor material layer to form a semiconductor column 10. In the formed semiconductor column 10, the width dimension of the channel region 11 along the first direction is smaller than the width dimension of the source region 12 along the first direction parallel to the first direction, so that the first band gap is smaller than the second band gap, and the first direction is parallel to the surface of the substrate 101.

[0136] That is to say, when the material of the source region 12 is the same as that of the channel region 11, only the width dimension of the channel region 11 and the width dimension of the source region 12 are changed, so that the cross-sectional dimension of the channel region 11 and the cross-sectional dimension of the source region 12 are different, so that in the same cross-sectional direction, the cross-sectional dimension of at least part of the channel region 11 is smaller than the cross-sectional dimension of the source region 12, so that the band gap width of at least part of the channel region 11 is smaller than the band gap width of the source region 12.

[0137] The first direction may be any direction parallel to the surface of the substrate 101 .

[0138] In some embodiments, a method of forming the semiconductor pillar 10 includes:

[0139] refer to Figure 12, providing a semiconductor material layer 20. In some embodiments, the material of the semiconductor material layer 20 can be silicon. In some embodiments, the semiconductor material layer 20 can also be germanium, germanium silicon, or silicon on insulator.

[0140] refer to Figures 13 to 14 A portion of the semiconductor material layer 20 is etched to form an initial semiconductor pillar 130. The remaining semiconductor material layer 20 forms the substrate 101. The width of the initial semiconductor pillar 130 remains constant in a direction away from the surface of the substrate 101. The initial semiconductor pillar 130 comprises a first portion 1 and an initial second portion 21, which are sequentially arranged in a direction away from the surface of the substrate 101. In other words, the cross-sectional area of ​​the initial semiconductor pillar 130 parallel to the surface of the substrate 101 remains constant in a direction away from the surface of the substrate 101. The initial second portion 21 is used to subsequently form the channel region 11 and the drain region 13, while the first portion 1 is used to form the source region 12.

[0141] In some embodiments, the initial semiconductor pillars 130 are arranged in an array, and the plurality of initial semiconductor pillars 130 are arranged at intervals along the second direction X and the third direction Y, where the second direction X and the third direction Y are different.

[0142] In some embodiments, the method for forming the initial semiconductor pillars 130 may include: performing a patterning process on the surface of the semiconductor material layer 20 to define the positions of the initial semiconductor pillars 130. In some embodiments, the semiconductor material layer 20 may be patterned using either a SADP (Self-aligned Double Patterning) process or a SAQP (Self-Aligned Quadruple Patterning) process. Subsequently, the patterned semiconductor material layer 20 is etched to a predetermined thickness to form discrete initial semiconductor pillars 130. In some embodiments, the etching process may be either a dry etching process or a wet etching process.

[0143] In some embodiments, the second portion is used to form a channel region 11 and a drain region 13 , and the first portion 1 is used to form a source region 12 .

[0144] refer to Figures 15 to 16 The sidewall of the initial second portion 21 is etched using a dry etching process to form a second portion 2. The width of the second portion 2 in the first direction is smaller than the width of the first portion 1 in the first direction. The first portion 1 and the second portion 2 form a semiconductor column 10.

[0145] In some embodiments, the dry etching process has a lower etching selectivity for the bottom of the initial second portion 21 than for the top of the initial second portion 21. As a result, the formed second portion includes a first region and a second region, wherein the width of the first region in the first direction is greater than the width of the second region in the first direction.

[0146] In some embodiments, the dry etching process maintains an etching selectivity ratio on the bottom of the initial second portion 21 in a direction away from the surface of the initial substrate 101 , so that the width of the formed second portion remains unchanged in the direction away from the surface of the initial substrate 101 .

[0147] In some embodiments, during the dry etching process of the initial second portion 21, to prevent damage to the first portion 1 caused by the dry etching process, a first sacrificial layer may be formed on the sidewalls of the first portion 1 to protect the first portion 1. In some embodiments, the material of the first sacrificial layer may be silicon oxide. In some embodiments, a deposition process, such as an atomic layer deposition process, may be used to form the first sacrificial layer on the sidewalls of the first portion 1. In some embodiments, if the material of the first portion 1 is silicon, a thermal oxidation deposition process may be used to form silicon oxide on the sidewalls of the first portion 1 as the first sacrificial layer.

[0148] refer to Figures 17 to 20 In some embodiments, the method for preparing the semiconductor structure further includes: forming a bit line 104, wherein the number of the bit lines 104 is multiple, the multiple bit lines 104 are arranged at intervals along the third direction Y, each bit line 104 extends along the second direction X, and the bit line 104 is electrically contacted with each first portion 1 of the multiple initial semiconductor pillars 130 arranged at intervals along the second direction X.

[0149] refer to Figures 17 to 18 In some embodiments, before forming the bit line 104 , a protective layer 140 is formed on the side and top surface of each second portion 2 and the side of each first portion 1 to prevent the process of forming the bit line 104 from causing process damage to the first portion 1 and the second portion 2 .

[0150] In some embodiments, the material of the protection layer 140 may be silicon oxide, and the protection layer 140 may be formed on the side and top surface of each second portion 2 and the side of each first portion 1 by a thermal oxidation process.

[0151] In some embodiments, a method of forming the bit line 104 includes:

[0152] refer to Figures 17 to 18The surface of the substrate 101 exposed to the gap between the first portions 1 adjacent in the second direction X is etched to etch a portion of the thickness of the substrate 101 to form a groove 30 in the substrate 101, the groove 30 exposing the bottom surface of the first portion 1 away from the initial second portion 21. In some embodiments, a wet etching process can be selected to etch the substrate 101. Since the wet etching process is an isotropic etching, the substrate 101 can be etched in a direction perpendicular to the surface of the substrate 101 and can be etched laterally in a direction parallel to the surface of the substrate 101, so that the portion of the substrate 101 directly opposite the first portion 1 can be etched to form the groove 30 exposing the bottom surface of the first portion 1 away from the second portion 2.

[0153] In some embodiments, a plurality of grooves 30 are formed, each groove 30 directly opposite a first portion 1, and adjacent grooves 30 are connected to each other in the second direction X. In this way, after the bit lines 104 are subsequently formed in the grooves 30, the bit lines 104 in the grooves 30 adjacent in the second direction X are connected to each other to form the bit lines 104 extending in the second direction X.

[0154] Reference Figures 19 to 20 After the grooves 30 are formed, the bit lines 104 are formed to fill the grooves 30, the bit lines 104 being in electrical contact with the first portions 1. In some embodiments, a deposition process can be used to form the bit lines 104 to fill each groove 30. In some embodiments, the deposition process can be any one of an atomic layer deposition process or a chemical vapor deposition process. In some embodiments, the material of the bit lines 104 can be a conductive material, for example, can be a metal material, the metal material can be at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or nails.

[0155] In some embodiments, the material of the semiconductor pillar 10 is silicon, and the method of forming the semiconductor pillar 10 can also include:

[0156] Reference Figures 21 to 22 A silicon layer is provided, and the silicon layer is etched to form an initial semiconductor pillar 130, the remaining silicon layer forming the substrate 101, the width dimension of the initial semiconductor pillar 130 being unchanged in a direction away from the surface of the substrate 101, the initial semiconductor pillar 130 having the first portion 1 and the initial second portion 21 arranged in sequence in the direction away from the surface of the substrate 101.

[0157] In some embodiments, the method of forming the initial semiconductor pillars 130 can include performing a patterning process on the surface of the silicon layer for defining the locations of the initial semiconductor pillars 130. In some embodiments, the patterning process can be performed on the semiconductor material layer 20 using either of the SADP process or the SAQP process. Thereafter, an etching process is performed on the patterned silicon layer to etch a pre-determined thickness of the silicon layer to form the initial semiconductor pillars 130 which are spaced apart from each other. In some embodiments, the etching process can be either of a dry etching process or a wet etching process.

[0158] Referring to Figures 21 to 22 In some embodiments, before performing the etching process on the sidewalls of the initial second portions 21 to form the second portions 2, the method of fabricating the semiconductor structure further includes forming bit lines 104, the number of the bit lines 104 is plural, the plural bit lines 104 are spaced apart along the third direction Y, each bit line 104 extends along the second direction X, and each bit line 104 is in electrical contact with each first portion 1 of the plural initial semiconductor pillars 130 which are spaced apart along the second direction X. In some embodiments, the method of forming the bit lines 104 can refer to the description of the method of forming the bit lines 104 as described above, and will not be described in detail hereinafter.

[0159] Referring to Figures 23 to 28 An in-situ water vapor oxidation process is performed on the sidewalls of the initial second portions 21 to convert part of the initial second portions 21 into silicon oxide layers 50.

[0160] Referring to Figures 23 to 24 It can be understood that, in order to prevent the in-situ water vapor oxidation process from converting the sidewalls of the first portions 1 and the surface of the substrate 101 into silicon oxide layers as well. A second sacrificial layer 40 is formed on the sidewalls of the first portions 1 and the exposed surface of the substrate 101 in the gaps between adjacent first portions 1 before the in-situ water vapor oxidation process is performed. In some embodiments, in order to prevent the in-situ water vapor oxidation process from converting the top surface of the initial second portions 21 into silicon oxide layers, resulting in the height of the second portions 2 being too small, the second sacrificial layer 40 is also formed on the top surface of the initial second portions 21.

[0161] In some embodiments, the material of the second sacrificial layer 40 is different from silicon oxide, for example, can be any one of photoresist, silicon nitride or silicon oxynitride. In some embodiments, the second sacrificial layer 40 can be formed using a deposition process, for example, can be any one of an atomic layer deposition process or a chemical vapor deposition process.

[0162] The in-situ water vapor oxidation process is a rapid thermal process. In some embodiments, the initial second portions 21 can be placed in a reaction chamber, and oxygen gas with a small amount of hydrogen gas doped is used as the reaction atmosphere, and the temperature of the reaction chamber is increased. At high temperature, the oxygen gas and the hydrogen gas produce a combustion chemical reaction to generate a large amount of gas-phase active free radicals, mainly atomic oxygen. Referring toFigures 25 to 26 Due to the strong oxidizing effect of atomic oxygen, it can react with the silicon used to form the initial second portion 21, so that a silicon oxide layer 50 is generated on the sidewall of the initial second portion 21.

[0163] refer to Figures 27 to 28 After an in-situ water vapor oxidation process, the silicon oxide layer 50 is removed, and the remaining initial second portion 21 forms the second portion 2. The width of the second portion 2 along the first direction is smaller than the width of the first portion 1 along the first direction. The first portion 1 and the second portion 2 form a semiconductor pillar 10. In some embodiments, the silicon oxide layer 50 can be removed using either a wet etching process or a dry etching process, thereby thinning the sidewalls of the initial second portion 21. However, because the sidewalls of the first portion 1 are covered by the second sacrificial layer 40, the sidewalls of the first portion 1 are not thinned, resulting in the width of the second portion 2 being smaller than the width of the first portion 1.

[0164] In some embodiments, after the silicon oxide layer 50 is removed, the second sacrificial layer 40 is removed. In some embodiments, the second sacrificial layer 40 may be removed by using either a dry etching process or a wet etching process.

[0165] In some embodiments, after removing the second sacrificial layer 40, a dielectric layer 41 is formed between adjacent first portions 1 using a deposition process to isolate adjacent first portions 1. In some embodiments, the dielectric layer 41 may be made of silicon nitride.

[0166] refer to Figures 29 to 30 In some embodiments, the method for preparing a semiconductor structure further includes:

[0167] A plurality of gate dielectric layers 103 are formed, each of which surrounds a sidewall of the channel region 11. A plurality of word lines 102 are formed and arranged at intervals along the second direction X. Each word line 102 extends along the third direction Y, and each word line 102 surrounds a surface of the gate dielectric layer 103 of each semiconductor pillar 10 of the plurality of semiconductor pillars 10 arranged at intervals along the second direction X.

[0168] In some embodiments, a deposition process may be used to form a gate dielectric layer 103 on the surface of the semiconductor pillar 10 in the channel region 11. In some embodiments, the gate dielectric layer 103 may be made of silicon oxide and may be formed on the surface of the semiconductor pillar 10 using a thermal oxidation process.

[0169] In some embodiments, a deposition process, such as an atomic layer deposition process or a chemical vapor deposition process, can be used to form the word line 102 on the surface of the gate dielectric layer 103. In some embodiments, the material of the word line 102 can be a conductive material, such as a metal material, and the metal material can be at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or ruthenium.

[0170] In some embodiments, the second part 2 is used to form the channel region 11 and the drain region 13, and the first part 1 is used to form the source region 12, the second part 2 has a uniform type of doping ions, the doping ion type of the first part 1 is different from the doping ion type of the second part 2, and the source region 12 includes a third region 121 and a fourth region 122 arranged in sequence along a direction away from the surface of the substrate 101, the fourth region 122 is in contact with the channel region 11, and the doping ion type of the third region 121 is different from the doping ion type of the fourth region 122. In some embodiments, the doping ion type of the third region 121 can be either of a P-type or an N-type, and the doping ion type of the fourth region 122 can be the other one of the P-type or the N-type. That is, the third region 121 and the fourth region 122 constitute a PN junction, which can effectively suppress the hot carriers excited by heat, reduce the off-state leakage current caused by excessive number of hot carriers transmitted into the channel, further reduce the on-off ratio of the transistor, and reduce the power consumption of the transistor.

[0171] In some embodiments, the method for forming the first part 1 and the second part 2 includes:

[0172] Referring to Figure 31 , a first sub-semiconductor material layer 60 is provided, and a doping process is performed on the top of the first sub-semiconductor material layer 60 to convert part of the first sub-semiconductor material layer 60 into a first semiconductor layer, and the remaining part of the first sub-semiconductor layer forms a substrate 101. The first semiconductor layer is used to form the first part 1.

[0173] In some embodiments, the first semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer arranged in sequence along a direction away from the surface of the substrate 101, the second sub-semiconductor layer is in contact with the second part 2, and the doping ion type of the first sub-semiconductor layer is different from the doping ion type of the second sub-semiconductor layer. The first sub-semiconductor layer is used to form the third region 121, and the second sub-semiconductor layer is used to form the fourth region 122.

[0174] In some embodiments, the method for forming the first sub-semiconductor layer and the second sub-semiconductor layer includes:

[0175] Referring to Figure 32 , a first doping process is performed on the first sub-semiconductor material layer 60, and doping ions are injected into the first sub-semiconductor material layer 60 from the top surface of the first sub-semiconductor material layer 60 to convert part of the top of the first sub-semiconductor material layer 60 into an initial second sub-semiconductor layer 70, and the remaining part of the first sub-semiconductor material layer 60 serves as an initial substrate 61. In some embodiments, an ion implantation process can be used to inject doping ions into the top surface of the first sub-semiconductor material layer 60.

[0176] Referring to Figure 33, a portion of the initial second sub-semiconductor layer 70 is etched to form separate second sub-semiconductor layers 71. In some embodiments, the surface of the initial second sub-semiconductor layer 70 can be patterned to define the position of the initial second sub-semiconductor layer 70. In some embodiments, the initial second sub-semiconductor layer 70 can be patterned using either a SADP process or a SAQP process. The formed second sub-semiconductor layers 71 are arranged in an alternating pattern along the second direction X and the third direction Y.

[0177] Continue to refer Figure 33 A second doping process is performed on the initial substrate 61 from the gaps between adjacent second sub-semiconductor layers 71 to form a plurality of initial first sub-semiconductor layers 80 in the initial substrate 61. The plurality of initial first sub-semiconductor layers 80 are arranged at intervals along the third direction Y, and each initial first sub-semiconductor layer 80 extends along the second direction X. Each initial first sub-semiconductor layer 80 contacts the bottom surface of each second sub-semiconductor layer 71 arranged at intervals along the second direction X. In some embodiments, the second doping process may be an ion implantation process, and the implantation angle of the ion implantation process is controlled to transform the initial substrate 61 directly opposite the second sub-semiconductor layer 71 and the initial substrate 61 directly opposite the gaps between adjacent second sub-semiconductor layers 71 along the second direction X into the initial first sub-semiconductor layer 80. The formed initial first sub-semiconductor layers 80 extend along the second direction X.

[0178] refer to Figure 34 After forming the initial first sub-semiconductor layer 80, an etching process is performed on the initial first sub-semiconductor to remove the initial first sub-semiconductor layer 80 directly facing the gap between the second sub-semiconductor layers 71 adjacent to each other along the second direction X. Only the initial first sub-semiconductor layer 80 directly facing the second sub-semiconductor layer 71 remains as the first sub-semiconductor layer 81, thereby forming mutually separate first sub-semiconductor layers 81. In some embodiments, the etching process can be a dry etching process.

[0179] It can be understood that in some embodiments, the type of doping ions used in the first doping process is different from the type of doping ions used in the second doping process, thereby forming a first sub-semiconductor layer 81 and a second sub-semiconductor layer 71 with different doping ion types.

[0180] In some embodiments, the first doping process implants P-type dopant ions into the first sub-semiconductor material layer 60 to form a P-type fourth region 122 , and the second doping process implants N-type dopant ions into the initial substrate 61 to form an N-type third region 121 .

[0181] In some embodiments, the first doping process implants N-type doping ions into the first sub-semiconductor material layer 60 to form the fourth region 122 of N-type, and the second doping process implants P-type doping ions into the initial substrate 61 to form the third region 121 of P-type.

[0182] In some embodiments, the P-type doping ions can include any one of boron ions, aluminum ions, gallium ions, or indium ions. In some embodiments, the N-type doping ions can include any one of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

[0183] In some embodiments, in the step of forming the first sub-semiconductor layer 81, a portion of the substrate 101 opposite to the first sub-semiconductor layer 81 is also etched to form a recess 30, and the recess 30 exposes the bottom surface of the first sub-semiconductor layer 81.

[0184] Reference is made to Figure 35 In some embodiments, a bit line 104 is also formed in the recess 30.

[0185] Reference is made to Figure 35 A second sub-semiconductor material layer 72 is formed on the surface of the first sub-semiconductor layer 81. In some embodiments, a deposition process, such as an atomic layer deposition process or a chemical vapor deposition process, can be used to form the second sub-semiconductor material layer 72 on the top surface of the first semiconductor layer. In some embodiments, the material of the first sub-semiconductor material layer 60 and the material of the second sub-semiconductor material layer 72 can be the same, such as silicon, germanium, silicon germanium, or silicon on insulator. In some embodiments, the second sub-semiconductor material layer 72 formed covers the surface of the first sub-semiconductor layer 81 and is located between adjacent first semiconductor layers.

[0186] Reference is made to Figure 36 The second sub-semiconductor material layer 72 is etched to form an initial second portion 21, and the first semiconductor layer is used to form a first portion 1. In some embodiments, only the second sub-semiconductor material layer 72 located between adjacent first semiconductor layers is etched, and the remaining second sub-semiconductor material layer 72 forms an initial second portion 21 located on top of a first sub-semiconductor layer 81.

[0187] An etching process is performed on the sidewall of the initial second portion 21 to form a second portion 2, so that the width of the second portion 2 along a first direction is smaller than the width of the first portion 1 along the first direction. In some embodiments, the method of performing the etching process on the sidewall of the initial second portion 21 can refer to the description of the above-mentioned method of etching the sidewall of the initial second portion 21, and the following will not be described again.

[0188] In some embodiments, after forming the second portion 2, different portions of the second portion 2 are doped to form the channel region 11 and the drain region 13 in the second portion 2. In some embodiments, different portions of the second sub-semiconductor material layer 72 may be doped to form the channel region 11 and the drain region 13 in the second sub-semiconductor material layer 72 before forming the second portion 2.

[0189] By doping different parts of the second portion 2 separately, for example, doping different parts of the second portion 2 by material ion implantation, the doping ion type and concentration of the channel region 11 and the doping ion type and concentration of the drain region 13 can be regulated.

[0190] In some embodiments, the doping ion type of the second portion 2 corresponding to the drain region 13 is different from the doping ion type of the second portion 2 corresponding to the channel region 11, the doping ion type of the second portion 2 corresponding to the channel region 11 is the same as the doping ion type of the first sub-semiconductor layer 81, and the doping ion concentration of the second portion 2 corresponding to the channel region 11 is less than the doping ion concentration of the first sub-semiconductor layer 81.

[0191] That is, the doping ion type of the third region 121 is the same as the doping ion type of the channel region 11 , and the doping ion type of the fourth region 122 is different from the doping ion type of the channel region 11 .

[0192] In some embodiments, the doping ion type of the fourth region 122 is P-type, the doping ion type of the third region 121 is N-type, and the doping ion type of the channel region 11 is P-type.

[0193] In some embodiments, the doping ion type of the fourth region 122 is N-type, the doping ion type of the third region 121 is P-type, and the doping ion type of the channel region 11 is N-type.

[0194] In a specific example, the dopant ion type of the third region 121 is P-type, the dopant ion type of the fourth region 122 is N-type, the dopant ion type of the channel region 11 is P-type, and the dopant ion type of the drain region 13 is N-type. In another specific example, the dopant ion type of the third region 121 may also be N-type, the dopant ion type of the fourth region 122 may also be P-type, the dopant ion type of the channel region 11 may also be N-type, and the dopant ion type of the drain region 13 may also be N-type.

[0195] In some embodiments, the doping ion type of the channel region 11 may be the same as the doping ion type of the fourth region 122, and the doping ion concentration of the channel region 11 is lower than the doping ion concentration of the fourth region 122. For example, the doping ion type of the channel region 11 and the doping ion type of the fourth region 122 are both P-type, or the doping ion type of the channel region 11 and the doping ion type of the fourth region 122 are both N-type.

[0196] In the method for preparing the semiconductor structure provided in the above embodiment, the average bandgap width of the formed channel region 11 is greater than the average bandgap width of the source region 12. When the transistor is turned on, due to the smaller average bandgap width of the source region 12, the source region 12 has a smaller barrier height, and a larger number of carriers can be transferred from the source region 12 to the drain region 13 via the channel region 11, which is beneficial to improving the carrier mobility. When the transistor is turned off, due to the larger average bandgap width of the channel region 11, the channel region 11 has a higher barrier height, making it almost impossible for electrons from the source region 12 to be transferred to the drain region 13 through the channel region 11, reducing the off-state leakage current of the channel region 11 when the transistor is turned off, and increasing the switching ratio of the transistor. It is not difficult to find that due to the increase in the on-state current of the transistor and the reduction in the off-state leakage current of the transistor, the switching ratio of the transistor is reduced, thereby reducing the subthreshold swing of the transistor, thereby improving the response rate of the transistor, and making the power consumption of the transistor lower.

[0197] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a semiconductor column located on the substrate, the semiconductor column comprising: a source region, a channel region, and a drain region sequentially arranged in a direction away from the substrate surface, the source region having an average band gap of a first band gap, the channel region having an average band gap of a second band gap, and the first band gap being smaller than the second band gap; The source region includes a first sub-source region and a second sub-source region arranged in sequence in a direction away from the substrate surface, the second sub-source region is in contact with the channel region, and the doping ion conductivity type of the first sub-source region is different from the doping ion conductivity type of the second sub-source region.

2. The semiconductor structure according to claim 1, wherein: The semiconductor pillar is an integrated structure, and the cross-sectional area of ​​the channel region in a direction parallel to the substrate surface is smaller than the cross-sectional area of ​​the source region in a direction parallel to the substrate surface, so that the first band gap is smaller than the second band gap.

3. The semiconductor structure according to claim 2, wherein: A width of the channel region along a first direction is smaller than a width of the source region along the first direction, and the first direction is parallel to the surface of the substrate.

4. The semiconductor structure according to claim 3, wherein: In a direction away from the substrate surface, the width of the channel region along the first direction remains unchanged, and the width of the source region along the first direction remains unchanged.

5. The semiconductor structure according to claim 3, wherein: The channel region includes: a first region and a second region arranged in sequence along a direction away from the substrate surface, the first region is in contact with the source region, at least part of the channel region is the second region, the orthographic projection of the second region on the substrate surface is located within the orthographic projection of the first region on the substrate surface, and the cross-sectional area of ​​the first region in a direction parallel to the substrate surface is not greater than the cross-sectional area of ​​the source region in a direction parallel to the substrate surface.

6. The semiconductor structure according to claim 5, wherein: In a direction away from the substrate surface, the width of the second region along the first direction remains constant, and the width of the first region along the first direction gradually decreases.

7. The semiconductor structure according to any one of claims 3 to 6, characterized in that: In a direction perpendicular to the surface of the substrate, the width of the source region along the first direction remains constant.

8. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The orthographic projection of the drain region on the substrate surface is located within the orthographic projection of the source region on the substrate surface.

9. The semiconductor structure according to any one of claims 1 to 6, wherein: The doping ion conductivity type of the channel region is the same as that of the drain region, and the doping ion conductivity type of the source region is different from that of the channel region.

10. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The doping ion conductivity type of the drain region is different from the doping ion conductivity type of the channel region, the doping ion conductivity type of the channel region is the same as the doping ion conductivity type of the first sub-source region, and the doping ion concentration of the channel region is less than the doping ion concentration of the first sub-source region.

11. The semiconductor structure according to claim 1 or 2, characterized in that: Also includes: a word line, the word line surrounding a side surface of the semiconductor column corresponding to the channel region; The bit line is located between the substrate and the semiconductor pillar and is in electrical contact with the semiconductor pillar corresponding to the source region.

12. The semiconductor structure according to claim 11, wherein: There are multiple semiconductor pillars, and the multiple semiconductor pillars are arranged at intervals along the second direction and the third direction, and the second direction is different from the third direction; wherein, There are a plurality of word lines, the plurality of word lines are arranged at intervals along the second direction, each word line extends along the third direction, and one word line surrounds a channel region of each semiconductor pillar in the plurality of semiconductor pillars arranged at intervals along the third direction; There are multiple bit lines, which are arranged at intervals along the third direction. Each word line extends along the second direction. One bit line is in electrical contact with a source region of each semiconductor column in the multiple semiconductor columns arranged at intervals along the second direction.

13. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a semiconductor column on the substrate, the semiconductor column comprising: a source region, a channel region, and a drain region sequentially arranged in a direction away from the surface of the substrate, the average band gap of the source region being a first band gap, the average band gap of the channel region being a second band gap, and the first band gap being smaller than the second band gap; The source region includes a first sub-source region and a second sub-source region arranged in sequence in a direction away from the substrate surface, the second sub-source region is in contact with the channel region, and the doping ion conductivity type of the first sub-source region is different from the doping ion conductivity type of the second sub-source region.

14. The method for preparing a semiconductor structure according to claim 13, wherein: A doping process is performed on the same semiconductor material layer to form the semiconductor column. In the formed semiconductor column, the width of the channel region along a first direction is smaller than the width of the source region along a direction parallel to the first direction, so that the first band gap is smaller than the second band gap, and the first direction is parallel to the substrate surface.

15. The method for preparing a semiconductor structure according to claim 14, wherein: The method of forming the semiconductor pillar includes: providing a semiconductor material layer; Etching a portion of the semiconductor material layer to form an initial semiconductor column, with the remaining semiconductor material layer forming the substrate, wherein the width of the initial semiconductor column remains unchanged in a direction away from the substrate surface, and the initial semiconductor column comprises a first portion and an initial second portion sequentially arranged in the direction away from the substrate surface; The sidewall of the initial second portion is etched by a dry etching process to form a second portion, wherein the width of the second portion in the first direction is smaller than the width of the first portion in the first direction. The first portion and the second portion form the semiconductor column.

16. The method for preparing a semiconductor structure according to claim 14, wherein: The method of forming the semiconductor pillar includes: providing a silicon layer; Etching the silicon layer to form an initial semiconductor pillar, with the remaining silicon layer forming the substrate, wherein the width of the initial semiconductor pillar remains unchanged in a direction away from the substrate surface, and the initial semiconductor pillar comprises a first portion and an initial second portion sequentially arranged in the direction away from the substrate surface; performing an in-situ water vapor oxidation process on the sidewall of the initial second portion to convert a portion of the initial second portion into a silicon oxide layer; The silicon oxide layer is removed, and the remaining portion of the initial second portion forms a second portion, wherein a width of the second portion along the first direction is smaller than a width of the first portion along the first direction, and the first portion and the second portion form the semiconductor pillar.

17. The method for preparing a semiconductor structure according to claim 15 or 16, characterized in that: The second portion is used to form the channel region and the drain region, and the first portion is used to form the source region. The method of forming the first portion and the second portion includes: Providing a first sub-semiconductor material layer, performing a doping process on a top portion of the first sub-semiconductor material layer to convert a portion of the first sub-semiconductor material layer into a first semiconductor layer, and the remaining portion of the first sub-semiconductor material layer forms the substrate; forming a second sub-semiconductor material layer on the surface of the first semiconductor layer; A portion of the second sub-semiconductor material layer is etched to form the initial second portion, and a portion of the first semiconductor layer is etched to form the first portion.

18. The method for preparing a semiconductor structure according to claim 17, wherein: The second portion has dopant ions of uniform conductivity type, and the dopant ion conductivity type of the first semiconductor layer is different from the dopant ion conductivity type of the second portion.

19. The method for preparing a semiconductor structure according to claim 18, wherein: The first semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer arranged in sequence in a direction away from the substrate surface, the second sub-semiconductor layer is in contact with the second portion, and the doping ion conductivity type of the first sub-semiconductor layer is different from the doping ion conductivity type of the second sub-semiconductor layer.

20. The method for preparing a semiconductor structure according to claim 19, wherein: The doping ion conductivity type of the second portion corresponding to the drain region is different from the doping ion conductivity type of the second portion corresponding to the channel region, the doping ion conductivity type of the second portion corresponding to the channel region is the same as the doping ion conductivity type of the first sub-semiconductor layer, and the doping ion concentration of the second portion corresponding to the channel region is less than the doping ion concentration of the first sub-semiconductor layer.

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