Circuit board and method for manufacturing the same

Abstract

The application provides a preparation method of a circuit board, comprising the following steps: providing a substrate unit, wherein the substrate unit comprises a first circuit unit, a first connecting layer and a second circuit unit. The first circuit unit comprises a first circuit layer and a first substrate layer, and the first substrate layer is a hydrophobic substrate layer. The first circuit layer is divided into a first region, a second region and a third region, the first region and the third region are attached to the first connecting layer, the first connecting layer is provided with a cavity, and the projection of the second region is placed in the cavity. Part of the second circuit unit on the cavity is removed to form a first slot part in the second circuit unit. The second region is removed to obtain a second slot part, so as to obtain a groove, and part of the first substrate layer is exposed in the groove. The first substrate layer exposed in the groove is treated by laser, so that part of the first substrate layer is changed into a hydrophilic region, and a conductive contact patch is formed on the hydrophilic region. The preparation method is beneficial to reduce the slotting precision requirement and simplify the preparation process. The application also provides a circuit board.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit board, in particular to a circuit board and a preparation method thereof. BACKGROUND

[0002] The circuit board usually comprises conductive pads (such as gold fingers) for transmitting electrical signals. The preparation steps of such circuit board usually comprise: preparing an inner layer circuit unit comprising conductive pads; sequentially forming a connecting layer and an additional layer circuit unit on the inner layer circuit unit; forming a groove penetrating through the connecting layer and the additional layer circuit unit to expose the conductive pads. However, high operation precision is required when the groove is formed. In addition, the manufacture of the additional layer circuit unit involves exposure, development and etching steps. In order to prevent the conductive pads from being etched, a protective layer such as a high-temperature adhesive tape or a tin layer needs to be formed on the surface of the conductive pads, thereby resulting in a relatively complicated preparation process of the circuit board. SUMMARY

[0003] Therefore, the present application provides a preparation method of a circuit board which is beneficial to reduce the slotting precision requirement and simplify the preparation process.

[0004] The present application also provides a circuit board.

[0005] The present application provides a preparation method of a circuit board, comprising the following steps:

[0006] providing a substrate unit, the substrate unit comprising a first circuit unit, a first connecting layer and a second circuit unit which are sequentially stacked along a first direction, the first circuit unit comprising a first circuit layer and a first substrate layer which are stacked, the first substrate layer being a hydrophobic substrate layer, the first circuit layer being divided into a first region, a second region and a third region along a second direction perpendicular to the first direction, the first region and the third region both being attached to the first connecting layer, the first connecting layer being provided with a cavity, a projection of the second region in the first direction being placed in the cavity;

[0007] removing part of the second circuit unit located on the cavity to form a first slot part in the second circuit unit;

[0008] removing the second region to obtain a second slot part, the second slot part, the cavity and the first slot part collectively forming a groove, part of the first substrate layer being exposed in the groove;

[0009] laser processing the first substrate layer exposed in the groove, so that part of the first substrate layer is converted into a hydrophilic region, the hydrophilic region being connected to at least the first region;

[0010] forming a conductive pad on the hydrophilic region.

[0011] The application also provides a circuit board, which comprises a first circuit unit, a first connecting layer and a second circuit unit which are sequentially stacked along a first direction. The first circuit unit comprises a first circuit layer and a first substrate layer which are stacked. The first substrate layer is a hydrophobic substrate layer. The circuit board is provided with a groove which penetrates the second circuit unit, the first connecting layer and the first circuit layer. Part of the first substrate layer is exposed in the groove, and the first substrate layer exposed in the groove has a hydrophilic region which is connected to the first circuit layer. The circuit board further comprises a conductive contact patch which is arranged on the hydrophilic region and connected to the first circuit layer.

[0012] In the application, the groove is formed so that part of the first substrate layer is exposed in the groove, the first substrate layer is then treated by laser to form a hydrophilic region, and finally a conductive contact patch is formed on the hydrophilic region. Since the conductive contact patch is formed after the groove is formed, the preparation method provided by the application has relatively low precision requirements for slotting. In addition, the application does not need to form a high-temperature adhesive tape on the surface of the conductive contact patch when the second circuit unit is prepared, and does not need to tear off the high-temperature adhesive tape after the circuit board is formed, so that the preparation method provided by the application is conducive to simplifying the preparation process. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 A cross-sectional view of a second substrate, a third substrate and a second connecting layer which are stacked and then pressed together according to an embodiment of the application;

[0014] Figure 2 A cross-sectional view of a second conductive layer of the second substrate, a third conductive layer of the third substrate and a fourth conductive layer of the fourth substrate which are sequentially stacked according to an embodiment of the application; Figure 1 A cross-sectional view of a third plating layer formed on the second conductive layer of the second substrate and a fourth plating layer formed on the third conductive layer of the third substrate according to an embodiment of the application;

[0015] Figure 3 A cross-sectional view of the second conductive layer, the third plating layer, the third conductive layer and the fourth plating layer which are etched according to an embodiment of the application; Figure 2 A cross-sectional view of a first circuit layer and a third circuit layer obtained by etching the second conductive layer, the third plating layer, the third conductive layer and the fourth plating layer according to an embodiment of the application;

[0016] Figure 4 A cross-sectional view of a first anti-welding layer formed on the first circuit layer according to an embodiment of the application; Figure 3 A cross-sectional view of a first connecting layer and a first substrate which are sequentially pressed together on the first circuit layer and a third connecting layer and a fourth substrate which are sequentially pressed together on the third circuit layer according to an embodiment of the application;

[0017] Figure 5 A cross-sectional view of a via hole formed according to an embodiment of the application; Figure 4

[0018] A cross-sectional view of a conductive contact patch formed on the via hole according to an embodiment of the application; Figure 6

[0019] Figure 7 A cross-sectional view of a second anti-welding layer formed on the conductive contact patch according to an embodiment of the application; Figure 6 ​A cross-sectional view showing the formation of a first plating layer on a first substrate and a fifth plating layer on a fourth substrate;

[0020] Figure 8 for etching Figure 7 A cross-sectional view showing the formation of a second circuit layer from the first plating layer and the first substrate and the fourth circuit layer from etching the fourth substrate and the fifth plating layer;

[0021] Figure 9 for forming a second anti-plating layer on Figure 8 A cross-sectional view showing the formation of a substrate unit from the second circuit layer and the fourth circuit layer;

[0022] Figure 10 for forming a first groove portion in Figure 9 A cross-sectional view showing the formation of a first groove portion in the substrate unit;

[0023] Figure 11 for forming a second groove portion communicating with Figure 10 A cross-sectional view showing the formation of a recess from the second groove portion and a hydrophilic region;

[0024] Figure 12 for Figure 11 A plan view showing the A portion;

[0025] Figure 13 for forming a first plating layer on Figure 11 A cross-sectional view showing the formation of a first plating layer on the hydrophilic region;

[0026] Figure 14 for forming a second plating layer on Figure 13 A cross-sectional view showing the formation of a second plating layer on the first plating layer;

[0027] Figure 15 for forming a first conductive protective layer on Figure 14 A cross-sectional view showing the formation of a first conductive protective layer on the second plating layer;

[0028] Figure 16 for Figure 15 A plan view showing the B portion;

[0029] Figure 17 A cross-sectional view of a circuit board obtained in an embodiment of the present application;

[0030] Figure 18 for Figure 17 A plan view of the circuit board.

[0031] Explanation of main element symbols

[0032] Circuit board 200 Substrate unit 100

[0033] First circuit layer 11 First substrate layer 12

[0034] First direction X First region 112

[0035] Second region 113 Third region 114

[0036] Hydrophilic region 121 Fifth circuit layer 13

[0037] First connection layer 20 First slot portion 201

[0038] Second slot portion 202 Groove 203

[0039] Second circuit unit 30 Second circuit layer 31

[0040] Second substrate layer 32 Seventh circuit layer 33

[0041] Conductive pad 40 First plating layer 41

[0042] Second plating layer 42 First conductive protection layer 43

[0043] Third circuit unit 50 Third circuit layer 51

[0044] Third substrate layer 52 Sixth circuit layer 53

[0045] Fourth circuit unit 60 Fourth circuit layer 61

[0046] Fourth substrate layer 62 Eighth circuit layer 63

[0047] First anti-weld layer 70 Second anti-weld layer 80

[0048] Window 81 Second conductive protection layer 90

[0049] Second connection layer 21 Third connection layer 22

[0050] Conductive hole 204 Through hole 205

[0051] Second plating layer 206 First conductive layer 311

[0052] First plating layer 312 First substrate 301

[0053] Fourth conductive layer 611 Fifth plating layer 612

[0054] Fourth substrate 601 Cavity 23

[0055] Second substrate 101 Third plating layer 110

[0056] Second conductive layer 115 Third substrate 501

[0057] Third conductive layer 511 Fourth plating layer 512

[0058] Second direction Y Third direction Z

[0059] First circuit unit 10

[0060] The following detailed description will further describe the present application with reference to the above-mentioned drawings. DETAILED DESCRIPTION

[0061] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments.

[0062] It should be noted that when an element is referred to as being "fixed" to another element, it can be directly on the other element or there can be an intervening element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or there can be an intervening element. When an element is referred to as being "disposed on" another element, it can be directly disposed on the other element or there can be an intervening element.

[0063] Embodiment 1

[0064] The present application provides a method for preparing a circuit board. The order of steps of the method can be changed according to different needs, and some steps can be omitted or combined. The method comprises the following steps:

[0065] Step one: referring to Figure 1 , a second substrate 101, a third substrate 501 and a second connecting layer 21 are provided. The second connecting layer 21 is stacked between the second substrate 101 and the third substrate 501 and is pressed to combine the three, so that the second connecting layer 21 connects the second substrate 101 and the third substrate 501 along the first direction X.

[0066] The second substrate 101 comprises a first base material layer 12 and a second conductive layer 115. The second conductive layer 115 is stacked on a surface of the first base material layer 12 away from the second connecting layer 21. In some embodiments, the second substrate 101 further comprises a fifth circuit layer 13 stacked on another surface of the first base material layer 12 away from the second conductive layer 115. The first base material layer 12 is a hydrophobic base material layer. For example, the material of the first base material layer 12 can be one of unsaturated polyvinyl resin, epoxy resin, phenolic resin, bismaleimide resin or polyimide resin. The materials of the second conductive layer 115 and the fifth circuit layer 13 can both be copper.

[0067] The third substrate 501 comprises a third base material layer 52 and a third conductive layer 511. The third conductive layer 511 is stacked on a surface of the third base material layer 52 which is away from the second connecting layer 21. In some embodiments, the third substrate 501 further comprises a sixth circuit layer 53 stacked on another surface of the third base material layer 52 away from the third conductive layer 511. The third base material layer 52 can be a hydrophilic base material layer. For example, the material of the third base material layer 52 can be one of polyvinyl alcohol, polymethyl acrylate, polymethyl methacrylate, polyacrylic acid or polymethacrylic acid. The material of the third conductive layer 511 and the sixth circuit layer 53 can both be copper. The second connecting layer 21 can be a glue layer, for example, a polypropylene glue, or a prepreg.

[0068] Step two: referring to Figure 2 A third plating layer 110 is formed on the second conductive layer 115. A fourth plating layer 512 is formed on the third conductive layer 511. The third plating layer 110 and the fourth plating layer 512 can be formed by electroplating or electroless plating. In this embodiment, the third plating layer 110 and the fourth plating layer 512 are formed by electroplating.

[0069] Step three: referring to Figure 2 and Figure 3 The second conductive layer 115 and the third plating layer 110 are etched to obtain a first circuit layer 11. The first circuit layer 11 is divided into a first region 112, a second region 113 and a third region 114 along a second direction Y which is perpendicular to the first direction X. The first circuit layer 11, the first base material layer 12 and the fifth circuit layer 13 jointly form a first circuit unit 10.

[0070] The third conductive layer 511 and the fourth plating layer 512 are etched to obtain a third circuit layer 51. The third circuit layer 51, the third base material layer 52 and the sixth circuit layer 53 jointly form a third circuit unit 50.

[0071] The third circuit layer 51 and the first circuit layer 11 can be obtained by selective etching through exposure and development of a graphic mask and using an acidic etching solution or an alkaline etching solution.

[0072] In another embodiment, the first circuit unit 10 can be directly provided. The first circuit unit 10 can only comprise the first circuit layer 11 and the first base material layer 12 which are stacked.

[0073] Step four: referring to Figure 4 A first anti-soldering layer 70 is formed on the first region 112. The first anti-soldering layer 70 can be formed by printing anti-soldering ink. The first anti-soldering layer 70 is adjacent to the second region 113 along the second direction Y. In this embodiment, the first anti-soldering layer 70 can only cover part of the first region 112.

[0074] In another embodiment, the first anti-soldering layer 70 can cover the whole first region 112.

[0075] Step five: Referring to Figure 5 The first connection layer 20 with the cavity 23 is laminated to the first circuit layer 11. The first connection layer 20 also covers part of the first anti-solder layer 70. Part of the first anti-solder layer 70 is exposed from the cavity 23. The cavity 23 penetrates through opposite surfaces of the first connection layer 20 along the first direction X. Illustratively, the first connection layer 20 can be a glue layer, such as a polypropylene glue, or a prepreg. The first region 112 and the third region 114 are attached to the first connection layer 20. The projection of the second region 113 on the first direction X is placed in the cavity 23, so that the second region 113 is exposed from the cavity 23. In some embodiments, the first region 112 forms a step structure with the part of the first connection layer 20 adjacent to the first region 112.

[0076] The first substrate 301 is stacked on the first connection layer 20. The first substrate 301 includes the second base material layer 32 and the first conductive layer 311 stacked. The first conductive layer 311 is disposed on a surface of the second base material layer 32 away from the first connection layer 20. In some embodiments, the first substrate 301 further includes the seventh circuit layer 33 stacked on another surface of the second base material layer 32 away from the first conductive layer 311. Illustratively, the second base material layer 32 can be a hydrophilic base material layer. The material of the second base material layer 32 can be one of polyvinyl alcohol, polymethyl acrylate, polymethyl methacrylate, polyacrylic acid, or polymethacrylic acid. The materials of the first conductive layer 311 and the seventh circuit layer 33 can both be copper.

[0077] In some embodiments, the third connection layer 22 and the fourth substrate 601 are sequentially stacked on the third circuit layer 51. Illustratively, the third connection layer 22 can be a glue layer, such as a polypropylene glue, or a prepreg. The fourth substrate 601 includes the fourth base material layer 62 and the fourth conductive layer 611 stacked on a surface of the fourth base material layer 62 away from the third connection layer 22. Illustratively, the fourth base material layer 62 can be a hydrophilic base material layer. The material of the fourth base material layer 62 can be one of polyvinyl alcohol, polymethyl acrylate, polymethyl methacrylate, polyacrylic acid, or polymethacrylic acid. In some embodiments, the fourth substrate 601 further includes the eighth circuit layer 63 stacked on another surface of the fourth base material layer 62 away from the fourth conductive layer 611, i.e., the eighth circuit layer 63 is disposed towards the third connection layer 22. Illustratively, the materials of the eighth circuit layer 63 and the fourth conductive layer 611 can be copper.

[0078] Step six: Referring to Figure 6The via 205 is formed to at least penetrate the first substrate 301, the first connection layer 20 and the third region 114 along the first direction X. In the embodiment, the via 205 penetrates the first substrate 301, the first connection layer 20, the first circuit unit 10, the second connection layer 21, the third circuit unit 50, the third connection layer 22 and the fourth substrate 601 along the first direction X. The via 205 can be formed by laser drilling, for example.

[0079] Step seven: referring to Figure 7 The first plating layer 312 is formed on the first conductive layer 311. The second plating layer 206 is formed in the via 205 and connected to the first plating layer 312, so that the via 205 forms the conductive hole 204.

[0080] In some embodiments, the fifth plating layer 612 is also formed on the fourth conductive layer 611 and connected to the second plating layer 206.

[0081] The first plating layer 312 and the fifth plating layer 612 can be formed by electroplating or electroless plating. In the embodiment, the first plating layer 312 and the fifth plating layer 612 are formed by electroplating.

[0082] The conductive hole 204 is electrically connected to the first circuit layer 11, the fifth circuit layer 13, the seventh circuit layer 33, the third circuit layer 51, the sixth circuit layer 53, the first conductive layer 311 and the fourth conductive layer 611. The conductive hole 204 facilitates the formation of the second plating layer 42 in the subsequent step.

[0083] Step eight: referring to Figure 7 and Figure 8 The first conductive layer 311 and the first plating layer 312 are etched to form the second circuit layer 31. The fourth conductive layer 611 and the fifth plating layer 612 are etched to form the fourth circuit layer 61. The second circuit layer 31 and the fourth circuit layer 61 can be formed by selective etching with a graphic mask exposed and developed, and an acidic etching solution or an alkaline etching solution. The conductive hole 204 is also electrically connected to the second circuit layer 31 and the fourth circuit layer 61.

[0084] Step nine: referring to Figure 9 The second solder mask layer 80 is formed on both the second circuit layer 31 and the fourth circuit layer 61 to form the substrate unit 100. The second solder mask layer 80 can be formed by printing solder mask ink, for example. The second solder mask layer 80 avoids the conductive hole 204.

[0085] In some embodiments, the second solder mask layer 80 on the fourth circuit layer 61 can be provided with a window 81. Part of the fourth circuit layer 61, such as a pad, is exposed to the window 81.

[0086] In another embodiment, the substrate unit 100 can be provided directly. The substrate unit 100 includes the first circuit unit 10, the first connection layer 20 and the second circuit unit 30 stacked in sequence along the first direction X. The first circuit unit 10 includes the first circuit layer 11 and the first substrate layer 12 stacked in sequence. The first substrate layer 12 is a hydrophobic substrate layer. The first circuit layer 11 is divided into the first region 112, the second region 113 and the third region 114 along the second direction Y perpendicular to the first direction X. The first region 112 and the third region 114 are attached to the first connection layer 20. The first connection layer 20 is provided with the cavity 23. The projection of the second region 113 on the first direction X is placed in the cavity 23.

[0087] Step ten: referring to Figure 9 and Figure 10 , the part of the second circuit unit 30 located on the cavity 23 is removed, and optionally, the part of the second solder resist layer 80 located on the cavity 23 is also removed, to form the first slot part 201 in the second circuit unit 30. In this embodiment, the part of the second circuit unit 30 and the second solder resist layer 80 located on the cavity 23 can be removed by laser cutting. At this time, the part of the first solder resist layer 70 adjacent to the second region 113 is exposed to the first slot part 201.

[0088] Step eleven: referring to Figure 10 and Figure 11 , the second region 113 is removed to obtain the second slot part 202. The second slot part 202, the cavity 23 and the first slot part 201 together form the groove 203. For example, the second region 113 can be etched by etching liquid to obtain the second slot part 202. The part of the first substrate layer 12 is exposed to the groove 203.

[0089] The first substrate layer 12 exposed to the groove 203 is treated by laser to make the part of the first substrate layer 12 into the hydrophilic region 121. For example, the first substrate layer 12 can be treated by laser with a single pulse energy of 1 μJ-50 μJ to make the first substrate layer 12 after laser irradiation into the hydrophilic region 121. Alternatively, the hydrophobicity of the first substrate layer 12 can be changed by controlling the laser intensity and the oxygen content of the ambient auxiliary gas. For example, the pulse width of the laser is 800 fs-800 ps, the wavelength is 800 nm-2000 nm, the power is 0.1 w to 100 w, and the frequency is 1 kHZ-100 kHZ. The ambient auxiliary gas can be a mixture of oxygen and nitrogen or oxygen and inert gas. Changing the hydrophobicity of the first substrate layer 12 by laser is prior art. The hydrophilic region 121 is connected to at least the first region 112. In some embodiments, the hydrophilic region 121 is connected to the first region 112 and the third region 114.

[0090] Please refer to Figure 12The laser treatment can form a plurality of hydrophilic regions 121. The plurality of hydrophilic regions 121 can be arranged in a third direction Z. The third direction Z is perpendicular to the first direction X and the second direction Y.

[0091] Step twelve: referring to Figure 11 and Figure 13 A first plating layer 41 is formed on the hydrophilic regions 121 by electroless plating.

[0092] Step thirteen: referring to Figure 14 A second plating layer 42 is formed on the first plating layer 41 by electroplating. During electroplating, an electric current can be applied to the third region 114 through the conductive holes 204 to form the second plating layer 42. The electroplating solution is contained in the grooves 203.

[0093] Step fourteen: referring to Figure 15 and Figure 16 A first conductive protective layer 43, such as a gold layer, is formed on the second plating layer 42 to obtain a conductive pad 40 (e.g., a gold finger). In an example, the first conductive protective layer 43 can be formed by electroplating or electroless plating. The conductive pad 40 is connected to the first region 112 and the third region 114 in the second direction Y.

[0094] A second conductive protective layer 90, such as a gold layer, is formed in the window 81 to electrically connect the fourth circuit layer 61.

[0095] In another embodiment, step fourteen can be omitted.

[0096] Step fifteen: the circuit board 200 is cut in the first direction X. The cutting line corresponds to the connection between the second region 113 and the third region 114 to remove the part of the circuit board 200 that does not contain the conductive pad 40 (refer to Figure 17 ). That is, only the B part in Figure 15 is retained. Referring to Figure 16 and Figure 18 , the end of the conductive pad 40 away from the first solder mask 70 is removed to obtain the circuit board 200. The conductive pad 40 is spaced from the end surface of the circuit board 200 in the second direction Y.

[0097] In another embodiment, step fifteen can be omitted.

[0098] In the present application, the groove 203 is formed so that part of the first substrate layer 12 is exposed to the groove 203, and then the first substrate layer 12 is treated by laser to form the hydrophilic region 121, and finally the conductive contact patch 40 is formed on the hydrophilic region 121. Since the conductive contact patch 40 is formed after the groove 203 is formed, the preparation method provided by the present application has relatively low precision requirements for slotting. In addition, the present application does not need to form a high-temperature adhesive tape on the surface of the conductive contact patch 40 when preparing the second circuit unit 30, and does not need to remove the high-temperature adhesive tape after forming the circuit board 200, so that the preparation method provided by the present application is conducive to simplifying the preparation process.

[0099] Embodiment 2:

[0100] With reference to Figure 17 and Figure 18 , the present application provides a circuit board 200. The circuit board 200 comprises a first circuit unit 10, a first connecting layer 20 and a second circuit unit 30 which are sequentially stacked in a first direction X. The first circuit unit 10 comprises a first circuit layer 11 and a first substrate layer 12 which are stacked. In some embodiments, the first circuit unit 10 further comprises a fifth circuit layer 13 which is stacked on the other surface of the first substrate layer 12 away from the first circuit layer 11. The first substrate layer 12 is a hydrophobic substrate layer. The circuit board 200 is provided with a groove 203 which penetrates the second circuit unit 30, the first connecting layer 20 and the first circuit layer 11. Part of the first substrate layer 12 is exposed to the groove 203. The first substrate layer 12 exposed to the groove 203 has a hydrophilic region 121. The hydrophilic region 121 is connected to the first circuit layer 11. The circuit board 200 further comprises a conductive contact patch 40. The conductive contact patch 40 is arranged on the hydrophilic region 121 and connected to the first circuit layer 11. In some embodiments, the conductive contact patch 40 comprises a first plating layer 41, a second plating layer 42 and a first conductive protection layer 43 which are sequentially stacked. The first plating layer 41 is attached to the hydrophilic region 121. The first plating layer 41 can be obtained by chemical plating. The second plating layer 42 can be obtained by electroplating.

[0101] In some embodiments, the circuit board 200 further comprises a first solder mask layer 70. The groove 203 comprises a cavity 23 which penetrates the first connecting layer 20, a first slot portion 201 which penetrates the second circuit unit 30, and a second slot portion 202 which penetrates the first circuit layer 11. The cavity 23 communicates the first slot portion 201 and the second slot portion 202 in the first direction X. The first circuit layer 11 comprises a first area 112 which is adjacent to the cavity 23 in a second direction Y perpendicular to the first direction X. The first solder mask layer 70 is arranged on the first area 112. Part of the first solder mask layer 70 is stacked between the first area 112 and the first connecting layer 20. Another part of the first solder mask layer 70 is exposed to the cavity 23.

[0102] In some embodiments, the second circuit unit 30 comprises a second substrate layer 32 and a second circuit layer 31 stacked on a surface of the second substrate layer 32 away from the first connection layer 20. In some embodiments, the second circuit unit 30 further comprises a seventh circuit layer 33 stacked on another surface of the second substrate layer 32 away from the second circuit layer 31.

[0103] The first circuit unit 10 away from the second circuit unit 30 is sequentially stacked with a second connection layer 21, a third circuit unit 50, a third connection layer 22 and a fourth circuit unit 60. The third circuit unit 50 comprises a third substrate layer 52 and a third circuit layer 51 stacked on a surface of the third substrate layer 52 away from the second connection layer 21. In some embodiments, the third circuit unit 50 further comprises a sixth circuit layer 53 stacked on another surface of the third substrate layer 52 away from the third circuit layer 51. The fourth circuit unit 60 comprises a fourth substrate layer 62 and a fourth circuit layer 61 stacked on a surface of the fourth substrate layer 62 away from the third connection layer 22. In some embodiments, the fourth circuit unit 60 further comprises an eighth circuit layer 63 stacked on a surface of the fourth substrate layer 62 away from the fourth circuit layer 61. The circuit board 200 further comprises a second solder mask layer 80. The second solder mask layer 80 covers the second circuit layer 31 and the fourth circuit layer 61. In some embodiments, the second solder mask layer 80 covering the fourth circuit layer 61 is provided with a window 81 to expose part of the fourth circuit layer 61. In some embodiments, the circuit board 200 further comprises a second conductive protection layer 90 provided in the window 81.

[0104] In some embodiments, at least one of the second substrate layer 32, the third substrate layer 52 and the fourth substrate layer 62 is a hydrophilic substrate layer.

[0105] Since the materials of the elements in the present embodiment are the same as those of the corresponding elements in Embodiment 1, no further description is given.

[0106] The above description is merely one optimized specific embodiment of the present application, but in actual application process, it cannot be limited to this embodiment. Other variations and changes made by the person skilled in the art according to the technical concept of the present application should all belong to the protection scope of the present application.

Claims

1. A method of manufacturing a circuit board, characterized by, The method comprises the following steps: providing a substrate unit comprising a first circuit unit, a first connecting layer and a second circuit unit stacked in sequence along a first direction, the first circuit unit comprising a first circuit layer and a first substrate layer stacked, the first substrate layer being a hydrophobic substrate layer, the first circuit layer being divided into a first region, a second region and a third region along a second direction perpendicular to the first direction, the first region and the third region being attached to the first connecting layer, the first connecting layer being provided with a cavity, a projection of the second region in the first direction being placed in the cavity; removing part of the second circuit unit on the cavity to form a first slot in the second circuit unit; removing the second region to obtain a second slot, the second slot, the cavity and the first slot collectively forming a groove, part of the first substrate layer being exposed in the groove; laser processing the first substrate layer exposed in the groove, so that part of the first substrate layer is converted into a hydrophilic region, the hydrophilic region being connected to at least the first region; forming a conductive contact on the hydrophilic region.

2. The production method according to claim 1, wherein The preparation of the conductive contact comprises: forming a first plating layer on the hydrophilic region by electroless plating; forming a second plating layer on the first plating layer by electroplating, the first plating layer and the second plating layer collectively forming the conductive contact.

3. The production method according to claim 2, wherein The preparation of the substrate unit comprises: pressing the first connecting layer with the cavity to the first circuit layer; stacking a first substrate on the first connecting layer, the first substrate comprising a second substrate layer and a first conductive layer stacked on a surface of the second substrate layer away from the first connecting layer; forming a first plating layer on the first conductive layer; and etching the first conductive layer and the first plating layer to obtain a second circuit layer, at least the second circuit layer and the second substrate layer constituting the second circuit unit.

4. The production method according to claim 3, wherein The preparation of the substrate unit further comprises: forming a through hole at least through the first substrate, the first connecting layer and the third region along the first direction; forming a second plating layer connected to the first plating layer in the through hole to obtain a conductive hole, the conductive hole electrically connecting the first circuit layer and the second circuit layer; in the step of obtaining the hydrophilic region, the hydrophilic region is also connected to the third region; in the step of forming the conductive contact, the conductive contact is also connected to the third region.

5. The production method according to claim 4, wherein The preparation of the substrate unit comprises: providing a second substrate, a third substrate and a second connecting layer, stacking the second connecting layer between the second substrate and the third substrate and pressing the three, the second substrate comprising the first substrate layer and a second conductive layer stacked on a surface of the first substrate layer away from the second connecting layer, the third substrate comprising a third substrate layer and a third conductive layer stacked on a surface of the third substrate layer away from the second connecting layer; forming a third plating layer on the second conductive layer and a fourth plating layer on the third conductive layer, The first circuit layer is formed by etching the second conductive layer and the third plating layer, and the third circuit layer is formed by etching the third conductive layer and the fourth plating layer. The via also penetrates the second connection layer and the third circuit layer, and the conductive via also electrically connects the third circuit layer.

6. The production method according to claim 4, wherein Before the first connection layer is pressed, the preparation method further comprises forming a first anti-soldering layer on the first region, the first anti-soldering layer being adjacent to the second region along the second direction; After the first connection layer is pressed, the first connection layer also covers part of the first anti-soldering layer, and part of the first anti-soldering layer is exposed in the cavity.

7. The production method according to any one of claims 1 to 6, wherein After the conductive contact piece is formed, the preparation method further comprises cutting the circuit board along the first direction, the cutting line of the cutting corresponding to the connection between the second region and the third region, so as to remove the part of the circuit board not containing the conductive contact piece.

8. A circuit board produced by the method of producing a circuit board according to Claim 1, comprising a first wiring unit, a first connection layer, and a second wiring unit which are sequentially stacked in a first direction, characterized in that, The first circuit layer includes a first circuit layer and a first substrate layer stacked in sequence, the first substrate layer being a hydrophobic substrate layer, the circuit board being provided with a groove penetrating the second circuit layer, the first connection layer and the first circuit layer, part of the first substrate layer being exposed in the groove, the first substrate layer exposed in the groove having a hydrophilic region, the hydrophilic region being connected to the first circuit layer, and the circuit board further comprising a conductive contact piece, the conductive contact piece being arranged on the hydrophilic region and connected to the first circuit layer.

9. The circuit board of claim 8, wherein, The circuit board further comprises a first anti-soldering layer, the groove comprising a cavity penetrating the first connection layer, a first slot part penetrating the second circuit layer, and a second slot part penetrating the first circuit layer, the cavity being in communication with the first slot part and the second slot part in the first direction, the first circuit layer comprising a first region adjacent to the cavity in a second direction perpendicular to the first direction, the first anti-soldering layer being arranged on the first region, part of the first anti-soldering layer being stacked between the first region and the first connection layer, and another part of the first anti-soldering layer being exposed in the cavity.

10. The circuit board of claim 8, wherein, The second circuit layer includes a second substrate layer and a second circuit layer stacked on a surface of the second substrate layer away from the first connection layer, and a side of the first circuit layer away from the second circuit layer is sequentially stacked with a second connection layer, a third circuit layer, a third connection layer and a fourth circuit layer; The third circuit layer includes a third substrate layer and a third circuit layer stacked on a surface of the third substrate layer away from the second connection layer, and the fourth circuit layer includes a fourth substrate layer and a fourth circuit layer stacked on a surface of the fourth substrate layer away from the third connection layer; The circuit board further comprises a second anti-soldering layer, the second anti-soldering layer covering the second circuit layer and the fourth circuit layer.

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