Semiconductor capacitor and method for manufacturing the same

Abstract

The present invention provides a semiconductor capacitor and a manufacturing method thereof, wherein the capacitor comprises: a first semiconductor functional layer; a second semiconductor functional layer, wherein the second semiconductor functional layer and the first semiconductor functional layer are arranged in the same substrate; a plurality of interlayer dielectric layers, which are stacked and distributed on the substrate; a metal layer, wherein the metal layer is arranged on each interlayer dielectric layer, wherein a metal layer is arranged as a capacitor connection layer; a capacitor, which is arranged on the capacitor connection layer; and a plurality of contact plugs, wherein one end of the contact plug is connected to the first semiconductor functional layer or the second semiconductor functional layer or the capacitor, and the other end of the contact plug is connected to the metal layer through the interlayer dielectric layer; wherein the capacitor connection layer is connected to the first semiconductor functional layer through the contact plug, and the capacitor connection layer is connected to the second semiconductor functional layer through another contact plug. The present invention provides a semiconductor capacitor and a manufacturing method thereof, which can improve the electrical performance of the capacitor and reduce the possibility of failure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor capacitor and a manufacturing method thereof. Background Art

[0002] In the field of semiconductor technology, potential induced degradation (PID) is a phenomenon that occurs when photovoltaic modules are subjected to external voltage for a long time. It will cause problems such as power attenuation, reduced efficiency and shortened life of semiconductor devices, seriously affecting the product reliability of semiconductor devices. Potential induced degradation occurs during the etching process, metal deposition process and ashing process, so it is difficult to eradicate. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor capacitor and a method for manufacturing the same, which can improve the electrical performance of the semiconductor device and reduce the possibility of failure of the semiconductor device.

[0004] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0005] The present invention provides a semiconductor device, comprising:

[0006] a first semiconductor functional layer;

[0007] a second semiconductor functional layer, wherein the second semiconductor functional layer and the first semiconductor functional layer are arranged in the same substrate;

[0008] A plurality of interlayer dielectric layers are stacked and distributed on the substrate;

[0009] A metal layer, the metal layer is arranged on each of the interlayer dielectric layers, wherein one metal layer is arranged as a capacitor connection layer;

[0010] A capacitor is disposed on the capacitor connection layer; and

[0011] a plurality of contact plugs, one end of each of the contact plugs being connected to the first semiconductor functional layer or the second semiconductor functional layer or the capacitor, and the other end of each of the contact plugs being connected to the metal layer through the interlayer dielectric layer;

[0012] The capacitor connection layer is connected to the first semiconductor functional layer through the contact plug, and the capacitor connection layer is connected to the second semiconductor functional layer through another contact plug.

[0013] In one embodiment of the present invention, the first semiconductor functional layer and the second semiconductor functional layer respectively include a plurality of working areas, the plurality of working areas are arranged in the substrate, and the plurality of working areas are sequentially connected through the contact plug and the metal layer.

[0014] In one embodiment of the present invention, the working area includes a first type of doped area and a second type of doped area, the first type of doped area serves as the positive input terminal of the working area, and the second type of doped area serves as the negative input terminal of the working area, wherein the capacitor connection layer is connected to the first type of doped area of ​​the first semiconductor functional layer and the second type of doped area of ​​the second semiconductor functional layer through the contact plug and the metal layer.

[0015] In one embodiment of the present invention, the first type of doped region in the working area is connected to the second type of doped region in the adjacent working area, and the doped regions of the first semiconductor functional layer and the second semiconductor functional layer are symmetrically distributed, wherein in the first semiconductor functional layer and the second semiconductor functional layer, the second type of doped region is close to the axis of symmetry, and the first type of doped region is far away from the axis of symmetry.

[0016] In one embodiment of the present invention, the interlayer dielectric layer is at least two layers, and along a direction away from the substrate, the semiconductor device includes:

[0017] a first interlayer dielectric layer, a first contact plug is disposed in the first interlayer dielectric layer, a first metal layer is disposed on the first interlayer dielectric layer, wherein the working area is connected to the first metal layer through the first contact plug, and adjacent working areas are connected to the same first metal layer through the first contact plug; and

[0018] A second interlayer dielectric layer, a second contact plug is arranged in the second interlayer dielectric layer, and the capacitor connection layer is arranged on the second interlayer dielectric layer, wherein the second contact plug is connected to the edge working area of ​​the first semiconductor functional layer through the first metal layer and the first contact plug, and the second contact plug is connected to the edge working area of ​​the second semiconductor functional layer through another first metal layer and another first contact plug.

[0019] In one embodiment of the present invention, the semiconductor device includes a third interlayer dielectric layer, the third interlayer dielectric layer is arranged on the second interlayer dielectric layer, a third contact plug is arranged in the third interlayer dielectric layer, and a third metal layer is arranged on the third interlayer dielectric layer, wherein the capacitor connection layer and the capacitor are arranged in the third interlayer dielectric layer, one end of the third contact plug is connected to the capacitor or the capacitor connection layer, and the other end of the third contact plug is connected to the third metal layer, wherein the third metal layer is the output port of the semiconductor device.

[0020] In one embodiment of the present invention, the capacitor comprises:

[0021] A first electrode layer, disposed on the capacitor connection layer, wherein the first electrode layer is connected to the first semiconductor functional layer and the second semiconductor functional layer through a plurality of the metal layers and a plurality of the contact plugs;

[0022] an insulating layer, disposed on the first electrode layer; and

[0023] The second electrode layer is arranged on the insulating layer, the second electrode layer is electrically connected to the metal layer through a contact plug, and the second electrode layer is electrically connected to the external functional module through multiple metal layers and multiple contact plugs, wherein the first electrode layer and the second electrode layer are conductive materials.

[0024] In one embodiment of the present invention, the first electrode layer, the insulating layer and the second electrode layer are distributed in parallel and are parallel to the surface of the substrate.

[0025] The present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0026] Providing a substrate, forming a first semiconductor functional layer and a second semiconductor functional layer in the substrate;

[0027] Forming a plurality of interlayer dielectric layers on the substrate, wherein the plurality of interlayer dielectric layers are stacked and distributed on the substrate;

[0028] After forming the interlayer dielectric layer and before forming the next interlayer dielectric layer, a plurality of contact plugs are formed in the interlayer dielectric layer, and a metal layer is formed on the interlayer dielectric layer, wherein one end of the contact plug is connected to the first semiconductor functional layer or the second semiconductor functional layer or the lower metal layer, wherein one of the metal layers is a capacitor connection layer; and

[0029] After forming one interlayer dielectric layer and before forming the next interlayer dielectric layer, a capacitor is formed on the capacitor connection layer, wherein the capacitor connection layer is connected to the first semiconductor functional layer through the contact plug, and the capacitor connection layer is connected to the second semiconductor functional layer through another contact plug.

[0030] In one embodiment of the present invention, the capacitor connection layer is a second metal layer, and before forming the capacitor connection layer, a first metal layer is formed on the first interlayer dielectric layer, wherein the first metal layer is connected to a first contact plug, and the first metal layer is connected between adjacent working areas of the first semiconductor functional layer or the second semiconductor functional layer through the first contact plug.

[0031] As described above, the present invention provides a semiconductor capacitor and a method for manufacturing the same, wherein the semiconductor device is a semiconductor capacitor, and the semiconductor device provided by the present invention can avoid the influence of the potential induced decay effect, thereby improving the leakage current performance, anti-breakdown performance, etc. of the semiconductor device, and according to the semiconductor capacitor and a method for manufacturing the same provided by the present invention, it is possible to avoid premature breakdown of the device due to an excessively thick interlayer dielectric layer, thereby improving the working reliability of the semiconductor device.

[0032] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 FIG. 4 is a schematic structural diagram of a shallow trench isolation structure in one embodiment of the present invention.

[0035] Figure 2 FIG. 4 is a schematic diagram of the structure of a deep well region in an embodiment of the present invention.

[0036] Figure 3 Schematic diagram of the structure of the working area in one embodiment of the present invention.

[0037] Figure 4 FIG. 4 is a schematic diagram of the structure of the source region and the drain region in one embodiment of the present invention.

[0038] Figure 5 FIG. 4 is a schematic diagram of the structure of the first interlayer dielectric layer in one embodiment of the present invention.

[0039] Figure 6FIG. 4 is a schematic diagram of the structure of a second interlayer dielectric layer and multiple metal layers in one embodiment of the present invention.

[0040] Figure 7 FIG. 4 is a schematic diagram of a wiring structure of a first metal layer in an embodiment of the present invention.

[0041] Figure 8 FIG. 4 is a schematic structural diagram of a semiconductor device in one embodiment of the present invention.

[0042] Fig. 9 FIG. 4 is a circuit diagram of a semiconductor device in one embodiment of the present invention.

[0043] In the figure: 100, substrate; 101, shallow trench isolation structure; 102, deep well region; 103a, first type well region; 103b, second type well region; 104a, first type doped region; 104b, second type doped region; 105, first interlayer dielectric layer; 106, first contact plug; 107, second interlayer dielectric layer; 108, first metal layer; 109, second contact plug; 110, second metal layer; 111, third interlayer dielectric layer; 112, capacitor; 1121, first plate layer; 1122, insulating layer; 1123, second plate layer; 113, third contact plug; 114, third metal layer; 200, functional module; 300, first protection circuit; 310, first type diode; 400, second protection circuit; 410, second type diode. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] The semiconductor device provided by the present invention is a semiconductor capacitor. Figures 1 to 8 As shown, the present invention provides a manufacturing method for forming the above-mentioned semiconductor device. Figure 1As shown, a substrate 100 is first provided. The substrate 100 is, for example, a silicon substrate for forming a semiconductor device. Specifically, the substrate 100 may include a substrate and a silicon layer disposed above the substrate, and the substrate may be, for example, a semiconductor substrate material such as silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc., and the silicon layer is formed above the substrate. The substrate 100 may be an intrinsic semiconductor, or ions may be implanted into the substrate 100 to form an N-type semiconductor or a P-type semiconductor. In this embodiment, an impurity element with a trivalent positive charge, such as boron, aluminum, etc., may be implanted into the substrate 100 by an ion implantation process, thereby converting the substrate 100 from an intrinsic semiconductor to a P-type semiconductor. Then, a shallow trench isolation structure 101 is formed in the substrate 100. In this embodiment, shallow trenches are sequentially formed in the substrate 100 by a shallow trench isolation process (Shallow Trench Isolation, STI), and the shallow trenches are filled to form a shallow trench isolation structure 101. The shallow trench isolation structure 101 separates a plurality of active regions in the substrate 100. After the plurality of active regions are separated, the purpose of each active region is planned. In this embodiment, the plurality of active regions are divided into a first functional region and a second functional region, a subsequent semiconductor manufacturing process is performed in the first functional region to form a first semiconductor functional layer, and a subsequent semiconductor manufacturing process is performed in the second functional region to form a second semiconductor functional layer.

[0046] See also Figure 1 As shown, in one embodiment of the present invention, in the substrate 100, the active areas belonging to the first functional area are distributed in a rectangular array, and the active areas belonging to the second functional area are distributed in a rectangular array. In this embodiment, the first functional area and the second functional area are adjacent. In other embodiments of the present invention, the active areas belonging to the first functional area may also be distributed in a linear array, and the active areas belonging to the second functional area may also be distributed in a linear array. In this embodiment, as Figure 3 As shown, the active areas located on the same straight line in the first functional area are, for example, 2 columns, and the active areas in the direction perpendicular to the paper are at least 2 rows. The active areas located on the same straight line in the second functional area are, for example, 2 columns, and the active areas in the direction perpendicular to the paper are at least 2 columns, thereby increasing the number of devices distributed per unit area. It should be noted that in the present invention, the number of active areas is related to the breakdown voltage of the semiconductor device. The higher the breakdown voltage, the more active areas are set in a single functional area, and the number of active areas in a single functional area is at least 2. In this embodiment, the active areas of the first functional area and the second functional area are symmetrically distributed.

[0047] See also Figure 2 and Figure 3As shown, in one embodiment of the present invention, after forming the shallow trench isolation structure 101, a deep well region 102 is formed in the substrate 100, a first type of well region 103a is formed in the deep well region 102, and a second type of well region 103b is formed in the substrate 100. In this embodiment, an impurity element with a pentavalent negative charge is injected into the active region of the first semiconductor functional layer by an ion implantation process, such as phosphorus, arsenic ions, so as to form the deep well region 102. In this embodiment, the deep well region 102 is formed in the active region of the first semiconductor functional layer. The surface of the deep well region 102 is flush with that of the shallow trench isolation structure 101, and the depth of the deep well region 102 in the substrate 100 is greater than the depth of the shallow trench isolation structure 101 in the substrate 100. Then, ions are implanted into the first semiconductor functional layer and the second semiconductor functional layer successively or simultaneously by an ion implantation process to form the first type of well region 103a and the second type of well region 103b. Specifically, an impurity element with a pentavalent negative charge, such as phosphorus or arsenic ions, is injected into the deep well region 102 to form a first-type well region 103a. An impurity element with a trivalent positive charge, such as boron or aluminum ions, is injected into the active region of the second semiconductor functional layer to form a second-type well region 103b.

[0048] See also Figure 3 and Figure 4As shown, in one embodiment of the present invention, ions are respectively implanted into the first type well region 103a and the second type well region 103b to form the first type doped region 104a and the second type doped region 104b in the first type well region 103a and the second type well region 103b, and the first type doped region 104a and the second type doped region 104b are formed in the first type well region 103a and the second type well region 103b. In this embodiment, impurity elements with trivalent positive charge, such as boron and aluminum ions, are implanted into the first type well region 103a and the second type well region 103b to form the first type doped region 104a, and impurity elements with pentavalent negative charge, such as phosphorus and arsenic ions, are implanted into the first type well region 103a and the second type well region 103b to form the second type doped region 104b, thereby forming the first semiconductor functional layer in the first functional region and the second semiconductor functional layer in the second functional region. In the first semiconductor functional layer and the second semiconductor functional layer, the first type doping region 104a serves as the positive terminal of the semiconductor device, and the second type doping region 104b serves as the negative terminal of the semiconductor device. When working, the electrons in the second type doping region 104b move along the wiring to the first type doping region 104a of the adjacent active region. It should be noted that the first semiconductor functional layer has a working area, and the working area of ​​the first semiconductor functional layer includes the deep well region 102, the first type well region 103a, the first type doping region 104a and the second type doping region 104b. The second semiconductor functional layer has a working area, and the working area of ​​the second semiconductor functional layer includes the second type well region 103b, the first type doping region 104a and the second type doping region 104b. In this embodiment, the depth of the first type doping region 104a and the second type doping region 104b in the substrate 100 is less than the depth of the shallow trench isolation structure 101 in the substrate 100.

[0049] See also Figure 4 and Figure 5As shown, in one embodiment of the present invention, after forming the first semiconductor functional layer and the second semiconductor functional layer, a first interlayer dielectric layer 105 is formed on the substrate 100, and a first contact plug 106 is formed in the first interlayer dielectric layer 105, wherein one end of the first contact plug 106 passes through the first interlayer dielectric layer 105 and is connected to the first type doping region 104a, and is connected to the second type doping region 104b. In this embodiment, materials such as silicon dioxide (SiO2), tetraethyl ortho silicate (TEOS) and the like are deposited on the substrate 100 by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD), thereby forming the first interlayer dielectric layer 105. The present invention does not limit the thickness of the first interlayer dielectric layer 105. Even when the thickness of the first interlayer dielectric layer 105 is large, the semiconductor device provided by the present invention can still have a good conduction performance. Then, a mask is formed on the first interlayer dielectric layer 105, and the first interlayer dielectric layer 105 is etched under the cover of the mask to form a deposition groove, wherein the deposition groove connects the first type doping region 104a and the second type doping region 104b. Then, the deposition groove is filled to form a first contact plug 106. The deposition groove can be filled with a metal material in the deposition groove by electroplating or sputtering, such as copper, aluminum, etc., to form the first contact plug 106.

[0050] See also Figures 5 to 7 As shown, in one embodiment of the present invention, a first metal layer 108 is formed on the first interlayer dielectric layer 105, and then a second interlayer dielectric layer 107 is formed on the first metal layer 108, and then a second contact plug 109 is formed in the second interlayer dielectric layer 107, and then a second metal layer 110 is formed on the second interlayer dielectric layer 107. In this embodiment, after the first contact plug 106 is formed, a metal material, such as copper, aluminum, etc., is attached to the first interlayer dielectric layer 105 by physical vapor deposition, electroplating, etc., so as to form a metal film. Then, the metal film is patterned and etched to form a first metal layer 108. The first metal layer 108 is connected to the first contact plug 106. The patterning of the metal film can be dry etching, wet etching, etc. In this embodiment, the first metal layer 108 is connected to at least one first contact plug 106, and the first metal layer 108 is connected to the first type doping region 104a and the second type doping region 104b of the adjacent working area through the first contact plug 106.

[0051] See also Figure 6 and Figure 7As shown, in one embodiment of the present invention, multiple first metal layers 108 are sequentially connected to different types of doped regions of adjacent working areas, thereby connecting multiple working areas of the first semiconductor functional layer in series in sequence, connecting multiple working areas of the second semiconductor functional layer in series in sequence, and connecting adjacent edge working areas of the two semiconductor functional layers, thereby connecting the working areas of the two semiconductor functional layers in series into a complete series circuit. The first metal layer 108, which serves as a connection between two adjacent working areas, is connected to two first contact plugs 106. The first metal layer 108 located at the edge of the series circuit is connected to the contact plug of the upper layer, and the first metal layer 108 at the edge of the series circuit is only connected to one first contact plug 106. In this embodiment, the doping region patterns of the first semiconductor functional layer and the second semiconductor functional layer are symmetrically distributed about the symmetry axis. As shown Figure 6 and Figure 7 As shown, in each working area of ​​the first semiconductor functional layer and the second semiconductor functional layer, the second type doping region 104b is close to the symmetry axis, and the first type doping region 104a is far away from the symmetry axis. In this embodiment, the doping region at the edge of the series loop is the first type doping region 104a.

[0052] See also Figure 6 and Figure 8 As shown, in one embodiment of the present invention, after forming the second metal layer 110, a capacitor 112 is formed on the second metal layer 110. Specifically, a first plate layer 1121 is formed on the second metal layer 110, an insulating layer 1122 is formed on the first plate layer 1121, and a second plate layer 1123 is formed on the insulating layer 1122. In this embodiment, the first plate layer 1121 and the second plate layer 1123 are both metal materials, such as copper, aluminum, etc. The first plate layer 1121 and the second plate layer 1123 are formed by electroplating or physical vapor deposition. In this embodiment, the insulating layer 1122 is an insulating material, such as aluminum oxide, silicon oxide, etc. In this embodiment, the first plate layer 1121 formed by deposition covers the second metal layer 110, and then the first plate layer 1121, the insulating layer 1122 and the second plate layer 1123 are etched and patterned with the help of a mask to form a capacitor 112. In this embodiment, in the step of forming the capacitor 112 , in order to protect the surface of the second interlayer dielectric layer 107 from being damaged, the second interlayer dielectric layer 107 may be covered with a photoresist layer, thereby preventing the etching process for forming the capacitor 112 from damaging the surface of the second interlayer dielectric layer 107 .

[0053] See also Figure 6 and Figure 8As shown, in one embodiment of the present invention, after forming the capacitor 112, a third interlayer dielectric layer 111 is formed on the second interlayer dielectric layer 107, wherein the third interlayer dielectric layer 111 covers the second interlayer dielectric layer 107, the second metal layer 110 and the capacitor 112. In this embodiment, the third interlayer dielectric layer 111 is formed by chemical vapor deposition. Then, a third contact plug 113 is formed in the third interlayer dielectric layer 111. In this embodiment, the third interlayer dielectric layer 111 is etched to form a deposition groove, wherein the surface of the deposition groove is connected to the surface of the second electrode layer 1123 or the surface of the second metal layer 110. Then, the deposition groove is filled to form the third contact plug 113. In this embodiment, one end of the third contact plug 113 is connected to the second electrode layer 1123 or the second metal layer 110, and the other end of the third contact plug 113 serves as an interface end of the semiconductor device.

[0054] See also Figure 8 and Fig. 9 As shown, in one embodiment of the present invention, after forming the third contact plug 113, a third metal layer 114 is formed on the third interlayer dielectric layer 111. The third metal layer 114 may be the wiring of the functional module 200. Figure 8 As shown, the semiconductor device provided by the present invention is electrically connected to the functional module 200. In this embodiment, the second electrode layer 1123 is connected to the wiring of the functional module 200 through the third contact plug 113, and the first electrode layer 1121 is connected to the wiring of the functional module 200 through the second metal layer 110 and the third contact plug 113. Fig. 9 As shown, capacitor 112 is connected in parallel with functional module 200. Fig. 9As shown, the semiconductor device includes a first protection circuit 300 and a second protection circuit 400. The first protection circuit 300 includes a plurality of first-type diodes 310, which are connected in series in sequence. In this embodiment, the first protection circuit 300 is a first semiconductor functional layer. The first-type diode 310 is the working area of ​​the first semiconductor functional layer. The second protection circuit 400 includes a plurality of second-type diodes 410, which are connected in series in sequence. In this embodiment, the second protection circuit 400 is a second semiconductor functional layer. The second-type diode 410 is the working area of ​​the second semiconductor functional layer. In this embodiment, the first protection circuit 300 and the second protection circuit 400 are connected in series to form a series loop. The positive pole of the first-type diode 310 located at the edge of the first protection circuit 300 is electrically connected to the capacitor 112, and is connected to the first plate layer 1121 of the capacitor 112. The negative pole of the second-type diode 410 located at the edge of the second protection circuit 400 is electrically connected to the capacitor 112, and is connected to the first plate layer 1121 of the capacitor 112. It should be noted that the present invention does not limit the type of the functional module 200 , and does not limit the connection object of the semiconductor device provided by the present invention.

[0055] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor capacitor, characterized in that: include: a first semiconductor functional layer; a second semiconductor functional layer, wherein the second semiconductor functional layer and the first semiconductor functional layer are arranged in the same substrate; A plurality of interlayer dielectric layers are stacked and distributed on the substrate; A metal layer, the metal layer is arranged on each of the interlayer dielectric layers, wherein one metal layer is arranged as a capacitor connection layer; A capacitor, disposed on the capacitor connection layer; as well as a plurality of contact plugs, one end of each of the contact plugs being connected to the first semiconductor functional layer or the second semiconductor functional layer or the capacitor, and the other end of each of the contact plugs being connected to the metal layer through the interlayer dielectric layer; Wherein, the capacitor connection layer is connected to the first semiconductor functional layer through the contact plug, and the capacitor connection layer is connected to the second semiconductor functional layer through another contact plug; The capacitor comprises: A first electrode layer, disposed on the capacitor connection layer, wherein the first electrode layer is connected to the first semiconductor functional layer and the second semiconductor functional layer through a plurality of the metal layers and a plurality of the contact plugs; an insulating layer, disposed on the first electrode layer; and The second electrode layer is arranged on the insulating layer, the second electrode layer is connected to the metal layer through the contact plug, and the second electrode layer is electrically connected to the external functional module through multiple metal layers and multiple contact plugs, wherein the first electrode layer and the second electrode layer are conductive materials.

2. A semiconductor capacitor according to claim 1, characterized in that: The first semiconductor functional layer and the second semiconductor functional layer respectively include a plurality of working areas, the plurality of working areas are arranged in the substrate, and the plurality of working areas are sequentially connected through the contact plug and the metal layer.

3. A semiconductor capacitor according to claim 2, characterized in that: The working area includes a first type of doped area and a second type of doped area, the first type of doped area serves as a positive input terminal of the working area, and the second type of doped area serves as a negative input terminal of the working area, wherein the capacitor connection layer is connected to the first type of doped area of ​​the first semiconductor functional layer and the first type of doped area of ​​the second semiconductor functional layer through the contact plug and the metal layer.

4. A semiconductor capacitor according to claim 3, characterized in that: The first type of doped region in the working area is connected to the second type of doped region in the adjacent working area, and the doped regions of the first semiconductor functional layer and the second semiconductor functional layer are symmetrically distributed, wherein in the first semiconductor functional layer and the second semiconductor functional layer, the second type of doped region is close to the symmetry axis, and the first type of doped region is far away from the symmetry axis.

5. A semiconductor capacitor according to claim 2, characterized in that: The interlayer dielectric layer is at least two layers, and along the direction away from the substrate, the semiconductor capacitor includes: a first interlayer dielectric layer, a first contact plug is disposed in the first interlayer dielectric layer, a first metal layer is disposed on the first interlayer dielectric layer, wherein the working area is connected to the first metal layer through the first contact plug, and adjacent working areas are connected to the same first metal layer through the first contact plug; and A second interlayer dielectric layer, a second contact plug is arranged in the second interlayer dielectric layer, and the capacitor connection layer is arranged on the second interlayer dielectric layer, wherein the second contact plug is connected to the edge working area of ​​the first semiconductor functional layer through the first metal layer and the first contact plug, and the second contact plug is connected to the edge working area of ​​the second semiconductor functional layer through another first metal layer and another first contact plug.

6. A semiconductor capacitor according to claim 5, characterized in that: The semiconductor capacitor includes a third interlayer dielectric layer, the third interlayer dielectric layer is arranged on the second interlayer dielectric layer, a third contact plug is arranged in the third interlayer dielectric layer, and a third metal layer is arranged on the third interlayer dielectric layer, wherein the capacitor connection layer and the capacitor are arranged in the third interlayer dielectric layer, one end of the third contact plug is connected to the capacitor or the capacitor connection layer, and the other end of the third contact plug is connected to the third metal layer, wherein the third metal layer is the output port of the semiconductor capacitor.

7. The semiconductor capacitor according to claim 1, characterized in that: The first electrode layer, the insulating layer and the second electrode layer are distributed in parallel and are parallel to the surface of the substrate.

8. A method for manufacturing a semiconductor capacitor, characterized in that: The following steps are involved: Providing a substrate, forming a first semiconductor functional layer and a second semiconductor functional layer in the substrate; Forming a plurality of interlayer dielectric layers on the substrate, wherein the plurality of interlayer dielectric layers are stacked and distributed on the substrate; After forming the interlayer dielectric layer and before forming the next interlayer dielectric layer, a plurality of contact plugs are formed in the interlayer dielectric layer, and a metal layer is formed on the interlayer dielectric layer, wherein one end of the contact plug is connected to the first semiconductor functional layer or the second semiconductor functional layer or the lower metal layer, wherein one of the metal layers is a capacitor connection layer; as well as After forming one interlayer dielectric layer and before forming the next interlayer dielectric layer, a capacitor is formed on the capacitor connection layer, wherein the capacitor connection layer is connected to the first semiconductor functional layer through the contact plug, and the capacitor connection layer is connected to the second semiconductor functional layer through another contact plug; The capacitor comprises: A first electrode layer, disposed on the capacitor connection layer, wherein the first electrode layer is connected to the first semiconductor functional layer and the second semiconductor functional layer through a plurality of the metal layers and a plurality of the contact plugs; an insulating layer, disposed on the first electrode layer; and The second electrode layer is arranged on the insulating layer, the second electrode layer is connected to the metal layer through the contact plug, and the second electrode layer is electrically connected to the external functional module through multiple metal layers and multiple contact plugs, wherein the first electrode layer and the second electrode layer are conductive materials.

9. The method for manufacturing a semiconductor capacitor according to claim 8, characterized in that: The capacitor connection layer is a second metal layer. Before forming the capacitor connection layer, a first metal layer is formed on the first interlayer dielectric layer, wherein the first metal layer is connected to a first contact plug, and the first metal layer is connected between adjacent working areas of the first semiconductor functional layer or the second semiconductor functional layer through the first contact plug.

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