A piezoresistive sensor and a processing method thereof

Abstract

The present invention relates to the field of sensor technology, and discloses a piezoresistive sensor and a processing method thereof, wherein the processing method uses at least 5 layers of SOI silicon wafers to prepare the piezoresistive sensor. Among them, a varistor is prepared in the first silicon layer of the 5-layer SOI silicon wafer; a silicon island is prepared in the third silicon layer of the 5-layer SOI silicon wafer to form a third structural layer; then the excess part of the first silicon layer is removed to form a connection structure connected to the varistor, thereby forming a first structural layer; and a composite layer is deposited at least on the varistor and the connection structure to form a stress enhancement structure. The thickness of the sensitive film in the island membrane structure of the prepared sensor is controllable, and the consistency of the thickness of the sensitive film is good, which can improve the sensitivity of the sensor. In addition, the stress enhancement structure is covered on the varistor, which can increase the stress at the varistor on the basis of protecting the varistor, thereby further improving the sensitivity of the sensor.

Description

Technical Field

[0001] The present invention relates to the technical field of sensors, and in particular to a piezoresistive sensor and a processing method thereof. Background Art

[0002] MEMS pressure sensors are widely used in the fields of automobiles, aerospace, military, medical care, etc. Among them, MEMS piezoresistive pressure sensors are the most widely used type of pressure sensors due to their simple structure and processing technology and easy signal extraction. In order to improve the sensitivity and linearity of pressure sensors, island membrane structure pressure sensors have been developed. In addition, in order to increase the operating temperature of pressure sensors, SOI island membrane structure pressure sensors have been developed. In the production of SOI island membrane structure pressure sensors, in order to improve the consistency of sensitivity, it is often necessary to accurately control the consistency of the sensitive film thickness. However, the effect of improving the sensitivity of pressure sensors only by controlling the consistency of the sensitive film thickness is limited, and it is impossible to obtain a piezoresistive pressure sensor with higher sensitivity (piezoresistive sensor for short). Summary of the invention

[0003] In order to solve the above technical problems, the present invention provides a piezoresistive sensor and a processing method thereof.

[0004] According to a first aspect of the present disclosure, a method for processing a piezoresistive sensor is provided, comprising the following steps: preparing a varistor in a first silicon layer of a 5-layer SOI silicon wafer; preparing a silicon island in a third silicon layer of the 5-layer SOI silicon wafer to form a third structural layer; removing excess portions of the first silicon layer to form a connecting structure connected to the varistor, thereby forming a first structural layer, wherein the connecting structure comprises a connecting island and a connecting beam, the connecting beam being connected to the periphery of the connecting island, and the varistor being connected to the connecting island via the connecting beam; and depositing a composite layer at least on the varistor and the connecting structure to form a stress enhancement structure.

[0005] Specifically, in some embodiments, the specific steps of forming the stress enhancement structure are: after depositing a composite layer on the upper surface of the 5-layer SOI silicon wafer after preparing the varistor, removing (removing) the composite layer above the first structural layer to form the stress enhancement structure.

[0006] Preferably, in some embodiments, the composite layer includes a silicon oxide layer, a polysilicon layer and a silicon nitride layer arranged from bottom to top.

[0007] Preferably, in some embodiments, the number of varistors and connecting beams are both constructed to be four, and each varistor is connected to a connecting island via a connecting beam; the first structural layer also includes a first frame connected to the varistor, and at least a portion of each varistor and the connecting island are arranged in the first frame; the thickness of the composite layer is 3~15μm.

[0008] Specifically, in some embodiments, the specific steps of preparing the silicon island in the third silicon layer are: after preparing the varistor on the first silicon layer of the 5-layer SOI silicon wafer, oxidize the upper and lower surfaces of the 5-layer SOI silicon wafer to form a first oxide film on the upper surface of the first silicon layer and a second oxide film on the lower surface of the third silicon layer; remove the middle part of the second oxide film by etching so that the remaining second oxide film forms the first oxide layer; apply photoresist on the lower surface of the 5-layer SOI silicon wafer, photolithograph to form the etching pattern of the silicon island, and the remaining photoresist after photolithography forms a transition etching mask; etch the lower surface of the 5-layer SOI silicon wafer for the first time under the protection of the transition etching mask to form a transition groove in the third silicon layer; after removing the transition etching mask, etch the lower surface of the 5-layer SOI silicon wafer for the second time under the protection of the first oxide layer so that the transition groove continues to deepen to form a groove, thereby forming a silicon island located inside the groove and a second frame located outside the groove. Wherein, the thickness of the silicon island is less than the thickness of the second frame.

[0009] In some embodiments, when etching the lower surface of the 5-layer SOI silicon wafer for the second time, the etching is stopped when the transition trench is further deepened to expose the second buried oxide layer between the third silicon layer and the second silicon layer.

[0010] In some embodiments, before removing the redundant portion of the first silicon layer to form the connection structure, the following steps are further included:

[0011] A through-hole-forming base layer is prepared in a common silicon wafer, and the base layer is connected to the bottom of the third structural layer by bonding.

[0012] In some embodiments, before preparing a through hole in an ordinary silicon wafer, the upper and lower surfaces of the ordinary silicon wafer are first oxidized to form a third oxide film and a fourth oxide film, and the middle portion of the third oxide film and the middle portion of the fourth oxide film are etched and removed to form a second oxide layer and a third oxide layer, respectively; the upper and lower surfaces of the ordinary silicon wafer are then etched to form a through hole; the first oxide layer is bonded to the second oxide layer; after the first oxide layer is bonded to the second oxide layer, the excess portion of the first silicon layer is first removed to form a first structural layer and then the first oxide film is removed, and then a composite layer is deposited on the upper surface of the 5-layer SOI silicon wafer to form a stress enhancement structure, and lead holes are formed in the stress enhancement structure and the first structural layer, and electrode leads electrically connected to the varistor are arranged in the lead holes.

[0013] Optionally, in some embodiments, the thickness of the first silicon layer of the 5-layer SOI silicon wafer is 2-5 μm, the thickness of the second silicon layer is 20-100 μm, and the thickness of the third silicon layer is 200-500 μm.

[0014] According to a second aspect of the present disclosure, a piezoresistive sensor is provided, which is prepared by the processing method according to the first aspect of the present disclosure. The piezoresistive sensor includes a first structural layer, a first insulating layer, a second structural layer, a second insulating layer, a third structural layer and a stress enhancement structure, which are arranged in sequence from top to bottom. The first structural layer is provided with a connection structure and a plurality of independent piezoresistors, the connection structure includes a connection island and a plurality of connection beams, the plurality of connection beams are connected to the periphery of the connection island, the plurality of piezoresistors are each connected to the connection structure through a connection beam to form a whole, and the third structural layer is provided with a silicon island. The stress enhancement structure is at least arranged on the piezoresistors and the connection structure, and the stress enhancement structure is constructed as a composite film. Among them, the first structural layer is prepared on the basis of the first silicon layer of a 5-layer SOI silicon wafer, the first insulating layer, the second structural layer and the second insulating layer are respectively the first buried oxide layer, the second silicon layer and the second buried oxide layer of the 5-layer SOI silicon wafer, and the third structural layer is prepared on the basis of the third silicon layer of the 5-layer SOI silicon wafer.

[0015] Features and advantages of the present disclosure include:

[0016] The processing method disclosed in the present invention adopts a 5-layer SOI silicon wafer to prepare a piezoresistive sensor. The thickness of the sensitive film in the island film structure of the sensor is controllable, and the thickness of the sensitive film can be customized according to the measurement needs of the sensor; and the sensitive film is processed on the basis of the first silicon layer, the first buried oxide layer, the second silicon layer, and the second buried oxide layer of the 5-layer SOI silicon wafer, and the consistency of the thickness of the sensitive film is good, which can improve the sensitivity of the sensor. In addition, the stress enhancement structure is covered on the varistor, which can increase the stress at the varistor on the basis of protecting the varistor, thereby further improving the sensitivity of the sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 , Figure 2 The structure diagram of the piezoresistive sensor of the present invention is shown in FIG. Figure 1 is a cross-sectional view, Figure 2 It is a top view;

[0019] Figure 3 The structure schematic diagram of the 5-layer SOI silicon wafer of the present invention is shown;

[0020] Figure 4 A schematic diagram of the structure of manufacturing a varistor on the first silicon layer of a 5-layer SOI silicon wafer is shown;

[0021] Figure 5 A schematic diagram showing a structure in which oxide films are formed on the upper and lower surfaces of a 5-layer SOI silicon wafer, and a portion of the oxide film at the bottom is removed to form a first oxide layer;

[0022] Figure 6 A schematic structural diagram of forming a transition etching mask on the lower surface of the first oxide layer and the third silicon layer is shown;

[0023] Figure 7 The schematic diagram of the structure of a 5-layer SOI silicon wafer after the first etching is shown;

[0024] Figure 8 The schematic diagram of the structure of the 5-layer SOI silicon wafer after the second etching is shown;

[0025] Fig. 9 The schematic diagram of the structure of a common silicon wafer is shown;

[0026] Fig.10 A schematic diagram of a structure for forming a through hole on a common silicon wafer is shown;

[0027] Fig.11 A schematic diagram of the structure of bonding a 5-layer SOI silicon wafer after the second etching to a common silicon wafer with a through hole formed is shown;

[0028] Fig.12 , Fig.13 The schematic diagram of the structure of removing the top oxide layer and the redundant first silicon layer to form the first structural layer is shown, wherein Fig.12 is a cross-sectional schematic diagram, Fig.13 It is a top view;

[0029] Fig.14 , Fig.15 The schematic diagram of the structure of depositing a composite layer on the top and removing the redundant composite layer to form a stress strengthening structure and a lead hole is shown, wherein Fig.14 is a cross-sectional view, Fig.15 It is a top view;

[0030] Fig.16 A schematic diagram of the structure of a piezoresistive sensor formed by depositing electrodes, leads, etc. is shown.

[0031] Description of reference numerals:

[0032] 100-piezoresistive sensor;

[0033] 101-first oxide film, 103-transition etching mask, 105-stress enhancement structure, 106-electrode lead, 107-pad, 108-lead hole, 109-stress enhancement hole, 112-first insulating layer, 114-second insulating layer, 116-third insulating layer, 116a-first oxide layer, 116b-second oxide layer, 118-third oxide layer;

[0034] 10-5-layer SOI silicon wafer, 11-first silicon layer, 12-first buried oxide layer, 13-second silicon layer, 14-second buried oxide layer, 15-third silicon layer, 17-transition trench;

[0035] 20-Ordinary silicon wafer;

[0036] 30-first structural layer, 31-varistor, 32-connecting structure, 32a-connecting island, 32b-connecting beam, 33-first frame;

[0037] 40- second structural layer;

[0038] 50 - third structural layer, 51 - groove, 52 - silicon island, 53 - second frame;

[0039] 60-base layer, 61-through hole. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] The present invention discloses a processing method for a piezoresistive sensor, which comprises preparing a piezoresistor and a connection structure in the first silicon layer of a 5-layer SOI silicon wafer, preparing a silicon island in the third silicon layer of the 5-layer SOI silicon wafer, and depositing a composite layer on the piezoresistor and the connection structure to form a stress enhancement structure. Since the thickness of the first silicon layer and the second silicon layer of the 5-layer SOI silicon wafer can be customized, the thickness of the sensitive film in the island film structure of the piezoresistive sensor obtained by the processing method is controllable, and the thickness of the sensitive film can be customized according to the measurement requirements of the sensor; and the sensitive film is processed on the basis of the first silicon layer, the first buried oxide layer, the second silicon layer, and the second buried oxide layer of the 5-layer SOI silicon wafer, and the consistency of the thickness of the sensitive film is good, which can improve the sensitivity of the sensor. In addition, the stress enhancement structure is covered on the piezoresistor, which can increase the stress at the piezoresistor on the basis of protecting the piezoresistor, thereby further improving the sensitivity of the sensor.

[0042] Combine the following Figure 1 , Figure 2 First, the piezoresistive sensor 100 provided by the present disclosure is introduced. The piezoresistive sensor 100 includes a first structural layer 30, a first insulating layer 112, a second structural layer 40, a second insulating layer 114 and a third structural layer 50 arranged in sequence from top to bottom. The first structural layer 30 is provided with a connection structure 32 and a plurality of independent piezoresistors 31, and the third silicon layer is provided with a silicon island 52. Figure 1 and Fig.13 , the connection structure 32 includes a connection island 32a and a plurality of connection beams 32b, and the plurality of connection beams 32b are arranged at the periphery of the connection island 32a, for example, the connection beams 32b are directly connected to the periphery of the connection island 32a. The plurality of piezoresistors 31 are connected to the connection structure 32 through a connection beam 32b, thereby forming a whole. The piezoresistive sensor 100 also includes a stress enhancement structure 105, and the stress enhancement structure 105 is at least arranged on the piezoresistors 31 and the connection structure 32, and the stress enhancement structure 105 is constructed as a composite film. In some embodiments, the composite film includes a silicon oxide layer, a polysilicon layer, and a silicon nitride layer arranged in sequence from bottom to top. In some embodiments, when an oxide layer is provided on the first structural layer 30 (for example, a first oxide film formed after oxidation of the surface of the first silicon layer is used as the oxide layer), the composite film includes a polysilicon layer and a silicon nitride layer arranged from bottom to top. The oxide layer and the silicon oxide layer have the function of insulating protection, the polysilicon layer can adjust the thickness of the composite film, and the silicon nitride layer can play a role of passivation protection for the sensor.

[0043] The piezoresistive sensor 100 is made of 5 layers of SOI silicon wafer, see Figure 3 The 5-layer SOI silicon wafer includes, from top to bottom, a first silicon layer 11, a first buried oxide layer 12, a second silicon layer 13, a second buried oxide layer 14 and a third silicon layer 15. The first structure layer 30 is prepared on the basis of the first silicon layer 11, the first insulating layer 112, the second structure layer 40 and the second insulating layer 114 are respectively the first buried oxide layer 12, the second silicon layer 13 and the second buried oxide layer 14 of the 5-layer SOI silicon wafer, and the third structure layer 50 is prepared on the basis of the third silicon layer 15.

[0044] Exemplarily, the number of varistors 31 and connecting beams 32b are both configured as 4, and the 4 connecting beams 32b are arranged around the connecting island 32a, and each varistor 31 is connected to the connecting island 32a through a connecting beam 32b. The first structural layer 30 also includes a first frame 33 connected to the varistor 31, and at least a portion of each varistor 31 and the connecting island 32a are arranged in the first frame 33. The first frame 33 is configured as a roughly square annular structure. Fig.13 It is shown that the first frame 33 is connected to one end and both sides of the varistor 31 so that at least a portion of the varistor 31 is embedded in the frame, and the varistor 31 is arranged at a stress-sensitive location.

[0045] The stress reinforcing structure 105 is disposed on the first structural layer 30, and the shape of the stress reinforcing structure 105 projected onto the horizontal plane is substantially consistent with the shape of the first structural layer 30 projected onto the horizontal plane. A stress reinforcing hole 109 penetrating the first insulating layer 112 is disposed on the top of the piezoresistive sensor 100. Specifically, the piezoresistive sensor 100 is provided with four independent stress reinforcing holes 109. The stress reinforcing hole 109 is located in the portion of the first structural layer 30, which is surrounded by the first frame 33, the piezoresistor 31, and the connecting structure 32. The portion is located on the outside of the connecting structure 32 and on the inside of the first frame 33. In some embodiments, the stress reinforcing structure 105 may be disposed only on the piezoresistor and the connecting structure 32.

[0046] Alternatively, see Figure 1 and Figure 2 The top of the piezoresistive sensor 100 is also provided with an electrode lead 106 and a pad 107 electrically connected to the piezoresistors 31. Specifically, the piezoresistive sensor 100 is provided with four electrode leads 106 and four pads 107, each pad 107 is respectively arranged on the periphery of a piezoresistors 31, and each pad 107 is respectively electrically connected to a piezoresistors 31 through an electrode lead 106. The four piezoresistors 31 can form a Wheatstone bridge through electrical connection, thereby improving the detection sensitivity of the sensor.

[0047] Specifically, the third structural layer 50 includes a silicon island 52, a groove 51 and a second frame 53. The groove 51 is configured in a ring shape, the silicon island 52 is located inside the ring-shaped groove 51, and the second frame 53 is located outside the ring-shaped groove 51. The second frame 53 is also configured in a ring shape. In particular, the groove 51 exposes the lower surface of the second insulating layer 114, and the lower surface of the silicon island 52 is indented inwardly relative to the lower surface of the second frame 53, that is, the thickness of the silicon island 52 is less than the thickness of the second frame 53.

[0048] Continue to see Figure 1 Optionally, the piezoresistive sensor 100 may further include a third insulating layer 116 and a base layer 60, wherein the third insulating layer 116 is disposed between the third structural layer 50 and the base layer 60. A through hole suitable for accommodating the silicon island 52 is provided in the middle of the third insulating layer 116 and the base layer 60, which can provide a space for the silicon island 52 to move downward, and can limit the transitional movement of the silicon island 52 downward to avoid causing damage to the sensor. Specifically, a first oxide layer 116a is provided on the lower surface of the third structural layer 50, and the shape of the first oxide layer 116a projected onto the horizontal plane is the same as the shape of the second frame 53 projected onto the horizontal plane. A second oxide layer 116b and a third oxide layer 118 are provided on the upper and lower surfaces of the base layer 60, respectively, and a through hole 61 penetrating the middle of the base layer 60, the second oxide layer 116b and the third oxide layer 118 is formed at the bottom of the piezoresistive sensor 100. The through hole 61 is configured to have a structure with large upper and lower openings and a small opening in the middle.

[0049] The first oxide layer 116a and the second oxide layer 116b together constitute the third insulating layer 116, and the third oxide layer 118 is the fourth insulating layer of the piezoresistive sensor 100. The first oxide layer 116a is processed from the second oxide film formed by oxidation of the third silicon layer 15, the base layer 60 is prepared from a common silicon wafer, and the second oxide layer 116b and the third oxide layer 118 are respectively processed from the third oxide film and the fourth oxide film formed by oxidation of the common silicon wafer. The first oxide layer 116a and the second oxide layer 116b are connected by bonding.

[0050] refer to Figures 4 to 16 , the processing method of the piezoresistive sensor 100 disclosed in the present invention is described in detail below. The processing method disclosed in the present invention adopts a 5-layer SOI silicon wafer and an ordinary silicon wafer, and the piezoresistive sensor 100 is prepared by processing. Preferably, the materials of the first silicon layer 11, the second silicon layer 13, and the third silicon layer 15 of the 5-layer SOI silicon wafer are all single crystal silicon. The thickness of the first silicon layer of the 5-layer SOI silicon wafer is 2~5μm, the thickness of the second silicon layer is 20~100μm, and the thickness of the third silicon layer is 200~500μm. The processing flow mainly includes: preparing a varistor on a 5-layer SOI silicon wafer, and etching to form a silicon island; etching an ordinary silicon wafer to form a through hole; bonding the processed 5-layer SOI silicon wafer to an ordinary silicon wafer, and processing to obtain a connection structure and a stress enhancement structure.

[0051] See also Figure 4 , a varistor 31 is prepared on the first silicon layer 11 of the 5-layer SOI silicon wafer. Specifically, the varistor 31 can be formed by performing a high-dose concentrated boron doping process on the first silicon layer 11. More specifically, the first silicon layer 11 can be doped with a high dose of concentrated boron by an ion implantation process or a high-temperature diffusion process. Since the first structural layer for setting the varistor is processed on the basis of the first silicon layer 11, the high temperature resistance of the SOI material can be brought into play, and the high temperature performance of the piezoresistive sensor 100 can be improved.

[0052] Preferably, four varistors 31 are prepared on the first silicon layer 11, and the arrangement of the four varistors 31 is as shown in Figure 2 or Fig.13 The four varistors 31 are electrically connected to each other. For example, in some embodiments, N-type or P-type doping elements may be doped in the first silicon layer 11 to electrically connect the four varistors 31 end to end in sequence to form a ring. In some embodiments, the four varistors 31 may be electrically connected to form a ring by depositing leads or the like.

[0053] See also Figures 5 to 8, a silicon island 52 is prepared on the third silicon layer 15 of the 5-layer SOI silicon wafer. Specifically, the process of preparing the silicon island 52 includes two etchings. The etching can be wet etching or dry etching, and preferably both etchings are dry etching. Through the two etchings, the thickness of the island structure can be reduced according to the needs of the sensor.

[0054] See also Figure 5 , the upper and lower surfaces of the 5-layer SOI silicon wafer are oxidized to form oxide films, specifically, the upper surface of the first silicon layer 11 is oxidized to form a first oxide film 101, and the lower surface of the third silicon layer 15 is oxidized to form a second oxide film. The middle part of the second oxide film is removed by etching so that the remaining second oxide film forms a first oxide layer 116a. Optionally, the shape of the first oxide layer 116a projected onto the horizontal plane is the same as the shape of the second frame 53 projected onto the horizontal plane. See Figure 6 , a photoresist is coated on the lower surface of the 5-layer SOI silicon wafer, and an etching pattern of the silicon island 52 is formed by photolithography, and the remaining photoresist after photolithography forms a transition etching mask 103. Optionally, the shape of the transition etching mask 103 projected onto the horizontal plane is the same as the shape of the second frame 53 and the silicon island 52 projected onto the horizontal plane.

[0055] See also Figure 7 , under the protection of the transition etching mask 103, the lower surface of the 5-layer SOI silicon wafer is etched for the first time to form a transition trench 17 in the third silicon layer 15. Figure 8 , remove the transition etching mask 103, and under the protection of the first oxide layer 116a, etch the lower surface of the 5-layer SOI silicon wafer for the second time, so that the transition groove 17 continues to deepen to form a groove 51, thereby forming a silicon island 52 located inside the groove 51 and a second frame 53 located outside the groove 51. In particular, in some embodiments, when etching the lower surface of the 5-layer SOI silicon wafer for the second time, the transition groove 17 continues to deepen until the second buried oxide layer 14 located between the third silicon layer 15 and the second silicon layer 13 is exposed before the etching is stopped. Since the sensitive film includes the first silicon layer 11, the first buried oxide layer 12, the second silicon layer 13, and the second buried oxide layer 14, and these layers all belong to the 5-layer SOI silicon wafer, the thickness consistency of each layer is good, thereby improving the consistency of the thickness of the sensor sensitive film. The thickness of the silicon island 52 obtained by the two etchings is smaller than the thickness of the second frame 53, that is, the lower surface of the second frame 53 is indented inward relative to the lower surface of the second frame 53.

[0056] See also Fig. 9 , Fig.10, the upper and lower surfaces of the common silicon wafer 20 are oxidized to form an oxide film, and the upper and lower surfaces are photoetched to form an etching pattern of the through hole. Specifically, the upper surface of the common silicon wafer is oxidized to form a third oxide film, and the lower surface of the common silicon wafer is oxidized to form a fourth oxide film. Photoetching is performed on the third oxide film and the fourth oxide film, and then the middle part of the third oxide film and the middle part of the fourth oxide film are etched to form a second oxide layer 116b and a third oxide layer 118 respectively, and then the common silicon wafer 20 is continuously etched to form a through hole 61. Specifically, the upper and lower surfaces of the common silicon wafer 20 are etched by a wet method or a dry method to form a through hole 61 that penetrates the upper and lower surfaces of the common silicon wafer, thereby obtaining a base layer 60. The base layer 60 is the unoxidized part of the common silicon wafer 20, and the second oxide layer 116b and the third oxide layer 118 are the remaining parts of the oxide film formed on the common silicon wafer 20 after being etched. In particular, the processing method disclosed in the present invention adopts wet etching, so that the opening of the through hole 61 gradually decreases from the upper and lower surfaces to the middle. The through hole 61 can provide space for the silicon island 52 to move downward, and can also limit the silicon island 52 from moving downward in a transitional manner to avoid damaging the sensor.

[0057] See also Fig.11 The first oxide layer 116a of the 5-layer SOI silicon wafer is connected to the second oxide layer 116b located on the upper side of the base layer 60 by bonding. The materials of the first oxide layer 116a and the second oxide layer 116b are both silicon oxide, and the specific bonding method can be silicon dioxide bonding or glass bonding.

[0058] See also Fig.12 , Fig.13 In some embodiments, after photolithography forms etching patterns such as the connection structure, a portion of the first silicon layer 11 is etched away to form a first frame 33 and a connection structure 32, thereby forming a first structure layer 30. The portion after etching away a portion of the first silicon layer 11 exposes the first buried oxide layer 12. It should be noted that the first frame 33 is not necessary. In some embodiments, the four corners of the first silicon layer 11 can be removed, that is, Fig.13 On the basis of, the removed portion is extended outward to the boundary of the first silicon layer 11. Optionally, after the first structure layer 30 is formed, the remaining first oxide film 101 on the first structure layer 30 is removed.

[0059] See also Fig.14 , Fig.15, a composite layer is deposited on the upper surface of the first structural layer 30, and the composite layers are silicon oxide layer, polysilicon layer and silicon nitride layer from bottom to top. The thickness of the composite layer is 3~15μm, the thickness of the silicon oxide layer is 0.5~2.5μm, the thickness of the polysilicon layer is 2~10μm, and the thickness of the silicon nitride layer is 0.5~2.5μm. Then, the etching pattern is formed by photolithography, and part of the composite layer is etched away to form a stress enhancement structure 105. Optionally, the stress enhancement structure 105 only covers the first structural layer 30, that is, it is located on the first frame 33, the varistor 31 and the connecting structure 32. The provision of the stress enhancement structure 105 is conducive to making the stress at the varistor 31 more concentrated, thereby increasing the sensitivity of the piezoresistive sensor 100. Four lead holes 108 are formed in the stress enhancement structure 105 and the first structural layer 30, and each lead hole 108 is respectively arranged close to a varistor 31 and is located outside the extension direction of the varistor 31.

[0060] Alternatively, after removing the first oxide film 101 located on the first silicon layer 11, a composite layer is deposited on the first silicon layer 11, and after photolithography forms etching patterns such as connection structures, the first silicon layer 11 and the redundant parts of the composite film are removed by etching to form stress enhancement holes 109, stress enhancement structures 105 and the first structural layer 30. Preferably, before depositing the composite layer, the first oxide film 101 is removed first, and then the silicon oxide layer, polysilicon layer and silicon nitride layer in the composite layer are deposited in sequence. Among them, using the newly deposited silicon oxide layer as an insulating layer is conducive to ensuring reliable insulation between the first silicon layer 11 and the deposited polysilicon layer.

[0061] Alternatively, in some embodiments, the first oxide film 101 may not be removed, and a composite layer may be deposited directly on the first oxide film 101, wherein the composite layer is a polysilicon layer and a silicon nitride layer from bottom to top, so that the first oxide film 101 serves as an insulating layer between the first silicon layer 11 and the deposited polysilicon layer.

[0062] See also Fig.16 , deposit electrode leads 106 in lead holes 108, deposit pads 107 on stress reinforcement structure 105, and connect each varistor 31 to a pad 107 through an electrode lead 106, thereby obtaining piezoresistive sensor 100. Pads 107 are used for wiring of piezoresistive sensor 100.

[0063] It should be noted that, in some embodiments, the base layer 60 is not necessary, and the piezoresistive sensor 100 without the base layer can be processed using only 5 layers of SOI silicon wafers. The processing flow at this time can be obtained by adaptively adjusting the above processing flow.

[0064] The above are only several embodiments of the present invention. Those skilled in the art may make various changes or modifications to the embodiments of the present invention based on the contents disclosed in the application documents without departing from the spirit and scope of the present invention.

Claims

1. A method for processing a piezoresistive sensor, characterized in that: The steps include: A varistor is prepared in the first silicon layer of a 5-layer SOI silicon wafer, where the thickness of the first silicon layer is 2-5 μm; A silicon island is prepared in the third silicon layer of the 5-layer SOI silicon wafer to form a third structural layer; Removing excess portions of the first silicon layer to form a connection structure connected to the varistor, thereby forming a first structural layer, wherein the connection structure includes a connection island and a connection beam, wherein the connection beam is connected to the periphery of the connection island, and the varistor is connected to the connection island through the connection beam; Depositing a composite layer at least on the varistor and the connecting structure to form a stress enhancement structure; The specific steps of forming the stress enhancement structure are: after depositing a composite layer on the upper surface of the 5-layer SOI silicon wafer after preparing the varistor, removing the composite layer except the composite layer above the first structural layer to form the stress enhancement structure; The composite layer includes a silicon oxide layer, a polysilicon layer and a silicon nitride layer arranged from bottom to top, and the thickness of the composite layer is 3-15 μm.

2. The method for processing a piezoresistive sensor according to claim 1, characterized in that: The number of the varistors and the connecting beams are both constructed to be four, and each varistor is connected to a connecting island via a connecting beam; the first structural layer also includes a first frame connected to the varistor, and at least a portion of each varistor and the connecting island are arranged in the first frame.

3. The method for processing a piezoresistive sensor according to claim 2, characterized in that: The specific steps of preparing silicon islands in the third silicon layer are: After preparing a varistor on the first silicon layer of the five-layer SOI silicon wafer, oxidizing the upper and lower surfaces of the five-layer SOI silicon wafer to form a first oxide film on the upper surface of the first silicon layer and a second oxide film on the lower surface of the third silicon layer; Etching and removing the middle portion of the second oxide film so that the remaining second oxide film forms a first oxide layer; A photoresist is coated on the lower surface of the 5-layer SOI silicon wafer, and an etching pattern of the silicon island is formed by photolithography, and the remaining photoresist after photolithography forms a transition etching mask; Under the protection of the transition etching mask, the lower surface of the 5-layer SOI silicon wafer is etched for the first time to form a transition trench in the third silicon layer; After removing the transition etching mask, the lower surface of the 5-layer SOI silicon wafer is etched for the second time under the protection of the first oxide layer, so that the transition trench is further deepened to form a trench, thereby forming a silicon island located inside the trench and a second frame located outside the trench; The thickness of the silicon island is smaller than the thickness of the second frame.

4. The method for processing a piezoresistive sensor according to claim 3, characterized in that: When etching the lower surface of the 5-layer SOI silicon wafer for the second time, the etching is stopped when the transition trench is further deepened to expose the second buried oxide layer between the third silicon layer and the second silicon layer.

5. The method for processing a piezoresistive sensor according to any one of claims 1 to 4, characterized in that: Before removing the redundant part of the first silicon layer to form the connection structure, the following steps are also included: A through-hole-forming base layer is prepared in a common silicon wafer, and the base layer is connected to the bottom of the third structural layer by bonding.

6. The method for processing a piezoresistive sensor according to claim 5, characterized in that: Before preparing a through hole in a common silicon wafer, the upper and lower surfaces of the common silicon wafer are first oxidized to form a third oxide film and a fourth oxide film, and the middle of the third oxide film and the middle of the fourth oxide film are etched away to form a second oxide layer and a third oxide layer respectively; and then the upper and lower surfaces of the common silicon wafer are etched to form a through hole; bonding the first oxide layer to the second oxide layer; After the first oxide layer is bonded to the second oxide layer, the excess portion of the first silicon layer is removed to form a first structural layer and then the first oxide film is removed. Subsequently, a composite layer is deposited on the upper surface of the 5-layer SOI silicon wafer to form a stress enhancement structure, and lead holes are formed in the stress enhancement structure and the first structural layer. Electrode leads electrically connected to the varistor are arranged in the lead holes.

7. The method for processing a piezoresistive sensor according to claim 6, characterized in that: The thickness of the second silicon layer of the five-layer SOI silicon wafer is 20-100 μm, and the thickness of the third silicon layer is 200-500 μm.

8. A piezoresistive sensor, manufactured by the piezoresistive sensor manufacturing method according to any one of claims 1 to 7, characterized in that: include: A first structural layer, a first insulating layer, a second structural layer, a second insulating layer and a third structural layer are arranged in sequence from top to bottom; The first structural layer is provided with a connection structure and a plurality of independent varistors, the connection structure includes a connection island and a plurality of connection beams, the plurality of connection beams are connected to the periphery of the connection island, the plurality of varistors are connected to the connection structure via a connection beam respectively to form a whole, and the third structural layer is provided with a silicon island; A stress enhancement structure, wherein the stress enhancement structure is at least disposed on the varistor and the connection structure, and the stress enhancement structure is configured as a composite film; Among them, the first structural layer is prepared on the basis of the first silicon layer of the 5-layer SOI silicon wafer, the thickness of the first silicon layer is 2~5μm, the first insulating layer, the second structural layer, and the second insulating layer are respectively the first buried oxide layer, the second silicon layer, and the second buried oxide layer of the 5-layer SOI silicon wafer, and the third structural layer is prepared on the basis of the third silicon layer of the 5-layer SOI silicon wafer.

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