A circuit for enabling system self-start-up by controlling power supply

Abstract

This invention discloses a circuit for achieving system self-start by controlling the power supply. It solves the problem of inability to promptly cut off power in abnormal equipment conditions. The invention includes a power supply module, a CPU module, and a control module circuit electrically connected to each other. The power supply module supplies power to the CPU module, maintaining normal system operation. The CPU module monitors the system's operating status through an internal mechanism and manages the output of the PWR_RESET signal to the control module circuit. The control module circuit is controlled by the PWR_RESET signal output by the CPU module, providing protection for the CPU module. This invention enables system self-start by controlling the power supply when an abnormality is detected internally, even without interrupting power to the power adapter. Furthermore, it allows adjustment of the time interval between power outage and power restoration, protecting the equipment and extending its lifespan.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a circuit that enables a system to start automatically by controlling the power supply. Background Technology

[0002] Currently in the industry, when a system malfunctions, the common approach is to manually disconnect the power adapter (hardware reboot) or trigger a reboot command via software (soft reboot). If the power is manually disconnected, the device may remain in an abnormal state for an extended period due to a failure to detect the anomaly in time. If a software reboot command is triggered, the power is not disconnected, and the system immediately resumes operation after shutdown, without allowing sufficient recovery time. This can easily lead to a vicious cycle, affecting the normal operation and lifespan of the equipment. Summary of the Invention

[0003] The purpose of this invention is to provide a circuit that enables system self-starting by controlling the power supply. When a system abnormality is detected, such as software crash or chip overheating, this invention can achieve system self-starting. The system automatically triggers signals to achieve self-recovery, mainly by controlling the power supply chips of each circuit to automatically shut down the system, while the power adapter remains powered. After a certain period of power-off, the power supply chips automatically resume operation, and the output voltage of each chip returns to normal, allowing the system to function normally again. This invention can also adjust the time interval for system power-on by charging and discharging capacitors, allowing the system to automatically power on again after a period of power-off.

[0004] This invention provides a circuit for achieving system self-start by controlling the power supply, comprising a power supply module, a CPU module, and a control module circuit that are electrically connected to each other;

[0005] The power module is used to supply power to the CPU module and maintain normal system operation;

[0006] The CPU module monitors the system's operating status through an internal mechanism and manages the output of the PWR_RESET signal to the control module circuit.

[0007] The control module circuit is controlled by the PWR_RESET signal output by the CPU module;

[0008] When the CPU module outputs a low level, the thyristor is turned off, the second P-MOS transistor is turned off, the first P-MOS transistor is turned on, the circuit maintains normal operation, VIN continuously supplies power to DVCC, and the CPU system is in a powered-on state.

[0009] When the CPU module outputs a high level, the thyristor is turned on, the second P-MOS transistor is turned on, and the first P-MOS transistor is turned off. VIN still has voltage, but DVCC has no voltage input, and the CPU system is in a power-off state. At this time, the sixth and seventh energy storage capacitors begin to discharge. When the sixth and seventh energy storage capacitors discharge to a current of less than 5mA, the thyristor is turned off, and the control logic restores the power supply to DVCC. The system is then powered on again and begins the self-starting process.

[0010] The power module includes pins IN, EN, and VOUT1. Pin IN receives the input voltage from DVCC, pin EN is connected to the control module circuit through a ninth resistor, and pin VOUT1 outputs the voltage to power the CPU module.

[0011] The CPU module's IN1 pin is connected to the power module's VOUT1 pin, and the CPU module's PWR_RESET signal output is connected to the control module circuit after being divided by the fifth resistor.

[0012] The control module circuit includes a power adapter, a first P-MOS transistor, a second P-MOS transistor, a thyristor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth energy storage capacitor, a seventh energy storage capacitor, an eighth energy storage capacitor, a ninth capacitor, a tenth energy storage capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, and an eighth resistor. The power adapter is connected to VIN. VIN is divided by the first and second resistors and then connected to the gate of the first P-MOS transistor through the third resistor. The source of the first P-MOS transistor is connected to the power supply VIN, and the drain of the first P-MOS transistor is connected to the power supply DVCC. The power supply VIN is connected to the gate of the second P-MOS transistor through a resistor. The source of the second P-MOS transistor is connected to the power supply VIN, and the drain of the second P-MOS transistor is connected to the gate of the first P-MOS transistor through the third resistor. The CPU's PWR_RESET signal output is connected to the gate of the thyristor and pulled down to ground through a resistor. The cathode of the thyristor is connected to ground, and the anode of the thyristor is connected to the gate of the second P-MOS transistor through the eighth resistor. The first, second, and third capacitors are connected at one end to the line connecting VIN and the source of the first P-MOS transistor, and at the other end to the line connecting VIN after voltage division to the gate of the first P-MOS transistor. The fourth, fifth, and tenth energy storage capacitors are connected at one end to the line connecting the drain of the first P-MOS transistor to the power supply DVCC, and at the other end to ground. The sixth and seventh energy storage capacitors are connected at one end to the line connecting the anode of the thyristor to the eighth resistor, and at the other end to ground. There are two eighth energy storage capacitors, one end of which is grounded, and the other end is connected to the lines connecting the eighth resistor to the gate of the second P-MOS transistor and VIN to the source of the second P-MOS transistor, respectively. The ninth capacitor is grounded at one end, and the other end is connected to the line connecting the fifth resistor to the gate of the thyristor.

[0013] The first, second, third, fourth, fifth, and ninth capacitors are used for capacitor filtering, and the sixth, seventh, eighth, and tenth energy storage capacitors are used for capacitor energy storage. Among them, the sixth and seventh energy storage capacitors play a role in power-off delay.

[0014] The beneficial effects of the present invention are as follows: The present invention provides a circuit for achieving system self-start by controlling the power supply. This circuit can achieve system self-start by controlling the power supply when an abnormality is detected in the system, even when the power adapter is not interrupted. Furthermore, it can adjust the time interval between system power failure and power restoration, thereby protecting the equipment and improving its service life. Attached Figure Description

[0015] To further understand the features and technical content of this invention, please refer to the following detailed description and accompanying drawings. However, the drawings are for reference and illustration only and are not intended to limit the invention.

[0016] Figure 1 This is a schematic diagram of the overall circuit of the present invention;

[0017] Figure 2 This is a schematic diagram of the control module circuit of the present invention;

[0018] Figure 3 This is a flowchart of the present invention. Detailed Implementation

[0019] To further illustrate the technical means and effects of the present invention, the following detailed description is provided in conjunction with the preferred embodiments of the present invention and their accompanying drawings.

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] This invention consists of three parts: a power module, a CPU module, and a control module circuit.

[0022] Power module: This module consists of DC-DC converters. The input voltage IN of the DC-DC converter is provided by DVCC. The EN pin is connected to the anode of the thyristor Q3 through the ninth resistor R9. The output voltage VOUT1 of the DC-DC converter supplies power to the CPU module to maintain normal system operation.

[0023] CPU module: This module is powered by the voltage VOUT1 output from the DC-DC converter of the power supply module to provide the normal operating voltage of the system. The CPU module monitors the operating status of the system and manages the output of the PWR_RESET signal through an internal mechanism.

[0024] Control Module: This module is controlled by the PWR_RESET signal output by the CPU module. When the CPU outputs a low level, thyristor Q3 is off, the second P-MOS transistor Q2 is off, and the first P-MOS transistor Q1 is on, maintaining normal operation of the circuit, with VIN continuously supplying power to DVCC. When the CPU outputs a high level, thyristor Q3 is on, the second P-MOS transistor Q2 is on, and the first P-MOS transistor Q1 is off. VIN still has voltage, but DVCC has no voltage input and cannot continue to supply power to the CPU system.

[0025] In summary, the power module of the present invention is supplied with input voltage by power supply DVCC and output voltage to power the CPU system. The main principle is to control the output voltage of the power module by controlling the power supply of DVCC, thereby realizing the self-starting function of the system.

[0026] Please see Figure 1-3 This invention provides a circuit for achieving system self-start by controlling the power supply, comprising a power supply module, a CPU module, and a control module circuit that are electrically connected to each other;

[0027] The power module is used to supply power to the CPU module and maintain normal system operation;

[0028] The CPU module monitors the system's operating status through an internal mechanism and manages the output of the PWR_RESET signal to the control module circuit.

[0029] The control module circuit is controlled by the PWR_RESET signal output by the CPU module;

[0030] When the CPU module outputs a low level, thyristor Q3 is turned off, second P-MOS transistor Q2 is turned off, first P-MOS transistor Q1 is turned on, the circuit maintains normal operation, VIN continuously supplies power to DVCC, and the CPU system is in a powered-on state.

[0031] When the CPU module outputs a high level, thyristor Q3 is turned on, the second P-MOS transistor Q2 is turned on, and the first P-MOS transistor Q1 is turned off. VIN still has voltage, but DVCC has no voltage input, and the CPU system is in a power-off state. At this time, the sixth energy storage capacitor C6 and the seventh energy storage capacitor C7 begin to discharge. When the discharge current of the sixth energy storage capacitor C6 and the seventh energy storage capacitor C7 is less than 5mA (the holding current Ih of the thyristor), thyristor Q3 is turned off, and the control logic restores the power supply to DVCC. The system is then powered on again, and the self-starting process begins.

[0032] The power module includes pins IN, EN, and VOUT1. Pin IN receives the input voltage from DVCC, pin EN is connected to the control module circuit via resistor R9, and pin VOUT1 outputs the voltage to power the CPU module.

[0033] The CPU module's IN1 pin is connected to the power module's VOUT1 pin, and the CPU module's PWR_RESET signal output is connected to the control module circuit after being divided by the fifth resistor R5.

[0034] The control module circuit includes a power adapter, a first P-MOS transistor Q1, a second P-MOS transistor Q2, a thyristor Q3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth energy storage capacitor C6, a seventh energy storage capacitor C7, an eighth energy storage capacitor C8, a ninth capacitor C9, a tenth energy storage capacitor EC1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and an eighth resistor R8. The power adapter is connected to VIN. VIN is divided by the first resistor R1 and the second resistor R2, and then connected to the gate (G) of the first P-MOS transistor Q1 through the third resistor R3. The source (S) of S-MOSFET Q1 is connected to power supply VIN, and the drain (D) of the first P-MOS transistor Q1 is connected to power supply DVCC. Power supply VIN is connected to the gate (G) of the second P-MOS transistor Q2 through resistor R4. The source (S) of the second P-MOS transistor Q2 is connected to power supply VIN, and the drain (D) of the second P-MOS transistor Q2 is connected to the gate (G) of the first P-MOS transistor Q1 through a third resistor R3. The PWR_RESET signal output terminal of the CPU is connected to the gate (G) of thyristor Q3 and pulled down to ground through resistor R5. The cathode (K) of thyristor Q3 is connected to ground, and the anode (A) of thyristor Q3 is connected to the second P-MOS transistor Q1 through an eighth resistor R8. The gate (G) of P-MOS transistor Q2; wherein, one end of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are electrically connected to the line connecting VIN and the source of the first P-MOS transistor Q1, and the other end of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are electrically connected to the line connecting VIN after voltage division and the gate of the first P-MOS transistor Q1; one end of the fourth capacitor C4, the fifth capacitor C5, and the tenth energy storage capacitor EC1 are electrically connected to the line connecting the drain (D) of the first P-MOS transistor Q1 and the power supply DVCC, and the other end of the fourth capacitor C4, the fifth capacitor C5, and the tenth energy storage capacitor EC1 is grounded; the sixth energy storage capacitor... One end of the sixth energy storage capacitor C6 and the seventh energy storage capacitor C7 are electrically connected to the line connecting the anode (A) of the thyristor Q3 and the eighth resistor R8. The other end of the sixth energy storage capacitor C6 and the seventh energy storage capacitor C7 is grounded. There are two eighth energy storage capacitors C8. One end of the eighth energy storage capacitor C8 is grounded, and the other end of the eighth energy storage capacitor C8 is electrically connected to the line connecting the eighth resistor R8 to the gate (G) of the second P-MOS transistor Q2 and VIN to the source (S) of the second P-MOS transistor Q2, respectively. One end of the ninth capacitor C9 is grounded, and the other end of the ninth capacitor C9 is electrically connected to the line connecting the fifth resistor R5 to the gate (G) of the thyristor Q3.

[0035] The first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the ninth capacitor C9 are used for capacitive filtering. The sixth energy storage capacitor C6, the seventh energy storage capacitor C7, the eighth energy storage capacitor C8, and the tenth energy storage capacitor EC1 are used for capacitive energy storage. Among them, the sixth energy storage capacitor C6 and the seventh energy storage capacitor C7 play the role of power-off delay.

[0036] When the system is working normally, the CPU defaults to input a low level through PWR_RESET all the time, which does not meet the conduction condition of the thyristor Q3. The anode of the thyristor Q3 is pulled up to VIN. Q2Vgs>Q2Vth, and the second P-MOS transistor Q2 is cut off. The gate of the first P-MOS transistor Q1 is divided by the first resistor R1 and the second resistor R2. Q1Vgs<Q1Vth, and the first P-MOS transistor Q1 is turned on. VIN normally supplies power to DVCC.

[0037] When the system is abnormal, the CPU inputs a high level through PWR_RESET, providing a high level to the gate of the thyristor Q3. The anode of the thyristor Q3 is pulled up to a high level through the fourth resistor R4 and the eighth resistor R8, making the thyristor Q3 turn on, and the anode of the thyristor Q3 is pulled down to the ground. At this time, the gate of the second P-MOS transistor Q2 is at a low level. Q2Vgs<Q2Vth, and the second P-MOS transistor Q2 is turned on. The drain of the second P-MOS transistor Q2 is pulled up to VIN. At this time, the gate voltage of the first P-MOS transistor Q1 is VIN. Q1Vgs>Q1Vth, and the first P-MOS transistor Q1 is cut off. The power supply DVCC has no voltage output and cannot maintain the voltage for the DCDC to supply power to the CPU system, and the system is powered off.

[0038] The sixth energy storage capacitor C6 and the seventh energy storage capacitor C7 at the anode of the thyristor Q3 discharge, and the voltage difference between the anode and the cathode of the thyristor Q3 gradually decreases, making the thyristor Q3 cut off. The gate of the second P-MOS transistor Q2 is pulled up to VIN through the fourth resistor R4. Q2Vgs>Q2Vth, and the second P-MOS transistor Q2 is cut off. The gate of the first P-MOS transistor Q1 is divided by the first resistor R1 and the second resistor R2. Q1Vgs<Q1Vth, and the first P-MOS transistor Q1 is turned on. The DVCC power supply resumes power supply, and the system is normal and starts to start.

[0039] 1. Initialization stage:

[0040] After the system is powered on, initialization is first performed, and PWR_RESET is set to the default low level state to ensure that the power supply module, the CPU module, and the control module are all in normal working states.

[0041] 2. System normal working state monitoring:

[0042] The CPU module continuously monitors the system's operating status through an internal mechanism. If the system is working normally and there are no abnormalities, the CPU continuously outputs a low-level PWR_RESET signal.

[0043] 3. System abnormal state detection and handling:

[0044] When the CPU detects a system anomaly (such as software crash, chip overheating, etc.), it outputs a high-level PWR_RESET signal; after the control module receives the high-level PWR_RESET signal, it executes the system power-off and restart process.

[0045] 4. System power failure restart procedure:

[0046] When the control module detects that PWR_RESET is high, it first cuts off the power supply to DVCC through the control logic of thyristor Q3 and the first P-MOS transistor Q1 and the second P-MOS transistor Q2. After the power supply is cut off, the system enters a power-off state. At this time, the sixth energy storage capacitor C6 and the seventh energy storage capacitor C7 begin to discharge. When the energy storage capacitor discharges to a current less than 5mA (the holding current Ih of the thyristor), thyristor Q3 is turned off, and the control logic restores the power supply to DVCC. The system is then powered on again and begins the self-starting process.

[0047] 5. Automatic startup time adjustment:

[0048] By adjusting the capacity of the sixth energy storage capacitor C6 and the seventh energy storage capacitor C7, the time interval between a power outage and the system being powered on again can be controlled; this time interval can be adjusted according to actual needs to achieve a suitable self-starting time.

[0049] 6. Cyclic monitoring and restart:

[0050] After the system restarts, return to step 2 and continue monitoring the system's working status; if an anomaly occurs again, repeat steps 3 to 5.

[0051] The embodiments of the present invention described above do not constitute a limitation on the scope of protection of the present invention.

Claims

1. A circuit for achieving system self-starting by controlling the power supply, characterized in that, This includes power supply modules, CPU modules, and control module circuits that are electrically connected to each other; The power module is used to supply power to the CPU module and maintain normal system operation; The CPU module monitors the system's operating status through an internal mechanism and manages the output of the PWR_RESET signal to the control module circuit. The control module circuit is controlled by the PWR_RESET signal output by the CPU module; When the CPU module outputs a low level, the thyristor is turned off, the second P-MOS transistor is turned off, the first P-MOS transistor is turned on, the circuit maintains normal operation, VIN continuously supplies power to DVCC, and the CPU system is in a powered-on state. When the CPU module outputs a high level, the thyristor is turned on, the second P-MOS transistor is turned on, and the first P-MOS transistor is turned off. VIN still has voltage, but DVCC has no voltage input, and the CPU system is in a power-off state. At this time, the sixth and seventh energy storage capacitors begin to discharge. When the sixth and seventh energy storage capacitors discharge to a current of less than 5mA, the thyristor is turned off, and the control logic restores the power supply to DVCC. The system is then powered on again and begins the self-starting process.

2. The circuit for achieving system self-starting by controlling the power supply as described in claim 1, characterized in that, The power module includes pins IN, EN, and VOUT1. Pin IN receives the input voltage from DVCC, pin EN is connected to the control module circuit through a ninth resistor, and pin VOUT1 outputs the voltage to power the CPU module.

3. The circuit for achieving system self-starting by controlling the power supply as described in claim 2, characterized in that, The CPU module's IN1 pin is connected to the power module's VOUT1 pin, and the CPU module's PWR_RESET signal output is connected to the control module circuit after being divided by the fifth resistor.

4. The circuit for achieving system self-starting by controlling the power supply as described in claim 3, characterized in that, The control module circuit includes a power adapter, a first P-MOS transistor, a second P-MOS transistor, a thyristor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth energy storage capacitor, a seventh energy storage capacitor, an eighth energy storage capacitor, a ninth capacitor, a tenth energy storage capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, and an eighth resistor. The power adapter is connected to VIN. VIN is divided by the first and second resistors and then connected to the gate of the first P-MOS transistor through the third resistor. The source of the first P-MOS transistor is connected to the power supply VIN, and the drain of the first P-MOS transistor is connected to the power supply DVCC. The power supply VIN is connected to the gate of the second P-MOS transistor through a resistor. The source of the second P-MOS transistor is connected to the power supply VIN. The drain of the second P-MOS transistor is connected to the gate of the first P-MOS transistor through a third resistor. The CPU's PWR_RESET signal output is connected to the gate of the thyristor and pulled down to ground through a resistor. The cathode of the thyristor is connected to ground, and the anode of the thyristor is connected to the gate of the second P-MOS transistor through an eighth resistor. One end of the first, second, and third capacitors is electrically connected to the line connecting VIN and the source of the first P-MOS transistor, and the other end is electrically connected to the line connecting the voltage divided VIN to the gate of the first P-MOS transistor. The fourth capacitor, the second capacitor, the third capacitor, and the fourth capacitor are all connected to the first P-MOS transistor. One end of the fifth capacitor and the tenth energy storage capacitor are electrically connected to the line connecting the drain of the first P-MOS transistor to the power supply DVCC. The other ends of the fourth capacitor, the fifth capacitor, and the tenth energy storage capacitor are grounded. One end of the sixth energy storage capacitor and the seventh energy storage capacitor are electrically connected to the line connecting the anode of the thyristor to the eighth resistor. The other ends of the sixth energy storage capacitor and the seventh energy storage capacitor are grounded. There are two eighth energy storage capacitors. One end of the eighth energy storage capacitor is grounded, and the other end of the eighth energy storage capacitor is electrically connected to the line connecting the eighth resistor to the gate of the second P-MOS transistor and VIN to the source of the second P-MOS transistor, respectively. One end of the ninth capacitor is grounded, and the other end of the ninth capacitor is electrically connected to the line connecting the fifth resistor to the gate of the thyristor.

5. The circuit for achieving system self-starting by controlling the power supply as described in claim 4, characterized in that, The first, second, third, fourth, fifth, and ninth capacitors are used for capacitor filtering, and the sixth, seventh, eighth, and tenth energy storage capacitors are used for capacitor energy storage. Among them, the sixth and seventh energy storage capacitors play a role in power-off delay.

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