A method, device, equipment and storage medium for reporting flow table statistics information

Abstract

The present application discloses a flow table statistical information reporting method, device, equipment and storage medium, which relates to the field of flow table processing technology and is applied to field programmable logic gate arrays, including: after a message hits a target flow table, obtaining statistical information according to a hash value; judging whether a storage address is in a preset active table based on an active table mark bit, if so, processing the statistical information and writing the processed information back to an external memory; dividing the reporting cycle, judging the valid flag bit of the entry to be uploaded according to the current time interval, and reading the statistical information if the valid flag bit is 1; after obtaining all the statistical information within the current time interval, reporting the statistical information, determining the next time interval as the new current time interval, and continuing to judge the valid flag bit of the entry to be uploaded according to the current time interval until all the statistical information is reported to a central processing unit. This avoids the occurrence of sudden memory access behavior in statistical reporting.

Description

Technical Field

[0001] The present invention relates to the technical field of flow table processing, and in particular to a flow table statistical information reporting method, device, equipment and storage medium. Background Art

[0002] The network flow table is a key data structure inside the network device, which is used to store and manage the relevant information of the network data flow. This information includes some parameters describing the characteristics of the data packet, such as the source address and destination address of the data packet. The existence of the flow table enables the network device to forward and filter the data packet quickly and accurately based on the pre-set rules.

[0003] FPGA (Field Programmable Gate Array) has become an important means to realize high-speed flow table functions with its high performance, low power consumption and powerful parallel computing capabilities. How to realize the reporting of large-capacity flow table statistics under the condition of high-speed flow table processing has become one of the technical problems that need to be solved. In the current existing FPGA method of realizing flow table hit reporting of more than one million levels, the FPGA logic detects that a message hits the flow table and immediately reports the statistical information to the CPU (Central Processing Unit). Although this does not consume additional storage resources, when a large amount of statistical information hitting the same flow is sent to the CPU, it is easy to cause insufficient memory and transmission bandwidth due to burst memory access, resulting in the loss of statistical data and the decline of CPU processing performance. When it is outside the reporting cycle, the FPGA records the statistical information in the external memory (DDR (Double Data Rate, double-rate synchronous dynamic random access memory), QDR (Quad Data Rate, quadruple data rate static random access memory), RLDRAM (Reduced Latency Dynamic Random Access Memory), etc.), and once a message hit is detected, the statistical information of the corresponding flow in the external storage is updated. When it is within the reporting cycle, because the FPGA does not know which entries in the flow table in the external memory have statistical information to be reported to the CPU, it needs to scan the entire external memory, causing great memory access pressure and consuming memory bandwidth. Therefore, how to solve the problem of burst reporting of large-capacity flow tables is currently a matter of consideration. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a method, device, equipment and storage medium for reporting flow table statistics, which can effectively avoid burst memory access and solve the problem of burst reporting of large-capacity flow tables. The specific scheme is as follows:

[0005] In a first aspect, the present application discloses a method for reporting flow table statistics information, which is applied to a field programmable gate array, comprising:

[0006] After a message input into the field programmable logic gate array hits a target flow table, a hash value is calculated according to feature information of the message, and statistical information of the target flow table in an external memory is obtained based on the hash value;

[0007] Based on the active table flag bit in the statistical information, determine whether the storage address of the statistical information is in the preset active table, and if so, directly process the statistical information accordingly, and write the processed information back to the external memory;

[0008] The reporting cycle is divided according to the number of rows of the preset active table within the reporting cycle to obtain a plurality of time intervals, and the valid flag bits of the entries to be uploaded in the preset active table are judged in turn according to the current time interval, and if the valid flag bit is 1, the statistical information in the external memory is read using the storage address in the entry to be uploaded;

[0009] After obtaining all the statistical information within the current time interval, the statistical information is reported to the central processing unit through the target interface, and the next time interval among the several time intervals is determined as the new current time interval, and then the process jumps again to the step of judging the valid flag bits of the entries to be uploaded in the preset active table in turn according to the current time interval, until all the statistical information corresponding to the reporting period is reported to the central processing unit.

[0010] Optionally, the characteristic information includes quintuple information and a media access control address; the quintuple information includes the source IP, destination IP, protocol, source port number and destination port number of the message; the statistical information includes the number of messages, the number of message bytes and the active table flag bit.

[0011] Optionally, the determining, based on an active table flag bit in the statistical information, whether the storage address of the statistical information is in a preset active table includes:

[0012] If the active table flag bit in the statistical information is 0, it is determined that the storage address of the statistical information is not in the preset active table;

[0013] If the active table flag bit in the statistical information is 1, it is determined that the storage address of the statistical information is in the preset active table.

[0014] Optionally, after determining whether the storage address of the statistical information is in a preset active table based on the active table flag bit in the statistical information, the method further includes:

[0015] If the storage address of the statistical information is not in the preset active table, the storage address is added to the preset active table, and the number of messages and the number of message bytes in the statistical information are processed, and the corresponding processed information is written back to the external memory.

[0016] Optionally, directly processing the statistical information accordingly and writing the processed information back to the external memory includes:

[0017] The number of messages and the number of message bytes in the statistical information are processed, and the corresponding processed information is written back to the external memory.

[0018] Optionally, after sequentially judging the valid flag bits of the to-be-uploaded entries in the preset active table according to the current time interval, the method further includes:

[0019] If the valid flag is 0, the corresponding entry to be uploaded is determined to be invalid, no report is made, and the valid flag of the next entry to be uploaded in the current time interval is determined.

[0020] Optionally, after reading the statistical information in the external memory using the storage address in the entry to be uploaded, the method further includes:

[0021] Determine that the target statistical information has been read, clear the target statistical information in the external memory, and set the valid flag position of the to-be-uploaded entry corresponding to the target statistical information to 0.

[0022] In a second aspect, the present application discloses a flow table statistical information reporting device, which is applied to a field programmable logic gate array, including:

[0023] A statistical information acquisition module, configured to calculate a hash value according to characteristic information of a message input into the field programmable logic gate array after the message hits a target flow table, and to acquire statistical information of the target flow table in an external memory based on the hash value;

[0024] A processed information write-back module is used to determine whether the storage address of the statistical information is in a preset active table based on the active table flag bit in the statistical information, and if so, directly process the statistical information accordingly and write the corresponding processed information back to the external memory;

[0025] A statistical information reading module, used to divide the reporting cycle according to the number of rows in the preset active table within the reporting cycle to obtain a plurality of time intervals, and to judge the valid flag bits of the entries to be uploaded in the preset active table in turn according to the current time interval, and if the valid flag bit is 1, read the statistical information in the external memory using the storage address in the entry to be uploaded;

[0026] A statistical information reporting module is used to report the statistical information to the central processing unit through a target interface after acquiring all the statistical information within the current time interval, and determine the next time interval among the several time intervals as the new current time interval, and then jump again to the step of judging the valid flag bits of the entries to be uploaded in the preset active table in turn according to the current time interval, until all the statistical information corresponding to the reporting period is reported to the central processing unit.

[0027] In a third aspect, the present application discloses an electronic device, comprising:

[0028] Memory, used to store computer programs;

[0029] The processor is used to execute the computer program to implement the aforementioned method for reporting flow table statistical information.

[0030] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the aforementioned method for reporting flow table statistical information.

[0031] When reporting flow table statistics, the present application first calculates a hash value according to the characteristic information of the message after the message input into the field programmable logic gate array hits the target flow table, and obtains the statistical information of the target flow table in the external memory based on the hash value; then, based on the active table mark bit in the statistical information, it is determined whether the storage address of the statistical information is in the preset active table. If so, the statistical information is directly processed accordingly, and the corresponding processed information is written back to the external memory; then, the reporting cycle is divided according to the number of rows in the preset active table within the reporting cycle to obtain several time intervals, and the time intervals are calculated according to the current time. The valid flag bits of the entries to be uploaded in the preset active table are judged in turn at intervals. If the valid flag bit is 1, the statistical information in the external memory is read using the storage address in the entry to be uploaded; finally, after obtaining all the statistical information in the current time interval, the statistical information is reported to the central processing unit through the target interface, and the next time interval in the several time intervals is determined as the new current time interval, and then the step of judging the valid flag bits of the entries to be uploaded in the preset active table in turn according to the current time interval is jumped again until all the statistical information corresponding to the reporting cycle is reported to the central processing unit. It can be seen that the present application uses an external memory to store the hit statistical information that needs to be reported to the CPU. When within the statistical reporting cycle, the FPGA reads the hit statistical information from the external memory according to the active entry information in the internally stored active table, and reports the statistical information through the FPGA and CPU communication interface. At the same time, the hit statistical reporting behavior is dispersed into multiple shorter time intervals, and the memory access behavior of the smooth statistical reporting logic can effectively avoid sudden memory access. During the reporting period, only the statistical information corresponding to the addresses stored in the active table is reported, and other flow statistical information is still stored in the external memory, which effectively solves the problem of sudden reporting of large-capacity flow tables. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0033] Figure 1 A flow chart of a method for reporting flow table statistics information disclosed in this application;

[0034] Figure 2 A schematic diagram of a statistical information format in an external memory disclosed in the present application;

[0035] Figure 3 A schematic diagram of an active table structure disclosed in this application;

[0036] FIG. 4 (a) is a schematic diagram of an active table structure disclosed in the present application; FIG. 4 (b) is a schematic diagram of an active table structure disclosed in the present application;

[0037] Figure 5 A schematic diagram of a specific method for reporting flow table statistics information disclosed in this application;

[0038] Figure 6 A schematic diagram of the structure of a flow table statistical information reporting device disclosed in this application;

[0039] Figure 7 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] In the current existing FPGA method for reporting flow table hits above a million levels, the FPGA logic detects that a message hits the flow table and immediately reports the statistical information to the CPU. Although this does not consume additional storage resources, when a large amount of statistical information that hits the same flow is sent to the CPU, it is easy to cause insufficient memory and transmission bandwidth due to burst memory access, resulting in the loss of statistical data and a decrease in CPU processing performance. When it is outside the reporting cycle, the FPGA records the statistical information in an external memory (DDR, QDR, RLDRAM, etc.), and once a message hit is detected, the statistical information of the corresponding flow in the external storage is updated. When it is within the reporting cycle, since the FPGA does not know which entries in the flow table in the external memory have statistical information that needs to be reported to the CPU, it is necessary to scan the entire external memory, causing great memory access pressure and consuming memory bandwidth. In order to solve the above technical problems, the present application discloses a flow table statistical information reporting method, device, equipment and storage medium, which can effectively avoid burst memory access and solve the problem of burst reporting of large-capacity flow tables.

[0042] See also Figure 1 As shown, an embodiment of the present invention discloses a method for reporting flow table statistics information, which is applied to a field programmable logic gate array, including:

[0043] Step S11: after a message input into the field programmable gate array hits a target flow table, a hash value is calculated according to feature information of the message, and statistical information of the target flow table in an external memory is obtained based on the hash value.

[0044] In this embodiment, when the message input into the FPGA hits the flow table, a hash value (CRC32 (Cyclic Redundancy Check) value) is calculated based on the characteristic information of the message. The characteristic information here includes five-tuple information and media access control address. The five-tuple information includes the source IP (Internet Protocol), destination IP, protocol, source port number and destination port number of the message. At the same time, the algorithm for calculating the hash value can be a crc32 (Cyclic Redundancy Check) algorithm or an xor (exclusive OR). The hash value is then used as the query address of the external memory to obtain the statistical information of the flow table. Figure 2 As shown, the statistical information in the external memory includes the number of messages, the number of message bytes and the active table flag. The external memory is used to store the hit statistics that need to be reported to the CPU. At the same time, it should be specially explained that the application method of the present application is applied to FPGA, which is only one of the implementation methods of reporting flow table statistics. The flow table statistics reporting method of the present application can also be applied to other hardware, such as ASIC (Application Specific Integrated Circuit), and the operation of the flow table statistics reporting method in the present application can also be performed. That is to say, the operation of reporting flow table statistics according to the method of the present application in ASIC or other implementable hardware also falls within the scope of protection of the present application.

[0045] Step S12: determine whether the storage address of the statistical information is in a preset active table based on the active table flag in the statistical information; if so, directly process the statistical information accordingly and write the processed information back to the external memory.

[0046] In this embodiment, Figure 3The active table structure (the maximum row value is m, the maximum column value is n) stored inside the FPGA and the format of the entries stored in the active table are shown. First, the active table flag bit in the acquired statistical information is judged. If the active table flag bit in the statistical information is 0, it is determined that the storage address of the statistical information is not in the preset active table; if the active table flag bit in the statistical information is 1, it is determined that the storage address of the statistical information is in the preset active table. In this way, it is determined whether the storage address of the statistical information is in the preset active table. If the storage address of the statistical information is not in the preset active table, that is, the active table flag bit is 0, the storage address is added to the preset active table, and the number of messages and the number of message bytes in the statistical information are processed, and the corresponding processed information is written back to the external memory. It should be noted that the processing of the number of messages and the number of message bytes here refers to the number of messages plus the number of messages currently hit, and the number of message bytes plus the number of messages currently hit. Until the number of valid entries in the row is n, the subsequent ones are not added to the active table.

[0047] As shown in Figure 4 (a) and Figure 4 (b); if the active table mark value is 1, it means that the corresponding statistical information storage address has been marked in the active table. At this time, it is only necessary to process the number of messages and the number of message bytes in the hit statistical information accordingly, that is, the number of messages plus the number of currently hit messages, and the number of message bytes plus the number of currently hit message bytes. Such processing operations are finally written back to the external memory.

[0048] Step S13: within the reporting cycle, the reporting cycle is divided according to the number of rows in the preset active table to obtain a number of time intervals, and the valid flag bits of the entries to be uploaded in the preset active table are judged in turn according to the current time interval; if the valid flag bit is 1, the statistical information in the external memory is read using the storage address in the entry to be uploaded.

[0049] In this embodiment, when within the reporting cycle, the reporting cycle is divided according to the number of rows in the preset active table (for example, divided into m intervals corresponding to the number of rows in the active table). In such a reporting cycle, each statistical information storage address is recorded at most once in the active table, which can greatly reduce the number of memory accesses in a single-stream scenario. Among them, the size of the active table is determined according to the storage resources inside the FPGA.

[0050] After dividing the reporting cycle and obtaining several time intervals, n entries in the active table row corresponding to the reporting pointer need to be reported within a single reporting time interval. The specific process is as follows: If the valid flag bit in the entry is 0, the entry is invalid and does not need to be reported, and the next entry is judged; if the valid flag bit in the entry is 1, the statistical information address in the entry is used as an index to query the statistical information in the external memory, and the next entry is judged until the nth entry. That is, it is known that all valid flag bits in the current active table row have been judged, and all statistical information in the external memory has been read using the storage address in the entry to be uploaded.

[0051] Step S14: After obtaining all the statistical information within the current time interval, the statistical information is reported to the central processing unit through the target interface, and the next time interval among the several time intervals is determined as the new current time interval, and then the process jumps again to the step of judging the valid flag bits of the entries to be uploaded in the preset active table in turn according to the current time interval, until all the statistical information corresponding to the reporting period is reported to the central processing unit.

[0052] After obtaining all the statistical information within a single time interval, the FPGA will send the statistical information read from the external memory to the CPU through the interface interconnected with the CPU. Among them, the physical properties of the interface can be an Ethernet interface, a PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) interface, etc. That is, the statistical information is uploaded in units of a single time interval. At the same time, the position of the reporting pointer has jumped down to the next row, and the statistical pointer has also jumped down to the next row. That is, it jumps back to the step of judging the valid flag bits of the entries to be uploaded in the preset active table in sequence according to the current time interval, and continues to judge the n entries in the active table row corresponding to the reporting pointer in the next time interval until all the statistical information corresponding to the reporting cycle is reported to the central processing unit. In this way, although at most m times n statistical information will be reported to the CPU in a reporting cycle, other flow statistical information still exists in the external memory, and when it is marked in the active table in the next reporting cycle, it will still be reported, which solves the problem of burst reporting of large-capacity flow tables very well. It should be noted that after reading the flow statistics in the external memory, the flow statistics in the external memory are written back and cleared, and the mark bit of the corresponding entry in the active table also needs to be set to 0. This means that the statistics of the flow table have been reported, and new statistics can be added again.

[0053] In summary, when reporting flow table statistical information, the present application first calculates a hash value based on the characteristic information of the message after the message input into the field programmable logic gate array hits the target flow table, and obtains the statistical information of the target flow table in the external memory based on the hash value; then, based on the active table mark bit in the statistical information, it is determined whether the storage address of the statistical information is in the preset active table. If so, the statistical information is directly processed accordingly, and the corresponding processed information is written back to the external memory; then, within the reporting cycle, the reporting cycle is divided according to the number of rows in the preset active table to obtain several time intervals, and according to the current The valid flag bits of the entries to be uploaded in the preset active table are judged in turn according to the time interval. If the valid flag bit is 1, the statistical information in the external memory is read using the storage address in the entry to be uploaded; finally, after obtaining all the statistical information in the current time interval, the statistical information is reported to the central processing unit through the target interface, and the next time interval in the several time intervals is determined as the new current time interval, and then the step of judging the valid flag bits of the entries to be uploaded in the preset active table according to the current time interval is jumped again until all the statistical information corresponding to the reporting cycle is reported to the central processing unit. It can be seen that the present application uses an external memory to store the hit statistical information that needs to be reported to the CPU. When within the statistical reporting cycle, the FPGA reads the hit statistical information from the external memory according to the active entry information in the internally stored active table, and reports the statistical information through the FPGA and CPU communication interface. At the same time, the hit statistical reporting behavior is dispersed into multiple shorter time intervals, and the memory access behavior of the smooth statistical reporting logic can effectively avoid sudden memory access. During the reporting period, only the statistical information corresponding to the addresses stored in the active table is reported, and other flow statistical information is still stored in the external memory, which effectively solves the problem of sudden reporting of large-capacity flow tables.

[0054] Based on the above embodiment, the present application discloses a flow table statistical information reporting method, which can disperse the statistical reporting behavior into multiple shorter time intervals, and can effectively avoid sudden memory access by smoothing the memory access behavior of the statistical reporting logic. Next, the specific flow table statistical information reporting process will be described.

[0055] like Figure 5As shown, first, outside the reporting cycle, when the message input to the FPGA hits the flow table, the CRC32 value is calculated according to the five-tuple of the message (source IP, destination IP, protocol, source port number, destination port number), and the CRC32 value is used as the query address of the external memory to obtain the statistical information of the flow table. The statistical information includes the number of messages, the number of message bytes, and the active table mark. Then the read statistical information value is judged: if the active table mark is 0, it means that the corresponding statistical information storage address is not in the active table, and it needs to be added to the active table. At the same time, the hit statistical information value is processed accordingly and written back to the external memory. Until the number of valid entries in the row is n, the subsequent ones are not added to the active table. If the active table mark is 1, it means that the corresponding statistical information storage address has been marked in the active table. At this time, it is only necessary to process the number of messages and the number of message bytes in the hit statistical information accordingly and write them back to the external memory.

[0056] When in the reporting cycle, the reporting cycle is divided into several small time intervals according to the number of rows in the active table (for example, if the number of rows in the active table is m, it is divided into m intervals). In such a reporting cycle, each statistical information storage address is recorded at most once in the active table. In a single reporting time interval, n entries in the active table row corresponding to the reporting pointer need to be reported. The specific process is as follows: If the valid flag bit in the entry is 0, the entry is invalid and does not need to be reported, and the next entry is judged; if the valid flag bit in the entry is 1, the statistical information address in the entry is used as an index to query the statistical information in the external memory, and the next entry is judged until the nth entry. That is to say, it is known that all the valid flag bits in the current active table row have been judged, and all the statistical information in the external memory has been read using the storage address in the entry to be uploaded.

[0057] After obtaining all the statistical information within a single time interval, the FPGA will send the statistical information read from the external memory to the CPU through the interface interconnected with the CPU. Among them, the physical properties of the interface can be an Ethernet interface, a PCIE interface, etc. That is, the statistical information is uploaded in units of a single time interval. At the same time, the position of the reporting pointer has jumped down to the next row, and the statistical pointer has also jumped down to the next row. That is, it jumps back to the step of judging the valid flag bits of the entries to be uploaded in the preset active table in sequence according to the current time interval, and continues to judge the n entries in the active table row corresponding to the reporting pointer in the next time interval until all the statistical information corresponding to the reporting cycle is reported to the central processor. In this process, after reading the flow statistical information in the external memory, the flow statistical information in the external memory is written back and cleared, and the mark bit of the corresponding entry in the active table also needs to be set to 0. It means that the statistical information of the flow table has been reported, and new statistical information can be added again. So far, by dispersing the hit statistical reporting behavior into multiple shorter time intervals, the memory access behavior through the smooth statistical reporting logic is completed, which can effectively avoid sudden memory access.

[0058] It can be seen that in this application, during the statistical reporting cycle, the FPGA reads the hit statistical information from the external memory according to the active entry information in the internally stored active table, and sends it through the FPGA and CPU communication interface. And the hit statistical reporting behavior is dispersed into multiple shorter time intervals, and the memory access behavior of the smooth statistical reporting logic can effectively avoid sudden memory access; at the same time, the reported statistical information of a single flow will only be marked once in a reporting cycle, which can greatly reduce the number of memory accesses in a single-flow scenario; although at most only m times n statistical information will be reported to the CPU in a reporting cycle, other flow statistical information still exists in the external memory, but when it is marked in the active table in the next reporting cycle, it will still be reported, which solves the problem of sudden reporting of large-capacity flow tables very well.

[0059] See also Figure 6 As shown, an embodiment of the present invention discloses a flow table statistical information reporting device, which is applied to a field programmable logic gate array, including:

[0060] A statistical information acquisition module 11 is used to calculate a hash value according to characteristic information of a message input into the field programmable logic gate array after the message hits the target flow table, and obtain statistical information of the target flow table in an external memory based on the hash value;

[0061] A processed information writing back module 12 is used to determine whether the storage address of the statistical information is in a preset active table based on the active table flag bit in the statistical information, and if so, directly process the statistical information accordingly and write the corresponding processed information back to the external memory;

[0062] The statistical information reading module 13 is used to divide the reporting cycle according to the number of rows in the preset active table within the reporting cycle to obtain a plurality of time intervals, and to judge the valid flag bits of the items to be uploaded in the preset active table in turn according to the current time interval, and if the valid flag bit is 1, read the statistical information in the external memory using the storage address in the item to be uploaded;

[0063] The statistical information reporting module 14 is used to report the statistical information to the central processing unit through the target interface after obtaining all the statistical information within the current time interval, and determine the next time interval among the several time intervals as the new current time interval, and then jump again to the step of judging the valid flag bits of the entries to be uploaded in the preset active table in turn according to the current time interval, until all the statistical information corresponding to the reporting period is reported to the central processing unit.

[0064] It can be seen that the present application uses an external memory to store hit statistics that need to be reported to the CPU. When within the statistical reporting cycle, the FPGA reads the hit statistics from the external memory based on the active entry information in the internally stored active table, and reports the statistics through the FPGA and CPU communication interface. At the same time, the hit statistics reporting behavior is dispersed into multiple shorter time intervals, and the memory access behavior of the smooth statistical reporting logic can be effectively avoided by burst memory access. During the reporting cycle, only the statistical information corresponding to the address stored in the active table is reported, and other flow statistics still exist in the external memory, which solves the problem of burst reporting of large-capacity flow tables.

[0065] In some specific embodiments, the processed information writing back module 12 may specifically include:

[0066] A first determination unit, configured to determine that the storage address of the statistical information is not in the preset active table if the active table flag bit in the statistical information is 0;

[0067] The second determination unit is configured to determine, if the active table flag bit in the statistical information is 1, that the storage address of the statistical information is in the preset active table.

[0068] In some specific embodiments, the device may further include:

[0069] A storage address adding module is used to add the storage address to the preset active table if the storage address of the statistical information is not in the preset active table, and process the number of messages and the number of message bytes in the statistical information, and write the corresponding processed information back to the external memory.

[0070] In some specific embodiments, the processed information writing back module 12 may specifically include:

[0071] The processed information writing back unit is used to process the number of messages and the number of message bytes in the statistical information, and write the corresponding processed information back to the external memory.

[0072] In some specific embodiments, the device may further include:

[0073] The invalidity determination module is used to determine that the corresponding entry to be uploaded is invalid if the valid flag is 0, and not report it, and to determine the valid flag of the next entry to be uploaded in the current time interval.

[0074] In some specific embodiments, the device may further include:

[0075] The target statistical information clearing module is used to determine that the target statistical information has been read, clear the target statistical information in the external memory, and set the valid flag position of the to-be-uploaded item corresponding to the target statistical information to 0.

[0076] Furthermore, the present application also discloses an electronic device. Figure 7 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0077] Figure 7 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the method for reporting flow table statistics disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0078] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0079] In addition, the memory 22 as a carrier for resource storage may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage method may be temporary storage or permanent storage.

[0080] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device 20, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the flow table statistical information reporting method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0081] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned disclosed method for reporting flow table statistics is implemented. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, and no further description will be given here.

[0082] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0083] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0084] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0085] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0086] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for reporting flow table statistics, characterized in that: Applications in field programmable gate arrays include: After a message input into the field programmable logic gate array hits a target flow table, a hash value is calculated according to feature information of the message, and statistical information of the target flow table in an external memory is obtained based on the hash value; Based on the active table flag bit in the statistical information, determine whether the storage address of the statistical information is in the preset active table, and if so, directly process the statistical information accordingly, and write the processed information back to the external memory; The reporting cycle is divided according to the number of rows of the preset active table within the reporting cycle to obtain a plurality of time intervals, and the valid flag bits of the entries to be uploaded in the preset active table are judged in turn according to the current time interval, and if the valid flag bit is 1, the statistical information in the external memory is read using the storage address in the entry to be uploaded; After obtaining all the statistical information within the current time interval, the statistical information is reported to the central processing unit through the target interface, and the next time interval among the several time intervals is determined as the new current time interval, and then the process jumps again to the step of judging the valid flag bits of the entries to be uploaded in the preset active table in turn according to the current time interval, until all the statistical information corresponding to the reporting period is reported to the central processing unit.

2. The method for reporting flow table statistics according to claim 1, characterized in that: The characteristic information includes five-tuple information and a media access control address; the five-tuple information includes the source IP, destination IP, protocol, source port number and destination port number of the message; the statistical information includes the number of messages, the number of message bytes and the active table flag bit.

3. The method for reporting flow table statistics according to claim 1, characterized in that: The determining, based on the active table flag bit in the statistical information, whether the storage address of the statistical information is in a preset active table includes: If the active table flag bit in the statistical information is 0, it is determined that the storage address of the statistical information is not in the preset active table; If the active table flag bit in the statistical information is 1, it is determined that the storage address of the statistical information is in the preset active table.

4. The method for reporting flow table statistics according to claim 3, characterized in that: After determining whether the storage address of the statistical information is in a preset active table based on the active table flag bit in the statistical information, the method further includes: If the storage address of the statistical information is not in the preset active table, the storage address is added to the preset active table, and the number of messages and the number of message bytes in the statistical information are processed, and the corresponding processed information is written back to the external memory; the processing is to add the number of messages to the number of currently hit messages and to add the number of message bytes to the number of currently hit message bytes.

5. The method for reporting flow table statistics according to claim 1, characterized in that: Directly processing the statistical information accordingly and writing the processed information back to the external memory includes: The number of messages and the number of message bytes in the statistical information are processed, and the corresponding processed information is written back to the external memory; the processing is to add the number of messages to the number of currently hit messages and to add the number of message bytes to the number of currently hit message bytes.

6. The method for reporting flow table statistics according to claim 1, characterized in that: After sequentially judging the valid flag bits of the entries to be uploaded in the preset active table according to the current time interval, the method further includes: If the valid flag is 0, the corresponding entry to be uploaded is determined to be invalid, no report is made, and the valid flag of the next entry to be uploaded in the current time interval is determined.

7. The method for reporting flow table statistics according to any one of claims 1 to 6, characterized in that: After reading the statistical information in the external memory using the storage address in the entry to be uploaded, the method further includes: Determine that the target statistical information has been read, clear the target statistical information in the external memory, and set the valid flag position of the to-be-uploaded entry corresponding to the target statistical information to 0.

8. A flow table statistical information reporting device, characterized in that: Applications in field programmable gate arrays include: A statistical information acquisition module, configured to calculate a hash value according to characteristic information of a message input into the field programmable logic gate array after the message hits a target flow table, and to acquire statistical information of the target flow table in an external memory based on the hash value; A processed information write-back module is used to determine whether the storage address of the statistical information is in a preset active table based on the active table flag bit in the statistical information, and if so, directly process the statistical information accordingly and write the corresponding processed information back to the external memory; A statistical information reading module, used to divide the reporting cycle according to the number of rows in the preset active table within the reporting cycle to obtain a plurality of time intervals, and to judge the valid flag bits of the entries to be uploaded in the preset active table in turn according to the current time interval, and if the valid flag bit is 1, read the statistical information in the external memory using the storage address in the entry to be uploaded; A statistical information reporting module is used to report the statistical information to the central processing unit through a target interface after acquiring all the statistical information within the current time interval, and determine the next time interval among the several time intervals as the new current time interval, and then jump again to the step of judging the valid flag bits of the entries to be uploaded in the preset active table in turn according to the current time interval, until all the statistical information corresponding to the reporting period is reported to the central processing unit.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the method for reporting flow table statistical information as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store a computer program, wherein when the computer program is executed by a processor, the method for reporting flow table statistical information according to any one of claims 1 to 7 is implemented.

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