A baseband prototype verification numerical analysis method and readable storage medium

Abstract

The present application relates to the field of digital signal processing operation and baseband prototype verification and simulation, and in particular to a baseband prototype verification numerical analysis method and a readable storage medium, which generates a prototype verification project by running on a prototype verification platform, and performs business tests, by inputting the output data of the previous level target operation circuit into the current level target operation circuit, and adding the current level numerical monitoring and analysis unit to the current level target operation circuit, monitoring and analyzing the current level target operation circuit and the previous level numerical monitoring and analysis unit. This method can quickly determine the level position of the target operation circuit with problems when an abnormality occurs in the business test of the prototype verification project.

Description

Technical Field

[0001] The present application relates to the field of digital signal processing operations and baseband prototype verification and simulation, and in particular to a baseband prototype verification numerical analysis method and a readable storage medium. Background Art

[0002] ASIC (Application Specific Integrated Circuit) is an integrated circuit designed for specific application requirements, with the characteristics of high performance and high efficiency. It usually contains components such as microprocessors and memories. According to the degree of customization, ASIC chips can be divided into two types: fully customized and semi-customized. ASIC design is a design method for integrated circuits customized for specific application requirements. Its design process is complex and involves multiple stages. The ASIC design process includes multiple stages such as specification and requirement definition, architecture and high-level design, logic design, and physical design. Each stage has its own specific challenges and considerations, such as performance, power consumption, and cost. The specific process includes steps such as RTL-level code design, simulation testing, logic synthesis, and physical layout. At present, for large-scale and complex ASIC designs, the mainstream and mature method for developers to verify the effectiveness of the design is to conduct board verification through the FPGA prototype verification platform. Large-scale ASIC design is generally divided into several operable sub-modules according to hierarchical and structured methods, and each sub-module is instantiated and connected in the top-level module. Large-scale ASIC design can be divided into N smaller sub-operation circuit structures according to function for cascade implementation. The data flow feature is that the output of the previous sub-operation circuit is the input of the next sub-operation circuit.

[0003] When the numerical calculation accuracy of large-scale ASIC is insufficient and BUGs recur (such as sudden bit errors in the signal tracking stage, etc.),

[0004] 1) If the prototype verification simulation platform uses the same top-level stimulus as the on-board verification to simulate from the initial state until the abnormal state is reproduced, the simulation may take hours, days, or even weeks due to the slow simulation speed;

[0005] 2) If the board is verified, it is difficult to capture the signal by adding an online logic analyzer (ILA) or using an external logic analyzer in the FPGA prototype verification project because it is uncertain which link of the digital signal operation circuit at each level has a problem.

[0006] In this regard, in order to solve the problem of rapid reproduction and location solution in prototype verification, this application is specially proposed. Summary of the invention

[0007] In order to solve one or several problems in the prior art, especially the problems of numerical anomalies and reliability detection in the existing baseband prototype verification, a baseband prototype verification numerical analysis method and a readable storage medium are provided, which are easy to implement and can quickly and accurately identify the unit where the numerical calculation problem is located.

[0008] In order to achieve the above application objectives, this application proposes a baseband prototype verification numerical analysis method, including:

[0009] S1: Run the prototype verification project on the prototype verification platform and perform business tests;

[0010] S2: the first-level target operation circuit outputs data, and a first-level numerical value monitoring and analysis unit is added to the first-level target operation circuit;

[0011] S3: inputting the output data of the first-level target operation circuit into the second-level target operation circuit, and adding a second-level numerical value monitoring and analysis unit in the second-level target operation circuit to monitor and analyze the second-level target operation circuit and the first-level numerical value monitoring and analysis unit,

[0012] S4: repeating step S3 until the output data of the N-1th target operation circuit is input into the Nth target operation circuit, and an Nth level numerical value monitoring and analysis unit is added to the Nth level target operation circuit to monitor and analyze the Nth level target operation circuit and the N-1th level numerical value monitoring and analysis unit, wherein N is the cascade number of the target operation circuit for digital signal processing, and N is a natural number ≥ 3;

[0013] S5: When an abnormal state occurs in the service test, the abnormal detection results of the state latch subunits of the first to N-level numerical monitoring and analysis units are read through the serial port or bus to quickly confirm the level of the target operation circuit with the problem.

[0014] In order to achieve the above application purpose, the present application also proposes another baseband prototype verification numerical analysis method, which is characterized in that the input data of the Nth level target operation circuit is the mixed input of the first to N-1th level target operation circuits, including:

[0015] S1: Run the prototype verification project on the prototype verification platform and perform business tests;

[0016] S2: the first-level target operation circuit outputs data, and a first-level numerical value monitoring and analysis unit is added to the first-level target operation circuit;

[0017] S3: inputting the output data of the first-level target operation circuit into the second-level target operation circuit, and adding a second-level numerical value monitoring and analysis unit in the second-level target operation circuit to monitor and analyze the second-level target operation circuit and the first-level numerical value monitoring and analysis unit;

[0018] S4: repeating step S3 until the output data of the N-2 target operation circuit is input into the N-1 target operation circuit, and an N-1 numerical value monitoring and analysis unit is added to the N-1 target operation circuit to monitor and analyze the N-1 target operation circuit and the N-2 numerical value monitoring and analysis unit, wherein N is the cascade number of the digital signal processing target operation circuit, and N is a natural number ≥ 3;

[0019] S5: Mixing and inputting all output data of the first to N-1 level target operation circuits into the N-th level target operation circuit, and adding an N-th level numerical value monitoring and analysis unit in the N-th level target operation circuit to monitor and analyze the N-th level target operation circuit and the N-1-th level numerical value monitoring and analysis unit;

[0020] S6: When an abnormal state occurs, the abnormal detection results of the state latch subunits of the first to N-level numerical monitoring and analysis units are read through the serial port or bus to quickly determine the level of the target operation circuit with the problem.

[0021] Based on the above method, when an abnormality occurs in the business test of the prototype verification project, the state latch results of each numerical monitoring and analysis unit can be read through the serial port or bus to quickly determine the problematic operation circuit.

[0022] Furthermore, the monitoring and analysis content of each of the first to N-level numerical monitoring and analysis units is determined by the target operation circuit of this level and the numerical monitoring and analysis unit of the previous level, and the first to N-level numerical monitoring and analysis units operate independently or are interconnected to exchange data.

[0023] Furthermore, the abnormal state includes a bit error.

[0024] Furthermore, each of the first to N-level numerical monitoring and analysis units includes three basic subunits, namely a data sampling subunit, an abnormality detection subunit and a state latching subunit.

[0025] The data sampling subunit receives the output data of the target operation circuit at this level and the state latch result of the numerical monitoring and analysis unit at the previous level, and selects and filters out the expected data, and saves the expected data for a period of time, wherein the expected data is determined based on the throughput, operation time of the target operation circuit at this level and the focus problem point of the numerical monitoring and analysis unit at the previous level.

[0026] The abnormality detection subunit detects whether the data output by the data sampling subunit meets the design requirements, and the detection rules used are at least one of data value overflow detection, data waveform detection, spectrum shape and spectrum line position detection, or comprehensive use of the monitoring results of the first to N-level numerical monitoring and analysis units for comprehensive judgment detection.

[0027] The state latching subunit latches the intermediate detection state and the final detection result output by the abnormality detection subunit.

[0028] Based on the above method, when an abnormality occurs in the operation of the prototype verification project, the state latch results of each numerical monitoring and analysis unit can be read through the serial port or bus to quickly determine the problematic operation circuit.

[0029] When an abnormal state occurs in the business test, the abnormal detection results of the state latch subunits of the first to N-level numerical monitoring and analysis units are read through the serial port or bus, and after quickly confirming the level of the target operation circuit with the problem, the data of the data sampling subunit of the numerical monitoring and analysis unit of the target operation circuit with the problem is further read, and the data of the data sampling subunit of the numerical monitoring and analysis unit of the target operation circuit with the problem is input as a stimulus to the prototype verification simulation platform for simulation and numerical analysis, and the algorithm correctness and data consistency verification are performed, so as to locate the internal problem point of the target operation circuit with the problem.

[0030] Based on the above method, since the input is data of a period of time near the moment of abnormal state occurring in the operation of the prototype verification project, and the numerical monitoring and analysis unit can obtain the input stimulus of each level of target operation circuits within the same time period, it is possible to tailor the prototype verification simulation platform to perform unit simulation of a certain level of target operation circuit, or to perform system simulation of cascaded target operation circuits of multiple levels, so as to locate the problem points inside a certain operation circuit more quickly and accurately.

[0031] Compared with the prior art, the present invention also has the following advantages:

[0032] The present application provides a method for numerical analysis of baseband prototype verification, which does not require the prototype verification platform to simulate for a long time or capture a large number of signals, but performs data sampling, anomaly detection and state latching based on a numerical monitoring and analysis unit. The method of the present application is easy to implement and can quickly and accurately identify the computing unit where the numerical calculation problem of the baseband prototype verification is located. The present application can not only be used in any baseband prototype verification project, but also in the design for testability (DFT) of ASIC design, and can continue to monitor the design after the chip is taped out, which has a high practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1This is a flow chart of the first embodiment of the present application;

[0034] Figure 2 The second embodiment of the present invention is shown in the figure for applying the method of the present application to a certain type of digital signal processing core board. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0036] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0037] Embodiment 1, as attached Figure 1 A baseband prototype verification numerical analysis method is shown, which generates a prototype verification project by running on a prototype verification platform and performs service testing;

[0038] Step 1: The first-level target operation circuit outputs data, and a first-level numerical value monitoring and analysis unit is added to the first-level target operation circuit;

[0039] Step 2: input the output data of the first-level target operation circuit into the second-level target operation circuit, and add a second-level numerical value monitoring and analysis unit in the second-level target operation circuit to monitor and analyze the second-level target operation circuit and the first-level numerical value monitoring and analysis unit;

[0040] Step 3: input the output data of the second-level target operation circuit into the third-level target operation circuit, and add a third-level numerical value monitoring and analysis unit in the third-level target operation circuit to monitor and analyze the third-level target operation circuit and the second-level numerical value monitoring and analysis unit; until

[0041] Step N: input the output data of the N-1th level target operation circuit into the Nth level target operation circuit, and add an Nth level numerical value monitoring and analysis unit in the Nth level target operation circuit to monitor and analyze the Nth level target operation circuit and the N-1th level numerical value monitoring and analysis unit, wherein N is the cascade number of the target operation circuit for digital signal processing, wherein N is a natural number ≥ 3;

[0042] Subsequently, if an abnormal state occurs in the service test, the abnormal detection results of the state latch subunits of the first to N-level numerical monitoring and analysis units are read through the serial port or bus to quickly confirm the level of the target operation circuit with the problem.

[0043] Based on this scheme, since the input is the data of a period of time near the abnormal state moment when the prototype verification project is running, and the numerical monitoring and analysis unit can obtain the input stimulus of each level of target operation circuit in the same time period, it is possible to tailor the prototype verification simulation platform to perform unit simulation of a certain level of target operation circuit, or perform system simulation of multiple levels of target operation circuit cascade, which can locate the problem point inside a certain operation circuit more quickly and accurately. This scheme does not require the prototype verification platform to simulate for a long time or capture a large number of signals, but performs data sampling, abnormality detection and state latching based on the numerical monitoring and analysis unit. The method of this scheme is easy to implement and can quickly and accurately confirm the operation unit where the baseband prototype verification numerical calculation problem is located. This scheme can not only be used for any baseband prototype verification project, but also can be applied to the design for testability (DFT) of ASIC design, and continue to monitor the design after the chip is taped out, which has high practical value.

[0044] Embodiment 2, as Figure 2 As shown, this is an application example of the present application method on a certain model of digital signal processing core board:

[0045] This model system is designed as a 4-element frequency domain anti-interference system, which is mainly divided into 4 cascaded digital signal processing circuits, so the value of N is 4;

[0046] Add a first-level numerical monitoring and analysis unit to the first-level operation circuit, i.e., the down-conversion circuit. In the actual implementation process, the data sampling subunit receives the output data of the operation circuit at this level, selects and caches 4-channel mixing output data; the abnormal detection subunit detects whether the truncation selection of the mixing output data output by the operation circuit at this level covers the numerical dynamic range, whether it overflows, and adds a 512-point time-frequency conversion FFT IP core. The center position of the spectrum line peak is detected by searching for the maximum power value, and it is converted into a frequency value according to the frequency resolution to determine whether the spectrum is shifted according to the configuration and whether it conforms to the mixing result of the algorithm model; the intermediate detection state and the final result saved by the state latch subunit are read through the bus to determine whether to enter the next step;

[0047] The input data of the time-frequency conversion circuit of the second-level operation circuit is the output data of the down-conversion circuit of the first-level operation circuit. In the second-level operation circuit, that is, the time-frequency domain conversion (1024-point FFT) circuit, a second-level numerical monitoring and analysis unit is added. The operation circuit of this level adopts time division multiplexing. By increasing the working clock, a time-frequency conversion core module is reused 4 times, and the 4-channel time domain data after mixing are converted into 4-channel frequency domain data respectively, and then output synchronously. In the actual implementation process, the data sampling subunit receives the output data of the operation circuit of this level and the state latch result of the numerical monitoring and analysis unit of the previous level, selects and caches 4 channels of frequency domain data; the abnormal detection subunit detects whether the frequency domain data value output by the operation circuit of this level overflows, and comprehensively compares it with the state latch result of the numerical monitoring and analysis unit of the previous level, that is, the intermediate frequency, to determine whether the spectrum peak position, that is, the intermediate frequency after mixing, is correct. By adding a counter to count the number of each channel of output frequency domain data, it can be further determined whether the 4 channels of frequency domain data are synchronized, etc.; the intermediate detection state and final result saved by the state latch subunit are read through the bus to determine whether to enter the next step;

[0048] The input data of the matrix decomposition and synthesis circuit of the third-level operation circuit is the output data of the time-frequency conversion circuit of the second-level operation circuit. A third-level numerical monitoring and analysis unit is added to the third-level operation circuit, i.e., the matrix decomposition and synthesis circuit. In the actual implementation process, the data sampling subunit receives the output data of the operation circuit of this level and the state latch result of the numerical monitoring and analysis unit of the previous level, selects and caches 4-way weighted frequency domain data; the abnormal detection subunit detects whether the value of the weighted frequency domain data output by the operation circuit of this level overflows, and comprehensively compares the calculated average power of the spectrum line with the result latched by the numerical monitoring and analysis unit of the previous level, i.e., the average power before anti-interference processing, to determine whether the narrowband and broadband interference are removed; the intermediate detection state and the final result saved by the state latch subunit are read through the bus to determine whether to enter the next step;

[0049] The input data of the fourth-level operation circuit is the output data of the third-level operation circuit. A fourth-level numerical monitoring and analysis unit is added to the fourth-level operation circuit, i.e., the frequency-time conversion (1024-point IFFT) circuit. In the actual implementation process, the data sampling subunit receives the output data of the operation circuit at this level and the state latch result of the numerical monitoring and analysis unit at the previous level, selects and caches 4-way time domain data, and simultaneously receives the state latch result of the data detection and analysis unit of the down-conversion circuit of the first-level operation circuit; the abnormal detection subunit detects whether the time domain data truncation selection output by the operation circuit at this level covers the numerical dynamic range and overflows, and makes a comprehensive comparison of the frequency domain power of the state latch result of the numerical monitoring and analysis unit at the previous level and the time domain power of the state latch result of the first-level numerical monitoring and analysis unit, so as to judge whether the anti-interference power output by the operation circuit at this level meets the expectation; the intermediate detection state and the final result saved by the state latch subunit are read through the bus for judgment. The prototype verification project generated by the above steps is run on the prototype verification platform. When a problem occurs, the operation circuit where the problem is located can be quickly located by reading the state latch results of all numerical detection and analysis units.

[0050] From the application of this example, the present application can be quickly implemented by adding a data monitoring and analysis unit to the existing baseband prototype verification project, and can quickly and accurately identify the computing unit where the numerical calculation problem of the baseband prototype verification is located.

[0051] Embodiment 3 is an application example of the method of the present application on a certain model of digital signal processing core board:

[0052] This model system is also designed as a 4-element frequency domain anti-interference system, which is mainly divided into 4 cascaded digital signal processing circuits, so the value of N is 4;

[0053] Add a first-level numerical monitoring and analysis unit to the first-level operation circuit, i.e., the down-conversion circuit. In the actual implementation process, the data sampling subunit receives the output data of the operation circuit at this level, selects and caches 4-channel mixing output data; the abnormal detection subunit detects whether the truncation selection of the mixing output data output by the operation circuit at this level covers the numerical dynamic range, whether it overflows, and adds a 512-point time-frequency conversion FFT IP core. The center position of the spectrum line peak is detected by searching for the maximum power value, and it is converted into a frequency value according to the frequency resolution to determine whether the spectrum is shifted according to the configuration and whether it conforms to the mixing result of the algorithm model; the intermediate detection state and the final result saved by the state latch subunit are read through the bus to determine whether to enter the next step;

[0054] The input data of the time-frequency conversion circuit of the second-level operation circuit is the output data of the down-conversion circuit of the first-level operation circuit. In the second-level operation circuit, that is, the time-frequency domain conversion (1024-point FFT) circuit, a second-level numerical monitoring and analysis unit is added. The operation circuit of this level adopts time division multiplexing. By increasing the working clock, a time-frequency conversion core module is reused 4 times, and the 4-channel time domain data after mixing are converted into 4-channel frequency domain data respectively, and then output synchronously. In the actual implementation process, the data sampling subunit receives the output data of the operation circuit of this level and the state latch result of the numerical monitoring and analysis unit of the previous level, selects and caches 4 channels of frequency domain data; the abnormal detection subunit detects whether the frequency domain data value output by the operation circuit of this level overflows, and comprehensively compares it with the state latch result of the numerical monitoring and analysis unit of the previous level, that is, the intermediate frequency, to determine whether the spectrum peak position, that is, the intermediate frequency after mixing, is correct. By adding a counter to count the number of each channel of output frequency domain data, it can be further determined whether the 4 channels of frequency domain data are synchronized, etc.; the intermediate detection state and final result saved by the state latch subunit are read through the bus to determine whether to enter the next step;

[0055] The input data of the matrix decomposition and synthesis circuit of the third-level operation circuit is the output data of the time-frequency conversion circuit of the second-level operation circuit. A third-level numerical monitoring and analysis unit is added to the third-level operation circuit, i.e., the matrix decomposition and synthesis circuit. In the actual implementation process, the data sampling subunit receives the output data of the operation circuit of this level and the state latch result of the numerical monitoring and analysis unit of the previous level, selects and caches 4-way weighted frequency domain data; the abnormal detection subunit detects whether the value of the weighted frequency domain data output by the operation circuit of this level overflows, and comprehensively compares the calculated average power of the spectrum line with the result latched by the numerical monitoring and analysis unit of the previous level, i.e., the average power before anti-interference processing, to determine whether the narrowband and broadband interference are removed; the intermediate detection state and the final result saved by the state latch subunit are read through the bus to determine whether to enter the next step;

[0056] The input data of the fourth-level operation circuit is a mixture of the output data of the first-level to third-level operation circuits. A fourth-level numerical monitoring and analysis unit is added to the fourth-level operation circuit, i.e., the frequency-time conversion (1024-point IFFT) circuit. In the actual implementation process, the data sampling subunit receives the output data of the operation circuit of this level and the state latch result of the numerical monitoring and analysis unit of the previous level, selects and caches 4-way time domain data, and simultaneously receives the state latch result of the data detection and analysis unit of the down-conversion circuit of the first-level operation circuit; the abnormal detection subunit detects whether the time domain data truncation selection output by the operation circuit of this level covers the numerical dynamic range and overflows, and calculates the power to make a comprehensive comparison of the frequency domain power of the state latch result of the numerical monitoring and analysis unit of the previous level and the time domain power of the state latch result of the first-level numerical monitoring and analysis unit, so as to judge whether the anti-interference power output by the operation circuit of this level meets the expectation; the intermediate detection state and the final result saved by the state latch subunit are read through the bus for judgment. The prototype verification project generated by the above steps is run on the prototype verification platform. When a problem occurs, the operation circuit where the problem is located can be quickly located by reading the state latch results of all numerical detection and analysis units.

[0057] From the application of this example, the present application can be quickly implemented on the existing baseband prototype verification project, in addition to adding a data monitoring and analysis unit. The input of the last stage of this embodiment is the mixed output of all previous stages. The use of this mixed output method can improve the accuracy and interpretation ability of the business test of the baseband prototype verification project, and can better describe the source of data anomalies, thereby providing a faster and more accurate confirmation of the calculation unit where the numerical calculation problem of the baseband prototype verification is located.

[0058] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided in this application and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0059] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, device, article or method including the element.

[0060] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A numerical analysis method for baseband prototype verification, characterized in that: include: S1: Run the prototype verification project on the prototype verification platform and perform business tests; S2: the first-level target operation circuit outputs data, and a first-level numerical value monitoring and analysis unit is added to the first-level target operation circuit; S3: inputting the output data of the first-level target operation circuit into the second-level target operation circuit, and adding a second-level numerical value monitoring and analysis unit in the second-level target operation circuit to monitor and analyze the second-level target operation circuit and the first-level numerical value monitoring and analysis unit, S4: repeating step S3 until the output data of the N-1th target operation circuit is input into the Nth target operation circuit, and an Nth level numerical value monitoring and analysis unit is added to the Nth level target operation circuit to monitor and analyze the Nth level target operation circuit and the N-1th level numerical value monitoring and analysis unit, wherein N is the cascade number of the target operation circuit for digital signal processing, and N is a natural number ≥ 3; S5: When the business test is abnormal, the abnormal detection result of the state latch subunit of the first ~ N-level numerical monitoring and analysis unit is read through the serial port or bus to quickly confirm the level of the target operation circuit with problems; Each of the first to N-level numerical monitoring and analysis units includes three basic subunits, namely a data sampling subunit, an abnormality detection subunit and a state latch subunit; The data sampling subunit receives the output data of the target operation circuit of the current level and the state latch result of the numerical monitoring and analysis unit of the previous level, and selects and filters out the expected data, and stores the expected data for a period of time, wherein the expected data is determined according to the throughput, operation time and focus problem point of the target operation circuit of the current level and the numerical monitoring and analysis unit of the previous level; The abnormality detection subunit detects whether the data output by the data sampling subunit meets the design requirements, and the detection rules used are at least one of data value overflow detection, data waveform detection, spectrum shape and spectrum line position detection, or comprehensive use of the monitoring results of the first to N-level numerical monitoring and analysis units for comprehensive judgment detection.

2. A numerical analysis method for baseband prototype verification, characterized in that: include: S1: Run the prototype verification project on the prototype verification platform and perform business tests; S2: the first-level target operation circuit outputs data, and a first-level numerical value monitoring and analysis unit is added to the first-level target operation circuit; S3: inputting the output data of the first-level target operation circuit into the second-level target operation circuit, and adding a second-level numerical value monitoring and analysis unit in the second-level target operation circuit to monitor and analyze the second-level target operation circuit and the first-level numerical value monitoring and analysis unit; S4: repeating step S3 until the output data of the N-2th target operation circuit is input into the N-1th target operation circuit, and an N-1th numerical value monitoring and analysis unit is added to the N-1th target operation circuit to monitor and analyze the N-1th target operation circuit and the N-2th numerical value monitoring and analysis unit, wherein N is the cascade number of the digital signal processing target operation circuit, and N is a natural number ≥ 3; S5: Mixing and inputting all output data of the first to N-1 level target operation circuits into the N-th level target operation circuit, and adding an N-th level numerical value monitoring and analysis unit in the N-th level target operation circuit to monitor and analyze the N-th level target operation circuit and the N-1-th level numerical value monitoring and analysis unit; S6: When an abnormal state occurs in the service test, the abnormal detection result of the state latch subunit of the first to N-level value monitoring and analysis units is read through the serial port or bus to quickly determine the level of the target operation circuit with the problem; Each of the first to N-level numerical monitoring and analysis units includes three basic subunits, namely a data sampling subunit, an abnormality detection subunit and a state latch subunit; The data sampling subunit receives the output data of the target operation circuit of the current level and the state latch result of the numerical monitoring and analysis unit of the previous level, and selects and filters out the expected data, and stores the expected data for a period of time, wherein the expected data is determined according to the throughput, operation time and focus problem point of the target operation circuit of the current level and the numerical monitoring and analysis unit of the previous level; The abnormality detection subunit detects whether the data output by the data sampling subunit meets the design requirements, and the detection rules used are at least one of data value overflow detection, data waveform detection, spectrum shape and spectrum line position detection, or comprehensive use of the monitoring results of the first to N-level numerical monitoring and analysis units for comprehensive judgment detection.

3. The baseband prototype verification numerical analysis method according to any one of claims 1-2, characterized in that: The monitoring and analysis content of each of the first to N-level numerical monitoring and analysis units is determined by the target operation circuit of this level and the numerical monitoring and analysis unit of the previous level. The first to N-level numerical monitoring and analysis units operate independently or are interconnected to exchange data.

4. The baseband prototype verification numerical analysis method according to any one of claims 1-2, characterized in that: The abnormal state includes a bit error.

5. The baseband prototype verification numerical analysis method according to claim 4, characterized in that: The state latching subunit latches the intermediate detection state and the final detection result output by the abnormality detection subunit.

6. The baseband prototype verification numerical analysis method according to claim 4, characterized in that: When an abnormal state occurs in the business test, the abnormal detection results of the state latch subunits of the first to N-level numerical monitoring and analysis units are read through the serial port or bus, and after quickly confirming the level of the target operation circuit with the problem, the data of the data sampling subunit of the numerical monitoring and analysis unit of the target operation circuit with the problem is further read, and the data of the data sampling subunit of the numerical monitoring and analysis unit of the target operation circuit with the problem is input as a stimulus to the prototype verification simulation platform for simulation and numerical analysis, and the algorithm correctness and data consistency verification are performed, so as to locate the internal problem point of the target operation circuit with the problem.

7. A readable storage medium, characterized in that The readable storage medium stores codes, and when the codes are executed on an electronic device, the electronic device executes the baseband prototype verification numerical analysis method according to any one of claims 1 to 6.

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