A control circuit and memory

Abstract

The disclosed embodiments relate to the field of circuits and provide a control circuit and memory. The control circuit includes: a memory block logic circuit configured to receive a first pulse signal, generate and output a first control signal corresponding to the first pulse signal, and enable a target memory block; a pulse trigger configured to receive the first pulse signal, generate and output a second pulse signal, and have an active level of a preset duration; and a sense amplifier control module, including a control signal generation module configured to receive the second pulse signal and generate a second control signal. The sense amplifier control module operates in response to the second control signal, and when the second control signal is at an active level, the sense amplifier control module turns on and transmits the first control signal. This can reduce power consumption of the control circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of circuits, and in particular to a control circuit and a memory. Background Art

[0002] Memory is typically composed of multiple memory cells. When multiple data are to be stored in or read from the memory, the memory intelligently responds to row select signals based on the memory address corresponding to each data point, thereby activating the memory cells on the corresponding word lines. This allows the data to be stored in or read from the corresponding memory cells. Therefore, in memory technology applications, multiple row decoders are used to generate multiple row select signals.

[0003] However, the current control circuit for generating the row selection signal consumes a large amount of power. Therefore, it is necessary to provide a control circuit to reduce the power consumption of the control circuit. Summary of the Invention

[0004] The embodiments of the present disclosure provide a control circuit that can at least reduce the power consumption of the control circuit.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a control circuit for reading and writing data in a memory, including: a storage block logic circuit, configured to receive a first pulse signal, generate and output a first control signal corresponding to the first pulse signal, and the first pulse signal is used to enable a target storage block; a pulse trigger, configured to receive the first pulse signal, generate and output a second pulse signal, and the second pulse signal has an effective level with a preset duration; a sensing amplifier control module, the sensing amplifier control module including a control signal generating module, configured to receive the second pulse signal and generate a second control signal, the sensing amplifier control module operates in response to the second control signal, wherein when the second control signal is at an effective level, the sensing amplifier control module is turned on and transmits the first control signal.

[0006] In some embodiments, the sense amplifier control module includes: at least one switch module, configured to receive the second control signal and conduct and output the first power signal and / or the second power signal during the period when the second control signal is at the valid level; at least one transmission module, the transmission module having a power supply terminal and a ground terminal, configured such that the power supply terminal receives the first power signal output by the switch module and / or the ground terminal receives the second power signal output by the switch module, and the transmission module is in operation.

[0007] In some embodiments, the switch module is turned on and outputs the first power signal during the period when the second control signal is at the valid level. The switch module includes: a first inverter, an input end of the first inverter receives the second control signal; a first PMOS transistor, a gate of the first PMOS transistor is connected to the output end of the first inverter, a source of the first PMOS transistor is connected to the first power supply, and a drain of the first PMOS transistor outputs the first power signal.

[0008] In some embodiments, the switch module is turned on and outputs the second power signal during the period when the second control signal is at the valid level. The switch module includes: a first NMOS transistor, the gate of the first NMOS transistor receives the second control signal, the source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor outputs the second power signal.

[0009] In some embodiments, the switch module is turned on to output the second power signal and the first power signal during the period when the second control signal is at the effective level. The switch module includes: a first inverter, wherein the input end of the first inverter receives the second control signal; a first PMOS transistor, wherein the gate of the first PMOS transistor is connected to the output end of the first inverter, the source of the first PMOS transistor is connected to the first power supply, and the drain of the first PMOS transistor outputs the first power signal; and a first NMOS transistor, wherein the gate of the first NMOS transistor receives the second control signal, the source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor outputs the second power signal.

[0010] In some embodiments, the sense amplifier control module includes: M transmission modules; the control signal generation module includes: N switch modules; and the switch modules are turned on to output the first power signal or the second power signal during the period when the second control signal is at the valid level. The transmission modules include: a first transmission module, the first transmission module including a first power supply terminal and a first ground terminal, the first power supply terminal receiving a power supply voltage, and the first ground terminal being turned on and receiving the ground voltage when receiving the second power supply signal; and a second transmission module, the second transmission module including a second power supply terminal and a second ground terminal, the second ground terminal receiving a ground voltage, and the second power supply terminal being turned on and receiving the power supply voltage when receiving the first power supply signal. M and N are positive integers greater than 1, and M is greater than or equal to N.

[0011] In some embodiments, M is equal to N, and the switch modules are connected to the transmission modules in a one-to-one correspondence.

[0012] In some embodiments, M transmission modules are connected in series, and the first transmission modules and the second transmission modules are arranged alternately.

[0013] In some embodiments, the transmission module includes: a pull-up unit, which is connected to the power supply end and is configured to receive the first control signal in the first level state when the second control signal is valid, and output the first output signal in the second level state when the switch module is in the on state; a pull-down unit, which is connected to the ground end and is configured to receive the first control signal in the second level state when the second control signal is valid, and output the first output signal in the first level state when the switch module is in the on state.

[0014] In some embodiments, the pull-up unit includes: a second PMOS tube, the gate of the second PMOS tube receives the first control signal, the source of the second PMOS tube is connected to the power supply end and receives the first power supply signal, and the drain of the second PMOS tube outputs the first output signal; the pull-down unit includes: a second NMOS tube, the gate of the second NMOS tube receives the first control signal, the drain of the second NMOS tube is connected to the drain of the second PMOS tube, the source of the second NMOS tube is connected to the ground end and receives the second power supply signal.

[0015] In some embodiments, the control signal generation module further includes: a signal synthesis unit configured to receive a third pulse signal and the second pulse signal, perform a logic operation to generate and output the second control signal, and the third pulse signal is used to enable the target storage sub-block.

[0016] In some embodiments, the signal synthesis unit includes: an OR gate, one input end of the OR gate receives the third pulse signal, the other input end of the OR gate is connected to the output end of the pulse trigger, and the output end of the OR gate is connected to the input end of the control signal generation module.

[0017] In some embodiments, the first pulse signal is a pulse signal having a first period, and the duration of the effective level of the second pulse signal is greater than or equal to 3 / 2 times of the first period.

[0018] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a memory, comprising the control circuit as described above.

[0019] The technical solution provided by the embodiment of the present disclosure has at least the following advantages: enabling the target storage block through a first pulse signal, and generating a first control signal through the storage block logic circuit in the storage block; generating a second pulse signal through a pulse trigger, and the second pulse signal has an effective level with a preset duration, and the second pulse signal is used to generate a second control signal; receiving the second pulse signal and outputting a second control signal through the sensing amplifier control module, and turning on and transmitting the first control signal in response to the second control signal, that is, by controlling the preset duration of the effective level of the second pulse signal to generate the required second control signal, when the second control signal is at an effective level, the sensing amplifier control module is continuously turned on. Compared with the related art in which the sensing amplifier control module is continuously switched on, the embodiment of the present disclosure can reduce the number of switching times of the sensing amplifier control module. The more switching times, the greater the dynamic power consumption of the current. The embodiment of the present disclosure can reduce the power consumption of the control circuit by reducing the number of switching times of the sensing amplifier control module. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A circuit diagram of a control circuit provided in one embodiment of the present disclosure;

[0022] Figure 2 A circuit diagram of a sense amplifier control module provided in one embodiment of the present disclosure;

[0023] Figure 3 A circuit diagram of a switch module provided in one embodiment of the present disclosure;

[0024] Figure 4 A circuit diagram of a second switch module provided in an embodiment of the present disclosure;

[0025] Figure 5 A circuit diagram of a control signal generating module and a third switch module provided in one embodiment of the present disclosure;

[0026] Figure 6 A circuit diagram of a transmission module provided in one embodiment of the present disclosure;

[0027] Figure 7A circuit diagram of a second transmission module provided in an embodiment of the present disclosure;

[0028] Figure 8 A timing diagram of some signals in a control circuit provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] As can be seen from the background technology, during the current reading and writing process of the memory, the sensing amplifier is often accompanied by stages such as pre-charging, offset cancellation, charge sharing or sensing amplification. During these stages, the pulse signal received by the control module corresponding to the sensing amplifier in the control circuit will be flipped multiple times. Therefore, the sensing amplifier control module of the control circuit in the related technology will be turned on and off a large number of times, which leads to high power consumption of the current control circuit.

[0030] An embodiment of the present disclosure provides a control circuit, which generates a second pulse signal with a preset duration and an effective level through a pulse trigger, and receives the second pulse signal and generates a second control signal through a control signal generation module. When the second control signal is at an effective level, the sensing amplifier control module is continuously turned on, thereby reducing the number of switching times of the sensing amplifier control module and thus reducing the power consumption of the control circuit.

[0031] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0032] refer to Figure 1 and Figure 2 , Figure 1 A circuit diagram of a control circuit provided by the present disclosure, Figure 2 A circuit diagram of a sense amplifier control module provided in an embodiment of the present disclosure.

[0033] In some embodiments, the control circuit may include a memory block logic circuit 100 configured to receive a first pulse signal banken, generate and output a first control signal ctrl_net corresponding to the first pulse signal banken, where the first pulse signal banken is used to enable a target memory block.

[0034] In some embodiments, the control circuit may further include: a pulse trigger 110 configured to receive the first pulse signal banken, generate and output a second pulse signal bkenpls, and the second pulse signal bkenpls has an effective level with a preset duration.

[0035] In some embodiments, the control circuit may further include: a sense amplifier control module 120, the sense amplifier control module 120 including a control signal generation module 130, configured to receive the second pulse signal bkenpls and generate a second control signal ctrl2, the sense amplifier control module 120 operates in response to the second control signal ctrl2, wherein when the second control signal ctrl2 is at an effective level, the sense amplifier control module 120 is turned on and transmits the first control signal ctrl_net.

[0036] That is, when the second control signal ctrl2 is at a valid level, the sensing amplifier control module 120 is in an on state and can transmit the first control signal ctrl_net. By controlling the duration of the valid level of the second control signal ctrl2, the number of switching times of the sensing amplifier control module 120 can be reduced, thereby achieving the purpose of reducing the dynamic power consumption of the current. The second control signal ctrl2 is related to the second pulse signal bkenpls. By controlling the second pulse signal bkenpls to have an effective level with a preset duration, the duration of the effective level of the second control signal ctrl2 can be controlled.

[0037] Taking a preset duration of 1000ns as an example, in the related art, taking a signal period of 50ns as an example, within 1000ns, the related art will flip 20 times, that is, the sensing amplifier control module in the related art will switch on and off 20 times, while in the embodiment of the present disclosure, the sensing amplifier control module 120 will only switch on and off once within the period of 1000ns, thereby reducing the number of opening and closing times and reducing the power consumption of the control circuit.

[0038] A first control signal ctrl_net is generated by the storage block logic circuit 100, and a second pulse signal bkenpls is generated by the pulse trigger 110, and the second pulse signal bkenpls has an effective level with a preset duration. The second pulse signal bkenpls is received by the sense amplifier control module 120 and a second control signal ctrl2 is output. In response to the second control signal ctrl2, the first control signal ctrl_net is transmitted. The preset duration of the effective level of the second pulse signal bkenpls is adjusted to generate the required second control signal ctrl2. When the second control signal ctrl2 is at an effective level, the sense amplifier control module 120 is continuously turned on. Compared with the sense amplifier control module in the related art that is continuously turned on and off, the embodiment of the present disclosure can reduce the number of switching times of the sense amplifier control module 120. The more switching times, the greater the current loss. By reducing the number of switching times of the sense amplifier control module 120, the embodiment of the present disclosure can reduce the power consumption of the control circuit.

[0039] In some embodiments, the storage block logic circuit 100 receives a first pulse signal banken. If banken is valid, it can be a high level, that is, logic 1, indicating that the corresponding storage block is the target storage block. The storage block logic circuit generates a first control signal ctrl_net accordingly. The first control signal ctrl_net is used to enable the row decoder module so that the row decoder module receives the address signal to drive the corresponding word line to open and close.

[0040] In some embodiments, the pulse trigger 110 can be a circuit or device with a delay function. The pulse trigger 110 receives the first pulse signal banken and delays the first pulse signal banken to generate a second pulse signal bkenpls with an effective level having a preset duration.

[0041] In some embodiments, the sense amplifier control module 120 may include a control signal generation module 130, which receives the second pulse signal bkenpls and generates a second control signal ctrl2. The second control signal ctrl2 is a signal used to control the conduction and disconnection of the entire sense amplifier control module 120. When the second control signal ctrl2 is at an effective level, the sense amplifier control module 120 can be controlled to be turned on and transmit the first control signal ctrl_net. When the second control signal ctrl2 is continuously at an effective level, that is, the sense amplifier control module 120 is in a continuously turned-on state and will not be disconnected, thereby achieving the purpose of saving current and energy consumption.

[0042] In some embodiments, the sense amplifier control module 120 may further include: at least one switch module 140 configured to receive the second control signal ctrl2 and conduct and output the first power signal vccz and / or the second power signal vssz when the second control signal ctrl2 is at an active level.

[0043] Here, the first power signal vccz may refer to a high level, and the second power signal vssz may refer to a low level.

[0044] When the second control signal ctrl2 is at an effective level, the switch module 140 is turned on and outputs the first power signal vccz and / or the second power signal vssz. The first power signal vccz and / or the second power signal vssz are used to control the conduction between other circuit structures in the sense amplifier control module 120 and the power signal, so that the sense amplifier control module 120 is turned on when the second control signal ctrl2 is at an effective level.

[0045] In some embodiments, the sense amplifier control module 120 may include: at least one transmission module 150, the transmission module 150 having a power supply terminal and a ground terminal, and being configured such that the power supply terminal receives the first power supply signal vccz output by the switch module 140 and / or the ground terminal receives the second power supply signal vssz output by the switch module 140, and the transmission module 150 is in operation.

[0046] That is to say, the first power signal vccz and the second power signal vssz serve as enable signals for the transmission module 150. When the second control signal ctrl2 is at a valid level, the switch module 140 outputs the first power signal vccz and / or the second power signal vssz. After the transmission module 150 receives the first power signal vccz or the second power signal vssz, the transmission module 150 works, and at this time the transmission module 150 can transmit signals.

[0047] Taking two transmission modules 150 as an example, the power supply end of one transmission module 150 receives the first power supply signal vccz, and the ground end of the other transmission module 150 receives the second power supply signal vssz, and the transmission module 150 receiving the first power supply signal vccz is defined as the first transmission module, and the transmission module 150 receiving the second power supply signal vssz is defined as the second transmission module, the ground end of the first transmission module is connected to the ground end, and the power supply end of the second transmission module is connected to the working power supply, that is, when the second control signal ctrl2 is at the valid level, the switch module 140 outputs the first power supply signal vccz and / or the second power supply signal vssz, the first transmission module receives the first power supply signal vccz to work, and the second transmission module receives the second power supply signal vssz to work.

[0048] Continuing with the example of two transmission modules 150, and the two transmission modules 150 are respectively the first transmission module and the second transmission module, at this time, the switch module 140 can be one, and one switch module 140 outputs the first power signal vccz and the second power signal vssz during the period when the second control signal ctrl2 is at the valid level. In some embodiments, there can be two switch modules 140, one switch module 140 outputs the first power signal vccz during the period when the second control signal ctrl2 is at the valid level, and the other switch module 140 outputs the second power signal vssz during the period when the second control signal ctrl2 is at the valid level, and the switch module 140 outputting the first power signal vccz is connected to the first transmission module, and the switch module 140 outputting the second power signal vssz is connected to the second transmission module.

[0049] In some embodiments, there may be only one transmission module 150, and one of the power supply end and the ground end of the transmission module 150 is electrically connected to the switch module 140. For example, the power supply end of the transmission module 150 receives the first power supply signal vccz, and the ground end is electrically connected to the ground end, or the ground end of the transmission module 150 receives the second power supply signal vssz, and the power supply end is electrically connected to the working power supply.

[0050] In some embodiments, the power supply end of the transmission module 150 receives the first power supply signal vccz, and the ground end receives the second power supply signal vssz. At this time, the switch module 140 needs to be able to simultaneously output the first power supply signal vccz and the second power supply signal vssz so that the transmission module 150 can work.

[0051] refer to Figure 3 , Figure 3 A circuit diagram of a switch module provided in accordance with one embodiment of the present disclosure. In some embodiments, the switch module 140 is turned on and outputs the first power signal vccz while the second control signal ctrl2 is at an active level. The switch module 140 includes: a first inverter 141, the input of which receives the second control signal ctrl2; and a first PMOS transistor MP1, the gate of which is connected to the output of the first inverter 141, the source of which is connected to the first power supply VCC, and the drain of which outputs the first power signal vccz.

[0052] It can be understood that when the second control signal ctrl2 is at an effective level, that is, the switch module 140 receives a high-level signal, the input end of the first inverter 141 receives a high-level signal, the first inverter 141 outputs a low-level signal, the low-level signal is transmitted to the gate of the first PMOS transistor MP1, the path between the source and drain of the first PMOS transistor MP1 is connected, and the drain of the first PMOS transistor MP1 outputs the first power supply signal vccz.

[0053] In some embodiments, the switch module 140 is turned on and outputs the first power signal during the period when the second control signal is at an effective level. The switch module 140 may also include: a third NMOS transistor, the gate of the third NMOS transistor receives the second control signal, the source of the third NMOS transistor is connected to the first power supply VCC, and the drain of the third NMOS transistor outputs the first power signal.

[0054] refer to Figure 4 , Figure 4This is a circuit diagram of a second switch module provided in an embodiment of the present disclosure. In some embodiments, the switch module 140 is turned on and outputs the second power signal vssz while the second control signal ctrl2 is at an active level. The switch module 140 includes a first NMOS transistor MN1, wherein the gate of the first NMOS transistor MN1 receives the second control signal ctrl2, the source of the first NMOS transistor MN1 is grounded, and the drain of the first NMOS transistor MN1 outputs the second power signal vssz.

[0055] It can be understood that when the second control signal ctrl2 is at a valid level, that is, the switch module 140 receives a high-level signal, the gate of the first NMOS transistor MN1 receives a high-level signal, the path between the source and drain of the first NMOS transistor MN1 is connected, and the drain of the first NMOS transistor MN1 outputs the second power supply signal vssz.

[0056] In some embodiments, the switch module is turned on and outputs the second power signal during a period when the second control signal is at an effective level. The switch module also includes: a second inverter, an input end of the second inverter receives the second control signal; a third PMOS transistor, a gate of the third PMOS transistor is connected to the output end of the second inverter, a drain of the third PMOS transistor is grounded, and a source of the third PMOS transistor outputs the second power signal.

[0057] refer to Figure 5 , Figure 5 A circuit diagram of a control signal generation module and a third type of switch module provided in one embodiment of the present disclosure. In some embodiments, the switch module 140 conducts and outputs the second power signal vssz and the first power signal vccz during the period when the second control signal ctrl2 is at an active level. The switch module 140 includes: a first inverter 141, the input of which receives the second control signal ctrl2; a first PMOS transistor MP1, the gate of which is connected to the output of the first inverter 141, the source of which is connected to the first power source, and the drain of which outputs the first power signal vccz; and a first NMOS transistor MN1, the gate of which receives the second control signal ctrl2, the source of which is grounded, and the drain of which outputs the second power signal vssz.

[0058] It can be understood that when the second control signal ctrl2 is at an active level, that is, the input terminal of the first inverter 141 receives a high-level signal, the first inverter 141 outputs a low-level signal, the low-level signal is transmitted to the gate of the first PMOS transistor MP1, the path between the source and drain of the first PMOS transistor MP1 is conductive, and the drain of the first PMOS transistor MP1 outputs the first power signal vccz; the gate of the first NMOS transistor MN1 receives a high-level signal, the path between the source and drain of the first NMOS transistor MN1 is conductive, and the drain of the first NMOS transistor MN1 outputs the second power signal vssz. In other words, by simultaneously outputting the first power signal vccz and the second power signal vssz through a single switch module 140, the layout area of ​​the circuit structure can be reduced.

[0059] In some embodiments, the switch module 140 is turned on and outputs the first power signal and the second power signal during the period when the second control signal is at an effective level. The switch module 140 may further include: a third NMOS transistor, the gate of the third NMOS transistor receives the second control signal, the source of the third NMOS transistor is connected to the first power supply VCC, and the drain of the third NMOS transistor outputs the first power signal; a second inverter, the input end of the second inverter receives the second control signal; a third PMOS transistor, the gate of the third PMOS transistor is connected to the output end of the second inverter, the drain of the third PMOS transistor is grounded, and the source of the third PMOS transistor outputs the second power signal.

[0060] refer to Figure 5 and Figure 6 ,in Figure 6 A circuit diagram of a transmission module provided in an embodiment of the present disclosure. In some embodiments, the sense amplifier control module 120 includes: M transmission modules 150; the control signal generation module 130 includes: N switch modules 140, and the switch modules 140 are turned on to output the first power signal vccz or the second power signal vssz during the period when the second control signal ctrl2 is at an active level. The transmission module 150 includes: a first transmission module 151, which includes a first power terminal and a first ground terminal, the first power terminal receiving a power voltage and turning on when the first ground terminal receives the second power signal vssz; and a second transmission module 152, which includes a second power terminal and a second ground terminal, the second ground terminal receiving a ground voltage and turning on when the second power terminal receives the first power signal vccz. M and N are positive integers greater than 1, and M is greater than or equal to N.

[0061] In other words, the first transmission module 151 is the transmission module 150 that is turned on when receiving the second power signal vssz, and the second transmission module 152 is the transmission module 150 that is turned on when receiving the first power signal vccz.

[0062] Taking M=3 and N=2 as an example, the three transmission modules 150 may include a first transmission module 151, a second transmission module 152, and a third transmission module 153. The third transmission module 153 includes a third power supply terminal and a third ground terminal. The third power supply terminal receives a power supply voltage, and the third ground terminal receives a ground voltage. That is, the third transmission module 153 is in a normally open state. Among the two switch modules 140, one switch module 140 outputs a first power supply signal vccz, and the other switch module 140 outputs a second power supply signal vssz. Some of the transmission modules in the transmission module 150 are connected to the switch module 140 to control the opening and closing of the first transmission module 151 and the second transmission module 152, so that the transmission module 150 of the sense amplifier control module 120 is in an open state when the second control signal ctrl2 is at a valid level.

[0063] It can be understood that the third transmission module 153 among the three transmission modules 150 can be located at the tail stage, that is, the end, that is, the transmission module 150 in the normally open state can be arranged behind the first transmission module 151 or the second transmission module 152, that is, the input end of the third transmission module 153 is connected to the output end of the first transmission module 151 or the output end of the second transmission module 152. In this way, if the first transmission module 151 or the second transmission module 152 is in the disconnected state, the third transmission module 153 will not receive the input signal, which can save the current consumption of the entire control circuit and save the circuit area.

[0064] It should be noted that the normally open state here means that the transmission module 150 is always in the on state. When the transmission module 150 receives the signal to be transmitted, it can output the corresponding signal to be transmitted; the disconnected state here means that the transmission module 150 is not enabled and cannot transmit signals.

[0065] In some embodiments, M is equal to N, and the switch modules 140 are connected one-to-one with the transmission modules 150. That is, each transmission module 150 has a corresponding switch module 140 that provides the first power signal vccz or the second power signal vssz. In other words, each transmission module 150 has a corresponding switch module 140 that controls its on-state. In other words, when the second control signal ctrl2 is at an active level, all transmission modules 150 are continuously on, and the sense amplifier control module 120 does not flip during the active level period, thereby preventing the sense amplifier control module 120 from switching on and off. This reduces the current consumption of the sense amplifier control module 120 due to switching on and off, thereby reducing the power consumption of the entire control circuit.

[0066] In some embodiments, the switch module 140 is turned on and outputs the first power signal vccz and the second power signal vssz during the period when the second control signal ctrl2 is at an effective level. Then, one switch module 140 can control the opening and closing of two transmission modules 150. Taking three transmission modules 150 as an example, the three transmission modules 150 can include a first transmission module 151, a second transmission module 152 and a third transmission module 153. That is to say, the sum of the number of first transmission modules 151 and the number of second transmission modules 152 can also be 2N.

[0067] In some embodiments, M transmission modules 150 are connected in series, and the first transmission modules 151 and the second transmission modules 152 are arranged alternately. Taking four transmission modules 150 as an example, the four transmission modules 150 include two first transmission modules 151 and two second transmission modules 152. The four transmission modules 150 connected in series can be arranged such that the first stage is the first transmission module 151, the second stage is the second transmission module 152, the third stage is the first transmission module 151, and the fourth stage is the second transmission module 152.

[0068] refer to Figure 7 , Figure 7 A circuit diagram of a transmission module provided in accordance with an embodiment of the present disclosure. In some embodiments, the transmission module 150 may include: a pull-up unit 160, connected to a power supply terminal and configured to receive a first control signal at a first level when a second control signal ctrl2 is valid, and to output a first output signal at a second level when the switch module 140 is in an on-state; and a pull-down unit 170, connected to a ground terminal and configured to receive a first control signal at a second level when the second control signal ctrl2 is valid, and to output a first output signal at a first level when the switch module 140 is in an on-state.

[0069] Taking the first level state as a low level signal and the second level state as a high level signal as an example, the pull-up unit 160 is a unit that pulls the low level state up to a high level state, and the pull-down unit 170 is a unit that pulls the high level state down to a low level state, thereby realizing that when the switch module 140 is in the on state, a first output signal that is opposite to the first input signal is output.

[0070] It can be understood that when the second control signal ctrl2 is valid, the switch module 140 is in the on state, and the pull-up unit 160 outputs the first output signal in the second level state; when the second control signal ctrl2 is valid, the switch module 140 is in the on state, and the pull-down unit 170 outputs the first output signal in the first level state.

[0071] Continue to refer Figure 7In some embodiments, the pull-up unit 160 includes a second PMOS transistor MP2. The gate of the second PMOS transistor MP2 receives a first control signal. The source of the second PMOS transistor MP2 is connected to the power supply terminal and receives the first power supply signal vccz. The drain of the second PMOS transistor outputs the first output signal. When the gate of the second PMOS transistor MP2 receives a low-level signal, the second PMOS transistor MP2 turns on, the drain of the power supply terminal provides a voltage, and the second PMOS transistor MP2 outputs a high-level signal.

[0072] In some embodiments, the pull-down unit 170 includes a second NMOS transistor MN2. The gate of the second NMOS transistor MN2 receives a first input signal, the drain of the second NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP2, and the source of the second NMOS transistor MN2 is connected to the ground terminal and receives the second power supply signal vssz. When the gate of the second PMOS transistor MP2 receives a low-level signal, the second PMOS transistor MP2 turns on, discharges the voltage through the ground terminal, and outputs a low-level signal.

[0073] In some embodiments, the control circuit includes multiple transmission modules 150, and the pull-up units 160 of some transmission modules 150 receive the first power signal vccz, that is, the source of the second PMOS transistor MP2 receives the first power signal vccz, and the pull-up units 160 of some transmission modules 150 receive the power supply voltage, that is, the source of the second PMOS transistor MP2 receives the power supply voltage; the pull-down units 170 of some transmission modules 150 receive the second power signal vssz, that is, the source of the second NMOS transistor MN2 receives the second power signal vssz.

[0074] In some embodiments, the control circuit includes multiple transmission modules 150, and the multiple transmission modules 150 include a first transmission module 151 and a second transmission module 152, wherein the first transmission module 151 is a transmission module 150 that receives the second power supply signal vssz, and the second transmission module 152 is a transmission module 150 that receives the first power supply signal vccz, wherein the pull-up unit 160 of the first transmission module 151 receives the power supply voltage, the pull-down unit of the first transmission module 151 receives the second power supply voltage vssz, the pull-up unit 160 of the second transmission module 152 receives the first power supply signal vccz, and the pull-down unit of the second transmission module 152 receives the ground voltage.

[0075] Continuing with the example of four transmission modules 150, the four transmission modules 150 connected in series may be a first transmission module 151 in the first stage, a second transmission module 152 in the second stage, the first transmission module 151 in the third stage, and the second transmission module 152 in the fourth stage. To output a low-level signal in the absence of a power supply voltage at the fourth stage, the second transmission module 152 in the fourth stage needs to have a path connected to the ground terminal. In other words, the second ground terminal of the second transmission module 152 in the fourth stage needs to receive the ground voltage, and the pull-down unit of the second transmission module 152 can be turned on. In other words, the gate of the second NMOS transistor MN2 needs to receive a high-level signal. For the gate of the second NMOS transistor MP2 to receive a high-level signal, the third stage needs to have a path continuously connected to the power supply voltage. In other words, the first power terminal of the first transmission module 151 in the third stage needs to receive the power supply voltage. This is deduced step by step, that is, the transmission modules 150 that receive the first power supply signal vccz and the transmission modules 150 that receive the second power supply signal vssz are arranged alternately.

[0076] In some embodiments, the control signal generation module 130 further includes: a signal synthesis unit 180, configured to receive a third pulse signal SectionEn and a second pulse signal bkenpls, perform a logic operation to generate and output a second control signal ctrl2, and the third pulse signal SectionEn is used to enable the target storage sub-block.

[0077] It can be understood that the first pulse signal is used to enable the target storage block, which includes multiple target storage word blocks. That is to say, the target storage block is turned on by the first pulse signal banken, and then the target storage sub-block in the target storage block is turned on by the third pulse signal SectionEn to achieve the purpose of selecting the target storage sub-block.

[0078] refer to Figure 5 In some embodiments, the signal synthesis unit 180 includes: an OR gate 181, one input end of the OR gate 181 receives the third pulse signal SectionEn, the other input end of the OR gate 181 is connected to the output end of the pulse trigger 110, and the output end of the OR gate 181 is connected to the input end of the control signal generation module 130.

[0079] refer to Figure 8 , Figure 8This is a timing diagram of some signals of the control circuit provided in an embodiment of the present disclosure. The second pulse signal bkenpls is a signal after the effective level of the first pulse signal banken is delayed. According to the principle of the OR gate 181, it can be obtained that the second control signal ctrl2 output by the signal synthesis unit 180 is at an effective level during the period when the second pulse signal bkenpls and the third pulse signal SectionEn are at an effective level, that is, the second control signal ctrl2 is at an effective level for at least a preset time length, that is, the sensing amplifier control module 120 is in an on state for at least a preset time length, thereby reducing the number of times the sensing amplifier control module 120 is turned on and off within the preset time length, thereby reducing the power consumption of the control circuit.

[0080] In some embodiments, the first pulse signal banken is a pulse signal having a first period, and the duration of the active level of the second pulse signal bkenpls is greater than or equal to 3 / 2 times the first period. In other words, within 3 / 2 times the first period, the first pulse signal banken has two rising edges and two falling edges, while the second pulse signal bkenpls has only one rising edge and one falling edge. This can reduce the number of times the sense amplifier control module 120 is turned on and off within the preset duration, thereby reducing the power consumption of the control circuit.

[0081] In some embodiments, the pulse trigger is triggered when the first pulse signal banken is a rising edge, and the effective level of the first pulse signal banken is delayed to obtain the second pulse signal bkenpls. After a preset time, the second pulse signal bkenpls drops to a low level. Afterwards, the second pulse signal bkenpls is refreshed when the first pulse signal banken has a rising edge again, that is, the pulse trigger 110 delays the first pulse signal banken again.

[0082] In some embodiments, the MOS transistors (including PMOS transistors and NMOS transistors) mentioned in the above embodiments may be low threshold voltage transistors (LVMOS low Voltage Metal Oxide Semiconductor), which can reduce the operating voltage and improve the signal transmission speed of the control circuit.

[0083] It should be noted that in the present disclosure, a high level refers to, for example, a state greater than or equal to the power supply voltage, and a low level refers to a state less than or equal to the ground voltage. Here, the terms high and low levels are relative, and the specific voltage ranges included need to be determined based on the specific device. For example, for an N-type field-effect transistor, a high level refers to the gate voltage range that can turn it on, and a low level refers to the gate voltage range that can turn it off. For a P-type field-effect transistor, a low level refers to the gate voltage range that can turn it on, and a high level refers to the gate voltage range that can turn it off.

[0084] It is worth noting that all units involved in this embodiment are logical units. In actual applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, to highlight the innovation of this disclosure, this embodiment does not include units that are not closely related to solving the technical problems proposed by this disclosure. However, this does not mean that other units do not exist in this embodiment.

[0085] A first control signal ctrl_net for enabling a target storage block is generated by the storage block logic circuit 100, and a second pulse signal bkenpls is generated by the pulse trigger 110, and the second pulse signal bkenpls has an effective level with a preset duration; the second pulse signal bkenpls is received by the sense amplifier control module 120 and a second control signal ctrl2 is output, and the first control signal ctrl_net is turned on and transmitted in response to the second control signal ctrl2, and the preset duration of the effective level of the second pulse signal bkenpls is adjusted to generate the required second control signal ctrl2. When the second control signal ctrl2 is at an effective level, the sense amplifier control module 120 is continuously turned on. Compared with the sense amplifier control module in the related art that is continuously switched on and off, the embodiment of the present disclosure can reduce the number of switches of the sense amplifier control module 120. The more the number of switches, the greater the power consumption. By reducing the number of switches of the sense amplifier control module 120, the embodiment of the present disclosure can reduce the power consumption of the control circuit.

[0086] Another embodiment of the present disclosure further provides a memory, including all or part of the control circuits as in the above embodiments. It should be noted that for the parts that are the same or corresponding to the above embodiments, reference can be made to the corresponding descriptions of the above embodiments, and will not be repeated below.

[0087] refer to Figure 1 , Figure 1This is a partial circuit diagram of a memory provided by an embodiment of the present disclosure. A memory block logic circuit 100 receives a first pulse signal banken and generates a first control signal ctrl net. The first control signal ctrl net is transmitted to a sense amplifier control module 120. While the sense amplifier control module 120 is on, the first control signal ctrl net is transmitted to a row decoder xdec to control the operation of the corresponding row decoder xdec.

[0088] It should be noted that the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory may be a volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphic double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0089] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A control circuit for reading and writing data in a memory, characterized in that: include: a memory block logic circuit configured to receive a first pulse signal, generate and output a first control signal corresponding to the first pulse signal, wherein the first pulse signal is used to enable a target memory block; A pulse trigger is configured to receive the first pulse signal, generate and output a second pulse signal, wherein the second pulse signal has an effective level of a preset duration; a sense amplifier control module, the sense amplifier control module including a control signal generation module configured to receive the second pulse signal and generate a second control signal, the sense amplifier control module operating in response to the second control signal, wherein when the second control signal is at an active level, the sense amplifier control module turns on and transmits the first control signal; The sense amplifier control module includes: at least one switch module, configured to receive the second control signal and conduct and output the first power signal and / or the second power signal when the second control signal is at the valid level; At least one transmission module, the transmission module having a power supply end and a ground end, and configured so that the power supply end receives the first power supply signal output by the switch module and / or the ground end receives the second power supply signal output by the switch module, and the transmission module works.

2. The control circuit according to claim 1, wherein: The switch module is turned on to output the first power signal during a period when the second control signal is at the effective level, and the switch module includes: a first inverter, wherein an input terminal of the first inverter receives the second control signal; A first PMOS transistor, wherein a gate of the first PMOS transistor is connected to the output end of the first inverter, a source of the first PMOS transistor is connected to a first power supply, and a drain of the first PMOS transistor outputs the first power supply signal.

3. The control circuit according to claim 1, wherein: The switch module is turned on to output a second power signal during a period when the second control signal is at the effective level, and the switch module includes: A first NMOS transistor, wherein a gate of the first NMOS transistor receives the second control signal, a source of the first NMOS transistor is grounded, and a drain of the first NMOS transistor outputs the second power signal.

4. The control circuit according to claim 1, wherein: The switch module is turned on to output the second power signal and the first power signal during a period when the second control signal is at the effective level, and the switch module includes: a first inverter, wherein an input terminal of the first inverter receives the second control signal; a first PMOS transistor, wherein a gate of the first PMOS transistor is connected to the output end of the first inverter, a source of the first PMOS transistor is connected to a first power supply, and a drain of the first PMOS transistor outputs the first power supply signal; A first NMOS transistor, wherein a gate of the first NMOS transistor receives the second control signal, a source of the first NMOS transistor is grounded, and a drain of the first NMOS transistor outputs the second power signal.

5. The control circuit according to claim 1, wherein: The sense amplifier control module includes: M transmission modules; the control signal generation module includes: N switch modules; and the switch modules are turned on to output the first power signal or the second power signal during a period when the second control signal is at the valid level; the transmission module includes: a first transmission module, the first transmission module comprising a first power supply terminal and a first ground terminal, the first power supply terminal receiving a power supply voltage, the first ground terminal being turned on and receiving a ground voltage when receiving the second power supply signal; A second transmission module, the second transmission module includes a second power supply terminal and a second ground terminal, the second ground terminal receives a ground voltage, and the second power supply terminal is turned on and receives the power supply voltage when receiving the first power signal, wherein M and N are positive integers greater than 1, and M is greater than or equal to N.

6. The control circuit according to claim 5, characterized in that: M is equal to N, and the switch modules are connected to the transmission modules in a one-to-one correspondence.

7. The control circuit according to claim 6, characterized in that: The M transmission modules are connected in series, and the first transmission modules and the second transmission modules are arranged alternately.

8. The control circuit according to claim 1, wherein: The transmission module includes: a pull-up unit connected to the power supply terminal and configured to receive the first control signal in a first level state when the second control signal is valid, and output a first output signal in a second level state when the switch module is in an on state; A pull-down unit is connected to the ground terminal and is configured to receive the first control signal in the second level state when the second control signal is valid, and output the first output signal in the first level state when the switch module is in the on state.

9. The control circuit according to claim 8, wherein: The pull-up unit includes: a second PMOS transistor, wherein a gate of the second PMOS transistor receives the first control signal, a source of the second PMOS transistor is connected to a power supply terminal and receives the first power signal, and a drain of the second PMOS transistor outputs the first output signal; The pull-down unit includes: a second NMOS transistor, a gate of the second NMOS transistor receives the first control signal, a drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, a source of the second NMOS transistor is connected to the ground end, and receives the second power supply signal.

10. The control circuit according to claim 1, wherein: The control signal generating module further includes: The signal synthesis unit is configured to receive a third pulse signal and the second pulse signal, perform a logic operation to generate and output the second control signal, and the third pulse signal is used to enable the target storage sub-block.

11. The control circuit according to claim 10, characterized in that: The signal synthesis unit includes: an OR gate, one input end of the OR gate receives the third pulse signal, the other input end of the OR gate is connected to the output end of the pulse trigger, and the output end of the OR gate is connected to the input end of the control signal generation module.

12. The control circuit according to claim 1, wherein: The first pulse signal is a pulse signal with a first period, and the duration of the effective level of the second pulse signal is greater than or equal to 3 / 2 times of the first period.

13. A memory, characterized in that: include: The control circuit according to any one of claims 1 to 12.

Images