Packaging structure and manufacturing method thereof

Abstract

A packaging structure and a manufacturing method thereof, the packaging structure comprising: an adapter plate having a first side and a second side opposite to each other in a direction perpendicular to the main surface thereof; a chip disposed on the first side of the adapter plate and electrically connected to the adapter plate; a first encapsulation layer disposed on the first side of the adapter plate and encapsulating the chip; a second encapsulation layer disposed on the second side of the adapter plate; a conductive member embedded in the second encapsulation layer and electrically connected to the adapter plate; and a conductive terminal disposed on a side of the second encapsulation layer away from the adapter plate and electrically connected to the conductive member, wherein the thermal expansion coefficient of the first encapsulation layer is greater than the thermal expansion coefficient of the adapter plate, and the thermal expansion coefficient of the second encapsulation layer is greater than the thermal expansion coefficient of the adapter plate. The packaging structure and the manufacturing method thereof can avoid or reduce packaging warpage, improve packaging yield, and improve device performance and reliability.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor packaging technology, and in particular, to a packaging structure and a manufacturing method thereof. Background Art

[0002] In semiconductor packaging technology, chips can be packaged to achieve chip protection, physical and / or electrical connection, etc. Multiple chips can be integrated together through packaging technology; for example, system chips and memory chips can be integrated together, and high-performance computing can be achieved. However, in the packaging structure, there may be warping problems, which may cause device defects and affect the packaging yield. How to improve the warping of the packaging structure is an important research topic in this field. Summary of the invention

[0003] According to at least one embodiment of the present disclosure, a packaging structure is provided, including: an adapter board having a first side and a second side opposite to each other in a direction perpendicular to its main surface; a chip arranged on the first side of the adapter board and electrically connected to the adapter board; a first encapsulation layer arranged on the first side of the adapter board and encapsulating the chip; a second encapsulation layer arranged on the second side of the adapter board; a conductive member embedded in the second encapsulation layer and electrically connected to the adapter board; and a conductive terminal arranged on a side of the second encapsulation layer away from the adapter board and electrically connected to the conductive member, wherein the thermal expansion coefficient of the first encapsulation layer is greater than the thermal expansion coefficient of the adapter board, and the thermal expansion coefficient of the second encapsulation layer is greater than the thermal expansion coefficient of the adapter board.

[0004] In the packaging structure provided according to at least one embodiment of the present disclosure, an absolute value of a difference between a thermal expansion coefficient of the first encapsulation layer and a thermal expansion coefficient of the second encapsulation layer is less than 20 ppm / °C.

[0005] In the packaging structure provided according to at least one embodiment of the present disclosure, the Young's modulus of the adapter plate is greater than the Young's modulus of the first encapsulation layer and the second encapsulation layer.

[0006] In the packaging structure provided according to at least one embodiment of the present disclosure, the adapter board includes a semiconductor substrate and an interconnect structure, wherein the interconnect structure is arranged on one side of the semiconductor substrate in a direction perpendicular to the main surface of the adapter board, and includes an inorganic dielectric structure and a conductive structure embedded in the inorganic dielectric structure.

[0007] In the packaging structure provided according to at least one embodiment of the present disclosure, the thermal expansion coefficients of the semiconductor substrate and the interconnect structure of the transfer board are both smaller than the thermal expansion coefficient of the first encapsulation layer and smaller than the thermal expansion coefficient of the second encapsulation layer.

[0008] In the package structure provided according to at least one embodiment of the present disclosure, the first encapsulation layer, the interposer, and the second encapsulation layer have side walls aligned in a direction perpendicular to a main surface of the interposer.

[0009] In the packaging structure provided according to at least one embodiment of the present disclosure, a surface of the second encapsulation layer away from the adapter board is flush with a surface of the conductive member away from the adapter board in a direction parallel to a main surface of the adapter board.

[0010] In the packaging structure provided according to at least one embodiment of the present disclosure, the conductive terminal is in direct contact with the conductive component and is electrically connected thereto.

[0011] The packaging structure provided according to at least one embodiment of the present disclosure further includes: a redistribution structure, which is placed on a side of the second encapsulation layer away from the adapter board and is electrically connected to the conductive component, wherein the conductive terminal is arranged on a side of the redistribution structure away from the second encapsulation layer and is electrically connected to the conductive component through the redistribution structure.

[0012] In the packaging structure provided according to at least one embodiment of the present disclosure, the redistribution structure includes an organic dielectric structure and a redistribution layer embedded in the organic dielectric structure, and the thermal expansion coefficient of the redistribution structure is greater than the thermal expansion coefficient of the adapter board.

[0013] In the packaging structure provided according to at least one embodiment of the present disclosure, the line width of the conductive traces in the redistribution layer is greater than the line width of the conductive traces in the conductive structure of the adapter board.

[0014] The packaging structure provided according to at least one embodiment of the present disclosure further includes: a packaging substrate, which is arranged on a side of the second encapsulation layer away from the adapter board and is electrically connected to the adapter board through the conductive terminals and the conductive components.

[0015] The packaging structure provided according to at least one embodiment of the present disclosure further includes: a bottom filling layer, which is arranged between the second encapsulation layer and the packaging substrate and surrounds the conductive terminal in a direction parallel to the main surface of the packaging substrate.

[0016] An embodiment of the present disclosure provides a method for manufacturing a packaging structure, comprising: providing an adapter board, the adapter board having a first side and a second side opposite to each other in a direction perpendicular to its main surface; mounting a chip on the first side of the adapter board and electrically connecting the chip to the adapter board; forming a first encapsulation layer on the first side of the adapter board to encapsulate the chip; forming a conductive member and a second encapsulation layer on the second side of the adapter board, the conductive member being embedded in the second encapsulation layer and electrically connected to the adapter board; and forming a conductive terminal on a side of the second encapsulation layer away from the adapter board to electrically connect to the conductive member, thereby forming a chip package, wherein the thermal expansion coefficient of the first encapsulation layer is greater than the thermal expansion coefficient of the adapter board, and the thermal expansion coefficient of the second encapsulation layer is greater than the thermal expansion coefficient of the adapter board.

[0017] In the manufacturing method of the packaging structure provided according to at least one embodiment of the present disclosure, forming the second encapsulation layer on the second side of the adapter board includes: forming a second encapsulation material layer to cover the surface of the second side of the adapter board and the side wall of the conductive component and its surface away from the adapter board; removing part of the second encapsulation material layer to expose the surface of the conductive component away from the adapter board, and forming the second encapsulation layer.

[0018] In the manufacturing method of the packaging structure provided according to at least one embodiment of the present disclosure, after forming the conductive component and the second encapsulation layer and before forming the conductive terminal, it also includes: forming a rewiring structure on a side of the second encapsulation layer away from the adapter board to be electrically connected to the conductive component; wherein the conductive terminal is formed on a side of the rewiring structure away from the second encapsulation layer and is electrically connected to the rewiring structure.

[0019] The method for manufacturing a packaging structure provided according to at least one embodiment of the present disclosure further includes: providing a packaging substrate, and mounting the chip package on the packaging substrate, wherein the chip package is electrically connected to the packaging substrate through the conductive terminals.

[0020] The packaging structure and manufacturing method thereof of the embodiments of the present disclosure can avoid or reduce the warping of the packaging structure, improve the packaging yield, and improve the device performance and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0022] Figure 1 A schematic cross-sectional view showing a package structure in which warping occurs.

[0023] Figures 2 to 5 Schematic cross-sectional views of packaging structures according to some embodiments of the present disclosure are respectively shown.

[0024] Figures 6 to 13 Schematic cross-sectional views showing structures of various steps in a method for manufacturing a package structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0026] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0027] Unless otherwise defined, the features such as "parallel", "perpendicular" and "same" used in the embodiments of the present disclosure include the situations of "parallel", "perpendicular", "same" in a strict sense, as well as the situations of "approximately parallel", "approximately perpendicular", "approximately the same", etc., which contain certain errors. For example, the above-mentioned "approximately" may mean that the difference of the compared objects is within 10% or 5% of the average value of the compared objects. When the number of a component or element is not specifically indicated in the following of the embodiments of the present disclosure, it means that the component or element may be one or more, or may be understood as at least one. "At least one" refers to one or more, and "plurality" refers to at least two.

[0028] Chip on wafer on substrate (CoWoS) packaging is an advanced packaging technology that can achieve high-density line connections between multiple chips and high-speed data transmission. The CoWoS package includes a chip on wafer (CoW) module and a packaging substrate. The CoW module usually includes a chip, a bottom fill layer, a plastic encapsulation material, a silicon-based adapter board, and a conductive bump. For example, the chip is mounted on a silicon-based adapter board, and the plastic encapsulation material and the chip are arranged on the same side of the silicon-based adapter board to encapsulate the chip. Multiple chips can be interconnected with each other through a silicon-based adapter board. The conductive terminal is arranged on the side of the silicon-based adapter board away from the chip, and is electrically connected to the chip through the silicon-based adapter board. In this article, a silicon-based adapter board generally refers to an adapter board including a semiconductor substrate, and the semiconductor substrate includes, for example, silicon, but may also include other semiconductors, such as germanium.

[0029] In some examples, a redistribution layer (RDL) structure can be used to replace a silicon-based adapter. The redistribution structure includes an organic dielectric structure and a redistribution layer embedded in the organic dielectric structure. Generally speaking, the line width and line spacing of the conductive traces in the redistribution layer are greater than the line width and line spacing of the conductive traces in the silicon-based adapter, that is, the silicon-based adapter has finer wiring. The wiring density of a silicon-based adapter is generally greater than the wiring density of a redistribution layer. Therefore, for some high-density interconnection requirements, CoW modules still need to use adapters formed on semiconductor substrates, such as silicon-based adapters with greater wiring density.

[0030] In the manufacturing process of CoWoS packaging, the packaging process of the CoW module is first completed, and then the flip chip ball grid array (FCBGA) assembly is performed to mount the CoW module on the packaging substrate to form a CoWoS packaging structure. For example, the CoW module can be mounted on the packaging substrate through a welding process.

[0031] However, in the process of soldering the CoW module to the packaging substrate, the CoW module may warp due to high temperature. For example, in the CoW module, there is a mismatch in thermal expansion coefficients between different materials such as the plastic encapsulation material and the silicon-based adapter plate, which causes the CoW module to warp at high temperatures due to this mismatch in thermal expansion coefficients; moreover, with the continuous development of 2.5D packaging technology, the size of CoW modules is getting larger and larger. For example, the maximum size may exceed 3 times the mask size, for example, up to an area of ​​about 50 millimeters (mm) × 60 mm. The larger the size of the CoW module, the greater the warping of a single CoW module may be at high temperature. When the CoW module is flip-chip mounted on the packaging substrate, if the warping of the CoW module is too large, defects such as cold soldering or bridging may occur, thereby affecting the packaging yield.

[0032] For example, Figure 1 A schematic cross-sectional view schematically shows a package structure in which warping occurs.

[0033] refer to Figure 1 , the packaging structure 10 includes a CoW module 6 and a packaging substrate 7. The CoW module 6 includes a silicon-based adapter board 1, a chip 2, a bottom filling layer 3, a plastic encapsulation material 4 and a conductive bump 5. The bottom filling layer 3 and the plastic encapsulation material 4 include organic dielectric materials, and the silicon-based adapter board 1 includes a silicon substrate and an interconnect structure with inorganic dielectric materials; due to the mismatch in thermal expansion coefficients between the silicon-based adapter board 1 and the plastic encapsulation material 4, the bottom filling layer 3 and other materials located above it, during the process of installing the CoW module 6 on the packaging substrate 7, different materials undergo different degrees of thermal expansion due to high temperature, causing the module to warp. For example, the thermal expansion coefficients of the bottom filling layer 3 and the plastic encapsulation material 4 are greater than the thermal expansion coefficient of the silicon-based adapter board 1, which causes the CoW module to warp in a "crying face" manner, that is, the central part of the CoW module bulges away from the packaging substrate; this may cause defects such as cold soldering or bridging, affecting the packaging yield. For example, some conductive bumps 5 on the side of the silicon-based adapter board 1 away from the chip may not be effectively electrically connected to the packaging substrate due to module warping, thereby affecting the device performance and reliability of the packaging structure.

[0034] In view of the above problems, the embodiments of the present disclosure provide a packaging structure and a manufacturing method thereof, which can avoid or reduce the warping of the packaging structure, improve the packaging yield, and improve the device performance and reliability.

[0035] For example, the packaging structure of an embodiment of the present disclosure includes: an interposer, including a semiconductor substrate and having a first side and a second side opposite to each other in a direction perpendicular to its main surface; a chip, arranged on the first side of the interposer and electrically connected to the interposer; a first encapsulating layer, arranged on the first side of the interposer and encapsulating the chip; a second encapsulating layer, arranged on the second side of the interposer; a conductive member, embedded in the second encapsulating layer and electrically connected to the interposer; and a conductive terminal, arranged on a side of the second encapsulating layer away from the interposer and electrically connected to the conductive member, wherein the thermal expansion coefficient of the first encapsulating layer is greater than the thermal expansion coefficient of the interposer, and the thermal expansion coefficient of the second encapsulating layer is greater than the thermal expansion coefficient of the interposer.

[0036] In the embodiment of the present disclosure, by arranging the first encapsulation layer and the second encapsulation layer on opposite sides of the adapter plate, it is beneficial to balance the thermal deformation (expansion / contraction) of the adapter plate and the encapsulation layers on opposite sides thereof, thereby avoiding or reducing the warping of the package structure, improving the package yield, and improving the device performance and reliability of the package structure. Specifically, since the first encapsulation layer and the second encapsulation layer are arranged on opposite sides of the adapter plate, and the thermal expansion coefficients of the first encapsulation layer and the second encapsulation layer are both greater than the thermal expansion coefficient of the adapter plate, under conditions such as high temperature, the thermal deformation (for example, thermal expansion) of the first encapsulation layer and the second encapsulation layer on both sides of the adapter plate can counteract each other, and the stress generated by the second encapsulation layer on the adapter plate due to the mismatch of the thermal expansion coefficient between the second encapsulation layer and the adapter plate and the stress generated by the first encapsulation layer on the adapter plate due to the mismatch of the thermal expansion coefficient between the second encapsulation layer and the adapter plate are opposite in direction and can offset each other, thereby balancing and controlling the thermal deformation of the above-mentioned different materials, thereby avoiding or reducing the overall warping of the package structure.

[0037] Figure 2 A schematic cross-sectional view showing a package structure according to some embodiments of the present disclosure is shown. Figure 3 A schematic cross-sectional view showing a more specific structure of a package structure according to some embodiments of the present disclosure.

[0038] refer to Figure 2 In some embodiments, the package structure 500 includes an interposer 100, one or more chips 80, a first encapsulation layer 110, a second encapsulation layer 120, a conductive member 119, and a conductive terminal 150. The interposer 100 has a first side S1 and a second side S2 opposite to each other in a direction perpendicular to its main surface (e.g., a first direction D1). The chip 80 is disposed on the first side S1 of the interposer 100 and is electrically connected to the interposer 100. The first encapsulation layer 110 is disposed on the first side S1 of the interposer 100 and encapsulates the chip 80. For example, the first encapsulation layer 110 may encapsulate at least the sidewalls of the chip 80, and in some embodiments may also encapsulate the surface of the chip 80 away from the interposer 100.

[0039] The conductive member 119 and the second encapsulation layer 120 are disposed on the second side S2 of the adapter board 100, and the conductive member 119 is embedded in the second encapsulation layer 120 and electrically connected to the adapter board 100. The conductive terminal 150 is disposed on a side of the second encapsulation layer 120 away from the adapter board 100, and is electrically connected to the conductive member 119, so that it can be electrically connected to the adapter board 100 through the conductive member 119, and electrically connected to the chip 80 through the conductive member 119 and the adapter board 100. The conductive terminal 150 can be used to electrically connect the package structure 500 to other package components, such as a package substrate. For example, a plurality of chips 80 are disposed on the adapter board 100, and can be interconnected to each other through the adapter board 100, and can be further connected to other package components through the adapter board 100, the conductive member 119 and the conductive terminal 150.

[0040] In some embodiments, the coefficient of thermal expansion (CTE) of the first encapsulation layer 110 is different from the coefficient of thermal expansion of the adapter plate 100, and the coefficient of thermal expansion of the second encapsulation layer 120 is also different from the coefficient of thermal expansion of the adapter plate 100; that is, there is a mismatch in the coefficient of thermal expansion between the first encapsulation layer 110 and the adapter plate 100, and between the second encapsulation layer 120 and the adapter plate 100. For example, the coefficient of thermal expansion of the first encapsulation layer 110 is greater than the coefficient of thermal expansion of the adapter plate 100, and the coefficient of thermal expansion of the second encapsulation layer 120 is greater than the coefficient of thermal expansion of the adapter plate 100. By arranging the first encapsulation layer 110 and the second encapsulation layer 120 on opposite sides of the adapter plate 100, under conditions such as high temperature, the thermal deformation (e.g., thermal expansion) of the first encapsulation layer 110 and the thermal deformation (e.g., thermal expansion) of the second encapsulation layer 120 on both sides of the adapter plate can counteract each other. For example, the degree of thermal expansion of the first encapsulation layer 110 and the degree of thermal expansion of the second encapsulation layer 120 can be substantially the same, and the first stress from the first encapsulation layer to which the adapter plate 100 is subjected due to the mismatch in thermal expansion coefficient with the first encapsulation layer 110 and the second stress from the second encapsulation layer to which the adapter plate 100 is subjected due to the mismatch in thermal expansion coefficient with the second encapsulation layer 120 are in opposite directions, and the first stress and the second stress can offset each other at least partially (e.g., partially or completely); in this way, the thermal deformation of each material layer such as the adapter plate, the first encapsulation layer and the second encapsulation layer in the packaging structure can be balanced and controlled, thereby avoiding or reducing the warping of the packaging structure.

[0041] In other words, the first encapsulation layer 110 and the second encapsulation layer 120 are arranged on opposite sides of the adapter board 100, so that the first warping direction WP1 of the first type of warping that may occur due to the mismatch in thermal expansion coefficients between the first encapsulation layer 110 and the adapter board 100 is opposite to the second warping direction WP2 of the second type of warping that may occur due to the mismatch in thermal expansion coefficients between the second encapsulation layer 120 and the adapter board 100, so that the two types of warping that may occur above can at least partially offset each other, for example, can completely offset each other, so that the thermal deformation of materials such as the adapter board and the encapsulation layer can be balanced and controlled under high temperature conditions, thereby avoiding or reducing the warping of the overall packaging structure.

[0042] Figure 2 The first warping direction WP1 of the first type of warping and the second warping direction WP2 of the second type of warping are schematically shown in FIG. It should be understood that the first type of warping refers to the warping that occurs when the second encapsulation layer is not provided on the second side of the adapter plate but the first encapsulation layer is provided on the first side, such as the "crying face" warping; the second type of warping refers to the warping that occurs when the first encapsulation layer is not provided on the first side of the adapter plate but the second encapsulation layer is provided on the second side, such as the "smiling face" warping. It should be understood that Figure 2 The first warping direction WP1 and the second warping direction WP2 shown in the figure are only for the purpose of facilitating understanding that the thermal deformation caused by the second encapsulation layer on the second side of the adapter plate can resist the thermal deformation caused by the first encapsulation layer on the first side of the adapter plate, that is, the above two types of warping can offset each other, and do not mean that the package structure 500 will actually warp. In the embodiment of the present disclosure, since the two types of warping can at least partially offset each other, the package structure may not warp, or the warping amplitude is very small and will not affect the overall performance of the package structure.

[0043] In some embodiments, the absolute value of the difference between the thermal expansion coefficient of the first encapsulating layer and the thermal expansion coefficient of the second encapsulating layer is less than 20 ppm / °C. For example, under the temperature condition that is less than the glass transition temperature of the first encapsulating layer and the glass transition temperature of the second encapsulating layer, the absolute value of the difference between the thermal expansion coefficients of the first encapsulating layer and the second encapsulating layer is less than 5 ppm / °C; under the temperature condition that is greater than the glass transition temperature of the first encapsulating layer and the glass transition temperature of the second encapsulating layer, the absolute value of the difference between the thermal expansion coefficients of the first encapsulating layer and the second encapsulating layer is less than 20 ppm / °C.

[0044] In some embodiments, the thermal expansion coefficient of the first encapsulating layer 110 may be substantially equal to the thermal expansion coefficient of the second encapsulating layer 120, that is, including the case where the thermal expansion coefficient of the first encapsulating layer 110 and the thermal expansion coefficient of the second encapsulating layer 120 are completely the same or close to each other. In some embodiments, under the same temperature conditions, the thermal expansion degree (i.e., the degree of dimensional change) of the first encapsulating layer 110 is substantially equal to the thermal expansion degree (i.e., the degree of dimensional change) of the second encapsulating layer 120; in other words, under the same temperature change conditions, the thermal expansion equivalent of the first encapsulating layer 110 is substantially equal to the thermal expansion equivalent of the second encapsulating layer 120. Here, the thermal expansion equivalent of the encapsulating layer refers to the change in its size (e.g., volume) before and after the temperature change.

[0045] In some embodiments, the Young's modulus (or stiffness) of the transfer plate 100 is greater than the Young's modulus (or stiffness) of the first encapsulation layer and the second encapsulation layer. The transfer plate 100 having a larger Young's modulus may also help to avoid or reduce warping of the transfer plate and the overall packaging structure.

[0046] refer to Figure 3 In some embodiments, the interposer 100 may include a semiconductor substrate 101, an interconnection structure 106, and a conductive connector 107. The interconnection structure 106 is disposed on one side of the semiconductor substrate 101 in a first direction D1 perpendicular to the main surface of the interposer 100. For example, the semiconductor substrate 101 may be located on a side close to the second encapsulation layer, and the interconnection structure 106 is located on a side of the semiconductor substrate 101 away from the second encapsulation layer and close to the chip. The conductive connector 107 is located on a side of the interconnection structure 106 away from the semiconductor substrate 101.

[0047] For example, the adapter board 100 may be a silicon-based adapter board, and the semiconductor substrate 101 may be or include a silicon substrate; or, the semiconductor substrate 101 may also include other semiconductor materials such as germanium. In some embodiments, a through substrate via (TSV) 102 is provided in the semiconductor substrate 101 to provide electrical connection between conductive members located on opposite sides of the semiconductor substrate 101. For example, the interconnect structure 106 includes an inorganic dielectric structure 103 and a conductive structure 105. The inorganic dielectric structure 103 may be a single-layer or multi-layer structure, and may include inorganic dielectric materials such as silicon oxide and silicon nitride. The conductive structure 105 is embedded in the inorganic dielectric structure, and may include one or more layers of conductive traces and conductive vias (not shown), and the conductive vias may be used to provide electrical connections between conductive traces of different layers, electrical connections between conductive traces and substrate vias, and / or electrical connections between conductive traces and conductive connectors 107.

[0048] In some embodiments, the thermal expansion coefficients of the semiconductor substrate 101 and the interconnect structure 106 (e.g., the inorganic dielectric structure 103 thereof) are both smaller than the thermal expansion coefficient of the first encapsulation layer 110, and smaller than the thermal expansion coefficient of the second encapsulation layer 120. The Young's modulus of the semiconductor substrate 101 and the interconnect structure 106 (e.g., the inorganic dielectric structure 103 thereof) may be larger than the Young's modulus of the first encapsulation layer 110, and larger than the Young's modulus of the second encapsulation layer 120.

[0049] In some embodiments, passive devices such as capacitors may be further provided in the adapter board 100. For example, the passive devices such as capacitors may be embedded in at least one of the semiconductor substrate 101 and the interconnect structure 106. For example, the capacitor may be or include a deep trench capacitor (DTC). By providing passive devices such as capacitors on the adapter board 100, it is helpful to reduce the power supply noise of the package structure and improve the power supply performance of the package structure and other device performance.

[0050] In some embodiments, the chip 80 may include a chip substrate 81, a device layer 82, and a conductive connector 83, etc.; the chip substrate 81 is a semiconductor substrate, and may be or include a silicon substrate, or may also include other semiconductor materials such as germanium; the device layer 82 is disposed on one side of the chip substrate 81, and may include active devices (e.g., transistors), passive devices (e.g., capacitors, inductors, etc.) or a combination thereof and a chip interconnection structure, and each device may be connected through the chip interconnection structure; the conductive connector 83 is located on the side of the device layer away from the substrate, and may be electrically connected to various devices on the chip substrate through the chip interconnection structure; the conductive connector 83 serves as an external connection point of the chip 80 to provide electrical connection between the chip 80 and other components (e.g., the adapter board 100), and may be referred to as the input / output (I / O) contact of the chip. The side of the chip 80 close to the device layer (e.g., the side with the conductive connector 83) may be referred to as the front side or active side of the chip, and the side of the chip where the substrate is located (i.e., the side opposite to the front side) may be referred to as the back side. For example, each chip 80 may be flip-chip mounted on the interposer 100 such that the front side thereof faces the interposer 100 .

[0051] In some embodiments, the chip 80 may be electrically connected to the interposer 100 via a conductive bump 108. For example, the conductive bump 108 is disposed between the conductive connector 83 of the chip 80 and the conductive connector 107 of the interposer 100 to provide an electrical connection between the chip 80 and the interposer 100. For example, the conductive bump 108 may include a conductive material such as metal and / or solder, and may be or include a micro-bump.

[0052] In some embodiments, the semiconductor substrate 101 of the adapter board 100 and the chip substrate 81 include similar and identical or different materials; for example, the semiconductor substrate 101 and the chip substrate 81 may both include semiconductor materials such as silicon. In some embodiments, the interconnect structure 106 of the adapter board 100 and the chip interconnect structure in the chip 80 include similar and identical or different materials, for example, both include inorganic dielectric materials. For example, the chip interconnect structure may include an inorganic dielectric structure and multilayer conductive traces and conductive vias embedded in the inorganic dielectric structure, and the inorganic dielectric structure may include inorganic dielectric materials such as silicon oxide and silicon nitride.

[0053] In some embodiments, since the material of the adapter plate 100 is similar to that of the chip, the thermal expansion coefficients of the adapter plate 100 and the chip 80 may match each other, for example, be close to or substantially the same; the Young's modulus of the adapter plate 100 and the chip 80 may also be close to or substantially the same. For example, the thermal expansion coefficient of the semiconductor substrate 101 of the adapter plate 100 matches the thermal expansion coefficient of the chip substrate 81, for example, may be substantially the same; the thermal expansion coefficient of the inorganic dielectric structure 103 in the interconnect structure 106 of the adapter plate 100 matches the thermal expansion coefficient of the inorganic dielectric structure in the chip interconnect structure, for example, may be substantially the same. The Young's modulus of the semiconductor substrate 101 may be substantially the same as that of the chip substrate 81, and the Young's modulus of the inorganic dielectric structure 103 in the adapter plate 100 may be substantially the same as that of the inorganic dielectric structure in the chip interconnect structure. That is, the thermal expansion coefficient of the chip 80 is smaller than that of the first encapsulation layer 110 , and the Young's modulus of the chip 80 is greater than that of the first encapsulation layer 110 .

[0054] For example, under conditions such as high temperature, the chip and the first encapsulation layer produce different degrees of thermal deformation due to the mismatch of thermal expansion coefficients, and the chip may be subjected to stress from the first encapsulation layer; in some embodiments, since the adapter plate 100 and the chip 80 have the above-mentioned characteristic settings such as matching thermal expansion coefficients, the adapter plate 100 can help to disperse the stress from the first encapsulation layer 110, thereby reducing the stress on the chip from the first encapsulation layer 110, thereby avoiding adverse effects on device performance.

[0055] In some embodiments, the first encapsulation layer 110 encapsulates at least the sidewalls of the chip 80, and the second encapsulation layer 120 encapsulates the sidewalls of the conductive member 119. The first encapsulation layer 110, the interposer 100, and the second encapsulation layer 120 may have sidewalls that are substantially aligned in a direction perpendicular to the main surface of the interposer 100.

[0056] For example, the first encapsulation layer 110 encapsulates the sidewall of the chip 80, and the surface of the first encapsulation layer 110 away from the interposer 100 may be substantially flush with the surface of the chip 80 away from the interposer 100 in a direction parallel to the main surface of the interposer 100 (e.g., a horizontal direction including the second direction D2). In other embodiments, the first encapsulation layer 110 may encapsulate the sidewall of the chip 80 and its surface away from the interposer 100; that is, in the first direction D1, compared to the main surface of the interposer 100, the surface of the first encapsulation layer 110 away from the interposer 100 may be higher than the surface of the chip 80 away from the interposer 100.

[0057] In some embodiments, the second encapsulation layer 120 encapsulates the sidewall of the conductive member 119, and the surface of the second encapsulation layer 120 away from the adapter plate 100 may be substantially flush with the surface of the conductive member 119 away from the adapter plate 100 in a direction parallel to the main surface of the adapter plate 100. That is, in a direction perpendicular to the main surface of the adapter plate (e.g., the first direction D1), the height of the conductive member 119 may be substantially equal to the thickness of the second encapsulation layer 120.

[0058] In some embodiments, the height of the conductive member 119 and the thickness of the second encapsulation layer 120 can be adjusted based on product design and requirements. For example, the size (e.g., thickness, etc.) of the second encapsulation layer 120 can be set and adjusted based on the size (e.g., thickness, width, area, etc.) of the chip 80 and the first encapsulation layer 110, so that the first encapsulation layer 110 and the second encapsulation layer 120 can cooperate with each other, thereby well balancing and controlling the thermal deformation of the transfer board and the materials on both sides thereof, thereby avoiding or reducing package warpage.

[0059] In some embodiments, the first encapsulation layer 110 and the second encapsulation layer 120 may have volumes that match each other, thereby facilitating balancing the thermal deformation of the two; for example, the volumes of the first encapsulation layer and the second encapsulation layer may be adjusted according to the product design and the thermal expansion coefficient of the encapsulation material, so that under various temperature conditions, the first encapsulation layer and the second encapsulation layer may have approximately the same degree of thermal expansion. For example, the area occupied by the second encapsulation layer in the direction parallel to the main surface of the adapter plate (i.e., the horizontal direction including the second direction D2) may be larger than the area occupied by the first encapsulation layer in the horizontal direction. In this case, the thickness of the second encapsulation layer 120 may be smaller than the thickness of the first encapsulation layer 110, thereby facilitating balancing the thermal deformation of the first encapsulation layer and the second encapsulation layer under conditions such as high temperature.

[0060] Continue to refer Figure 2 and Figure 3In some embodiments, the conductive terminal 150 is directly formed on the conductive member 119 and is directly in contact with the conductive member 119 to be electrically connected. For example, the conductive terminal 150 may include a conductive column 130 and a solder ball 140; the conductive column 130 is in contact with the conductive member 119, and the solder ball 140 is disposed on a side of the conductive column 130 away from the second encapsulation layer 120.

[0061] Figure 4 Schematic cross-sectional views of package structures according to other embodiments of the present disclosure are shown. Figure 2 or Figure 3 The package structure shown is similar, with the difference being that the package structure of this embodiment further includes a redistribution structure.

[0062] In some embodiments, the packaging structure also includes a redistribution structure, which is arranged on a side of the second encapsulation layer away from the adapter board and is electrically connected to the conductive component, wherein the conductive terminal is arranged on a side of the redistribution structure away from the second encapsulation layer and is electrically connected to the conductive component through the redistribution structure.

[0063] In some embodiments, the redistribution structure includes an organic dielectric structure and a redistribution layer embedded in the organic dielectric structure, and the thermal expansion coefficient of the redistribution structure is greater than the thermal expansion coefficient of the adapter. In some embodiments, the line width of the conductive traces in the redistribution layer is greater than the line width of the conductive traces in the conductive structure of the adapter.

[0064] refer to Figure 4 In some embodiments, the package structure 500 further includes a redistribution structure 125, which is disposed on a side of the second encapsulation layer 120 away from the adapter 100 and is electrically connected to the conductive member 119, and is electrically connected to the adapter 100 through the conductive member 119. For example, the redistribution structure 125 may include an organic dielectric structure 121 and a redistribution layer 122, the redistribution layer 122 is embedded in the organic dielectric structure 121, and may include one or more layers of conductive traces and / or conductive vias, the conductive vias being used to provide electrical connections between conductive wires of different layers, between conductive wires and the conductive member 119, and / or between conductive wires and the conductive terminals 150. It should be understood that the number of layers of conductive wires in the redistribution layer 122 shown in the figure is only for illustration, and the present disclosure is not limited thereto.

[0065] In some embodiments, the thermal expansion coefficient of the redistribution structure 125 is greater than the thermal expansion coefficient of the adapter board 100. For example, the thermal expansion coefficient of the organic dielectric structure 121 is greater than the thermal expansion coefficient of the semiconductor substrate 101 and / or the inorganic dielectric structure 103 in the adapter board 100. In this embodiment, the thermal expansion coefficient of the first encapsulation layer 110 located on the first side of the adapter board 100 is greater than the thermal expansion coefficient of the adapter board 100, and the thermal expansion coefficient of the second encapsulation layer 120 and the redistribution structure 125 located on the second side of the adapter board 100 is also greater than the thermal expansion coefficient of the adapter board 100; under conditions such as high temperature, the second encapsulation layer 120 and the redistribution structure 125 located on the second side of the adapter board 100 as a whole resist the thermal deformation of the first encapsulation layer located on the first side of the adapter board 100, so that the thermal deformation of the adapter board and the material layers on the opposite sides thereof can be balanced and controlled, for example, the thermal expansion degrees of the material layers on the opposite sides of the adapter board under the same temperature conditions can be substantially the same, thereby avoiding or reducing package warping. In some embodiments, the dimensions and other settings of the first encapsulation layer, the second encapsulation layer, and the redistribution structure may be adjusted based on product design and requirements, so that package warping may be effectively avoided or reduced.

[0066] In some embodiments, the conductive terminal 150 is disposed on a side of the redistribution structure 125 away from the second encapsulation layer 120 and is electrically connected to the redistribution layer 122 in the redistribution structure 125 , and further electrically connected to the chip 80 through the redistribution layer 122 , the conductive component 119 and the adapter board 100 .

[0067] In some embodiments, at least part of the interconnection between the plurality of chips 80 is realized through the adapter 100, and the rewiring structure 125 is at least used to provide electrical connection between the adapter 100 and the conductive terminal 150. In some embodiments, the rewiring structure 125 can also be used to provide interconnection between the plurality of chips 80. For example, part of the interconnection between the plurality of chips 80 is realized through the adapter 100, and another part of the interconnection between the plurality of chips 80 can be realized through the adapter 100, the conductive member 119 and the rewiring structure 125. For example, the line width / line spacing of the conductive traces in the rewiring layer 122 can be different from the line width / line spacing of the conductive traces of the conductive structure 105 in the adapter 100. For example, the line width / line spacing of the conductive traces in the rewiring layer 122 can be greater than the line width / line spacing of the conductive traces in the conductive structure 105 of the adapter 100. By providing conductive lines with different line widths / line spacings in the adapter 100 and the rewiring structure 125, different interconnection requirements between the plurality of chips can be met. Furthermore, the thermal expansion coefficient of the redistribution structure 125 is greater than the thermal expansion coefficient of the adapter board 100 , which can also help balance the thermal deformation of the materials on both sides of the adapter board and avoid or reduce the warping of the packaging structure.

[0068] refer to Figures 2 to 4In some embodiments, the package structure 500 further includes an underfill layer 109. The underfill layer may include an organic material such as epoxy resin. The underfill layer 109 may fill the space between the chip 80 and the adapter board 100 and surround the conductive bump 108 in a direction parallel to the main surface of the adapter board. In some embodiments, the underfill layer 109 may also extend to cover the sidewalls of the chip 80. The first encapsulation layer 110 also encapsulates the underfill layer 109. The material of the underfill layer 109 is similar to that of the first encapsulation layer 110 and has a similar thermal expansion coefficient. For example, the thermal expansion coefficient of the underfill layer 109 is also greater than the thermal expansion coefficient of the adapter board 100. In the case where the underfill layer 109 is provided, the thermal expansion generated by the underfill layer and the first encapsulation layer on the first side of the adapter board and the thermal expansion generated by the second encapsulation layer on the second side of the adapter board counteract each other.

[0069] In some embodiments, the bottom filling layer 109 may also be omitted, and the first encapsulation layer 110 may further extend to fill the space between the chip 80 and the interposer 100 and surround the conductive bumps 108 .

[0070] Figure 5 Schematic cross-sectional views of package structures according to other embodiments of the present disclosure are shown.

[0071] In some embodiments, the packaging structure further includes a packaging substrate, which is disposed on a side of the second encapsulation layer away from the adapter plate and is electrically connected to the adapter plate through the conductive terminal and the conductive member. In some embodiments, the packaging structure further includes a bottom filling layer, which is disposed between the second encapsulation layer and the packaging substrate and surrounds the conductive terminal in a direction parallel to the main surface of the packaging substrate.

[0072] refer to Figure 5 In some embodiments, the package structure 500 may further include a package substrate 200, which is disposed on a side of the second encapsulation layer 120 away from the transfer board 100 and is electrically connected to the transfer board 100 through the conductive terminal 150 and the conductive member 119. For example, Figures 2 to 4 The package structure shown is a chip-on-wafer (CoW) package. Figure 5 The package structure shown is a chip-on-wafer-on-substrate (CoWoS) package, and can be formed by mounting a CoW package on a package substrate. For example, the CoW package is electrically connected to the package substrate 200 via the conductive terminal 150. It should be understood that Figure 5 The CoW package in the package structure shown can have Figures 2 to 4 Any of the structures shown, and herein Figure 2The structure shown is taken as an example for illustration.

[0073] In some embodiments, the package structure 500 may further include a reinforcement structure 210 and a conductive terminal 220. The conductive terminal 220 is disposed on a side of the package substrate 200 away from the adapter board 100 and can be used to further connect the package structure 500 to other package components, such as a printed circuit board. The reinforcement structure 210 and the CoW package are disposed on the same side of the package substrate 200. For example, the reinforcement structure 210 is disposed on an edge of the package substrate 200 and can be attached to the package substrate 200 through an adhesive layer 201. The CoW package may be located in an area surrounded by the reinforcement structure 210 in a direction parallel to the main surface of the package substrate. The reinforcement structure 210 may be helpful in controlling and reducing the warping of the package substrate and the overall package structure. In some embodiments, as Figure 5 As shown, the reinforcement structure 210 may be a reinforcement ring; in an alternative embodiment, the reinforcement structure 210 may also be a reinforcement cover, that is, it may also include a cover portion located on the side of the chip 80 away from the transfer board.

[0074] In some embodiments, the package structure 500 may further include an underfill layer 160. The underfill layer 160 may fill the space between the package structure 500 and the package substrate 200 and surround the plurality of conductive terminals 150 in a direction parallel to the main surface of the package substrate.

[0075] The bottom filling layer 160 covers and contacts the surface of the second encapsulation layer 120 away from the transfer board 100; or, in an embodiment where a redistribution structure is provided ( Figure 4 ), the bottom filling layer 160 covers and contacts the surface of the redistribution structure (e.g., its organic dielectric structure) away from the transfer board 100. In some embodiments, the bottom filling layer 160 may also cover and contact the sidewalls of the package structure 500, such as part of the sidewalls of the CoW. Figure 5 As shown, the bottom filling layer 160 may cover the sidewalls of the second encapsulation layer 120, the sidewalls of the transfer board 100, and part of the sidewalls of the first encapsulation layer 110. In other examples, the bottom filling layer 160 may also cover part or all of the sidewalls of the second encapsulation layer 120, but not the sidewalls of the transfer board 100 and the first encapsulation layer 110; or, the bottom filling layer 160 may cover the sidewalls of the second encapsulation layer 120 and part or all of the sidewalls of the transfer board 100, but not the sidewalls of the first encapsulation layer 110.

[0076] An embodiment of the present disclosure provides a method for manufacturing a packaging structure, comprising: providing an adapter board, the adapter board having a first side and a second side opposite to each other in a direction perpendicular to its main surface; mounting a chip on the first side of the adapter board and electrically connecting the chip to the adapter board; forming a first encapsulation layer on the first side of the adapter board to encapsulate the chip; forming a conductive member and a second encapsulation layer on the second side of the adapter board, the conductive member being embedded in the second encapsulation layer and electrically connected to the adapter board; and forming a conductive terminal on a side of the second encapsulation layer away from the adapter board to electrically connect to the conductive member, wherein the thermal expansion coefficient of the first encapsulation layer is greater than the thermal expansion coefficient of the adapter board, and the thermal expansion coefficient of the second encapsulation layer is greater than the thermal expansion coefficient of the adapter board.

[0077] In some embodiments, forming the second encapsulation layer on the second side of the adapter plate includes: forming a second encapsulation material layer to cover the surface of the second side of the adapter plate and the side walls of the conductive component and its surface away from the adapter plate; removing a portion of the second encapsulation material layer to expose the surface of the conductive component away from the adapter plate, and forming the second encapsulation layer.

[0078] In some embodiments, after forming the conductive component and the second encapsulating layer, and before forming the conductive terminal, it also includes: forming a rewiring structure on a side of the second encapsulating layer away from the adapter board to be electrically connected to the conductive component; wherein the conductive terminal is formed on a side of the rewiring structure away from the second encapsulating layer, and is electrically connected to the rewiring structure.

[0079] In some embodiments, the method for manufacturing a packaging structure further includes: providing a packaging substrate, and mounting the chip package on the packaging substrate, wherein the chip package is electrically connected to the packaging substrate through the conductive terminals.

[0080] Figures 6 to 13 Schematic cross-sectional views showing structures of various steps in a method for manufacturing a package structure according to some embodiments of the present disclosure.

[0081] refer to Figure 6 In some embodiments, a carrier 60 is provided. The carrier 60 may be a glass carrier or the like that can provide support for a structure subsequently placed thereon and will be removed in a subsequent process, so it may also be referred to as a temporary carrier.

[0082] An adapter plate 100 is provided and attached to a carrier 60. For example, the adapter plate 100 may be mounted on the carrier 60 via an attachment layer 61. The attachment layer 61 may be or include a temporary bonding and debonding (TBDB) layer, and may be used to bond the adapter plate 100 to the carrier 60 in this step, and may be used to detach the adapter plate 100 and the structure thereon from the carrier 60 in a subsequent step.

[0083] For example, the adapter board 100 has a first side S1 and a second side S2 that are opposite to each other in a first direction D1 perpendicular to its main surface. For example, the first side S1 is a side close to the interconnection structure of the adapter board 100, and the second side S2 is a side close to the substrate of the adapter board 100, or vice versa. For example, the second side S2 of the adapter board 100 faces the carrier board 60 and is attached to the carrier board 60 through the attachment layer 61. The specific structure of the adapter board 100 can be referred to the above description of Figure 3 The content of the description.

[0084] Continue to refer Figure 6 , one or more chips 80 are mounted on the first side S1 of the interposer 100, and the chips 80 are electrically connected to the interposer 100. For example, the chip 80 can be bonded to the interposer 100 through a conductive bump 108, and the conductive bump 108 can be or include a micro bump, etc. For example, a plurality of chips 80 can be arranged side by side on the interposer 100, and the plurality of chips 80 can include chips of the same type or different types.

[0085] For example, the number and type of chips can be selected according to product requirements; for example, one or more chips 80 may include a system on chip (SoC), a digital signal processor (DSP) chip, a graphic processing unit (GPU), an application specific integrated circuit (ASIC) chip, a high bandwidth memory chip (HBM) and other memory chips, a central processing unit (CPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), and a general-purpose graphics processing unit (GPGPU). One or more.

[0086] After the chip 80 is bonded to the transfer board 100, a bottom filling layer 109 may be formed by a bottom filling process, which may include a dispensing process. The bottom filling layer 109 fills the space between each chip 80 and the transfer board 100, and surrounds and protects the conductive bumps 108. In some embodiments, the bottom filling layer 109 may also extend to cover the sidewalls of the chip 80, for example, it may cover part or all of the sidewalls of the chip 80. The bottom filling layer may include an organic material such as epoxy resin.

[0087] Next, a first encapsulation layer 110 is formed on the first side S1 of the interposer 100 to encapsulate the chip 80 and the bottom filling layer 109. In some embodiments, the bottom filling process may be omitted and the first encapsulation layer 110 may be directly formed to encapsulate the chip and fill the space between the chip and the interposer.

[0088] For example, the first encapsulation layer 110 may include a molding compound, which may include, for example, an epoxy molding compound (EMC), and may be formed by a molding process. The first encapsulation layer 110 may include a main material and a filler; the main material may include an organic material such as epoxy resin; the filler is dispersed in the organic material and may include a semiconductor material, an inorganic insulating material, etc., such as silicon, aluminum oxide, etc. In some examples, the physical properties such as the thermal expansion coefficient of the first encapsulation layer may be adjusted by adjusting the type of filler and its proportion in the encapsulation material, so as to obtain a first encapsulation layer with desired properties. The bottom filling layer may also include a filler, and its physical properties such as the thermal expansion coefficient may also be adjusted by adjusting the type and proportion of the filler.

[0089] For example, the bottom filling layer can also be regarded as part of the first encapsulation layer. The first encapsulation layer can generally refer to the encapsulation material located on the first side of the adapter board for surrounding the encapsulated chip, and in some embodiments, it can include a molding compound and a bottom filling layer, or in other embodiments, the bottom filling layer can be omitted and only the molding compound can be included.

[0090] For example, the formation process of the first encapsulation layer 110 may include forming a first encapsulation material layer on the interposer 100, wherein the first encapsulation material layer encapsulates the sidewall of the chip 80 and the surface thereof on the side away from the interposer 100; then, the first encapsulation material layer may be subjected to a planarization process to remove the portion of the first encapsulation material layer located on the side away from the interposer of the chip 80, thereby exposing the surface of the chip 80 on the side away from the interposer. The planarization process may include a grinding process, such as a physical grinding process or a chemical mechanical polishing process. After the planarization process, the surface of the first encapsulation layer 110 on the side away from the interposer 100 may be substantially flush with the surface of the chip 80 on the side away from the interposer in a direction parallel to the main surface of the interposer. In other embodiments, the planarization process may be omitted or the chip surface may not be exposed after the planarization process, and the first encapsulation layer 110 may be formed to also encapsulate the surface of the chip 80 on the side away from the interposer.

[0091] refer to Figure 6 and Figure 7 , remove the carrier 60 and the attachment layer 61, and expose the second side S2 of the adapter plate 100. For example, the attachment layer 61 may be irradiated with laser or ultraviolet (UV) light, so that the attachment layer 61 loses its stickiness under the light, so that the attachment layer 61 and the carrier 60 can be separated from the overlying structure such as the adapter plate 100, and the second side S2 of the adapter plate 100 is exposed. Figure 6The structure is turned upside down to facilitate subsequent processes on the second side of the adapter plate 100.

[0092] refer to Figure 7 , a conductive member 119 is formed on the second side S2 of the adapter board 100 to be electrically connected to the adapter board 100. For example, the conductive member 119 may be formed in a substrate through hole (eg, Figure 3 The conductive member 119 may include a plurality of conductive pillars, and the plurality of conductive pillars may be arranged corresponding to the plurality of substrate through-holes of the adapter plate 100, for example, one-to-one. The conductive member 119 may include a metal material such as copper, and may be formed by a plating process such as electroplating.

[0093] In some embodiments, the conductive member 119 may be formed on the second side S2 of the interposer 100 before the interposer 100 is bonded to the carrier 60 and may also be considered as a part of the interposer 100. Figure 6 In the steps shown, before the adapter board 100 is mounted on the carrier board 60, the conductive member 119 is formed on the second side of the adapter board 100 and is electrically connected to the substrate through-hole of the adapter board 100; when the adapter board 100 is mounted on the carrier board 60, the conductive member 119 can be embedded in the attachment layer 61, and the attachment layer can be Figure 6 The conductive component 119 is protected in the process steps shown; after that, the attachment layer 61 and the carrier 60 are removed, so that the second side of the transfer board 100 and the conductive component 119 located on the second side are exposed.

[0094] In other embodiments, the conductive member 119 may also be formed on the second side of the adapter board 100 after removing the attachment layer 61 and the carrier board 60. For example, after removing the attachment layer 61 and the carrier board 60, the substrate through-hole located on the second side of the adapter board 100 is exposed, and then the conductive member 119 is formed to be electrically connected to the substrate through-hole.

[0095] refer to Figure 8, a second encapsulation material layer 12 is formed on the second side S2 of the adapter board 100 to cover the surface of the adapter board 100 away from the chip 80, and to encapsulate the sidewall of the conductive member 119 and the surface of the side away from the adapter board 100. The material of the second encapsulation material layer 12 may be the same as or similar to the material of the first encapsulation layer 110. For example, the second encapsulation material layer 12 may include a molding compound, such as an epoxy resin molding compound, and may be formed by a molding process. Similar to the first encapsulation layer, the second encapsulation material layer 12 may include a main material and a filler; the main material may include an organic material such as epoxy resin; the filler is dispersed in the organic material and may include a semiconductor material, an inorganic insulating material, etc., for example, silicon, aluminum oxide, etc. In some examples, the physical properties such as the thermal expansion coefficient of the second encapsulation material layer may be adjusted by adjusting the type of filler and its proportion in the encapsulation material, so as to obtain an encapsulation layer with desired properties.

[0096] refer to Figure 8 and Fig. 9 , a planarization process is performed on the second encapsulation material layer 12 to remove a portion of the second encapsulation material layer 12, and to form a second encapsulation layer 120, and to expose the surface of the conductive member 119 on the side away from the adapter plate 100. For example, the planarization process may include a grinding process, such as a physical grinding process or a chemical mechanical polishing process. For example, after the planarization process, the surface of the second encapsulation layer 120 on the side away from the adapter plate 100 may be substantially flush with the surface of the conductive member 119 on the side away from the adapter plate 100 in a direction parallel to the main surface of the adapter plate.

[0097] refer to Fig.10 A conductive terminal 150 is formed on a side of the second encapsulation layer 120 away from the interposer 100 . For example, the conductive terminal 150 is formed on the conductive member 119 and is electrically connected to the conductive member 119 .

[0098] In some embodiments, Figures 6 to 10 The process shown is a wafer level process and is Fig.10 In the steps shown, a wafer-level structure 50 including a plurality of package structures 500 (eg, CoW packages) is formed. For example, the wafer-level structure 50 has a plurality of package regions PR, and a package structure 500 is formed in each package region PR. It should be understood that Figures 6 to 10 Only the structure of one package area PR is specifically shown, and Fig.10The ellipsis in the figure schematically indicates that there may be other packaging areas around the packaging area PR, and the packaging processes performed in each packaging area may be substantially the same, and the packaging structures formed in each packaging area have substantially the same structure. For example, the adapter plate 100 is formed from a silicon wafer, and is wafer-shaped in the wafer-level process step, and extends continuously in multiple packaging areas PR. The first encapsulation layer 110 and the second encapsulation layer 120 are formed on opposite sides of the adapter plate 100, and may also extend continuously in multiple packaging areas PR.

[0099] refer to Fig.10 and Fig.11 , a cutting process is performed on the wafer-level structure 50 to separate the plurality of package structures 500. For example, a cutting process may be performed along the cutting line 300 to form a plurality of independent package structures 500. The cutting process may be or include a mechanical cutting process, a laser cutting process, or a combination thereof. Afterwards, the package structure 500 may be turned upside down for connection with a package substrate. Fig.11 A package structure 500 , ie, a CoW package, is shown after a sawing process. Fig.10 and Fig.11 The package structure 500 shown may also be referred to as a chip package.

[0100] In some embodiments, the first encapsulation layer 110, the adapter plate 100, and the second encapsulation layer 120 are all subjected to a cutting process, and after the cutting process, the side walls of the first encapsulation layer 110, the side walls of the adapter plate 100, and the side walls of the second encapsulation layer 120 can be roughly aligned in a direction perpendicular to the main surface of the adapter plate (for example, the first direction D1).

[0101] refer to Fig.12 , providing a packaging substrate 200, and Fig.11 The CoW package is shown mounted on a package substrate 200. For example, the CoW package can be electrically connected to the package substrate 200 via a conductive terminal 150. In some embodiments, the conductive terminal 150 may include a solder ball, such as a controlled collapsed chip connection (C4) bump. The CoW package can be soldered to the package substrate 200 by a soldering process.

[0102] Under the high temperature conditions of the welding process, the materials of different components in the CoW package will undergo different degrees of thermal deformation (e.g., thermal expansion) due to different thermal expansion coefficients. For example, the thermal expansion coefficients of the first encapsulation layer 110 and the second encapsulation layer 120 are both greater than the thermal expansion coefficient of the adapter 100, so the thermal expansion degree of the first encapsulation layer 110 and the second encapsulation layer 120 is greater than the thermal expansion degree of the adapter 100. The thermal expansion of the first encapsulation layer 110 and the second encapsulation layer 120 on both sides of the adapter 100 can counteract each other, for example, the first encapsulation layer and the second encapsulation layer can have approximately the same degree of thermal expansion to balance and control the thermal deformation of the adapter 100 and the encapsulation layers on both sides thereof, thereby avoiding or reducing the warping of the CoW package. For example, in the above process, the adapter 100 will be subjected to a first stress (e.g., downward stress) from the first encapsulation layer 110, and will be subjected to a second stress (e.g., upward stress) from the second encapsulation layer 120, and the first stress and the second stress are in opposite directions and can offset each other at least partially. In addition, the thermal expansion coefficients of the adapter plate 100 and the chip 80 are roughly matched, so the adapter plate 100 can also help disperse the stress of the first encapsulation layer 110 on the chip 80. By arranging the first encapsulation layer and the second encapsulation layer on opposite sides of the adapter plate, the stress can be balanced, and the adapter plate can be prevented from warping due to a large stress on one side, thereby avoiding or reducing the warping of the entire packaging structure. In addition, compared with the encapsulation layer, the rigidity of the adapter plate 100 is relatively large, which can also help control the warping.

[0103] refer to Fig.13 After the CoW package is mounted on the package substrate 200, an underfill layer 160 may be formed by an underfill process. In some embodiments, a reinforcement structure 210 may be further mounted on the package substrate 200 to facilitate controlling the warpage of the package structure 500. In some embodiments, a conductive terminal 220 is formed on a side of the package substrate 200 away from the package structure 500, and the conductive terminal 220 may be or include a ball grid array (BGA).

[0104] In the package structure and manufacturing method of the embodiment of the present disclosure, by arranging the first encapsulation layer and the second encapsulation layer on opposite sides of the adapter board, the warping of the package structure can be avoided or reduced. For example, under conditions such as high temperature, the thermal expansion of the second encapsulation layer can resist the thermal expansion of the encapsulation material such as the first encapsulation layer (plastic encapsulation material and / or bottom filling layer), and the degree of thermal expansion of the second encapsulation layer can be roughly the same as the degree of thermal expansion of the first encapsulation layer, and finally the thermal expansion and contraction balance of the materials on both sides of the adapter board is achieved, thereby avoiding or reducing the warping of the overall package structure. For example, the package structure can be prevented from warping under high temperature conditions in the bonding process of installing the chip package (for example, CoW package) to the package substrate, thereby avoiding defects such as cold soldering or bridging, ensuring effective electrical connection between the chip package and the package substrate, and thus improving the device performance and reliability of the package structure. In some examples, when the CoW package size exceeds 2 times the mask size (for example, 33mm×52mm) or more, and the number of chips on the adapter board exceeds 8 or more, the application of the package structure and manufacturing method of the embodiment of the present disclosure can also greatly reduce defects such as cold soldering and bridging, and improve the package yield.

[0105] There are a few points to note:

[0106] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures may refer to the general design; (2) In the absence of conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0107] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A packaging structure, comprising: an adapter plate having a first side and a second side opposite to each other in a direction perpendicular to a major surface thereof; A chip, disposed on the first side of the adapter board and electrically connected to the adapter board; A first encapsulation layer, disposed on the first side of the adapter plate and encapsulating the chip; A second encapsulation layer, disposed on the second side of the adapter plate; A conductive member, embedded in the second encapsulation layer and electrically connected to the adapter plate; as well as a conductive terminal, disposed on a side of the second encapsulation layer away from the adapter plate and electrically connected to the conductive component, wherein the thermal expansion coefficient of the first encapsulation layer is greater than the thermal expansion coefficient of the adapter plate, and the thermal expansion coefficient of the second encapsulation layer is greater than the thermal expansion coefficient of the adapter plate, The adapter plate includes a semiconductor substrate and an interconnect structure, wherein the interconnect structure is disposed on one side of the semiconductor substrate in a direction perpendicular to a main surface of the adapter plate and includes an inorganic dielectric structure and a conductive structure embedded in the inorganic dielectric structure; as well as The thermal expansion coefficients of the semiconductor substrate and the interconnect structure of the transfer board are both smaller than the thermal expansion coefficient of the first encapsulation layer, and smaller than the thermal expansion coefficient of the second encapsulation layer. 2 . The packaging structure according to claim 1 , wherein an absolute value of a difference between a thermal expansion coefficient of the first encapsulation layer and a thermal expansion coefficient of the second encapsulation layer is less than 20 ppm / ° C. 3 . The packaging structure according to claim 1 , wherein a Young's modulus of the interposer is greater than Young's moduli of the first encapsulation layer and the second encapsulation layer. 4 . The package structure according to claim 1 , wherein the first encapsulation layer, the interposer, and the second encapsulation layer have sidewalls aligned in a direction perpendicular to a major surface of the interposer. 5 . The packaging structure according to claim 1 , wherein a surface of the second encapsulation layer away from the interposer is flush with a surface of the conductive member away from the interposer in a direction parallel to a main surface of the interposer. The package structure according to claim 1 , wherein the conductive terminal is in direct contact with the conductive member to be electrically connected.

7. The package structure according to claim 1, further comprising: a redistribution structure, disposed on a side of the second encapsulation layer away from the adapter plate and electrically connected to the conductive member, The conductive terminal is disposed on a side of the redistribution structure away from the second encapsulation layer and is electrically connected to the conductive component through the redistribution structure. 8 . The packaging structure according to claim 7 , wherein the redistribution structure comprises an organic dielectric structure and a redistribution layer embedded in the organic dielectric structure, and a thermal expansion coefficient of the redistribution structure is greater than a thermal expansion coefficient of the adapter board. 9 . The packaging structure according to claim 8 , wherein the line width of the conductive traces in the redistribution layer is greater than the line width of the conductive traces in the conductive structure of the adapter board.

10. The packaging structure according to any one of claims 1 to 9, further comprising: The packaging substrate is disposed on a side of the second encapsulation layer away from the adapter plate and is electrically connected to the adapter plate through the conductive terminals and the conductive components.

11. The package structure according to claim 10, further comprising: The bottom filling layer is disposed between the second encapsulation layer and the packaging substrate and surrounds the conductive terminal in a direction parallel to the main surface of the packaging substrate.

12. A method for manufacturing a packaging structure, comprising: providing an adapter plate having a first side and a second side opposite each other in a direction perpendicular to a major surface thereof; Mounting a chip on the first side of the adapter board and electrically connecting the chip to the adapter board; forming a first encapsulation layer on the first side of the transfer board to encapsulate the chip; forming a conductive member and a second encapsulation layer on the second side of the adapter plate, wherein the conductive member is embedded in the second encapsulation layer and is electrically connected to the adapter plate; as well as A conductive terminal is formed on a side of the second encapsulation layer away from the transfer board to be electrically connected to the conductive member, thereby forming a chip package. wherein the thermal expansion coefficient of the first encapsulation layer is greater than the thermal expansion coefficient of the adapter plate, and the thermal expansion coefficient of the second encapsulation layer is greater than the thermal expansion coefficient of the adapter plate, The adapter plate includes a semiconductor substrate and an interconnect structure, wherein the interconnect structure is disposed on one side of the semiconductor substrate in a direction perpendicular to a main surface of the adapter plate and includes an inorganic dielectric structure and a conductive structure embedded in the inorganic dielectric structure; as well as The thermal expansion coefficients of the semiconductor substrate and the interconnect structure of the transfer board are both smaller than the thermal expansion coefficient of the first encapsulation layer, and smaller than the thermal expansion coefficient of the second encapsulation layer.

13. The method for manufacturing a package structure according to claim 12, wherein forming the second encapsulation layer on the second side of the transfer board comprises: forming a second encapsulation material layer to cover the surface of the second side of the adapter plate and the sidewall of the conductive member and the surface of the side away from the adapter plate; A portion of the second encapsulation material layer is removed to expose the surface of the conductive member at a side away from the transfer board, and to form the second encapsulation layer.

14. The method for manufacturing a package structure according to claim 12, wherein after forming the conductive member and the second encapsulation layer and before forming the conductive terminal, the method further comprises: forming a redistribution structure on a side of the second encapsulation layer away from the adapter plate to be electrically connected to the conductive member; The conductive terminal is formed on a side of the redistribution structure away from the second encapsulation layer and is electrically connected to the redistribution structure.

15. The method for manufacturing a packaging structure according to any one of claims 12 to 14, further comprising: A packaging substrate is provided, and the chip package is mounted on the packaging substrate, wherein the chip package is electrically connected to the packaging substrate through the conductive terminals.

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