Semiconductor device structure, preparation method thereof and corresponding chip

Abstract

The invention discloses a semiconductor device structure, a preparation method thereof and a corresponding chip, and belongs to the technical field of semiconductor devices. The semiconductor device structure comprises a gold-silver alloy bump and a UBM layer, the UBM layer is composed of a seed layer and an adhesion layer, the bottom of the gold-silver alloy bump is connected with the seed layer, the adhesion layer is connected with a chip electrode, and the thermal expansion coefficient difference value of the gold-silver alloy bump and the adhesion layer is below 9ppm / K. According to the technical scheme provided by the invention, the technical problem that the gold-silver alloy bump and the existing UBM layer cannot pass a high-low temperature cycle reliability test is solved, the obtained semiconductor device structure and the corresponding chip can pass various reliability tests, the implementation feasibility is realized by replacing the pure gold bump with the gold-silver alloy, and the reliability of the gold-silver alloy bump is improved. Therefore, the production cost of the flip chip is greatly reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices and relates to a semiconductor device structure and a preparation method thereof and a corresponding chip. Background Art

[0002] Flip chip technology is mainly divided into two categories. One is soldering reflow solder balls. Although lead-free soldering materials are already mature, the solder becomes liquid at high temperatures, which may cause bridging between adjacent solder bumps and is not suitable for fine-pitch flip chip applications. The other is bonding through non-reflowable columnar gold bumps, in which the gold bumps are electrically connected to the substrate through hot press soldering or anisotropic conductive adhesive. Although the reliability of gold bumps is very good and there is no bridging problem between adjacent gold bumps, the material cost of gold is very high. For Chip-on-Film packaging, the gold content of a 12-inch wafer is about 0.8 grams, and for Chip-on-Glass packaging, the gold content of a 12-inch wafer is about 1.9 grams. With the rising price of gold, the development of new materials to replace gold is currently a hot topic of research. Considering some of the characteristic requirements for gold bumps, such as hardness, roughness, solderability and other indicators, there are not many alternative solutions, among which gold-silver alloy replacing gold bumps is one of the most promising solutions.

[0003] TWI469288B mentioned electroplated gold-silver bumps. In order to prevent the problem of silver oxidation, the top or side of the gold-silver bumps are electroplated or chemically plated with gold, palladium, copper or nickel to prevent silver oxidation, among which copper or nickel is more easily oxidized than silver. TW201044527A mentioned that the electroplated gold-silver bumps contain no less than 80% silver content, and then a protective layer is formed on the gold and silver surface by replacing gold or reducing gold to prevent silver oxidation. TW201019440A mentioned that the material of the silver bumps can be selected from pure silver or silver alloys. The silver alloy system of these silver bumps can contain no less than 80% silver content, and then a layer of pure gold or gold alloy is plated on the surface of the silver alloy to solve the problem of anti-oxidation.

[0004] CN117542818B found that by increasing the gold content in the gold-silver bump to more than 60%, the anti-oxidation or anti-sulfurization performance of the silver in the gold-silver bump can be significantly improved. In the same electroplating tank, a gold-silver alloy body with a gold content of 20% to 50% is first prepared at a low current density as a connecting layer, and then a protective layer with a gold content of more than 60% is prepared on the surface of the bump at a high current density, and the height of the protective layer is 10 to 500 nm. In order to solve the problem of poor welding caused by silver oxidation, CN118398588B selectively removes metallic silver on the surface of the bump by electrochemical etching to form a nanoporous gold structure, which will neither affect the hardness of the bump itself nor cause poor welding problems.

[0005] Although the above technical solutions propose to solve the problems of hardness, oxidation resistance or poor welding caused by sulfurization of gold and silver bumps, none of them mention the bonding strength between gold and silver bumps and different metal layers during the manufacturing process. After the bumps are prepared, they need to undergo various reliability tests, such as TCT (Temperature Cycle Test): -65℃(15min) ~150℃(15min), more than 350 cycles, PCT (Pressure Cooker Test): 121℃, 100% RH, 2atm, 168 hrs, THT (Temperature Humidity Test): 85℃ / 85% RH, 1000 hrs, HTST (High Temperature Storage Life Test): 150℃, 1000 hrs, LTST (Low Temperature Storage Life Test): -65℃, 1000 hrs. These tests are used to check the bonding strength between the bump and the under bump metal layer UBM (Under Bump Metal). The specific method is to perform a thrust shear test on the bump after the above reliability test to check whether the UBM layer underneath is exposed.

[0006] Most reliability failures occur due to poor bonding between the bump and the UBM layer, so the choice of UBM material metal is very important for the bonding force. In the process of trying to use gold-silver alloy bumps to replace gold bumps for flip chips, the inventor found that if the UBM layer used by the gold bumps in the prior art is used, the UBM layer will be exposed when the gold-silver alloy bumps are subjected to thrust shear tests after high and low temperature cycle tests, resulting in reliability failure. Only when the gold-silver alloy bumps pass the above reliability tests and thrust shear tests can they be used as a substitute for gold bumps in flip chips. Therefore, only by solving the technical problem that the gold-silver alloy bumps and the existing UBM layer cannot pass the high and low temperature cycle reliability test can the gold bumps be replaced by gold-silver alloy bumps in the field of flip chips, thereby significantly reducing production costs. Summary of the invention

[0007] The purpose of the present invention is to solve the technical problem that the gold-silver alloy bump and the existing UBM layer cannot pass the high and low temperature cycle reliability test. By selecting a suitable UBM material, the gold-silver alloy bump can pass various reliability tests and ensure the bonding strength of the device after the reliability test. In order to solve this technical problem, the inventor carried out a lot of theoretical analysis and experimental research, determined that the difference in thermal expansion coefficient between the gold-silver alloy bump and the UBM material is the key factor, and finally obtained the technical solution provided by the present invention, the specific content is as follows.

[0008] The primary aspect of the present invention is to provide a semiconductor device structure, including a gold-silver alloy bump and a UBM layer, wherein the UBM layer is composed of a seed layer and an adhesion layer, the bottom of the gold-silver alloy bump is connected to the seed layer, the adhesion layer is connected to the chip electrode, and the difference in thermal expansion coefficient between the gold-silver alloy bump and the adhesion layer is less than 9 ppm / K, ppm is 10 -6 .

[0009] Furthermore, the thickness of the gold-silver alloy bump is 5-20 μm.

[0010] Furthermore, the gold content in the gold-silver alloy bump is 10-60wt%. If the gold content is too low, the hardness, roughness, anti-oxidation and sulfidation properties of the gold-silver alloy bump are too different from those of the gold bump; if the gold content is too high, firstly, the hardness is too high and defects such as gold nodules are easily generated, and secondly, it is difficult to reduce costs.

[0011] When the gold content in the gold-silver alloy is 10-60wt%, in order to meet the difference in thermal expansion coefficient between the gold-silver alloy bump and the adhesion layer below 9ppm / K and meet other performance requirements of the flip chip, the adhesion layer is preferably a Ti layer, a TiN layer, or a double layer of a Ti layer and a TiN layer.

[0012] Furthermore, the thickness of the adhesion layer is 10-1000 nm.

[0013] Furthermore, the seed layer is a gold layer, a silver layer, a gold-silver alloy layer, or a double layer of a gold layer and a silver layer.

[0014] Furthermore, the thickness of the seed layer is 10-1000 nm.

[0015] Another aspect of the present invention is to provide a method for preparing the semiconductor device structure, comprising the following steps: S1. Selecting a material such that the difference in thermal expansion coefficient between the gold-silver alloy bump and the adhesive layer is less than 9 ppm / K; S2: preparing an adhesion layer and a seed layer in sequence on a chip wafer by physical vapor deposition (such as evaporation or magnetron sputtering) to obtain a UBM layer; S3 applies photoresist and exposes the area to be plated; S4 prepares a gold-silver alloy bump by electroplating using a gold-silver electroplating solution; S5: removing excess photoresist and UBM layer.

[0016] In the preparation method provided by the present invention, the key is to select suitable materials to prepare the adhesion layer, and ensure that the difference in thermal expansion coefficient between the gold-silver alloy bump and the adhesion layer is less than 9ppm / K. The specific operations: preparing the adhesion layer and the seed layer by physical vapor deposition, coating the photoresist, and preparing the gold-silver alloy bump by electroplating, etc., can all adopt the technical solutions disclosed in the prior art.

[0017] Another aspect of the present invention is to provide a chip, wherein the chip includes the semiconductor device structure provided by the present invention.

[0018] Furthermore, the chip is a liquid crystal driver chip, a memory chip, a logic chip or a power chip.

[0019] The technical solution provided by the present invention solves the technical problem that the gold-silver alloy bump and the existing UBM layer cannot pass the high and low temperature cycle reliability test. The obtained semiconductor device structure and corresponding chip can pass various reliability tests, making it feasible to replace the pure gold bump with the gold-silver alloy, thereby greatly reducing the production cost of the flip chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the semiconductor device structure provided by the present invention.

[0021] Reference numerals: 101 - wafer substrate, 102 - electrode, 103 - passivation layer, 104 - adhesion layer, 105 - seed layer, 106 - gold-silver alloy bump.

[0022] Figure 2 These are optical photographs of the semiconductor device structures of Example 1 and Comparative Example 1 subjected to thrust shear after TCT testing.

[0023] Figure 3 These are the SEM analysis results of thrust shear of the semiconductor device structures of Example 1 and Comparative Example 1 after TCT testing, wherein Figure a is the overall morphology of Example 1, Figure b is an enlarged view of the boxed area in Figure a, and Figure c is a FIB slice of Figure b; Figure d is the overall morphology of Comparative Example 1, Figure e is an enlarged view of the boxed area in Figure d, and Figure f is the EDX element analysis of point 1 in Figure e.

[0024] Figure 4 These are the SEM analysis results of the semiconductor device structures of Example 1 and Comparative Example 1 without thrust shear after TCT testing. DETAILED DESCRIPTION

[0025] The technical solution of the present invention is described clearly and completely below in conjunction with the accompanying drawings of the specification. Obviously, the described implementation is only a part of the implementation of the present invention, not all of the implementations. Based on the implementation of the present invention, all other implementations obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Example 1

[0026] A semiconductor device structure, such as Figure 1 As shown, it includes a gold-silver alloy bump 106 and a UBM layer. The UBM layer is composed of a seed layer 105 and an adhesion layer 104. The bottom of the gold-silver alloy bump 106 is connected to the seed layer 105, and the adhesion layer 104 is connected to the chip electrode 102. The structure of the entire chip is as follows: the bottom layer is a silicon-based wafer substrate 101, on which transistors have been deployed; on it is a conductive layer aluminum electrode 102; on both sides of the aluminum electrode are passivation layers 103, which are mainly used to protect and isolate the circuit. The passivation layer material can be selected from silicon dioxide or silicon nitride and other materials, and is prepared by evaporation or magnetron sputtering; on the aluminum electrode 102 is a UBM layer, including an adhesion layer 104 and a seed layer 105. The material of the adhesion layer 104 is titanium, with a thickness of 50nm; the material of the seed layer 105 is gold, with a thickness of 30nm; the gold content in the gold-silver alloy bump 106 is 18wt%, and the thickness is 9μm.

[0027] The specific preparation process is as follows. On the completed 12-inch liquid crystal driver chip wafer, first use magnetron sputtering to form a 50nm Ti adhesion layer. The sputtering conditions are: vacuum degree of 0.003Torr, bias voltage of 90V, power of 5kW, and sputtering time of 200s; then switch the Au target in the same chamber to sputter a 30nm Au seed layer. The sputtering conditions are: vacuum degree of 0.003Torr, bias voltage of 60V, power of 2kW, and sputtering time of 150s. Nitrogen is introduced to cool down and the wafer is taken out; spin-coat the wafer with photoresist JSR 121 and expose the area to be electroplated. The photoresist height is 20μm; after plasma cleaning, use gold-silver alloy electroplating solution to prepare a gold-silver conductive metal layer. The plating solution temperature is 30℃, pH is 9.0, the current density is 0.5ASD, and the electroplating time is 36min; finally, remove the photoresist and UBM layer. Example 2

[0028] A semiconductor device structure, the overall structure is the same as that of embodiment 1, except that: the thickness of the adhesion layer is 150 nm, and the thickness of the seed layer is 50 nm. Example 3

[0029] A semiconductor device structure, the overall structure is the same as that of embodiment 1, except that: the thickness of the adhesion layer is 300 nm, and the thickness of the seed layer is 100 nm. Example 4

[0030] A semiconductor device structure, the overall structure is the same as that of embodiment 1, except that: the thickness of the adhesion layer is 500nm; the material of the seed layer is silver, and the thickness of the seed layer is 300nm. Example 5

[0031] A semiconductor device structure, the overall structure is the same as that of embodiment 1, except that: the thickness of the adhesion layer is 750nm; the material of the seed layer is silver, and the thickness of the seed layer is 500nm. Example 6

[0032] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the thickness of the adhesion layer is 1000nm; the material of the seed layer is a gold-silver alloy, and the thickness of the seed layer is 1000nm; the gold content of the gold-silver alloy bump is 10wt%. Example 7

[0033] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the material of the adhesion layer is titanium nitride with a thickness of 100nm; the gold content of the gold-silver alloy bump is 32wt%. Example 8

[0034] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the material of the adhesion layer is titanium nitride, with a thickness of 100nm; the material of the seed layer is silver, and the gold content of the gold-silver alloy bump is 50wt%. Example 9

[0035] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the adhesion layer is a double-layer structure of a titanium layer and a titanium nitride layer, wherein the titanium layer is connected to a gold-silver alloy bump, and the thickness of the titanium layer and the titanium nitride layer are both 50nm; the thickness of the seed layer is 80nm; and the gold content of the gold-silver alloy bump is 32wt%. Example 10

[0036] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the adhesion layer is a double-layer structure of a titanium nitride layer and a titanium layer, wherein the titanium nitride layer is connected to a gold-silver alloy bump, and the thickness of the titanium nitride layer and the titanium layer are both 100nm; the thickness of the seed layer is 80nm; and the gold content of the gold-silver alloy bump is 50wt%. Comparative Example 1

[0037] A semiconductor device structure, the overall structure is the same as that of embodiment 1, except that the material of the adhesion layer is TiW. Comparative Example 2

[0038] A semiconductor device structure, the overall structure is the same as that of comparative example 1, except that: the bump is made of pure gold. Embodiment 11

[0039] The semiconductor device structures of Example 1 and Comparative Example 1 were subjected to TCT, LTST, PCT, HTST and THT tests respectively, and the semiconductor device structure of Comparative Example 2 was subjected to TCT test. The test results are shown in Table 1.

[0040] Table 1 Test results under different reliability test conditions

[0041]

[0042] It can be seen from Table 1 that the semiconductor device structure of Example 1 can pass all reliability tests, the semiconductor device structure of Comparative Example 1 can pass most reliability tests, but cannot pass the TCT test, and Comparative Example 2 can pass the TCT test. It can be seen that the key to passing the TCT test lies in the matching of the bump and the adhesion layer: the pure gold bump of the prior art can match the TiW adhesion layer of the prior art (Comparative Example 2); the gold-silver alloy bump cannot match the TiW adhesion layer of the prior art (Comparative Example 1), and the gold-silver alloy bump can match the Ti adhesion layer (Example 1).

[0043] from Figure 2 It can be seen that the semiconductor device structure of Comparative Example 1 is subjected to thrust shear after the TCT test, and a flat interface is obviously exposed on the right side of the bump. This is due to the poor bonding between the TiW layer and the alloy bump above, and the TiW layer below is exposed after the thrust shear. The semiconductor device structure of Example 1 is subjected to thrust shear after the TCT test, and the UBM layer is not exposed, and can pass the high and low temperature reliability test.

[0044] In order to further confirm the above experimental results, SEM analysis was performed on the samples subjected to thrust shear after TCT test, as shown in Figure 2. Figure 3 As shown, the cross section of the gold-silver alloy layer with broken edges after thrust shearing in Example 1 is honeycomb-shaped, indicating ductile fracture, and the interface structure shows that the thinnest part is 242nm. Since the Ti layer is only 50nm and the Au layer is 30nm, it can be fully judged that the UBM structural layer is not exposed. In Comparative Example 1, it can be clearly seen that the UBM structural layer is exposed after thrust shearing, and EDX element analysis shows that W and Ti are the main elements, that is, the UBM adhesion layer.

[0045] Figure 4This is a slice of the interface of the semiconductor device structure of Example 1 and Comparative Example 1 after the TCT test, but before thrust shear. When the UBM layer is Ti, there is no separation at the interface between the metal layers, but when the UBM layer is TiW, the gold seed layer and the underlying TiW layer are clearly separated (the position circled in the figure), which shows that the interface separation in the high and low temperature cycle test is closely related to the material properties.

[0046] Back to the results shown in Table 1, when the UBM layer is TiW, the gold and silver bumps can pass the LTST low temperature test (-65°C), PCT high temperature, high pressure and high humidity test (121°C), HTST high temperature test (150°C), and THT (85°C) high temperature and high humidity test, but cannot pass the TCT high and low temperature hot and cold cycle test (-65°C~150°C). The inventors therefore thought that the failure of the TCT test may be caused by the different thermal expansion coefficients between different metals.

[0047] The inventor tried to explain the above phenomenon with the theory of thermal expansion. When the thermal expansion coefficients of the electroplated metal bump conductive layer and the adhesion layer of the UBM layer are greatly different, the deformation mismatch of the material is greater with the thermal shock, resulting in fracture at the edge. As shown in Table 2, the thermal expansion coefficients of different metals are listed, where the thermal expansion coefficients of alloys are calculated using a simple approximation. For example, the UBM layer Ti1W9, in which Ti atoms are 10% and W atoms are 90%, can be calculated based on the thermal expansion coefficient of Ti 10.8 and the thermal expansion coefficient of W 4.5, that is, the thermal expansion coefficient of Ti1W9 is 10.8×0.1+4.5×0.9=5.1.

[0048] Table 2 Thermal expansion coefficients of different metals and the difference in thermal expansion coefficients between different metal pairs

[0049] For the relatively mature gold bump process of liquid crystal, Ti1W9 is used as the adhesion layer of UBM. Table 1 shows that it can pass the high and low temperature cycle test. Therefore, the difference in thermal expansion coefficient between pure gold and Ti1W9 is 9.07 as a reference value. The thermal expansion coefficient between the electroplated metal bump and UBM is higher than this value, which means that there is a risk of interface failure in the high and low temperature test. As can be seen from Table 2, when AuAg alloy is used as the bump and the adhesion layer of UBM is TiW layer, the difference in thermal expansion coefficient can reach 12.25~13.31, which is much higher than the difference in thermal expansion coefficient of Au-TiW metal pair, so the sample fails. When the UBM adhesion layer material is Ti or TiN, the difference in thermal expansion coefficient between the electroplated gold and silver bump and the UBM layer is lower than the reference value of Au-Ti1W9, which is expected to solve the problem of interface failure in high and low temperature tests. When the UBM adhesion layer is TiW or Ta, since it is higher than the reference value of Au-Ti1W9, there is a risk of interface failure after high and low temperature cycle test.

[0050] It can also be inferred from Table 2 that when the gold content in the gold-silver alloy bump is higher, the thermal expansion coefficient of the AuAg alloy is lower. For example, the thermal expansion coefficient of Au2Ag8 is 18.4, while the thermal expansion coefficient of Au4Ag6 is 17.4. Because the thermal expansion coefficient of the gold-silver bump is higher than that of the UBM adhesion layer, increasing the gold content in the gold-silver bump can reduce the difference in thermal expansion coefficients between the gold-silver alloy and the UBM layer, which is beneficial to reduce the risk of interface failure.

[0051] It is feasible to use gold or silver or a combination of the two for the seed layer in UBM, because the hardness of the coating is reduced after annealing after electroplating. During this process, the seed layer and the electroplated gold-silver alloy will diffuse, so the bonding force between the seed layer and the electroplated gold-silver is sufficient.

[0052] The semiconductor device structures of Examples 1 to 10 were subjected to TCT tests (-65°C (15 min) ~ 150°C (15 min), 350 cycles), and the test results are shown in Table 3.

[0053] Table 3 Thrust shear test results of semiconductor device structures of Examples 1 to 10 after TCT test

[0054] It can be seen from Table 3 that when the UBM adhesion layer uses Ti or TiN of different thicknesses or a stack of the two, the seed layer is Au or Ag or a gold-silver alloy of different thicknesses, and the bump is a gold-silver alloy of different proportions, the thrust shear test results after the TCT test do not expose the UBM layer.

[0055] In order to solve the technical problem that the gold-silver alloy bump and the existing UBM layer cannot pass the high and low temperature cycle reliability test, based on the technical solution of the present invention, those skilled in the art can further select the materials of the adhesion layer and the seed layer. As long as these adhesion layer and seed layer materials make the difference in thermal expansion coefficient between the gold-silver alloy bump and the adhesion layer less than 9ppm / K and meet other physical and chemical performance requirements of the UBM layer, they are all suitable.

[0056] Although the embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and cannot be understood as limiting the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention without departing from the principles and purpose of the present invention. The protection scope of the present invention is defined by the claims and their equivalent technical solutions.

Claims

1. A semiconductor device structure, comprising a gold-silver alloy bump and a UBM layer, wherein the UBM layer is composed of a seed layer and an adhesion layer, the bottom of the gold-silver alloy bump is connected to the seed layer, and the adhesion layer is connected to the chip electrode, characterized in that: The difference in thermal expansion coefficient between the gold-silver alloy bump and the adhesion layer is less than 9 ppm / K.

2. The semiconductor device structure according to claim 1, characterized in that The thickness of the gold-silver alloy bump is 5-20 μm.

3. The semiconductor device structure according to claim 1, characterized in that: The gold content in the gold-silver alloy bump is 10-60wt%.

4. The semiconductor device structure according to claim 3, characterized in that: The adhesion layer is a Ti layer, a TiN layer, or a double layer of a Ti layer and a TiN layer.

5. The semiconductor device structure according to claim 1, characterized in that: The thickness of the adhesion layer is 10-1000 nm.

6. The semiconductor device structure according to claim 1, characterized in that: The seed layer is a gold layer, a silver layer, a gold-silver alloy layer, or a double layer of a gold layer and a silver layer.

7. The semiconductor device structure according to claim 1, characterized in that: The thickness of the seed layer is 10-1000 nm.

8. The method for preparing a semiconductor device structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1. Selecting a material such that the difference in thermal expansion coefficient between the gold-silver alloy bump and the adhesive layer is less than 9 ppm / K; S2 sequentially prepares an adhesion layer and a seed layer on a chip wafer by a physical vapor deposition method to obtain a UBM layer; S3 applies photoresist and exposes the area to be plated; S4 prepares a gold-silver alloy bump by electroplating using a gold-silver electroplating solution; S5: removing excess photoresist and UBM layer.

9. A chip, characterized in that: The chip comprises the semiconductor device structure according to any one of claims 1-7.

10. The chip according to claim 9, characterized in that: The chip is a liquid crystal drive chip, a memory chip, a logic chip or a power chip.

Images