Three-dimensional stacked optoelectronic chip package structure and fabrication method

Abstract

The application provides a three-dimensional stacked optoelectronic chip packaging structure and a manufacturing method, the optical chip and the electronic chip are 3D stacked and packaged, and the packaging area can be effectively reduced; and the optical chip and the electronic chip are interconnected and led out through a rewiring layer and a conductive column, the transmission path of the optical chip and the electronic chip can be effectively shortened, the transmission path can be shortened by 20 times compared with a 2D optoelectronic integrated packaging, and low insertion loss and RC delay are achieved.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of chip packaging, and relates to a three-dimensional stacked optoelectronic chip packaging structure and a manufacturing method. BACKGROUND

[0002] By 2022, global Internet traffic is expected to reach nearly 400 EB per month, and the demand for data center interconnection bandwidth will continue to grow exponentially. It is predicted that by 2030, with the continuous growth of data center energy consumption, the global data center electricity consumption will exceed 3 PWh, and even possibly as high as 8 PWh. In order to meet the demand of Internet traffic, the data center node bandwidth needs to reach 10 Tb / s, and in order to slow down the trend of data center energy consumption growth, it is necessary to reduce the power consumption of the system and the device. The number of I / O pins per package is almost doubled every 6 years, and the total I / O bandwidth is doubled every 3 to 4 years.

[0003] Light has the performance of small signal attenuation, low energy consumption, high bandwidth and compatibility with CMOS, which directly affects the bandwidth and energy consumption of I / O. The purpose of introducing silicon photonics technology is to increase the I / O bandwidth and maximize the reduction of energy consumption. How to package the optical integrated circuit (PIC) and the electrical integrated circuit (EIC) is very important, and improper integration of light and electricity will offset all potential advantages of silicon photonics.

[0004] Most of the existing optoelectronic integrated semiconductor packaging structures directly bond the optical integrated chip and the electrical integrated chip on the substrate for 2D packaging, and are electrically connected with the substrate through wire-bonds or flip-chip. Theoretically, this packaging is very good, but in reality it is not. The silicon photonics process node is relatively backward compared with the electrical chip process. The most advanced process for monolithic integration development is 45nm and 32nm process, which is very backward in performance compared with the electrical chip 10nm and below process. The performance of the existing optoelectronic integrated packaging structure is difficult to meet the demand of high-density integrated packaging. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a three-dimensional stacked optoelectronic chip packaging structure and a manufacturing method, which solves the problem of high-density integrated packaging of optical chips and electrical chips in the prior art.

[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a manufacturing method of a three-dimensional stacked optoelectronic chip packaging structure, comprising the following steps:

[0007] A substrate is provided, a first re-distribution layer is formed on the substrate, and a conductive column is formed on the first re-distribution layer, the conductive column and the first re-distribution layer being electrically connected;

[0008] The application provides an optical chip, which comprises oppositely arranged first and second surfaces, and the first surface of the optical chip is provided with an optical chip pad and an optical signal area; the first surface of the optical chip is bonded to a first re-wiring layer, wherein the optical chip pad is electrically connected to the first re-wiring layer.

[0009] A packaging layer is formed on the first re-wiring layer, and the packaging layer covers the conductive column and the optical chip, wherein the packaging layer exposes the top of the conductive column.

[0010] A second re-wiring layer is formed on the packaging layer, the second re-wiring layer is electrically connected to the conductive column, and the substrate is removed.

[0011] The application provides an electrical chip, which comprises oppositely arranged first and second surfaces, and the first surface of the electrical chip is provided with an electrical chip pad; the first surface of the electrical chip is bonded to the first re-wiring layer away from the packaging layer, and the electrical chip pad is electrically connected to the first re-wiring layer, wherein the electrical chip does not cover the optical signal area in the vertical projection.

[0012] An opening is formed in the first re-wiring layer, the opening exposes the optical signal area, and an optical bridge structure is formed on the side of the first re-wiring layer away from the packaging layer, the optical bridge structure covers the opening to correspond to the optical signal area.

[0013] Optionally, the first surface of the optical chip is further provided with a convex ring, and the convex ring surrounds the optical signal area in the horizontal direction, wherein after the first surface of the optical chip is bonded to the first re-wiring layer, the convex ring is in contact with the first re-wiring layer.

[0014] Optionally, the convex ring comprises a copper convex ring.

[0015] Optionally, the optical chip is bonded to the side of the first re-wiring layer away from the substrate by a flip chip bonding method.

[0016] Optionally, the electrical chip is bonded to the side of the first re-wiring layer away from the packaging layer by a flip chip bonding method.

[0017] Optionally, a separation layer is further formed between the substrate and the first re-wiring layer, and the substrate is removed based on the separation layer, wherein after the substrate is removed, the side of the first re-wiring layer away from the packaging layer is exposed.

[0018] Optionally, the method for forming the opening in the first re-wiring layer comprises a laser drilling method or a dry etching method.

[0019] Optionally, the conductive pillar comprises a copper pillar.

[0020] The application further provides a three-dimensional stacked optoelectronic chip packaging structure, comprising:

[0021] a second re-wiring layer;

[0022] a conductive pillar above the second re-wiring layer, the conductive pillar being electrically connected with the second re-wiring layer;

[0023] a first re-wiring layer above the conductive pillar, the first re-wiring layer being electrically connected with the conductive pillar;

[0024] an optical chip between the first re-wiring layer and the second re-wiring layer, the optical chip comprising oppositely arranged first and second surfaces, the first surface of the optical chip being provided with an optical chip pad and an optical signal region, the optical chip pad being electrically connected with the first re-wiring layer;

[0025] a packaging layer between the first re-wiring layer and the second re-wiring layer, the packaging layer covering exposed surfaces of the optical chip and the conductive pillar;

[0026] an electronic chip above the first re-wiring layer, the electronic chip being electrically connected with the first re-wiring layer, wherein, in a vertical projection, the electronic chip does not cover the optical signal region;

[0027] an opening penetrating through the first re-wiring layer to expose the optical signal region;

[0028] an optical bridge structure above the first re-wiring layer, the optical bridge structure covering the opening to correspond to the optical signal region.

[0029] Optionally, the first surface of the optical chip is further provided with a convex ring, in a horizontal direction, the convex ring surrounding the optical signal region, wherein an end of the convex ring away from the optical chip is in contact with the first re-wiring layer.

[0030] As described above, in the three-dimensional stacked optoelectronic chip packaging structure and the manufacturing method thereof, the optical chip and the electronic chip are 3D stacked and packaged, which can effectively reduce the packaging area; and the optical chip and the electronic chip are interconnected and led out through the re-wiring layer and the conductive pillar, which can effectively shorten the transmission path of the optical chip and the electronic chip, the transmission path can be shortened by 20 times compared with a 2D optoelectronic integrated packaging, and the application has low insertion loss and RC delay. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 A process flow chart of a manufacturing method of a three-dimensional stacked optoelectronic chip packaging structure in an embodiment of the application is shown.

[0032] Figure 2 A schematic diagram showing the formation of a separation layer on a substrate in an embodiment of the application.

[0033] Figure 3 A schematic diagram showing the formation of a first re-routed layer and conductive pillars in an embodiment of the application.

[0034] Figure 4 A cross-sectional view of an optical chip in an embodiment of the application.

[0035] Figure 5 A top view of an optical chip in an embodiment of the application.

[0036] Figure 6 A schematic diagram showing the bonding of an optical chip to a first re-routed layer in an embodiment of the application.

[0037] Figure 7 A schematic diagram showing the formation of an encapsulation layer in an embodiment of the application.

[0038] Figure 8 A schematic diagram showing the thinning of an encapsulation layer in an embodiment of the application.

[0039] Figure 9 A schematic diagram showing the formation of a second re-routed layer in an embodiment of the application.

[0040] Figure 10 A schematic diagram showing the removal of a substrate in an embodiment of the application.

[0041] Figure 11 A schematic diagram showing the provision of an electrical chip and the bonding of the electrical chip to a first re-routed layer in an embodiment of the application.

[0042] Figure 12 A schematic diagram showing the formation of an opening in an embodiment of the application.

[0043] Figure 13 A schematic diagram showing the formation of an optical bridge structure in an embodiment of the application.

[0044] Element Number Description

[0045] 1 substrate

[0046] 2 separation layer

[0047] 3 first re-routed layer

[0048] 4 conductive pillars

[0049] 5 optical chip

[0050] 500 optical chip solder pad

[0051] 501 optical signal region

[0052] 502 convex ring

[0053] 6 first underfill layer

[0054] 7 encapsulation layer

[0055] 8 second re-distribution layer

[0056] 9 solder ball

[0057] 10 electrical chip

[0058] 1000 electrical chip solder joint

[0059] 11 second underfill layer

[0060] 12 opening

[0061] 13 optical bridge structure

[0062] S1-S6 steps DETAILED DESCRIPTION

[0063] The present application is herein described, by way of example only, with reference to embodiments thereof. It is to be understood that variations and modifications will be apparent to those skilled in the art and that the scope of the application encompasses all such variations and modifications. The embodiments described herein are intended to be merely illustrative of the present application and not in limitation thereof. The scope of the present application is to be limited only by the appended claims.

[0064] Reference is made to Figures 1 to 13 . It is to be understood that the drawings are to be used only for illustrative purposes and that the shown drawings and the number, shape, size and arrangement of the components shown therein are to be varied as desired in actual implementation of the present application.

[0065] The present embodiment provides a method for manufacturing a three-dimensional stacked optoelectronic chip package structure, please refer to Figure 1 , comprising the following steps:

[0066] S1: providing a substrate, forming a first re-distribution layer on the substrate, forming a conductive pillar on the first re-distribution layer, the conductive pillar and the first re-distribution layer are electrically connected;

[0067] S2: providing an optical chip, the optical chip comprises a first surface and a second surface arranged oppositely, the first surface of the optical chip is provided with an optical chip solder joint and an optical signal area, the first surface of the optical chip is bonded to the first re-distribution layer, wherein the optical chip solder joint is electrically connected to the first re-distribution layer;

[0068] S3: forming an encapsulation layer on the first re-wiring layer, the encapsulation layer covering the conductive pillars and the optical chip, wherein the encapsulation layer exposes the top of the conductive pillars;

[0069] S4: forming a second re-wiring layer on the encapsulation layer, the second re-wiring layer being electrically connected with the conductive pillars, and removing the substrate;

[0070] S5: providing an electrical chip, the electrical chip including a second surface opposite to a first surface, the first surface of the electrical chip being provided with an electrical chip pad, bonding the first surface of the electrical chip to a side of the first re-wiring layer away from the encapsulation layer, the electrical chip pad being electrically connected with the first re-wiring layer, wherein in a vertical projection, the electrical chip does not cover the optical signal region;

[0071] S6: forming an opening in the first re-wiring layer, the opening exposing the optical signal region, and forming an optical bridge structure on a side of the first re-wiring layer away from the encapsulation layer, the optical bridge structure covering the opening to correspond to the optical signal region.

[0072] The manufacturing method of the three-dimensional stacked optoelectronic chip package structure of the embodiment will be described in detail below in combination with specific drawings.

[0073] First, refer to Figure 2 and Figure 3 , step S1 is performed: providing a substrate 1, forming a first re-wiring layer 3 on the substrate 1, forming conductive pillars 4 on the first re-wiring layer 3, the conductive pillars 4 being electrically connected with the first re-wiring layer 3.

[0074] As an example, the substrate 1 can include, for example, a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, a ceramic substrate, etc., and the substrate 1 provides support for subsequent processes; specifically, in the embodiment, the substrate 1 is a glass substrate.

[0075] As an example, before forming the first re-wiring layer 3, a step of forming a separation layer 2 on the surface of the substrate 1 is further included, the separation layer 2 including, but not limited to, a tape and a polymer layer, for example, the separation layer 2 can be an optothermal conversion layer, so that in subsequent processes, the separation layer 2 can be heated, for example, by a laser, to remove the substrate 1, improving the convenience of operation.

[0076] As an example, the first re-wiring layer 3 is formed above the separation layer 2, the first re-wiring layer 3 can be a Damascus re-wiring layer, an organic re-wiring layer or a stacked combination of the two, that is, the material of the dielectric layer can include silicon oxide, silicon nitride or polyimide (PI) and the like, and the material of the metal wiring can include copper, aluminum and the like, and the material, number of layers, layout, preparation method and the like of the first re-wiring layer 3 can be selected as needed, which is not limited here.

[0077] As an example, the method for forming the conductive column 4 on the first re-wiring layer 3 includes a bonding method, an electroplating method and the like, the conductive column 4 adopts a copper column, and the bottom end of the conductive column 4 is electrically connected with the metal wiring in the first re-wiring layer 3.

[0078] As an example, the conductive column 4 occupies a part of the space above the first re-wiring layer 3, and the space above the first re-wiring layer 3 is reserved for the subsequent bonding of the optical chip 5.

[0079] Next, please refer to Figures 4 to 6 , step S2 is performed: providing an optical chip 5, the optical chip 5 includes oppositely arranged first and second surfaces, the first surface of the optical chip 5 is provided with an optical chip solder point 500 and an optical signal area 501, and the first surface of the optical chip 5 is bonded to the first re-wiring layer 3, wherein the optical chip solder point 500 is electrically connected with the first re-wiring layer 3.

[0080] As an example, the first surface of the optical chip 5 is also provided with a convex ring 502, which surrounds the optical signal area 501 in the horizontal direction, and the optical chip solder point 500 is located at the periphery of the convex ring 501; in the vertical direction, the top end of the convex ring 502 is higher than the optical signal area 501; specifically, in this embodiment, the convex ring 502 adopts a copper convex ring (Cu bar), and the optical chip solder point 500 adopts a solder bump.

[0081] As an example, the optical chip 5 is bonded to the first re-wiring layer 3 by using a flip-chip bonding method (FC Bond for short), and the optical chip solder point 500 is electrically connected with the first re-wiring layer 3, wherein after the bonding connection of the optical chip 5 and the first re-wiring layer 3, the end of the convex ring 502 away from the optical chip 5 is in contact with the first re-wiring layer 3, and the convex ring 502 protects the optical signal area 501 from being contaminated in the subsequent process.

[0082] As an example, a step of forming a first underfill layer 6 to fill the gap between the optical chip 5 and the first re-routed layer 3 is further included to form a protective layer, improve the bonding strength, and avoid the influence of moisture, gas, etc. The material of the first underfill layer 6 can be selected as needed, and can be an insulating material, which is not limited here.

[0083] Next, referring to Figures 7 to 8 , a step S3 of forming an encapsulation layer 7 on the first re-routed layer 3 is performed, the encapsulation layer 7 covering the conductive pillars 4 and the optical chip 5, wherein the encapsulation layer 7 exposes the top of the conductive pillars 4.

[0084] As an example, the method of forming the encapsulation layer 7 can include molding, vacuum lamination molding, spin coating molding, etc., and the material of the encapsulation layer 7 can use commonly used epoxy resin, and the material and preparation method of the encapsulation layer 7 are not limited here.

[0085] As an example, the encapsulation layer 7 is thinned by grinding to expose the conductive pillars 4, such as chemical mechanical grinding (CMP), etc., to obtain a relatively flat surface, which is beneficial for subsequent processes.

[0086] Next, referring to Figures 9 to 10 , a step S4 of forming a second re-routed layer 8 on the encapsulation layer 7 is performed, the second re-routed layer 8 being electrically connected to the conductive pillars 4, and the substrate 1 is removed.

[0087] As an example, the second re-routed layer 8 can be a Damascus re-routed layer, an organic re-routed layer, or a stacked combination of the two, i.e., the material of the dielectric layer can include silicon oxide, silicon nitride, or polyimide (PI), etc., and the material of the metal wiring can include copper, aluminum, etc., and the material, number of layers, layout, preparation method, etc. of the second re-routed layer 8 can be selected as needed, which is not limited here.

[0088] As an example, after the second re-routed layer 8 is formed, a step of forming a solder ball 9 on the second re-routed layer 8 is further included, the solder ball 9 being electrically connected to the second re-routed layer 8, and the solder ball 9 being used to realize soldering between the packaging structure and external devices; specifically, the ball mount method is used to form the solder ball 9 in the embodiment.

[0089] As an example, the substrate 1 is removed based on the separation layer 2, and after the substrate 1 is removed, the side of the first re-routed layer 3 away from the encapsulation layer 7 is exposed.

[0090] Next, referring to Figure 11, execute step S5: provide an electrical chip 10, the electrical chip 10 includes a second face opposite the first face, the electrical chip 10 is provided with an electrical chip pad 1000, the first face of the electrical chip 10 is bonded to the first re-wiring layer 3 away from the packaging layer 7 side, the electrical chip pad 1000 is electrically connected with the first re-wiring layer 3, wherein, in the vertical direction, the projection of the electrical chip 10 does not cover the optical signal area 501.

[0091] As an example, the structure after removing the substrate 1 is turned over, and the electrical chip 10 and the first re-wiring layer 3 are bonded and connected by flip-chip bonding (FC Bond).

[0092] As an example, it also includes the step of forming a second underfill layer 11 between the electrical chip 10 and the first re-wiring layer 3 to form a filling gap, to form a protective layer, improve the bonding strength, and avoid the influence of moisture, gas and the like. The material of the second underfill layer 11 can be selected as needed, which is an insulating material, which is not limited here.

[0093] As an example, in the first re-wiring layer 3, no metal wiring is formed in the dielectric layer directly above the optical signal area 501, which is beneficial to subsequent opening of the optical port.

[0094] Next, please refer to Figures 12 to 13 , execute step S6: form an opening 12 in the first re-wiring layer 3, the opening 12 exposes the optical signal area 501, and an optical bridge structure 13 is formed on the side of the first re-wiring layer 3 away from the packaging layer 7, the optical bridge structure 13 covers the opening 12 to correspond to the optical signal area 501.

[0095] As an example, the opening 12 can be formed by laser drilling or dry etching.

[0096] As an example, the optical bridge structure 13 can be an optical fiber, an optical waveguide, a microlens or any other suitable optical bridge device, and the optical bridge structure 13 can be disposed on the first re-wiring layer 3 by adhesion, bonding or any other suitable method; the optical chip 5 exchanges optical signals with the external environment through the optical signal area 501 and the optical bridge structure 13.

[0097] As an example, the optical bridge structure 13 extends to the side surface of the packaging structure, which can increase the modular combination capability.

[0098] So far, a three-dimensional stacked optoelectronic chip packaging structure is prepared, please refer to Figure 13The three-dimensional stacked optoelectronic chip package structure comprises a second re-wiring layer 8, a conductive column 4, a first re-wiring layer 3, an optical chip 5, a packaging layer 7, an electrical chip 10, an opening 12, and an optical bridge structure 13. The conductive column 4 is located above the second re-wiring layer 8, and the conductive column 4 is electrically connected with the second re-wiring layer 8. The first re-wiring layer 3 is located above the conductive column 4, and the first re-wiring layer 3 is electrically connected with the conductive column 4. The optical chip 5 is located between the first re-wiring layer 3 and the second re-wiring layer 8. The optical chip 5 comprises a first face and a second face arranged oppositely. The first face of the optical chip 5 is provided with an optical chip solder point 500 and an optical signal area 501. The optical chip solder point 500 is electrically connected with the first re-wiring layer 3. The packaging layer 7 is located between the first re-wiring layer 3 and the second re-wiring layer 8. The packaging layer 7 covers the exposed surface of the optical chip 5 and the conductive column 4. The electrical chip 10 is located above the first re-wiring layer 3. The electrical chip 10 is electrically connected with the first re-wiring layer 3. In the projection in the vertical direction, the electrical chip 10 does not cover the optical signal area 501. The opening 12 penetrates through the first re-wiring layer 3 to expose the optical signal area 501. The optical bridge structure 13 is located above the first re-wiring layer 3. The optical bridge structure 13 covers the opening 12 to correspond to the optical signal area 501.

[0099] As an example, the second re-wiring layer 8 can be a Damascus re-wiring layer, an organic re-wiring layer, or a stacked combination of the two, i.e., the material of the dielectric layer can include silicon oxide, silicon nitride, or polyimide (PI), etc., and the material of the metal wiring can include copper, aluminum, etc.

[0100] As an example, the first re-wiring layer 3 can be a Damascus re-wiring layer, an organic re-wiring layer, or a stacked combination of the two, i.e., the material of the dielectric layer can include silicon oxide, silicon nitride, or polyimide (PI), etc., and the material of the metal wiring can include copper, aluminum, etc.

[0101] As an example, the conductive column 4 adopts a copper column. One end of the conductive column 4 is electrically connected with the metal wiring in the first re-wiring layer 3, and the other end of the conductive column 4 is electrically connected with the metal wiring in the second re-wiring layer 8.

[0102] As an example, the first face of the optical chip 5 is further provided with a convex ring 502. In the horizontal direction, the convex ring 502 surrounds the optical signal area 501, and the optical chip solder point 500 is located at the periphery of the convex ring 501. One end of the convex ring 501 away from the optical chip 5 is in contact with the first re-wiring layer 3.

[0103] As an example, a first underfill layer 6 is arranged between the optical chip 5 and the first rewire layer 3 to fill the gap, form a protective layer, improve the bonding strength, and avoid the influence of moisture, gas and the like. The material of the first underfill layer 6 can be selected as needed, and is an insulating material, which is not limited here.

[0104] As an example, the material of the packaging layer 7 is commonly used epoxy resin.

[0105] As an example, the second rewire layer 8 is provided with a solder ball 9 on the side away from the packaging layer 7, the solder ball 9 is electrically connected with the second rewire layer 8, and the solder ball 9 is used to realize the welding of the packaging structure and external devices.

[0106] As an example, the electrical chip 10 is provided with an electrical chip solder point 1000 on the side facing the first rewire layer 3, the electrical chip 10 is bonded and connected with the first rewire layer 3 by flip chip bonding, and the electrical chip solder point 1000 is electrically connected with the first rewire layer 3.

[0107] As an example, a second underfill layer 11 is arranged between the electrical chip 10 and the first rewire layer 3 to fill the gap, form a protective layer, improve the bonding strength, and avoid the influence of moisture, gas and the like.

[0108] As an example, the optical bridge structure 13 can be an optical fiber, an optical waveguide, a microlens or any other suitable optical bridge device, and the optical bridge structure 13 can be arranged on the first rewire layer 3 by adhesion, bonding or any other suitable method; the optical chip 5 exchanges optical signals with the external environment through the optical signal area 501 and the optical bridge structure 13.

[0109] As an example, the optical bridge structure 13 extends to the side surface of the packaging structure, which can increase the modular combination capability.

[0110] In summary, in the three-dimensional stacked optoelectronic chip packaging structure and manufacturing method, the optical chip and the electrical chip are 3D stacked and packaged, which can effectively reduce the packaging area; and the optical chip and the electrical chip are interconnected and led out through the rewire layer and the conductive column, which can effectively shorten the transmission path of the optical chip and the electrical chip, and compared with the 2D optoelectronic integrated packaging, the transmission path can be shortened by 20 times, and has low insertion loss and RC delay. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0111] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A method for fabricating a three-dimensional stacked optoelectronic chip packaging structure, characterized in that, Includes the following steps: A substrate is provided, a first redistribution layer is formed on the substrate, and conductive pillars are formed on the first redistribution layer, wherein the conductive pillars are electrically connected to the first redistribution layer; An optical chip is provided, the optical chip including a first side and a second side disposed opposite to each other. The first side of the optical chip is provided with optical chip solder joints and an optical signal area. The first side of the optical chip is bonded to a first redistribution layer. The optical chip solder joints are electrically connected to the first redistribution layer. The first side of the optical chip is also provided with a convex ring. In the horizontal direction, the convex ring surrounds the optical signal area. After the first side of the optical chip is bonded to the first redistribution layer, the convex ring contacts the first redistribution layer. An encapsulation layer is formed on the first redistribution layer, the encapsulation layer covering the conductive pillar and the optical chip, wherein the top of the conductive pillar is exposed in the encapsulation layer; A second redistribution layer is formed on the encapsulation layer, the second redistribution layer is electrically connected to the conductive pillar, and the substrate is removed; An electrical chip is provided, the electrical chip including a second side opposite to a first side, the first side of the electrical chip having electrical chip solder joints, the first side of the electrical chip being bonded to the side of a first redistribution layer away from the encapsulation layer, the electrical chip solder joints being electrically connected to the first redistribution layer, wherein, in a vertical projection, the electrical chip does not cover the optical signal area; An opening is formed in the first redistribution layer, the opening exposing the optical signal area, and an optical bridging structure is formed on the side of the first redistribution layer away from the encapsulation layer, the optical bridging structure covering the opening to correspond to the optical signal area, wherein no metal wiring is formed in the dielectric layer located directly above the optical signal area in the first redistribution layer.

2. The method for fabricating a three-dimensional stacked optoelectronic chip packaging structure according to claim 1, characterized in that: The convex ring includes a copper convex ring.

3. The method for fabricating a three-dimensional stacked optoelectronic chip packaging structure according to claim 1, characterized in that: The optical chip is bonded to the side of the first redistribution layer away from the substrate via flip-chip bonding.

4. The method for fabricating a three-dimensional stacked optoelectronic chip packaging structure according to claim 1, characterized in that: The electrical chip is bonded to the side of the first redistribution layer away from the encapsulation layer via flip-chip bonding.

5. The method for fabricating a three-dimensional stacked optoelectronic chip packaging structure according to claim 1, characterized in that: A separation layer is also formed between the substrate and the first redistribution layer, and the substrate is removed based on the separation layer, wherein, after the substrate is removed, the side of the first redistribution layer away from the encapsulation layer is exposed.

6. The method for fabricating a three-dimensional stacked optoelectronic chip packaging structure according to claim 1, characterized in that: The method for forming the opening in the first redistribution layer includes laser drilling or dry etching.

7. The method for fabricating a three-dimensional stacked optoelectronic chip packaging structure according to claim 1, characterized in that: The conductive pillars include copper pillars.

8. A three-dimensional stacked optoelectronic chip packaging structure, characterized in that, The three-dimensional stacked optoelectronic chip packaging structure is fabricated by the method for fabricating a three-dimensional stacked optoelectronic chip packaging structure according to any one of claims 1-7, including: Second rerouting layer; A conductive post is located above the second redistribution layer, and the conductive post is electrically connected to the second redistribution layer. A first redistribution layer is located above the conductive pillar, and the first redistribution layer is electrically connected to the conductive pillar. An optical chip is located between the first redistribution layer and the second redistribution layer. The optical chip includes a first surface and a second surface disposed opposite to each other. The first surface of the optical chip is provided with optical chip solder joints and an optical signal area. The optical chip solder joints are electrically connected to the first redistribution layer. The first surface of the optical chip is also provided with a convex ring. In the horizontal direction, the convex ring surrounds the optical signal area. The end of the convex ring away from the optical chip is in contact with the first redistribution layer. An encapsulation layer is located between the first redistribution layer and the second redistribution layer, and the encapsulation layer covers the exposed surfaces of the optical chip and the conductive pillars; An electrical chip is located above the first redistribution layer and is electrically connected to the first redistribution layer, wherein, in a vertical projection, the electrical chip does not cover the optical signal area; An opening extends through the first redistribution layer to expose the optical signal area; An optical bridging structure is located above the first redistribution layer, the optical bridging structure covering the opening to correspond to the optical signal area.

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