A cascaded CLS switched capacitor integration circuit applied to sigma-delta ADC

Abstract

The application is suitable for the field of modulators, and provides a cascade CLS switched capacitor integration circuit applied to a sigma-delta ADC, which comprises: a switched capacitor network unit for sampling a first voltage signal and a second voltage signal respectively and performing integration operation on the first voltage signal and the second voltage signal and outputting integration results in response to a first time control signal; a cascade CLS network unit for changing an output path of an operational amplifier to change the gain of the operational amplifier in response to a second time control signal; and the operational amplifier for generating a virtual short effect by using the gain to assist the switched capacitor network unit in performing the integration operation. The technical scheme provided by the application can change the gain of the operational amplifier without improving the original structure of the operational amplifier, and can assist the switched capacitor network unit in performing the integration operation through the changed gain, and can be flexibly adapted to sigma-delta ADCs with different resolution requirements.

Description

Technical Field

[0001] The present invention belongs to the technical field of modulators, and in particular relates to a cascaded CLS switched capacitor integration circuit applied to a sigma-delta ADC. Background Art

[0002] The sigma-delta ADC, also known as the ∑-Δ ADC, is a high-precision modulator widely used in fields such as medicine and high-precision instrumentation due to its high resolution. The high resolution of the sigma-delta ADC is closely related to the switched capacitor integrator circuit on it. The higher the integration accuracy of the switched capacitor integrator circuit, the higher the resolution of the sigma-delta ADC. Currently, the main approach to improving integration accuracy is to improve the operational amplifier structure in the switched capacitor integrator circuit. However, despite the numerous operational amplifier structures proposed, this approach is often limited by manufacturing technology, resulting in low integration accuracy and difficulty adapting to sigma-delta ADCs with different resolution requirements. Therefore, there is a need to provide a switched capacitor integrator circuit that can achieve high integration accuracy and flexibly adapt to sigma-delta ADCs with different resolution requirements. Summary of the Invention

[0003] To solve the above problems, the present invention provides a cascaded CLS switched capacitor integrator circuit for sigma-delta ADC. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0004] The present invention provides a cascaded CLS switched capacitor integration circuit for sigma-delta ADC, comprising: a switched capacitor network unit, an operational amplifier, and a cascaded CLS network unit; the cascaded CLS network unit comprises at least two CLS units connected in series; the switched capacitor network unit has a first input terminal for receiving a first voltage signal, a second input terminal for receiving a second voltage signal, and a third input terminal for receiving a common-mode voltage signal V CM , the control end is used to receive the first time control signal, the first output end is connected to the inverting input end of the operational amplifier, the second output end is connected to the first output end of the cascaded CLS network unit, the third output end is connected to the non-inverting input end of the operational amplifier, and the fourth output end is connected to the second output end of the cascaded CLS network unit; the operational amplifier, the non-inverting output end is connected to the first input end of the cascaded CLS network unit, the inverting output end is connected to the second input end of the cascaded CLS network unit; the third input end of the cascaded CLS network unit is used to receive the common mode voltage signal V CM, the control end is used to receive a second time control signal; the switched capacitor network unit is used to sample the first voltage signal and the second voltage signal respectively in response to the first time control signal, and to perform integration operations on the first voltage signal and the second voltage signal and output the integration results; the cascaded CLS network unit is used to change the output path of the operational amplifier in response to the second time control signal to change the gain of the operational amplifier; the operational amplifier is used to use the gain to generate a virtual short effect to assist the switched capacitor network unit in performing integration operations.

[0005] In one embodiment, the circuit composition of each CLS unit in the cascaded CLS network unit is the same; each CLS unit includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor and a second capacitor; one end of the first switch is used to connect the common mode voltage signal V CM The other end of the first switch is connected to one end of the second switch and one end of the first capacitor respectively, the other end of the second switch is connected to one end of the third switch, serving as the first input end of the CLS unit, and the other end of the third switch is connected to the other end of the first capacitor, serving as the first output end of the CLS unit; one end of the fourth switch is used to receive the common-mode voltage signal V CM The other end of the fourth switch is respectively connected to one end of the fifth switch and one end of the second capacitor, the other end of the fifth switch is connected to one end of the sixth switch, serving as the second input end of the CLS unit, and the other end of the sixth switch is connected to the other end of the second capacitor, serving as the second output end of the CLS unit.

[0006] In one embodiment, when the cascaded CLS network unit includes a first CLS unit and a second CLS unit, the first input terminal of the second CLS unit is connected to the non-inverting output terminal of the operational amplifier, the second input terminal of the second CLS unit is connected to the inverting output terminal of the operational amplifier, the first output terminal of the second CLS unit is connected to the first input terminal of the first CLS unit, the second output terminal of the second CLS unit is connected to the second input terminal of the first CLS unit, the first output terminal of the first CLS unit is connected to the second output terminal of the switch capacitor network unit, and the second output terminal of the first CLS unit is connected to the fourth output terminal of the switch capacitor network unit.

[0007] In one embodiment, the cascaded CLS network unit includes N CLS units connected in series, and the second time control signal includes N time control signals, wherein the generation time of the nth time control signal is earlier than the n+1th time control signal, and the control end of the nth CLS unit is used to access the nth time control signal, where the value of n is 1 to N-1, and N is a positive integer greater than 1.

[0008] In one embodiment, the second time control signal includes: a time control signal A and a time control signal B, wherein the generation time of the time control signal A is earlier than the generation time of the time control signal B; the time control signal A includes a control signal Φ 11 and control signal Ф 12 ; The Ф 11 and the Φ 12 Inversion; the time control signal B includes a control signal Ф 21 and control signal Ф 22 ; The Ф 21 and the Φ 22 Inverting; the control ends of the first switch K1, the third switch K3, the fourth switch K4 and the sixth switch K6 in the first CLS unit are connected to the Ф 11 The control ends of the second switch K2 and the fifth switch K5 in the first CLS unit are connected to the Φ 12 The first switch K7, the third switch K9, and the fourth switch K in the second CLS unit 10 and the sixth open K 12 The control end is connected to the Ф 21 , the second switch K8 and the fifth switch K in the second CLS unit 11 The control end is connected to the Ф 22 .

[0009] In one embodiment, within one clock cycle, the Φ 11 Output high level and the Ф 12 When the output is low level, the K1, K3, K4 and K6 in the first CLS unit are closed, the K2 and K5 are disconnected, and one end of the first capacitor C1 in the first CLS unit and one end of the second capacitor C2 in the first CLS unit are connected to the common mode voltage signal V CM The first input end of the second CLS unit is connected to the other end of the C1 via the K3, the other end of the C1 is also connected to the second output end of the switch capacitor network unit, the second input end of the second CLS unit is connected to the other end of the C2 via the K6, and the other end of the C2 is also connected to the fourth output end of the switch capacitor network unit.

[0010] In one embodiment, within one clock cycle, the Φ 11 Output low level and the Ф 12 When a high level is output, the K1, the K3, the K4 and the K6 in the first CLS unit are disconnected, the K2 and the K5 are closed, the first input end of the second CLS unit is connected to one end of the C1 via the K2, the other end of the C1 is connected to the second output end of the switch capacitor network unit, the second input end of the second CLS unit is connected to one end of the C2 via the K5, and the other end of the C2 is connected to the fourth output end of the switch capacitor network unit.

[0011] In one embodiment, within one clock cycle, the Φ 21 Output high level and the Ф 22 When the output is low, the K7, K9, and K 10 and the K 12 Closed, the K8 and the K 11 Disconnect, one end of the first capacitor C3 in the second CLS unit and one end of the second capacitor C4 in the second CLS unit are connected to the common mode voltage signal V CM The positive output terminal of the operational amplifier is connected to the other end of the C3 via the K9, the other end of the C3 is also connected to the first input terminal of the first CLS unit, and the negative output terminal of the operational amplifier is connected to the K 12 The other end of C4 is connected to the second input end of the first CLS unit.

[0012] In one embodiment, within one clock cycle, the Φ 21 Output low level and the Ф 22 When outputting a high level, the K7, K9, and K 10 and the K 12 Disconnect, the K8 and the K 11 The positive output terminal of the operational amplifier is connected to one end of the C3 via the K8, the other end of the C3 is connected to the first input terminal of the first CLS unit, and the negative output terminal of the operational amplifier is connected to the K 11 Connected to one end of C4, and the other end of C4 is connected to the second input end of the first CLS unit.

[0013] In one embodiment, the first time control signal includes: a control signal S 2D , control signal S 1D , control signal S2 and control signal S1; the switch capacitor network unit includes: switch K13 , switch K 14 , switch K 15 , switch K 16 , switch K 17 , switch K 18 , switch K 19 , switch K 20 , sampling capacitor C5, sampling capacitor C6, integrating capacitor C7 and integrating capacitor C8; the K 13 One end of the K 13 The other end is connected to one end of the C5 and the K 14 One end of the K 14 The other end is connected to the common mode voltage signal V CM , the other end of the C5 is connected to the K 15 One end and the K 16 One end of the K 15 The other end is connected to the common mode voltage signal V CM , the K 16 The other end of the K is connected to the inverting input end of the operational amplifier and one end of the C7, and the other end of the C7 is connected to the first output end of the cascaded CLS network unit; 17 One end of the K 17 The other end is connected to one end of C6 and the K 18 One end of the K 18 The other end is connected to the common mode voltage signal V CM , the other end of the C6 and the K 19 One end and the K 20 One end of the K 19 The other end is connected to the common mode voltage signal V CM , the K 20 The other end of the K is connected to the non-inverting input end of the operational amplifier and one end of the C8, and the other end of the C8 is connected to the second output end of the cascaded CLS network unit; 13 and the K 17 The control terminal is used to access the S 2D , the K 14 and the K 18 The control terminal is used to access the S 1D , the K 16 and the K 20 The control terminal is used to access the S1, the K 15 and the K 19 The control end is used to access the S2.

[0014] The present invention has the following beneficial technical effects: In response to the problem that the existing switched capacitor integration circuit applied to sigma-delta ADC relies on improving the operational amplifier structure to improve the integration accuracy, which has low integration accuracy and is difficult to adapt to sigma-delta ADCs with different resolution requirements, the present invention proposes a cascaded CLS switched capacitor integration circuit applied to sigma-delta ADC. The circuit does not need to improve the original structure of the operational amplifier. Instead, at least two CLS units in the cascaded CLS network unit change the output path of the operational amplifier to change the gain of the operational amplifier. With the changed gain value, the operational amplifier assists the switched capacitor network unit in performing integration operations. Compared with the traditional switched capacitor integration circuit that can only increase the gain of the operational amplifier once, the cascaded CLS switched capacitor integration circuit proposed by the present invention has higher integration accuracy. In addition, the CLS units in the cascaded CLS network unit can be flexibly adjusted according to actual needs. The more CLS units there are, the higher the integration accuracy of the switched capacitor integration circuit. In other words, the technical solution proposed by the present invention can be flexibly adapted to sigma-delta ADCs with different resolution requirements.

[0015] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a structural block diagram of a cascaded CLS switched capacitor integration circuit applied to a sigma-delta ADC provided by an embodiment of the present invention;

[0017] Figure 2 1 is a schematic diagram of the generation timing of the first time control signal and the second time control signal provided by an embodiment of the present invention;

[0018] Figure 3 1 is a schematic diagram of voltages at the input and output terminals of the operational amplifier provided by an embodiment of the present invention when the operational amplifier is in a virtual short state;

[0019] Figure 4 The figure is a schematic structural diagram of a cascaded CLS switched capacitor integration circuit applied to a sigma-delta ADC provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0021] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0022] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0023] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0024] The cascaded CLS switched capacitor integration circuit applied to the sigma-delta ADC proposed in the present invention is now described in detail. Figure 1 FIG is a block diagram of a cascaded CLS switched capacitor integration circuit for sigma-delta ADC provided by an embodiment of the present invention. Figure 1 As shown, the circuit includes: a switched capacitor network unit, an operational amplifier and a cascaded CLS network unit; the cascaded CLS network unit includes at least two CLS units connected in series; the switched capacitor network unit, the first input end is used to access the first voltage signal, the second input end is used to access the second voltage signal, and the third input end is used to access the common mode voltage signal V CM, the control end is used to receive the first time control signal, the first output end is connected to the inverting input end of the operational amplifier, the second output end is connected to the first output end of the cascaded CLS network unit, the third output end is connected to the non-inverting input end of the operational amplifier, and the fourth output end is connected to the second output end of the cascaded CLS network unit; the operational amplifier, the non-inverting output end is connected to the first input end of the cascaded CLS network unit, the inverting output end is connected to the second input end of the cascaded CLS network unit; the cascaded CLS network unit, the third input end is used to receive the common mode voltage signal V CM , the control end is used to access the second time control signal; the switched capacitor network unit is used to sample the first voltage signal and the second voltage signal respectively in response to the first time control signal, and to perform an integration operation on the first voltage signal and the second voltage signal and output the integration result; the cascaded CLS network unit is used to change the output path of the operational amplifier in response to the second time control signal to change the gain of the operational amplifier; the operational amplifier is used to use the gain to generate a virtual short effect to assist the switched capacitor network unit in performing the integration operation.

[0025] Here, the first time control signal and the second time control signal are generated by an external clock circuit, and the first time control signal and the second time control signal are within one clock cycle. To ensure that the control signal is accurately sent to the preset location, a delay device is used to make the first time control signal and the second time control signal generated at different times. Figure 2 Schematic diagram of the generation time of the first time control signal and the second time control signal provided by the embodiment of the present invention. Figure 2 As shown, the first time control signal includes: control signal S 2D , control signal S 1D , control signal S2 and control signal S1; S1 and S 1D In phase, S1 and S2 are in opposite phase, S2 and S 2D In phase. In addition, when the cascaded CLS network unit includes a first CLS unit and a second CLS unit, the second time control signal includes: a time control signal A and a time control signal B, the generation time of the time control signal A is earlier than the generation time of the time control signal B; the time control signal A includes a control signal Φ 11 and control signal Ф 12 ; Ф 11 and Φ 12 Inversion; time control signal B includes control signal Ф 21 and control signal Ф 22 ; Ф 21 and Φ 22 Invert.

[0026] It should be understood that the example here is that the cascaded CLS network unit includes only two CLS units to illustrate the signal types included in the second time control signal. In actual operation, the number of CLS units in the cascaded CLS network unit can be flexibly increased according to the required integration accuracy or required resolution.

[0027] It should be noted that the cascaded CLS network unit includes N CLS units connected in series, and the corresponding second time control signal includes N time control signals, wherein the generation time of the nth time control signal is earlier than the n+1th time control signal, and the control end of the nth CLS unit is used to access the nth time control signal, and the value of n is 1 to N, and N is a positive integer greater than 2.

[0028] Here, in order to clearly understand the virtual short effect of the operational amplifier, Figure 3 1 is a schematic diagram of the voltages at the input and output terminals of the operational amplifier provided by the embodiment of the present invention when the operational amplifier is in a virtual short state. Figure 3 As shown, the voltage value V3 at the non-inverting output terminal of the operational amplifier is equal to the product of the voltage value V1 at the inverting input terminal and the gain value, and the voltage value V4 at the inverting output terminal of the operational amplifier is equal to the product of the voltage value V2 at the non-inverting input terminal and the gain value. In other words, the numerical value of the gain value can be expressed by the formula (V3-V4) / (V2-V1). It is known that when the operational amplifier is in a virtual short state, the voltage value V1 at the inverting input terminal of the operational amplifier is equal to the voltage value V2 at the non-inverting input terminal, and the voltage value V3 at the non-inverting output terminal of the operational amplifier is equal to the voltage value V4 at the inverting output terminal. However, the voltage value V1 at the inverting input terminal is the voltage value of the first capacitor signal collected by the switched capacitor network unit, and the voltage value V2 at the non-inverting input terminal is the voltage value of the second capacitor signal collected by the switched capacitor network unit. The first voltage signal and the second voltage signal are not necessarily the same, and the corresponding voltage values ​​are not necessarily the same. Only when V1 and V2 are both 0 or extremely small and close to 0 can the requirement of V1 and V2 being equal be met. When V1 and V2 are both 0 or extremely small and close to 0, the gain value of the operational amplifier is infinite, and the operational amplifier is in a virtual short state.

[0029] Here, the switched capacitor network unit includes a sampling capacitor and an integrating capacitor; the collected first and second voltage signals are stored in the sampling capacitor in the form of charge, and the charge in the sampling capacitor is transferred to the integrating capacitor, which is the integration process. The positive and negative input terminals of the operational amplifier respectively collect the voltage values ​​of the first and second voltage signals. As the charge in the sampling capacitor is transferred to the integrating capacitor, the voltage values ​​obtained by the positive and negative input terminals of the operational amplifier decrease synchronously, and the virtual short effect of the operational amplifier increases, which further increases the potential difference between the sampling capacitor and the integrating capacitor, promoting the transfer of charge in the sampling capacitor to the integrating capacitor. The two complement each other, and ultimately the charge in the sampling capacitor is transferred to the integrating capacitor as completely as possible, completing the integration. The less residual charge in the sampling capacitor, the higher the integration accuracy.

[0030] The process of controlling the switched capacitor network unit to perform sampling and charge transfer by the first time control signal is now described in detail. Figure 4 FIG is a schematic diagram of the structure of a cascaded CLS switched capacitor integration circuit applied to a sigma-delta ADC provided by an embodiment of the present invention. Figure 4 As shown, the switched capacitor network unit includes: switch K 13 , switch K 14 , switch K 15 , switch K 16 , switch K 17 , switch K 18 , switch K 19 , switch K 20 , sampling capacitor C5, sampling capacitor C6, integration capacitor C7 and integration capacitor C8; K 13 One end of the circuit is connected to the first voltage signal, K 13 The other end of C5 and K 14 One end of the connection, K 14 The other end is connected to the common mode voltage signal V CM , the other end of C5 and K 15 One end and K 16 One end of K 15 The other end is connected to the common mode voltage signal V CM , K 16 The other end of K is connected to the inverting input of the operational amplifier and one end of C7 respectively, and the other end of C7 is connected to the first output end of the cascaded CLS network unit; 17 One end of the second voltage signal is connected, K 17 The other end of C6 and K 18 One end of the connection, K 18 The other end is connected to the common mode voltage signal V CM , the other end of C6 and K 19 One end and K20 One end of the connection, K 19 The other end is connected to the common mode voltage signal V CM , K 20 The other end of is connected to the non-inverting input end of the operational amplifier and one end of C8 respectively, and the other end of C8 is connected to the second output end of the cascaded CLS network unit.

[0031] Here, K 13 and K 17 The control terminal is used to access S 2D , K 14 and K 18 The control terminal is used to access S 1D , K 16 and K 20 The control terminal is used to access S1, K 15 and K 19 The control end is used to access S2.

[0032] Specifically, during the sampling phase, S2 and S 2D Output high level, and S1 and S 1D Output low level, K 13 , K 15 , K 17 and K 19 Closed, K 14 , K 16 , K 18 and K 20 The switched capacitor network unit collects the first voltage signal and the second voltage signal respectively, wherein the first voltage signal is stored in C5 in the form of charge, and the second voltage signal is stored in C6 in the form of charge. 2D Output low level, and S1 and S 1D Output high level, K 13 , K 15 , K 17 and K 19 Disconnect, K 14 , K 16 , K 18 and K 20 Closed; the charge in C5 is transferred to C7, and the charge in C6 is transferred to C8.

[0033] The following describes in detail how the cascaded CLS network unit changes the output path of the operational amplifier to change the gain of the operational amplifier. First, the circuit composition of the cascaded CLS network unit is introduced. The cascaded CLS network unit includes N CLS units connected in series, where N is a positive integer greater than 1. Each CLS unit in the cascaded CLS network unit has the same circuit composition; each CLS unit includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor, and a second capacitor; one end of the first switch is used to connect to the common-mode voltage signal V CM The other end of the first switch is connected to one end of the second switch and one end of the first capacitor respectively, the other end of the second switch is connected to one end of the third switch, serving as the first input end of the CLS unit, and the other end of the third switch is connected to the other end of the first capacitor, serving as the first output end of the CLS unit; one end of the fourth switch is used to access the common-mode voltage signal V CM The other end of the fourth switch is respectively connected to one end of the fifth switch and one end of the second capacitor, the other end of the fifth switch is connected to one end of the sixth switch, serving as the second input end of the CLS unit, and the other end of the sixth switch is connected to the other end of the second capacitor, serving as the second output end of the CLS unit.

[0034] Here, to specifically illustrate the series connection method of the CLS unit, when the cascaded CLS network unit includes a first CLS unit and a second CLS unit, the first input end of the second CLS unit is connected to the non-inverting output end of the operational amplifier, the second input end of the second CLS unit is connected to the inverting output end of the operational amplifier, the first output end of the second CLS unit is connected to the first input end of the first CLS unit, the second output end of the second CLS unit is connected to the second input end of the first CLS unit, the first output end of the first CLS unit is connected to the second output end of the switched capacitor network unit, and the second output end of the first CLS unit is connected to the fourth output end of the switched capacitor network unit.

[0035] Here, each CLS unit in the cascaded CLS network receives a different timing control signal and opens or closes its switches according to the specific timing of the timing control signal, thereby changing the circuit transmission path. For example, in a cascaded CLS network unit consisting of only a first CLS unit and a second CLS unit, the first CLS unit receives timing control signal A, while the second CLS unit receives timing control signal B. Time control signal A is generated earlier than time control signal B. Consequently, within a clock cycle, the first CLS unit first performs a corresponding operation in response to timing control signal A to increase the gain of the operational amplifier. In this case, the first CLS unit and the operational amplifier can be considered a single entity. Subsequently, the second CLS unit performs a corresponding operation in response to timing control signal B, further increasing the gain of the operational amplifier. By amplifying the gain of the operational amplifier twice within a clock cycle using the first and second CLS units, the gain of the operational amplifier can be increased to a desired value without modifying the original structure of the operational amplifier. Furthermore, the greater the number of CLS units, the greater the gain of the operational amplifier.

[0036] Please continue to refer to Figure 4 The control terminals of the first switch K1, the third switch K3, the fourth switch K4 and the sixth switch K6 in the first CLS unit are connected to Φ 11 , the control terminals of the second switch K2 and the fifth switch K5 in the first CLS unit are connected to Φ 12 The first switch K7, the third switch K9, and the fourth switch K in the second CLS unit 10 and the sixth open K 12 The control terminal is connected to Ф 21 , the second switch K8 and the fifth switch K in the second CLS unit 11 The control terminal is connected to Ф 22 .

[0037] Here, within one clock cycle, Ф 11 Output high level and Ф 12 When the output is low, K1, K3, K4 and K6 in the first CLS unit are closed, K2 and K5 are disconnected, and one end of the first capacitor C1 in the first CLS unit and one end of the second capacitor C2 in the first CLS unit are connected to the common mode voltage signal V CM The first input end of the second CLS unit is connected to the other end of C1 via K3, the other end of C1 is also connected to the second output end of the switch capacitor network unit, the second input end of the second CLS unit is connected to the other end of C2 via K6, and the other end of C2 is also connected to the fourth output end of the switch capacitor network unit.

[0038] Here, within one clock cycle, Ф 11 Output low level and Ф 12When the output is high, K1, K3, K4 and K6 in the first CLS unit are disconnected, K2 and K5 are closed, the first input end of the second CLS unit is connected to one end of C1 via K2, the other end of C1 is connected to the second output end of the switch capacitor network unit, the second input end of the second CLS unit is connected to one end of C2 via K5, and the other end of C2 is connected to the fourth output end of the switch capacitor network unit.

[0039] It should be noted that when the first CLS unit performs the corresponding operation in response to the time control signal A, the capacitance of capacitors C1 and C2 will not change, that is, no charge transfer will occur on C1 and C2. Taking the first CLS unit as an example, ignoring the second cascaded CLS unit, when K1, K3, K4 and K6 are closed and K2 and K5 are open, one end of C1 is connected to the common mode voltage signal V CM The other end of C1 is connected to the first output terminal of the operational amplifier and one end of the integrating capacitor C7, and one end of C2 is connected to the common mode voltage signal V CM , the other end of C2 is connected to the second output terminal of the operational amplifier and one end of the integrating capacitor C8 respectively; when K1, K3, K4 and K6 are disconnected, and K2 and K5 are closed, C1 is originally connected to the common mode voltage signal V CM One end of C2 becomes the first input end of the first CLS unit (connected to the first output end of the operational amplifier), and C2 is originally connected to the common mode voltage signal V CM One end of the first CLS unit becomes the second input end of the first CLS unit (connected to the second output end of the operational amplifier). Since the capacitance of capacitors C1 and C2 does not change, the voltage values ​​at the two output ends of the operational amplifier are the same, both V CM , that is, the output of the operational amplifier is 0. According to the input-output relationship of the operational amplifier, the input of the operational amplifier is also zero. In other words, the output path of the operational amplifier is changed by the first CLS unit, so that the new operational amplifier is in a virtual short state. The new operational amplifier is composed of the first CLS unit and the operational amplifier.

[0040] Here, within one clock cycle, Ф 21 Output high level and Ф 22 When the output is low, K7, K9, K 10 and K 12 Closed, K8 and K 11 Disconnect, one end of the first capacitor C3 in the second CLS unit and one end of the second capacitor C4 in the second CLS unit are connected to the common mode voltage signal V CM The positive output terminal of the operational amplifier is connected to the other end of C3 via K9, and the other end of C3 is also connected to the first input terminal of the first CLS unit. The negative output terminal of the operational amplifier is connected to the other end of C3 via K9.12 The other end of C4 is connected to the second input end of the first CLS unit.

[0041] Here, within one clock cycle, Ф 21 Output low level and Ф 22 When outputting high level, K7, K9, K 10 and K 12 Disconnect, K8 and K 11 Closed, the positive output terminal of the operational amplifier is connected to one end of C3 via K8, the other end of C3 is connected to the first input terminal of the first CLS unit, and the negative output terminal of the operational amplifier is connected to the first input terminal of the first CLS unit via K8. 11 Connected to one end of C4, and the other end of C4 is connected to the second input end of the first CLS unit.

[0042] It should be noted that when the second CLS unit performs the corresponding operation in response to the timing control signal B, the capacitances of capacitors C3 and C4 do not change, that is, no charge transfer occurs on C3 and C4. The second CLS unit continues to change the output path of the new operational amplifier (composed of the first CLS unit and the operational amplifier) ​​based on the new operational amplifier, so that the updated operational amplifier is in a virtual short state. The updated operational amplifier is composed of the first CLS unit, the second CLS unit, and the operational amplifier.

[0043] It should be understood that when the cascaded CLS network unit includes N CLS units connected in series, the nth CLS unit changes the output path of a new operational amplifier formed by the first n-1 CLS units and the original operational amplifier. Each CLS unit changes the output path of the operational amplifier in the same manner. For the sake of brevity, this description will not be repeated here.

[0044] To address the problems of existing switched capacitor integration circuits used in sigma-delta ADCs, which rely on improving the operational amplifier structure to improve integration accuracy, resulting in low integration accuracy and difficulty adapting to sigma-delta ADCs with different resolution requirements, the present invention proposes a cascaded CLS switched capacitor integration circuit for sigma-delta ADCs. This circuit does not require improving the original structure of the operational amplifier. Instead, it changes the gain of the operational amplifier by changing the output path of the operational amplifier through at least two CLS units in the cascaded CLS network unit. With the changed gain value, the operational amplifier assists the switched capacitor network unit in performing integration operations. Compared to the traditional switched capacitor integration circuit that can only increase the gain of the operational amplifier once, the cascaded CLS switched capacitor integration circuit proposed in the present invention has higher integration accuracy. Moreover, the CLS units in the cascaded CLS network unit can be flexibly adjusted according to actual needs. The greater the number of CLS units, the higher the integration accuracy of the switched capacitor integration circuit. In other words, the technical solution proposed in the present invention can be flexibly adapted to sigma-delta ADCs with different resolution requirements.

[0045] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A cascaded CLS switched capacitor integrator circuit for sigma-delta ADC, characterized in that: include: A switched capacitor network unit, an operational amplifier, and a cascaded CLS network unit; the cascaded CLS network unit includes at least two CLS units connected in series; The switch capacitor network unit has a first input terminal for receiving a first voltage signal, a second input terminal for receiving a second voltage signal, and a third input terminal for receiving a common mode voltage signal V CM , the control end is used to receive the first time control signal, the first output end is connected to the inverting input end of the operational amplifier, the second output end is connected to the first output end of the cascaded CLS network unit, the third output end is connected to the non-inverting input end of the operational amplifier, and the fourth output end is connected to the second output end of the cascaded CLS network unit; the operational amplifier, the non-inverting output end is connected to the first input end of the cascaded CLS network unit, the inverting output end is connected to the second input end of the cascaded CLS network unit; the third input end of the cascaded CLS network unit is used to receive the common mode voltage signal V CM , the control terminal is used to access the second time control signal; The switched capacitor network unit is configured to sample the first voltage signal and the second voltage signal respectively in response to the first time control signal, and perform an integration operation on the first voltage signal and the second voltage signal and output an integration result; The cascaded CLS network unit is configured to change an output path of the operational amplifier in response to the second time control signal to change a gain of the operational amplifier; The operational amplifier is configured to utilize the gain to generate a virtual short effect, so as to assist the switched capacitor network unit in performing an integration operation; The circuit composition of each CLS unit in the cascaded CLS network unit is the same; each CLS unit includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor and a second capacitor; One end of the first switch is used to connect to the common mode voltage signal V CM , the other end of the first switch is connected to one end of the second switch and one end of the first capacitor respectively, the other end of the second switch is connected to one end of the third switch as a first input end of the CLS unit, and the other end of the third switch is connected to the other end of the first capacitor as a first output end of the CLS unit; One end of the fourth switch is used to connect to the common mode voltage signal V CM , the other end of the fourth switch is connected to one end of the fifth switch and one end of the second capacitor respectively, the other end of the fifth switch is connected to one end of the sixth switch to serve as a second input end of the CLS unit, and the other end of the sixth switch is connected to the other end of the second capacitor to serve as a second output end of the CLS unit; The cascaded CLS network unit includes N CLS units connected in series, and the second time control signal includes N time control signals, wherein the generation time of the nth time control signal is earlier than the n+1th time control signal, and the control end of the nth CLS unit is used to access the nth time control signal, where the value of n is 1 to N-1, and N is a positive integer greater than 1.

2. The cascaded CLS switched capacitor integration circuit for sigma-delta ADC according to claim 1, wherein: In the case where the cascaded CLS network unit includes a first CLS unit and a second CLS unit, the first input end of the second CLS unit is connected to the non-inverting output end of the operational amplifier, the second input end of the second CLS unit is connected to the inverting output end of the operational amplifier, the first output end of the second CLS unit is connected to the first input end of the first CLS unit, the second output end of the second CLS unit is connected to the second input end of the first CLS unit, the first output end of the first CLS unit is connected to the second output end of the switch capacitor network unit, and the second output end of the first CLS unit is connected to the fourth output end of the switch capacitor network unit.

3. The cascaded CLS switched capacitor integration circuit for sigma-delta ADC according to claim 2, wherein: The second time control signal includes: a time control signal A and a time control signal B, wherein the generation time of the time control signal A is earlier than the generation time of the time control signal B; the time control signal A includes a control signal Φ 11 and control signal Ф 12 ; The Ф 11 and the Φ 12 Inversion; the time control signal B includes a control signal Ф 21 and control signal Ф 22 ; The Ф 21 and the Φ 22 Inverted; The control terminals of the first switch K1, the third switch K3, the fourth switch K4 and the sixth switch K6 in the first CLS unit are connected to the Φ 11 The control ends of the second switch K2 and the fifth switch K5 in the first CLS unit are connected to the Φ 12 ; The first switch K7, the third switch K9, the fourth switch K 10 and the sixth open K 12 The control end is connected to the Ф 21 , the second switch K8 and the fifth switch K in the second CLS unit 11 The control end is connected to the Ф 22 .

4. The cascaded CLS switched capacitor integration circuit for sigma-delta ADC according to claim 3, wherein: In one clock cycle, the Φ 11 Output high level and the Ф 12 When the output is low level, the K1, K3, K4 and K6 in the first CLS unit are closed, the K2 and K5 are disconnected, and one end of the first capacitor C1 in the first CLS unit and one end of the second capacitor C2 in the first CLS unit are connected to the common mode voltage signal V CM The first input end of the second CLS unit is connected to the other end of the C1 via the K3, the other end of the C1 is also connected to the second output end of the switch capacitor network unit, the second input end of the second CLS unit is connected to the other end of the C2 via the K6, and the other end of the C2 is also connected to the fourth output end of the switch capacitor network unit.

5. The cascaded CLS switched capacitor integration circuit for sigma-delta ADC according to claim 4, wherein: In one clock cycle, the Φ 11 Output low level and the Ф 12 When a high level is output, the K1, the K3, the K4 and the K6 in the first CLS unit are disconnected, the K2 and the K5 are closed, the first input end of the second CLS unit is connected to one end of the C1 via the K2, the other end of the C1 is connected to the second output end of the switch capacitor network unit, the second input end of the second CLS unit is connected to one end of the C2 via the K5, and the other end of the C2 is connected to the fourth output end of the switch capacitor network unit.

6. The cascaded CLS switched capacitor integration circuit for sigma-delta ADC according to claim 3, wherein: In one clock cycle, the Φ 21 Output high level and the Ф 22 When the output is low, the K7, K9, and K 10 and the K 12 Closed, the K8 and the K 11 Disconnect, one end of the first capacitor C3 in the second CLS unit and one end of the second capacitor C4 in the second CLS unit are connected to the common mode voltage signal V CM The positive output terminal of the operational amplifier is connected to the other end of the C3 via the K9, the other end of the C3 is also connected to the first input terminal of the first CLS unit, and the negative output terminal of the operational amplifier is connected to the K 12 The other end of C4 is connected to the second input end of the first CLS unit.

7. The cascaded CLS switched capacitor integration circuit for sigma-delta ADC according to claim 6, wherein: In one clock cycle, the Φ 21 Output low level and the Ф 22 When outputting a high level, the K7, K9, and K 10 and the K 12 Disconnect, the K8 and the K 11 The positive output terminal of the operational amplifier is connected to one end of the C3 via the K8, the other end of the C3 is connected to the first input terminal of the first CLS unit, and the negative output terminal of the operational amplifier is connected to the K 11 The first terminal of the first CLS unit is connected to one end of the C4, and the other end of the C4 is connected to the second input end of the first CLS unit.

8. The cascaded CLS switched capacitor integration circuit for sigma-delta ADC according to claim 1, wherein: The first time control signal includes: a control signal S 2D , control signal S 1D , control signal S2 and control signal S1; the switch capacitor network unit includes: switch K 13 , switch K 14 , switch K 15 , switch K 16 , switch K 17 , switch K 18 , switch K 19 , switch K 20 , sampling capacitor C5, sampling capacitor C6, integrating capacitor C7 and integrating capacitor C8; The K 13 One end of the K 13 The other end is connected to one end of the C5 and the K 14 One end of the K 14 The other end is connected to the common mode voltage signal V CM , the other end of the C5 is connected to the K 15 One end and the K 16 One end of the K 15 The other end is connected to the common mode voltage signal V CM , the K 16 The other end of is connected to the inverting input end of the operational amplifier and one end of C7 respectively, and the other end of C7 is connected to the first output end of the cascaded CLS network unit; The K 17 One end of the K 17 The other end is connected to one end of C6 and the K 18 One end of the K 18 The other end is connected to the common mode voltage signal V CM , the other end of the C6 and the K 19 One end and the K 20 One end of the K 19 The other end is connected to the common mode voltage signal V CM , the K 20 The other end of is connected to the non-inverting input end of the operational amplifier and one end of C8 respectively, and the other end of C8 is connected to the second output end of the cascaded CLS network unit; The K 13 and the K 17 The control terminal is used to access the S 2D , the K 14 and the K 18 The control terminal is used to access the S 1D , the K 16 and the K 20 The control terminal is used to access the S1, the K 15 and the K 19 The control end is used to access the S2.

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