Two-level threshold frequency domain signal detection method and electronic equipment

Abstract

The present invention provides a two-level threshold frequency domain signal detection method and electronic device. The two-level threshold frequency domain signal detection method includes: applying multi-channel digital down-conversion processing to multi-channel synchronous ADC data to obtain synchronous down-converted data; processing single-channel down-converted data using stepped FFT and multi-channel parallel FFT through a reconnaissance path and a direction-finding path, and then sequentially performing complex amplitude estimation and bit width compression; performing synchronous alignment processing on the FFT absolute value and FFT bit width reduction to obtain a synchronous alignment result; packaging the reconnaissance spectrum data to obtain spectrum framing, and using double-precision floating-point calculation threshold arrays; obtaining the threshold array through an FPGA, and after applying two-level threshold detection, obtaining frequency domain signal detection results for the multi-channel synchronous ADC data. The present invention has the beneficial effects of improving resource utilization and frequency domain signal detection efficiency of the FPGA when performing frequency domain signal detection.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to a two-level threshold frequency domain signal detection method and electronic equipment. Background Art

[0002] Frequency-domain signal detection in communications and radar systems (i.e., detecting the FFT results of digitally down-converted signals) plays a crucial role in signal processing. Due to the high real-time performance and high bandwidth of FFT calculations implemented in FPGAs, it has become a widely used method for detecting and identifying communication and radar signals. A more suitable method for frequency-domain signal detection implemented in FPGAs is the threshold comparison-based method for detecting frequency-domain spectrum peaks.

[0003] When detecting high-speed frequency-hopping signals, the FFT length needs to be as small as possible while meeting the frequency resolution to obtain better time resolution, and each FFT window must be detected. When the channel bandwidth is high, traditional CPU calculations and even GPU-accelerated calculations can no longer meet the data processing throughput requirements. Summary of the Invention

[0004] The main purpose of the embodiments of the present invention is to provide a two-level threshold frequency domain signal detection method and electronic equipment, which improves the resource utilization of FPGA when performing frequency domain signal detection and improves the efficiency of frequency domain signal detection.

[0005] One aspect of the present invention provides a two-level threshold frequency domain signal detection method, including:

[0006] Acquire multi-channel synchronous ADC data through FPGA, and perform multi-channel digital down-conversion processing on the multi-channel synchronous ADC data to obtain synchronous down-conversion data, wherein the synchronous down-conversion data includes single-channel down-conversion data and multi-channel down-conversion data;

[0007] Processing the single-channel down-converted data using a stepped FFT through a detection path to obtain a first FFT result, performing complex amplitude estimation processing on the first FFT result to obtain an FFT absolute value;

[0008] Processing the multi-channel down-converted data using a multi-channel parallel FFT through a direction finding path to obtain a second FFT result, and performing bit width compression processing on the second FFT result to obtain FFT bit width reduction;

[0009] Performing synchronization alignment processing on the FFT absolute value and the FFT bit width reduction to obtain a synchronization alignment result, wherein the synchronization alignment result includes synchronized reconnaissance spectrum data and direction finding spectrum data;

[0010] The detected spectrum data is packaged to obtain a spectrum frame, the spectrum frame is obtained by a host computer, and a threshold array is calculated using a double-precision floating point;

[0011] Acquiring the threshold array through FPGA, and performing first-level frequency domain detection on the synchronization alignment result using the threshold array to obtain a first-level spectrum cache and a first-level detection result cache;

[0012] A second-level frequency domain detection is performed on the first-level spectrum cache and the first-level detection result cache to obtain a second-level detection result cache, wherein the second-level detection result cache is a frequency domain signal detection result of multiple synchronous ADC data.

[0013] According to the two-level threshold frequency domain signal detection method, wherein the multi-channel synchronous ADC data is subjected to multi-channel digital down-conversion processing to obtain synchronous down-conversion data, the method includes:

[0014] Obtain down-conversion frequency parameters from the host computer and cache them;

[0015] According to the down-conversion frequency parameters, multi-channel digital down-conversion processing is performed using a DDS instance through DDS, and then filtering is performed using an FIR filter to obtain the synchronous down-conversion data, wherein the frequency conversion points of each channel of the multi-channel digital down-conversion processing are consistent, and the frequency conversion point parameters of the DDS and FIR filters are set consistently.

[0016] According to the two-level threshold frequency domain signal detection method, the single-channel down-converted data is processed by a detection path using a stepped FFT to obtain a first FFT result, and the first FFT result is subjected to complex amplitude estimation processing to obtain an FFT absolute value, including:

[0017] The single-channel down-converted data is used as input and processed by a detection path using four FFT calculation instances with a step size of 1 / 4, wherein the first calculation instance does not skip data, and subsequent FFT calculation instances skip 1 / 4, 2 / 4, and 3 / 4 of the data in sequence, to obtain an FFT combination with a step size of 1 / 4.

[0018] The linear operation method is used to calculate the real and imaginary parts of the 1 / 4 step FFT combination, each of which is a 32-bit complex number. The formula of the linear operation method is:

[0019] mag=max(|I|,|Q|)*31 / 32+min(|I|,|Q|)*11 / 32

[0020] Where mag is the complex amplitude, I is the complex real part, and Q is the complex imaginary part.

[0021] According to the two-level threshold frequency domain signal detection method, wherein the multi-channel down-converted data is processed by a direction finding path using a multi-channel parallel FFT to obtain a second FFT result, and the second FFT result is subjected to bit width compression processing to obtain FFT bit width reduction, including:

[0022] Taking the multiple channels of down-converted data as input, processing the multiple channels of down-converted data through a direction finding path using an FFT calculation instance consistent with the number of channels of the multiple channels of down-converted data to obtain a second FFT result;

[0023] The second FFT result is compressed by using a signed square root, including compressing the real and imaginary parts of the second FFT result into 32-bit wide data, and compressing the real and imaginary parts into 16-bit wide data by using a signed square root in a two's complement manner, wherein the two's complement manner includes complementing the 32-bit wide data, retaining the corresponding sign bit information bit, and then performing a square root operation, converting the 32-bit wide data into a signed number according to the sign bit information bit, thereby obtaining a reduced FFT bit width.

[0024] According to the two-level threshold frequency domain signal detection method, the method further includes:

[0025] When the 16-bit wide data with reduced FFT bit width is sent to the host computer, the host computer performs a signed square operation on the 16-bit wide data to restore the 16-bit wide data.

[0026] According to the two-level threshold frequency domain signal detection method, the FFT absolute value and the FFT bit width reduction are synchronously aligned to obtain a synchronous alignment result, including:

[0027] A first-in-first-out queue cache having the same number as the down-conversion processing is used to perform synchronous alignment processing on the FFT absolute value and the FFT bit width reduction, wherein the synchronous alignment processing includes aligning a first calculation instance after complex amplitude estimation with the FFT bit width reduction; wherein the depth of the first-in-first-out queue cache is not less than the data volume difference caused by the delay difference between the reconnaissance path and the direction finding path.

[0028] According to the two-level threshold frequency domain signal detection method, the detection spectrum data is packaged and processed to obtain spectrum framing, the spectrum framing is obtained by the host computer and the threshold array is calculated using double-precision floating point, including:

[0029] The threshold array is obtained by using sorting-based noise estimation and weighted fitting processing;

[0030] According to the threshold array, the host computer is updated and the updated threshold array is sent to the FPGA, and the threshold array and the copy of the threshold array are cached by the FPGA using a threshold cache RAM that is consistent with the number of detection path calculation instances.

[0031] According to the two-level threshold frequency domain signal detection method, wherein the threshold array is obtained through FPGA, the threshold array is used to perform first-level frequency domain detection on the synchronization alignment result to obtain a first-level spectrum cache and a first-level detection result cache, including:

[0032] Performing a first-level frequency domain detection using a first-level state machine, including resetting the first-level state machine and transferring the first-level state machine from an IDLE state to a GET_RISE_EDGE state;

[0033] When in the GET_RISE_EDGE state and a rising edge of a frequency domain spectrum peak is detected, the first-level state machine is transferred from the GET_RISE_EDGE state to the GET_FALL_EDGE state;

[0034] In the GET_FALL_EDGE state and detecting the falling edge of the frequency domain spectrum peak, the first-level state machine is transferred from the GET_FALL_EDGE state to the IDLE state;

[0035] Repeat the frequency domain detection of the first-level state machine to obtain the first-level detection result cache;

[0036] When frequency domain detection is performed on the first-level state machine, the spectrum data of the detection channel is written into the cache to obtain the first-level spectrum cache.

[0037] According to the two-level threshold frequency domain signal detection method, performing a second-level frequency domain detection on the first-level spectrum cache and the first-level detection result cache to obtain a second-level detection result cache includes:

[0038] Using the second-level state machine to perform the second-level frequency domain detection, including resetting the second-level state machine and transferring the second-level state machine from the IDLE state to the RD_COA state;

[0039] When in the RD_COA state and a first-level detection result cache is read, the second-level state machine is transferred from the RD_COA state to the SEARCH_LEFT state;

[0040] In the SEARCH_LEFT state and the peak point of the indicated spectrum peak is detected to the left, the detection is continued until the first end condition is triggered, where the first end condition is that the amplitude corresponding to the current frequency index is less than the threshold array or the left half width of the spectrum peak exceeds a spectrum peak range. After the first end condition is triggered, the state is transferred to the PRE_SEARCH_RIGHT state;

[0041] When in the PRE_SEARCH_RIGHT state, the variables of the second-level state machine are reset and transferred to the SEARCH_RIGHT state;

[0042] When in the SEARCH_RIGHT state and the peak point of the indicated spectrum peak is detected to the right, the detection is continued until the second end condition is triggered, where the second end condition is that the amplitude corresponding to the current frequency index is less than the threshold array or the right half width of the spectrum peak exceeds a spectrum range. After the end condition is triggered, it transfers to the WR_RESULT state;

[0043] When in the WR_RESULT state, the detection result of the second-level state machine is written into the first-in-first-out queue cache and transferred to the IDLE state;

[0044] The frequency domain detection of the second-level state machine is repeatedly executed to obtain a second-level detection result cache.

[0045] Another aspect of an embodiment of the present invention provides an electronic device, including a processor and a memory;

[0046] The memory is used to store programs;

[0047] The processor executes the program to implement the method described above.

[0048] The beneficial effects of the present invention are as follows: through configurable multi-channel digital down-conversion processing, frequency conversion consistency is achieved during subsequent multi-channel processing; through the use of linear operation in the detection path for complex amplitude estimation processing, waste of system resources caused by excessively high bit width is reduced; through the bit width compression processing in the complement method, wiring difficulties existing in the direction finding path when detecting high bit width data are improved, detection performance and resource consumption ratio are improved; before frequency domain signal detection, synchronous alignment is performed to ensure that the detection path and the direction finding path have completely consistent structures and delays before FFT calculation, and a double-precision floating-point calculation algorithm is used to calculate the threshold array, thereby improving the detection effect of frequency bands with uneven background noise; and through the use of a two-level threshold detection method, resource utilization rate of FPGA when performing frequency domain signal detection is improved, and frequency domain signal detection efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0050] Figure 1 It is a flowchart of a two-level threshold frequency domain signal detection method according to an embodiment of the present invention.

[0051] Figure 2 It is a schematic diagram of a multi-channel digital down-conversion processing flow in an embodiment of the present invention.

[0052] Figure 3 Schematic diagram of synchronous alignment of a direction finding path and a reconnaissance path according to an embodiment of the present invention.

[0053] Figure 4 4 is a schematic diagram of a threshold calculation process according to an embodiment of the present invention.

[0054] Figure 5 Schematic diagram of a threshold cache RAM copy according to an embodiment of the present invention.

[0055] Figure 6 Schematic diagram of the first-level detection state machine of an embodiment of the present invention.

[0056] Figure 7 2 is a schematic diagram of a second-level detection state machine according to an embodiment of the present invention.

[0057] Figure 8 2 is a schematic diagram of frequency domain detection with two-level thresholds according to an embodiment of the present invention.

[0058] Figure 9 Schematic diagram of the frequency domain signal detection framework with two-level thresholds. DETAILED DESCRIPTION

[0059] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. In the subsequent description, suffixes such as "module," "component," or "unit" used to represent elements are used solely to facilitate the description of the present invention and have no specific meaning in themselves. Therefore, "module," "component," or "unit" may be used interchangeably. "First," "second," and the like are used solely to distinguish technical features and should not be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features. In this subsequent description, the consecutive numbering of method steps is for ease of review and understanding. In conjunction with the overall technical solution of the present invention and the logical relationship between the various steps, adjusting the order of implementation of the steps does not affect the technical effects achieved by the technical solution of the present invention. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and should not be construed as limiting the present invention.

[0060] refer to Figure 1 , Figure 1 This is a flow chart of a two-level threshold frequency domain signal detection method according to an embodiment of the present invention. It includes but is not limited to the following steps:

[0061] S100, acquiring multi-channel synchronous ADC data through FPGA, performing multi-channel digital down-conversion processing on the multi-channel synchronous ADC data to obtain synchronous down-converted data, wherein the synchronous down-converted data includes single-channel down-converted data and multi-channel down-converted data.

[0062] In some embodiments, the multi-channel synchronous ADC data is a frequency domain signal to be detected.

[0063] In some embodiments, reference Figure 2 The multi-channel digital down-conversion process flow diagram shown includes but is not limited to steps S110 to S120:

[0064] S110, obtaining down-conversion frequency parameters from the host computer and caching them;

[0065] S120 , performing multi-channel digital down-conversion processing using a DDS instance according to the down-conversion frequency parameters, and then performing filtering processing using an FIR filter to obtain a synchronous down-conversion frequency.

[0066] In some embodiments, the frequency conversion points of each channel of the multi-channel digital down-conversion processing are consistent, and the frequency conversion point parameters of the DDS and FIR filters are set consistently. Preferably, it is best to use only one DDS instance to ensure the consistency of the frequency conversion processing of each channel of the multi-channel digital down-conversion processing.

[0067] For example, multi-channel downconversion uses a DDS+FIR architecture, and the DDS frequency is configurable. The host computer sends the downconversion frequency parameters to the corresponding buffer in the FPGA. This allows the same downconversion frequency to be used for all six channels, with the same low-pass FIR filter parameters, to produce six channels of synchronized downconverted data. It's worth noting that it's best to use only one DDS instance to ensure consistency across all six channels.

[0068] S200 , processing the single-channel down-converted data by using a stepped FFT through a detection path to obtain a first FFT result, performing complex amplitude estimation processing on the first FFT result to obtain an FFT absolute value.

[0069] In some embodiments, the first FFT result represents a frequency domain magnitude.

[0070] In some embodiments, a single channel of down-converted data is used as input and processed by a detection path using four FFT calculation instances with a step size of 1 / 4, wherein the first calculation instance does not skip data, and subsequent FFT calculation instances skip 1 / 4, 2 / 4, and 3 / 4 of the data in sequence, to obtain an FFT combination with a step size of 1 / 4.

[0071] The linear operation method is used to calculate the real and imaginary parts of the 1 / 4 step FFT combination, each of which is a 32-bit complex number. The formula of the linear operation method is:

[0072] mag=max(|I|,|Q|)*31 / 32+min(|I|,|Q|)*11 / 32

[0073] Where mag is the complex amplitude, I is the complex real part, and Q is the complex imaginary part.

[0074] Exemplarily, the reconnaissance path takes the first channel of data from the six channels of synchronous down-converted data as input, processes the single channel of down-converted data using a stepped FFT, and converts the FFT result into an absolute value form using a complex amplitude estimation.

[0075] In some embodiments, the stepped FFT sets the FFT length to 8192 and the step to 1 / 4, and uses 4 FFT calculation instances. When the calculation starts, the first FFT calculation instance does not skip data, the second skips 2048 data, the third skips 4096 data, and the fourth skips 6144 data, thereby forming an FFT combination with a 1 / 4 step. The purpose of this embodiment of the present invention is to improve the time resolution, that is, when calculating the time resolution, the equivalent number of FFT points is 2048, not 8192.

[0076] In some embodiments, the data before the FFT operation for complex amplitude estimation is a complex number with 16 bits of real and imaginary parts, and the data after the FFT operation is a complex number with 32 bits of real and imaginary parts. Using the standard ABS method or only calculating the sum of squares will cause waste of resources due to the high bit width. A simple linear operation method is used to perform amplitude estimation with an acceptable error.

[0077] S300 , processing the multi-channel down-converted data by using a multi-channel parallel FFT through a direction finding channel to obtain a second FFT result, and performing bit width compression processing on the second FFT result to obtain FFT bit width reduction.

[0078] In some embodiments, the second FFT result is a frequency domain IQ bit width compressed value.

[0079] In some embodiments, a plurality of down-converted data are input and processed through a direction finding path using an FFT calculation instance consistent with the number of channels of the multi-channel down-converted data to obtain a second FFT result; the second FFT result is subjected to data bit width compression using a signed number square root, including compressing the real part and the imaginary part of the second FFT result into 16-bit wide data by using a signed number square root in a two's complement manner, wherein the two's complement manner includes complementing the 32-bit wide data, retaining the corresponding sign bit information bit, and then performing a square root operation, converting the 32-bit wide data into a signed number according to the sign bit information bit, thereby obtaining FFT bit width reduction.

[0080] In some embodiments, the direction finding path takes the last five channels of data from the six channels of synchronous down-converted data as input. The direction finding path processes the multiple channels of down-converted data using multiple parallel FFTs and converts the FFT results into a reduced-bitwidth format using bit width compression.

[0081] In some embodiments, multi-channel parallel FFT uses five identical FFT calculation instances to process five channels of data. It should be noted that the FFT calculation instance here is exactly the same as the FFT instance used in the reconnaissance path. Most fundamentally, the number of FFT points is consistent, thereby ensuring a one-to-one correspondence between the FFT index for reconnaissance and the FFT index for direction finding.

[0082] In some embodiments, bit width compression is used to ensure the accuracy of the direction finding information output by the multi-channel parallel FFT. It is necessary to retain data with a bit width of 32 bits for the real and imaginary parts, totaling 64 bits. Due to the high data bit width, serious layout and wiring difficulties are encountered when framing the data. To solve this problem, the method of square root of signed numbers is used to compress the data bit width.

[0083] In some embodiments, the real and imaginary parts are respectively squared with signed numbers, thereby compressing the bit width to 16 bits for each of the real and imaginary parts, thereby solving this problem.

[0084] In some embodiments, the method of square root of a signed number is implemented by using the complement method. First, the complement of the original data is calculated and the corresponding sign bit information is retained. Then the square root operation is performed normally, and finally it is converted into a signed number based on the sign bit information.

[0085] Correspondingly, in subsequent host computer processing, the corresponding signed square operation needs to be performed to restore the data that has undergone this bit width compression. After error analysis, the direction-finding error introduced by this method can be ignored, achieving a balance between performance and resources during signal detection.

[0086] S400 , performing synchronization alignment processing on the FFT absolute value and the FFT bit width reduction to obtain a synchronization alignment result, wherein the synchronization alignment result includes synchronized reconnaissance spectrum data and direction finding spectrum data.

[0087] In some embodiments, a first-in-first-out queue cache having the same number of down-conversion processes is used to perform synchronous alignment processing on the FFT absolute value and the FFT bit width reduction, wherein the synchronous alignment processing includes aligning the first calculation instance after complex amplitude estimation with the FFT bit width reduction; wherein the depth of the first-in-first-out queue cache is not less than the data volume difference caused by the delay difference between the reconnaissance path and the direction finding path.

[0088] refer to Figure 3 The schematic diagram of the synchronous alignment of the direction finding path and the reconnaissance path is shown in FIG. 2 . The reconnaissance path and the direction finding path have completely identical structures and delays before FFT calculation. However, after FFT calculation, as shown in FIG. Figure 3 As shown in the figure, the reconnaissance path needs to calculate the frequency domain amplitude, while the direction finding path needs to calculate the frequency domain IQ bit width compression value. The delays of these two processes are inconsistent, so a cache is needed to synchronize the two types of data to ensure strict alignment. Specifically, six identical FIFOs are used to form this cache. It is important to ensure that the FIFO depth is not less than the data volume difference caused by the delay difference between the reconnaissance path and the direction finding path.

[0089] like Figure 3 As shown, synchronization alignment refers to synchronizing the first FFT of the quarter-step of the direction-finding and reconnaissance paths (i.e., the one that starts the calculation first). The FFT outputs of the other three reconnaissance paths are not tied to the direction-finding information. During frequency-domain detection, paths without direction-finding information simply set the relevant inputs to 0, creating no mechanical difference from paths with direction-finding information. After combining the multi-path detection results into a single data stream, it can be transmitted to the host computer.

[0090] S500: Packaging the detected spectrum data to obtain spectrum frames, obtaining the spectrum frames through the host computer and calculating the threshold array using double-precision floating point.

[0091] In some embodiments, a threshold array is obtained by using sorting-based background noise estimation and weighted fitting processing; based on the threshold array, the host computer is updated, and the updated threshold array is sent to the FPGA, and the threshold array and a copy of the threshold array are cached by the FPGA using a threshold cache RAM that is consistent with the number of detection path calculation instances.

[0092] In some embodiments, reference Figure 4The threshold calculation process diagram shown in the figure requires first packaging the spectrum data of the detection path, appending frame headers and footers, and then transmitting it to the host computer. The host computer uses a double-precision floating-point calculation algorithm to calculate the threshold array. It mainly consists of two steps: sorting-based noise floor estimation and weighted fitting. In this way, it can achieve better detection effect on frequency bands with uneven noise floor.

[0093] In some embodiments, reference Figure 5 As shown in the threshold cache RAM copy diagram, the host computer sends the calculated threshold array to the FPGA through the PCIe interface. The FPGA saves the threshold array in the first-level detection threshold cache and uses the threshold in frequency domain detection.

[0094] Since the FFT step of the reconnaissance path is 1 / 4 and 4 FFT calculation instances are used, there are actually 4 copies of its threshold array. After 8192 data, they will be used simultaneously. Therefore, when receiving the thresholds sent by the host computer, they are written into the same 4 cache RAMs at the same time.

[0095] S600: Obtain a threshold array through FPGA, use the threshold array to perform first-level frequency domain detection on the synchronization alignment result, and obtain a first-level spectrum cache and a first-level detection result cache.

[0096] In some embodiments, the first-level frequency domain detection is performed by using a first-level state machine. Specifically, refer to Figure 6 The first-level detection state machine diagram shown in the figure requires three states to complete the first-level detection function. After reset is completed, the state transitions from IDLE to GET_RISE_EDGE. In this state, if a rising edge of a frequency domain spectrum peak is detected, the state transitions from GET_RISE_EDGE to GET_FALL_EDGE. In this state, if a falling edge of a frequency domain spectrum peak is detected, the state transitions from GET_FALL_EDGE to IDLE. At this point, the next detection cycle can begin.

[0097] S700 , performing second-level frequency domain detection on the first-level spectrum cache and the first-level detection result cache to obtain a second-level detection result cache, wherein the second-level detection result cache is a frequency domain signal detection result of multiple channels of synchronous ADC data.

[0098] In some embodiments, the second-level frequency domain detection is performed by using a second-level state machine. Specifically, refer to Figure 7The first-level detection state machine diagram shown requires six states to complete the second-level detection function. After reset, the state transitions from the IDLE state to the RD_COA state. In this state, a first-level detection result is read. The state then transitions to the SEARCH_LEFT state. In this state, detection is performed from the peak point of the spectrum indicated by the first-level detection result to the left, in the direction of decreasing frequency index, until the end condition is triggered. This condition is when the amplitude corresponding to the current frequency index is less than the threshold or the left half-width of the spectrum peak exceeds a certain range. After the end condition is triggered, the state transitions to the PRE_SEARCH_RIGHT state. In this state, certain variables are reset and the state transitions to the SEARCH_RIGHT state. In this state, detection is performed from the peak point of the spectrum indicated by the first-level detection result to the right, in the direction of increasing frequency index, until the end condition is triggered. This condition is when the amplitude corresponding to the current frequency index is less than the threshold or the right half-width of the spectrum peak exceeds a certain range. After the end condition is triggered, the state transitions to the WR_RESULT state. In this state, the second-level detection result is written to the buffer FIFO and the state transitions to the IDLE state. At this point, the next detection cycle can begin.

[0099] In some embodiments, reference Figure 8 The diagram shows a two-level threshold frequency domain detection scheme. Synchronous frequency domain data for reconnaissance and direction finding is input into the first-level detection module. The first-level detection module reads the first-level detection threshold buffer, performs detection on the frequency domain data, and generates a first-level detection result (this result primarily includes the peak point index, second-level threshold, and peak point direction finding information). This result is then written to the first-level detection result buffer. Simultaneously, the spectrum of the reconnaissance channel is continuously written to the spectrum buffer. The second-level detection module first reads a first-level detection result, then performs a second-level detection on the spectrum buffer based on the second-level detection threshold contained in this result. Finally, the second-level detection result (this result primarily includes the spectrum peak bandwidth, spectrum peak power, spectrum peak center frequency index, spectrum peak start frequency index, spectrum peak end frequency index, and multi-channel direction finding information associated with the spectrum peak point) is written to the buffer.

[0100] In some embodiments, reference Figure 9 The schematic diagram of the two-level threshold frequency domain signal detection framework is shown in Figure 1. Its functions are as follows:

[0101] a) Use a multi-channel digital down-conversion module with configurable frequency points to process the input multi-channel synchronous ADC data;

[0102] b) Constructing a detection path: Using a stepped FFT module to process the single-channel down-converted data, and using a complex amplitude estimation module to convert the FFT results into absolute value form;

[0103] c) Building a direction finding path: Using a multi-channel parallel FFT module to process the multi-channel down-converted data, and using a bit width compression module to convert the FFT results into a reduced bit width form;

[0104] d) Transmitting the real-time spectrum data to the host computer, which uses a sorting-based threshold algorithm to calculate the first-level detection threshold array and sends it to the FPGA;

[0105] e) FPGA receives and caches the first-level detection threshold array from the host computer, performs frequency domain detection and direction finding information extraction;

[0106] f) framing the test results and transmitting them to the host computer;

[0107] g) Perform subsequent processing on the host computer, such as receiving and storing test results.

[0108] An embodiment of the present invention further provides an electronic device, the electronic device including a processor and a memory;

[0109] The memory stores a program;

[0110] The processor executes a program to perform the aforementioned two-level threshold frequency domain signal detection method; the electronic device has the function of carrying and running the two-level threshold frequency domain signal detection software system provided by the embodiment of the present invention, such as a personal computer, a minicomputer, a main frame, a workstation, a network or distributed computing environment, a separate or integrated computer platform, or communicating with a charged particle tool or other imaging device, etc.

[0111] An embodiment of the present invention further provides a computer-readable storage medium, wherein the storage medium stores a program, and the program is executed by a processor to implement the frequency domain signal detection method with two-level thresholds as described above.

[0112] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided in an exemplary manner for the purpose of providing a more comprehensive understanding of the technology. The disclosed method is not limited to the operation and logic flow presented herein. Optional embodiments are contemplated in which the order of the various operations is changed and the sub-operations described as a part of a larger operation are performed independently.

[0113] An embodiment of the present invention further discloses a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium and execute the computer instructions, causing the computer device to perform the aforementioned two-level threshold frequency domain signal detection method.

[0114] Furthermore, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise indicated, one or more of the functions and / or features described may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It will also be understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present invention. More specifically, given the properties, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the module will be understood within the ordinary skill of an engineer. Therefore, a person skilled in the art using ordinary skill will be able to implement the present invention set forth in the claims without undue experimentation. It will also be understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0115] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0116] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0117] More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic devices), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering, or processing in another suitable manner as necessary, and then stored in a computer memory.

[0118] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0119] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0120] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

[0121] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A two-level threshold frequency domain signal detection method, characterized in that: include: Acquire multi-channel synchronous ADC data through FPGA, and perform multi-channel digital down-conversion processing on the multi-channel synchronous ADC data to obtain synchronous down-conversion data, wherein the synchronous down-conversion data includes single-channel down-conversion data and multi-channel down-conversion data; Processing the single-channel down-converted data using a stepped FFT through a detection path to obtain a first FFT result, performing complex amplitude estimation processing on the first FFT result to obtain an FFT absolute value; Processing the multi-channel down-converted data using a multi-channel parallel FFT through a direction finding path to obtain a second FFT result, and performing bit width compression processing on the second FFT result to obtain FFT bit width reduction; Performing synchronization alignment processing on the FFT absolute value and the FFT bit width reduction to obtain a synchronization alignment result, wherein the synchronization alignment result includes synchronized reconnaissance spectrum data and direction finding spectrum data; The detected spectrum data is packaged to obtain a spectrum frame, the spectrum frame is obtained by a host computer, and a threshold array is calculated using a double-precision floating point; Acquiring the threshold array through FPGA, and performing first-level frequency domain detection on the synchronization alignment result using the threshold array to obtain a first-level spectrum cache and a first-level detection result cache; A second-level frequency domain detection is performed on the first-level spectrum cache and the first-level detection result cache to obtain a second-level detection result cache, wherein the second-level detection result cache is a frequency domain signal detection result of multiple synchronous ADC data.

2. The two-level threshold frequency domain signal detection method according to claim 1, characterized in that: The multi-channel digital down-conversion processing is performed on the multi-channel synchronous ADC data to obtain synchronous down-conversion data, including: Obtain down-conversion frequency parameters from the host computer and cache them; According to the down-conversion frequency parameters, multi-channel digital down-conversion processing is performed using a DDS instance through DDS, and then filtering is performed using an FIR filter to obtain the synchronous down-conversion data, wherein the frequency conversion points of each channel of the multi-channel digital down-conversion processing are consistent, and the frequency conversion point parameters of the DDS and FIR filters are set consistently.

3. The two-level threshold frequency domain signal detection method according to claim 1, characterized in that: The step-by-step FFT is used to process the single-channel down-converted data through the detection path to obtain a first FFT result, and the complex amplitude estimation process is performed on the first FFT result to obtain an FFT absolute value, including: The single-channel down-converted data is used as input and processed by a detection path using four FFT calculation instances with a step size of 1 / 4, wherein the first calculation instance does not skip data, and subsequent FFT calculation instances skip 1 / 4, 2 / 4, and 3 / 4 of the data in sequence, to obtain an FFT combination with a step size of 1 / 4. The linear operation method is used to calculate the real and imaginary parts of the 1 / 4 step FFT combination, each of which is a 32-bit complex number. The formula of the linear operation method is: mag=max(|I|,|Q|)*31 / 32+min(|I|,|Q|)*11 / 32 Where mag is the complex amplitude, I is the complex real part, and Q is the complex imaginary part.

4. The two-level threshold frequency domain signal detection method according to claim 3, characterized in that: The method of processing the multi-channel down-converted data by using a multi-channel parallel FFT through a direction finding path to obtain a second FFT result, and performing bit width compression processing on the second FFT result to obtain FFT bit width reduction includes: Taking the multiple channels of down-converted data as input, processing the multiple channels of down-converted data through a direction finding path using an FFT calculation instance consistent with the number of channels of the multiple channels of down-converted data to obtain a second FFT result; The second FFT result is compressed by using a signed square root, including compressing the real and imaginary parts of the second FFT result into 32-bit wide data, and compressing the real and imaginary parts into 16-bit wide data by using a signed square root in a two's complement manner, wherein the two's complement manner includes complementing the 32-bit wide data, retaining the corresponding sign bit information bit, and then performing a square root operation, converting the 32-bit wide data into a signed number according to the sign bit information bit, thereby obtaining a reduced FFT bit width.

5. The two-level threshold frequency domain signal detection method according to claim 4, characterized in that: The method further comprises: When the 16-bit wide data with reduced FFT bit width is sent to the host computer, the host computer performs a signed square operation on the 16-bit wide data to restore the 16-bit wide data.

6. The two-level threshold frequency domain signal detection method according to claim 3, characterized in that: The performing synchronization alignment processing on the FFT absolute value and the FFT bit width reduction to obtain a synchronization alignment result includes: A first-in-first-out queue cache having the same number as the down-conversion processing is used to perform synchronous alignment processing on the FFT absolute value and the FFT bit width reduction, wherein the synchronous alignment processing includes aligning a first calculation instance after complex amplitude estimation with the FFT bit width reduction; wherein the depth of the first-in-first-out queue cache is not less than the data volume difference caused by the delay difference between the reconnaissance path and the direction finding path.

7. The two-level threshold frequency domain signal detection method according to claim 1, characterized in that: The process of packaging the detected spectrum data to obtain spectrum framing, obtaining the spectrum framing through a host computer, and calculating a threshold array using a double-precision floating point includes: The threshold array is obtained by using sorting-based noise estimation and weighted fitting processing; According to the threshold array, the host computer is updated and the updated threshold array is sent to the FPGA, and the threshold array and the copy of the threshold array are cached by the FPGA using a threshold cache RAM that is consistent with the number of detection path calculation instances.

8. The two-level threshold frequency domain signal detection method according to claim 1, characterized in that: The acquiring the threshold array through the FPGA, performing a first-level frequency domain detection on the synchronization alignment result using the threshold array, and obtaining a first-level spectrum cache and a first-level detection result cache, includes: Performing a first-level frequency domain detection using a first-level state machine, including resetting the first-level state machine and transferring the first-level state machine from an IDLE state to a GET_RISE_EDGE state; When in the GET_RISE_EDGE state and a rising edge of a frequency domain spectrum peak is detected, the first-level state machine is transferred from the GET_RISE_EDGE state to the GET_FALL_EDGE state; In the GET_FALL_EDGE state and detecting the falling edge of the frequency domain spectrum peak, the first-level state machine is transferred from the GET_FALL_EDGE state to the IDLE state; Repeat the frequency domain detection of the first-level state machine to obtain the first-level detection result cache; When frequency domain detection is performed on the first-level state machine, the spectrum data of the detection channel is written into the cache to obtain the first-level spectrum cache.

9. The two-level threshold frequency domain signal detection method according to claim 1, characterized in that: The performing second-level frequency domain detection on the first-level spectrum cache and the first-level detection result cache to obtain a second-level detection result cache includes: Using the second-level state machine to perform the second-level frequency domain detection, including resetting the second-level state machine and transferring the second-level state machine from the IDLE state to the RD_COA state; When in the RD_COA state and a first-level detection result cache is read, the second-level state machine is transferred from the RD_COA state to the SEARCH_LEFT state; In the SEARCH_LEFT state and the peak point of the indicated spectrum peak is detected to the left, the detection is continued until the first end condition is triggered, where the first end condition is that the amplitude corresponding to the current frequency index is less than the threshold array or the left half width of the spectrum peak exceeds a spectrum peak range. After the first end condition is triggered, the state is transferred to the PRE_SEARCH_RIGHT state; When in the PRE_SEARCH_RIGHT state, the variables of the second-level state machine are reset and transferred to the SEARCH_RIGHT state; When in the SEARCH_RIGHT state and the peak point of the indicated spectrum peak is detected to the right, the detection is continued until the second end condition is triggered, where the second end condition is that the amplitude corresponding to the current frequency index is less than the threshold array or the right half width of the spectrum peak exceeds a spectrum range. After the end condition is triggered, it transfers to the WR_RESULT state; When in the WR_RESULT state, the detection result of the second-level state machine is written into the first-in-first-out queue cache and transferred to the IDLE state; The frequency domain detection of the second-level state machine is repeatedly executed to obtain a second-level detection result cache.

10. An electronic device, characterized in that: Including processor and memory: The memory is used to store programs; The processor executes the program to implement the two-level threshold frequency domain signal detection method according to any one of claims 1 to 9.

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