Voltage regulator

Abstract

The present disclosure relates to voltage regulators. The voltage regulator has a first output connected to a capacitive element. A current source is coupled between the first output and a first node that receives a supply voltage. The current source delivers a first DC current in response to assertion of a first binary signal. A comparator asserts a second binary signal when a first voltage on the first output is lower than a setpoint voltage. A first circuit controls assertion of the first signal for a first fixed time period when the second binary signal is asserted.

Description

[0001] CLAIM

[0002] This application claims the priority benefit of French Patent Application No. 2305578, filed on June 2, 2023, the entire contents of which are incorporated herein by reference to the maximum extent legally permissible. TECHNICAL FIELD

[0003] The present disclosure relates generally to electronic circuits (e.g., integrated electronic circuits), and more particularly to voltage regulators. BACKGROUND

[0004] A voltage regulator is a device or circuit configured to deliver a regulated DC voltage based on a DC supply voltage, the regulated DC voltage having a value determined by a setpoint voltage or value. Many voltage regulators are known.

[0005] For example, known linear voltage regulators include a metal-oxide-semiconductor (MOS) transistor coupling an application node of a supply voltage to a node for delivering a regulated voltage, and a comparator delivering a signal representative of a comparison of the value of the regulated voltage to the value of the setpoint voltage, or an error amplifier delivering an error signal representative of an error between the value of the regulated voltage and the setpoint value. A gate of the MOS transistor is then controlled according to the signal delivered by the comparator or amplifier, so that the regulated voltage is equal to the setpoint voltage. The transistor can have a P-channel (PMOS) or N-channel (NMOS) configuration. NMOS transistors have a better power supply rejection ratio (PSRR) than PMOS transistors. However, implementing the control of such NMOS transistors requires a prior knowledge of the static power consumption of the load. Now, this static power consumption depends on PVT (“process-voltage-temperature”) parameters, which raises a problem.

[0006] Furthermore, when trying to reduce the static power consumption of the regulator, the bandwidth of known linear voltage regulators is reduced, for example so that the static power consumption of the regulator is lower than 5% of the average power consumption of the load (for example, less than or equal to about 10 μΑ at 27°C), or for example so that the static power consumption of the regulator is lower than 200 nA, or even lower than 100 nA for a load having a static power consumption of the order of 3 μΑ. This reduction of the regulator bandwidth is not desirable, as it leads to an increase of the variations of the regulated voltage around its setpoint value.

[0007] As an alternative example, known charge pump voltage regulators include switched-capacitor elements. However, the provision of the capacitive elements of the charge pump makes these regulators bulky. Furthermore, the capacitive elements are usually assembled outside the chip including the charge pump switches, which makes the charge pump circuit more complex. This also requires an increase in the number of input / output pads on the chip, which is not always possible.

[0008] As another alternative example, known voltage regulators include Switched Mode Power Supplies (SMPS). However, Switched Mode Power Supplies require the provision of coils, which makes the regulator bulky. Moreover, SMPS-type regulators are noise sources for the electronic systems to which they belong, which creates problems when these systems include noise-sensitive circuits (or applications).

[0009] The three known examples of voltage regulators described above all have drawbacks related to their power consumption and / or bulk and / or regulation speed.

[0010] More generally, known voltage regulators have drawbacks.

[0011] There is a need to overcome all or part of the drawbacks of known voltage regulators.

[0012] For example, there is a need for a voltage regulator that has low static power consumption, is small in bulk and is fast in response.

[0013] For example, there is a need for a voltage regulator that enables limiting the value of the inrush current on the output of the regulator.

[0014] For example, there is a need for a regulator that supplies information indicating the average value of the current consumed by a load connected to the output of the regulator. SUMMARY

[0015] Embodiments overcome all or part of the drawbacks of known voltage regulators.

[0016] For example, embodiments provide a voltage regulator that has low static power consumption (e.g. lower than 200 nA, or even lower than 100 nA) when the load it powers is idle and has a static power consumption of the order of 3 μΑ, and that is small in bulk and fast in response.

[0017] Embodiments provide a voltage regulator comprising: a first output intended to be connected to a capacitive element; a current source coupling the first output to a first node configured to receive a supply voltage, the current source being configured to deliver a first DC current only when a first binary signal is in its first binary state (enabling state); a comparator configured to deliver a second binary signal in its first binary state (enabling state) when a first voltage on the first output is lower than a setpoint voltage; and a first circuit configured to set the first signal to its first binary state and for a first fixed time period when the second binary signal is in its first binary state.

[0018] According to embodiments, the first time period is fixed and independent of the supply voltage, or is fixed and determined by the supply voltage.

[0019] According to an embodiment, the DC current has a fixed value independent of temperature.

[0020] According to an embodiment, the DC current has a value proportional to the absolute value of temperature.

[0021] According to an embodiment, the regulator further comprises a surge current regulation circuit configured to periodically force the second binary signal to reach its second binary state (non-active state) and to last for a second fixed time period during a surge current regulation phase.

[0022] According to an embodiment, the regulator comprises a measurement circuit configured to supply, at the end of each of said measurement periods, a number of first time periods that have started during said measurement period.

[0023] According to an embodiment, the first time periods and the current source are configured so that, for a given temperature value and power supply voltage value, the amount of charge supplied to the first output during each first time period is fixed.

[0024] According to an embodiment, the first circuit comprises a second circuit adapted to deliver two control signals to two switches of a switch mode converter of the pulse frequency modulation type, each first time period being determined based on at least one of the two control signals (preferably, based on both of the two control signals).

[0025] According to an embodiment: the first output is also intended to be connected to a first terminal of an inductive element; the regulator comprises a second output intended to be connected to a second terminal of the inductive element, a first switch connected between the first node and the second output, and a second switch connected between the second output and a second node configured to receive a reference potential; the first circuit is configured to set the first control signal to its first binary state (active state) for a third time period when the second binary signal is in its first binary state, and then, at the end of the third time period, to set the second control signal to its first binary state (active state) for a fourth time period; the first circuit is also configured to control the conduction state of the first switch when the first control signal is in its first binary state and to control the conduction state of the second switch when the second control signal is in its first binary state in a first operating mode, and to set the first signal to its first binary state as long as one of the second and third signals is in its first binary state in a second operating mode.

[0026] According to an embodiment, the third time period is fixed and determined by the power supply voltage, or is fixed and independent of the power supply voltage, and the fourth time period is fixed and determined by the power supply voltage, or is fixed and independent of the power supply voltage.

[0027] According to an embodiment, the first operating mode is of the pulse frequency modulation type.

[0028] According to an embodiment, when the second binary signal is in its first binary state, the first circuit is configured to generate a first voltage ramp, compare the first voltage ramp to a first threshold voltage, and set the first control signal to its first binary state from the start of the first voltage ramp until the first voltage ramp intersects the first threshold voltage; and generate a second voltage ramp when the first voltage ramp intersects the setpoint voltage, compare the second voltage ramp to a second threshold voltage, and set the second control signal to its first binary state from the start of the second voltage ramp until the second voltage ramp intersects the second threshold voltage.

[0029] One embodiment provides an apparatus comprising a voltage regulator as described above, and a load connected to the first output of the regulator.

[0030] One embodiment provides an apparatus comprising a voltage regulator as described above, a load connected to the first output of the regulator, and an inductive element connected between the first output and the second output of the regulator.

[0031] According to an embodiment, the apparatus comprises an integrated circuit chip comprising the regulator, the inductive element being arranged outside the chip.

[0032] According to an embodiment, the apparatus further comprises a capacitive element connected to the first output of the regulator. BRIEF DESCRIPTION OF DRAWINGS

[0033] The foregoing features and advantages, as well as others, will be described in detail in the remaining part of the present disclosure with reference to the drawings, in which:

[0034] Figure 1 An example of a linear type voltage regulator is shown;

[0035] Figure 2 An example of a voltage regulator of the switched mode power supply type operating with pulse frequency modulation is shown;

[0036] Figure 3 An embodiment of a voltage regulator is shown;

[0037] Figure 4 An alternative embodiment of the regulator of Figure 3 is shown;

[0038] Figure 5 The operating modes of the regulator of Figure 4 are illustrated in a timing diagram;

[0039] Figure 6 Another alternative embodiment of the regulator of Figure 3 is shown;

[0040] Figure 7 Operation modes of the regulator of Figure 6 are illustrated in timing diagrams; and

[0041] Figure 8 Another operation mode of the regulator of Figure 6 is illustrated in timing diagrams. DETAILED DESCRIPTION

[0042] In the various drawings, like features are designated by like reference numerals. In particular, structural and / or functional features common to the various embodiments can have the same reference numerals and can have the same structural, dimensional, and material properties.

[0043] For the sake of clarity, only the steps and elements useful for an understanding of the described embodiments are illustrated and described in detail.

[0044] Unless otherwise stated, when two elements are mentioned to be connected together, this means a direct connection without any intermediate element other than a conductor, whereas when two elements are mentioned to be coupled together, this means that the two elements can be connected or they can be coupled through one or more other elements.

[0045] In the following description, unless otherwise stated, when a term defining an absolute position such as the terms "edge", "behind", "top", "bottom", "left", "right", etc. or a term defining a relative position such as the terms "on", "under", "upper", "lower", etc. are mentioned, or a term defining a direction such as the terms "horizontal", "vertical", etc. are mentioned, this refers to the orientation of the drawing.

[0046] Unless otherwise stated, the expressions "about", "approximately", "substantially" and "on the order of" mean positive / negative ten percent, preferably positive / negative five percent.

[0047] In the rest of the description, for simplicity, when two nodes are at the same electrical potential, the two nodes have the same reference numerals and are described as if they correspond to the same node, it should be understood that in practice the two nodes can be different.

[0048] Figure 1 An example of a linear voltage regulator 1 is shown.

[0049] The regulator 1 comprises a MOS transistor T1, with N channel in this example, coupling a node 100 configured to receive a supply voltage VDD to an output 102 of the regulator 1. The source of the transistor T1 is connected to the output 102, the drain of the transistor T1 is connected to the node 100. The regulator 1 is configured to deliver on its output 102 a regulated voltage Vout, the regulated voltage Vout having a value determined by a setpoint voltage Vref, for example the voltage Vout is equal to the voltage Vref.

[0050] To this end, in this example where the transistor T1 has N channel, the regulator 1 comprises a comparator 104 configured to receive on its non-inverting input + the voltage Vref and on its inverting input the voltage Vout, and configured to deliver a signal err representative of the mutual comparison of these two voltages. It should be noted that in the example where the transistor T1 has P channel, the comparator 104 is preferably replaced with an error amplifier 104 configured to receive on its non-inverting input + the voltage Vref and on its inverting input the voltage Vout, and configured to deliver a signal err representative of the comparison of these two voltages.

[0051] The gate of the transistor T1 is controlled on the basis of the signal err, so that the voltage Vout is equal to the voltage Vref.

[0052] A load 106 Figure 1 is connected between the output 102 and a node 108 configured to receive a reference potential GND, for example a ground potential. The load 106 is controlled by the voltage Vout. A capacitive element C is connected to the output 102. For example, this capacitive element C is able to smooth variations of the voltage Vout.

[0053] For example, as shown in the example of Figure 1 , this capacitive element C is a capacitor connected in parallel with the load 106 between the nodes 102 and 108. As another example not illustrated, this capacitive element C corresponds to a capacitance of the load 106.

[0054] The use of an N channel transistor T1 makes it possible to suppress a voltage drop between the node 100 and the output 102, which would be caused by the use of a PMOS type transistor T1 whose source is connected to the node 100 and whose drain is connected to the output 102. The use of an N channel transistor T1 also allows a better PSRR than with a P channel transistor T1.

[0055] However, as Figure 1As illustrated in the middle, using a NMOS type transistor T1 implies that in the regulator 1 a charge pump CP is provided between the output of the error amplifier 104 and the gate of the transistor T1. This also implies that in the regulator 1 a start-up circuit SU is provided, the start-up circuit SU being configured to pre-charge the charge pump, i.e. it is configured to pre-charge the gate of the transistor T1 to a value that allows the regulator 1 to start-up. This pre-charge value of the transistor T1 gate is actually determined based on the static power consumption of the load 106 connected to the output 102. Now, as previously mentioned, the static power consumption of this load depends on the PVT parameters, whereby the configuration of the circuit SU also depends on the PVT parameters, which is not desirable.

[0056] Figure 2 An example of a switched mode power supply type voltage regulator 2 operating in pulse frequency modulation (PFM) is shown.

[0057] The switched mode power supply 2 comprises a high-side switch ITH (e.g. a PMOS transistor) connected between a node 200 configured to receive a supply voltage VDD and an output 202 of the regulator 2. The switched mode power supply 2 further comprises a low-side switch ITL (e.g. a NMOS transistor) connected between the output 202 and a node 204 configured to receive a reference potential GND, e.g. a ground potential.

[0058] A coil L is connected between the output 202 and an output 206 of the regulator 2, the coil L having a terminal connected to the output 202 and a terminal connected to the output 206.

[0059] The switched mode power supply 2 is configured to deliver on its output 206 a regulated voltage Vout to a load 208 (in the block “Load” in the middle) connected to the output 206 to be powered by the voltage Vout. For example, the load 208 is connected between the output 206 and the node 204 at the reference potential GND. A capacitive element C is connected to the output 206. For example, this capacitive element C is able to smooth variations of the voltage Vout. Figure 2

[0060] For example, as shown in the example of Fig. 1, the capacitive element C is a capacitor connected in parallel to the load 208 between the nodes 206 and 204. As another example not illustrated, the capacitive element C corresponds to a capacitance of the load 106. Figure 2

[0061] The regulator 2 is configured to deliver on its output 206 a voltage Vout regulated at a value determined by a set-point voltage Vref (e.g. equal to the value of the voltage Vref).

[0062] ​​To this end, in this example where the switch mode power supply 2 operates at a pulsed frequency modulation, the regulator 2 comprises a comparator 210 and a circuit 212 (in block "CTRL" in Fig. 2). Figure 2

[0063] The comparator 210 is configured to compare the voltage Vout to a voltage Vref. For example, the comparator 210 receives the voltage Vout at its inverting input - and the voltage Vref at its non-inverting input +, and delivers an output signal sigl at a first low binary state when the voltage Vout is lower than the voltage Vref, and at a second high binary state when the voltage Vout is greater than the voltage Vref. As an alternative example, the comparator 210 receives the voltage Vref at its inverting input - and the voltage Vout at its non-inverting input +, and delivers an output signal sigl at a first high binary state when the voltage Vout is lower than the voltage Vref, and at a second low binary state when the voltage Vout is greater than the voltage Vref.

[0064] The circuit 212 is configured to deliver two signals sigH and sigL for controlling respective switches ITH and ITL. More particularly, when the comparator 210 indicates that the voltage Vout is lower than the voltage Vref (the signal sigl being at its first binary state), the circuit 212 is configured to set the signal sigH to its first binary state for a time period Ton, and then to set the signal sigL to its first binary state for a time period Toff at the end of the time period Ton. Outside the time periods Ton and Toff, the circuit 212 is configured to have the signal sigH at its second binary state and to have the signal sigL at its second binary state. The circuit 212 is also configured to have the signal sigL at its second binary state during each time period Ton, and to have the signal sigH at its first binary state during each time period Toff.

[0065] The regulator 2 is configured to have the switch ITH turned on when the signal sigH is at its first binary state, and to have the switch ITL turned on when the signal sigL is at its first binary state. Thus, the switches ITH and ITL are turned on and off, respectively, during each time period Ton, turned off and on, respectively, during each time period Toff, and both off outside the time periods Ton and Toff.

[0066] For example, each time period Ton and Toff is fixed and determined by the power supply voltage, for example, so that the maximum current (also called peak current) in the coil L at the end of each time period Ton has the same value whatever the value of the voltage VDD. ​

[0067] As an alternative example, each of the time periods Ton and Toff is fixed and independent of the voltage VDD.

[0068] The drawback of the regulator 2 is that it requires a coil L, which makes it bulky. Moreover, the regulator 2 is a source of noise, for example induced by the voltage variation across the coil L occurring at least at the end of the time period Ton.

[0069] To overcome the drawbacks of known voltage regulators, there is provided a voltage regulator, wherein, when the regulated voltage Vout is lower than the setpoint voltage Vref, the regulator is configured to deliver a DC current I to the output of the regulator, at which the regulated voltage Vout is available, for a time period Tload, the time period Tload being fixed and independent of the supply voltage, or fixed and determined by the supply voltage (i.e. fixed for a given supply voltage value). A capacitive element is connected to the output of the regulator, at which the regulated voltage Vout is available, the capacitive element corresponding to the capacitance of the load connected to the output and / or to the capacitance of the capacitive element connected to the output.

[0070] This voltage regulator does not require a coil, does not require a start-up circuit dependent on PVT parameters, and does not require bulky capacitive elements (such as the capacitive elements of charge pumps).

[0071] Advantageously, to control the controllable current source delivering the DC current I only during each time period Tload, the voltage regulator can reuse known circuits to control the high-side and low-side switches of a switch-mode power supply operating with pulse frequency modulation. Indeed, the provided regulator has a similar operation as a switch-mode power supply operating with pulse frequency modulation, except that it does not require a coil L. Of course, the present description is not limited to the case where the control circuit of the current source reuses circuits to control the high-side and low-side switches of a switch-mode power supply of the PFM type. Indeed, the fixed time period Tload (dependent or not on the supply voltage) can be generated by a dedicated circuit (for example by a circuit configured to generate a pulse of duration Tload) that does not reuse circuits to control the high-side and low-side switches of a switch-mode power supply of the PFM type.

[0072] According to an embodiment, the value of the current I delivered during each time period Tload is fixed.

[0073] According to an alternative embodiment, the current I delivered during each time period Tload has a value proportional to the absolute value of the temperature, or in other words, is a proportional to the absolute value (PTAT) current. Therefore, in the same way as the leakage current of the load, its static power consumption increases as the temperature increases, the value of the current I increasing as the temperature. This can better regulate the voltage Vout.

[0074] According to an embodiment, the value of the time period Tload and of the current I are determined so that, for a given temperature value and for a given power supply voltage value, the regulator delivers the same amount of charge on its output, on which the regulated voltage Vout is available, during each time period Tload. In other words, the amount of charge delivered by the regulator on the output during each time period Tload determines the current I and the time period Tload.

[0075] The amount of charge delivered during each time period Tload determines the maximum current that the load can draw from the regulator, while regulating the output voltage of the regulator is maintained at its setpoint value. Conversely, the load connected to the regulator, in particular the power consumption of this load, determines the amount of charge that the regulator must deliver during each time period Tload to maintain the regulation of the output voltage at its setpoint value, then the time period Tload and the current I are chosen to obtain this amount of charge.

[0076] By way of example, when the regulator can operate in continuous injection and is effectively operating in continuous injection, i.e. when a new time period Tload starts immediately after the end of each time period Tload, the regulator is then at its maximum current regulation limit. In other words, the regulator operates in continuous injection when the current consumed by the load powered by the regulator is equal to the maximum regulated current that the regulator can deliver.

[0077] The voltage regulator provided herein is advantageously adapted to implementation in low-power applications. For example, the static power consumption of the voltage regulator provided herein is lower than 5% of the static power consumption of the load it powers. For example, when the size of the voltage regulator provided herein is designed to power a load having a static power consumption of the order of 3 μΑ, it has a static power consumption lower than 200 nA or even lower than 100 nA.

[0078] Figure 3 An example of an embodiment of such a voltage regulator is shown in the figure, which is designated by the reference 3.

[0079] The device 3 comprises an output 300 configured to deliver a regulated voltage Vout equal to a setpoint voltage Vref. A load 301 ( Figure 3The block "Load" in Fig. 1 is intended to be connected to the output 300 of the regulator 3 to be powered by the voltage Vout. In Figure 3 In the example of Fig. 1, the load 301 is shown as being connected to the output 300. For example, the load 301 is connected between the output 300 and a node 302 configured to receive a reference potential GND (e.g. ground potential).

[0080] The capacitive element C is intended to be connected to the output 300. As an example, the capacitive element C is a capacitor connected in parallel to the load 301 between the output 300 and the node 302. As another example, the capacitive element C corresponds to the capacitance of the load 302. As another example, the capacitive element corresponds to the capacitance of the load 301 and the capacitance of a capacitive element connected in parallel to the load 301.

[0081] The circuit 3 further comprises a current source 304. The current source 304 couples the output 300 to a node 306. For example, the current source 304 has a terminal coupled to (preferably connected to) the node 306, and a terminal coupled to (preferably connected to) the output 300.

[0082] The node 306 is configured to receive a supply voltage VDD of the regulator 3. The voltage VDD is referenced to the potential GND. The voltage VDD is for example positive.

[0083] The current source 304 is configured to deliver a DC current I only when the binary signal sig2 is in its first (active) binary state. Thus, when the signal sig2 is in its second (inactive) binary state, the current source 304 does not provide the current I, or in other words, provides zero current.

[0084] According to an embodiment, the current I has a fixed value independent of temperature. According to another embodiment, the current I has a value with a positive temperature coefficient (PTAT).

[0085] The regulator 3 comprises a comparator 308 configured to compare the voltage Vout available on the output 300 with a setpoint voltage Vref, similarly as the regulator 2 described in connection with Figure 2 The regulator 3 comprises a comparator 308 configured to compare the voltage Vout available on the output 300 with a setpoint voltage Vref, similarly as the regulator 2 described in connection with Figure 3

[0086] ​For example, the comparator 308 receives the voltage Vout on its inverting input and the voltage Vref on its non-inverting input + and delivers an output signal sigl in a first low binary state when the voltage Vout is less than the voltage Vref and in a second high binary state when the voltage Vout is greater than the voltage Vref. As an alternative example, the comparator 308 receives the voltage Vref on its inverting input - and the voltage Vout on its non-inverting input + and delivers an output signal sigl in a first high binary state when the voltage Vout is less than the voltage Vref and in a second low binary state when the voltage Vout is greater than the voltage Vref.

[0087] The regulator 3 further comprises a circuit 310 (in the block "CIRC" in Figure 3 When the comparator 308 indicates that the voltage Vout is lower than the voltage Vref, or in other words when the signal sigl is in its first binary state, the circuit 310 is configured to set the signal sig2 in its first binary state during a time period Tload.

[0088] As a result, when the voltage Vout becomes lower than the voltage Vref, the signal sigl switches to its first binary state, which causes the circuit 310 to set the signal sig2 in the first binary state during the time period Tload. Delivering the current I to the element C during the time period Tload tends to increase the voltage Vout, which approaches or even exceeds its setpoint value (i.e. the value of the voltage Vref).

[0089] According to an embodiment, the circuit 310 comprises a circuit similar or identical to the circuit CTRL previously described in connection with Figure 2 In other words, the circuit 310 comprises a circuit configured to deliver two control signals sigH and sigL to two switches ITH and ITL of a switched mode power supply operating with a pulsed frequency modulation, respectively, whereas such switches ITH and ITL and the coil L are not present in the regulator 3 of Figure 3 but more generally in the device illustrated in Figure 3 .

[0090] In such an embodiment, the time period Tload can then be determined by the time period Ton in the on state of the switch ITH and / or the time period Toff in the off state of the switch ITL.

[0091] For example, each time period Tload is then equal to (or the same as) the corresponding time period Ton. However, in this example, if the voltage Vout is still lower than the voltage Vref at the end of the time period Tload, the new time period Tload must be executed only after the next time period Toff ends, which may adversely affect the efficiency of regulator 3 in regulating the voltage Vout.

[0092] As an alternative example, each time period Tload is then equal to (or the same as) the corresponding time period Toff. However, in this example, after the voltage Vout becomes lower than the voltage Vref, the delivery of current I to the output 300 will only occur after the end of the time period Ton preceding this time period Toff, which reduces the response time of regulator 3.

[0093] As another alternative example, each time period Tload corresponds to the total duration of the corresponding time period Ton and the next time period Toff. Compared to the two examples above, this allows regulator 3 to deliver current I during the time period Tload that begins immediately after voltage Vout becomes lower than voltage Vref, and furthermore, if voltage Vout is lower than voltage Vref at the end of the current time period Tload, regulator 3 can deliver current I during a new time period Tload that begins immediately after the end of the current time period Tload. In other words, the regulator can operate under continuous current injection.

[0094] Other implementations of circuit 310 are within the capabilities of those skilled in the art, based on the instructions given in this specification (e.g., the functional instructions given in this application).

[0095] Specifically, according to an embodiment, circuit 310 does not include the previously combined Figure 2 The circuit described is similar to or equivalent to CTRL. In this case, circuit 310 is configured to deliver signal sig2, which is in its first binary state, during the time period Tload if voltage Vout is lower than voltage Vref (i.e., if signal sig1 is in its first binary state). As an example, circuit 310 may then include a pulse generator controlled by signal sig1 for a duration of Tload, for example, a pulse generator including a Schmitt trigger.

[0096] According to an embodiment, the regulator 3 forms part of an integrated circuit chip, and the capacitive element C is arranged outside the chip, the assembly of the regulator 3 and the element C forming an electronic device. In this case, the output 300 of the regulator 3 corresponds for example to an output terminal of the integrated circuit chip. Moreover, the load 301 can form part of the same integrated circuit chip as the regulator, or conversely be arranged outside the chip, outside the assembly of the regulator, the element C and the charge 301 forming the electronic device.

[0097] Figure 4 An embodiment of the regulator 3 is shown in combination with Figure 3 An example of an alternative embodiment of the regulator 3 is described.

[0098] In this alternative embodiment, the regulator 3 is configured to selectively operate according to a first operating mode or a second operating mode. In other words, the regulator 3 alternates between an operating phase in which it operates according to the first operating mode and an operating phase in which it operates according to the second operating mode.

[0099] In the second operating mode, the regulator 3 operates in the manner described with respect to Figure 3 In other words, in the second operating mode, when the voltage Vout is lower than the voltage Vref, the regulator 3 delivers the current I to its output I during the time period Tload.

[0100] In the first operating mode, the regulator 3 operates as a switched mode power supply operating with pulse frequency modulation.

[0101] Figure 4 The alternative embodiment of the regulator 3 exploits the fact that then parts (or circuits) of the regulator 3 can be used in each of the first and second operating modes. As an example, this enables a compact regulator 3 which is able to operate alternately according to the first operating mode and the second operating mode. As an alternative example, this enables this same regulator 3 to be placed in an application which operates according to the first mode only, or conversely in an application which operates according to the second mode only.

[0102] The regulator 3 described herein with respect to Figure 4 includes many elements in common with the regulator 3 described with respect to Figure 4 Here, only the differences between these two regulators are highlighted.

[0103] More particularly, compared with the regulator 3 described with respect to Figure 3 the regulator 3 described with respect to Figure 4 further comprises (similarly to the regulator 2 described with respect to Figure 2 ) a high-side switch ITH (for example a PMOS transistor) and a low-side switch IT (for example an NMOS transistor).

[0104] Switch ITH couples node 306, which receives voltage VDD, to output 400 of regulator 3, while switch ITL couples output 400 to node 302, which receives reference potential GND.

[0105] In addition, Figure 4 In, with Figure 2 Similar to regulator 2, the output 300 of regulator 3 is intended to be connected to one terminal of the coil or inductor element L, and the output 400 of regulator 3 is intended to be connected to another terminal of the inductor element L. Figure 4 In the example, element L is shown connected between outputs 300 and 400 of regulator 3. The presence of element L enables regulator 3 to operate according to a first operating mode.

[0106] exist Figure 4 In the embodiment, circuit 310 ( Figure 4 The box “CIRC” in the diagram is configured such that when comparator 308 indicates that voltage Vout (output 300) is lower than voltage Vref, signal sigH is set to its first (effective) binary state for duration Ton, and then at the end of time period Ton, signal sigL is set to its first (effective) binary state for duration Toff. For example, time periods Ton and Toff are configured to... Figure 2 It is determined in the same way as in the middle.

[0107] In the first operating mode (i.e., when the regulator 3 operates as a switch-mode power supply modulated by a pulse frequency), the regulator 3 (more specifically its circuit 310) is configured to: set the switch ITH to the on state when the signal sigH is in its first binary state; and set the switch ITL to the on state when the signal sigL is in its first binary state.

[0108] In the second operating mode (i.e., when regulator 3 is as about Figure 3 When operating as described, regulator 3 (more particularly its circuit 310) is configured to set signal sig2, which is used to control current source 304, to its first binary state only when signal sigH is in its first binary state, or in one variation, only when signal sigL is in its first binary state, or in another variation, only when one or the other of signals sigH and sigL is in its first binary state.

[0109] According to an embodiment, the binary signal M of the regulator 3 (e.g., a signal M delivered to the regulator 3 by another circuit (e.g., a microcontroller) determines the operating mode of the regulator 3. For example, a first binary state of signal M corresponds to a first operating mode, while a second binary state of signal M corresponds to a second operating mode.

[0110] According to an embodiment, the circuit 310 comprises, with respect to the Figure 2 circuit 212 described in Figure 4 the block "CTRL". In the same way as it delivers the signals sigH and sigL based on the Figure 2 signal sig1 in the circuit 212 described in Figure 4 , the circuit 212 delivers the signals sigH and sigL based on the signal sig1 in the circuit 212 described in Figure 2 . In this embodiment, based on the signals sigH and sigL, the circuit 310 is configured to control the switches ITH and ITL as described with respect to Figure 3 , to keep the signal sig2 in its second binary state when the regulator 3 operates according to the first operating mode, and to control the current source 304 as described with respect to , and to keep the switches ITH and ITL off when the regulator 3 operates according to the second operating mode.

[0111] For example, as shown in Figure 4 , the circuit 310 comprises two routing circuits 402 and 403, for example two demultiplexers 402 and 404. The circuits 402, 404 receive the signals M and sigH and the signals M and sigL, respectively.

[0112] When the signal M is in its first binary state (first operating mode control state), the circuits 402, 404 deliver the signals sigH, sigL, respectively, on their outputs 408, 410, respectively, which control the switches ITH, ITL, respectively. The output 408 of the circuit 402, the output 410 of the circuit 404 are coupled to (preferably connected to) the gates of the transistors ITH and ITL, respectively. When the signal M is in its second binary state (second operating mode), the outputs 408 and 410 cause the switches ITH and ITL to be off.

[0113] When the signal M is in its second binary state (second operating mode control state), the circuits 402, 404 deliver the signals sigH, sigL, respectively, on their outputs 412, 414, respectively. The outputs 412 and 414 are coupled to (preferably connected to) the inputs of a logic gate 416. The logic gate 416, as well as the circuits 402 and 404, are configured to deliver the signal sig2 based on the signals sigH and sigL, so that: when the signal M is in its second binary state, the signal sig2 is in its first binary state, and in this example, one or the other of the signals sigH and sigL is in its first binary state; when the signal M is in its second binary state and both signals sigH and sigL are in their second binary state simultaneously, the signal sig2 is in its second binary state; and when the signal M is in its first binary state, the signal sig2 is in its second binary state.

[0114] In the above example, when in the second operating mode, each duration Tload is equal to the total duration of the corresponding time period Ton and the time period Toff following this time period Ton, and the circuit 310 determines the signal sig2 based on the signals sigH and sigL.

[0115] In other examples, not illustrated, in the second operating mode, each duration Tload is equal to the duration of the corresponding time period Ton, and the circuit 310 determines the signal sig2 based on the signal sigH only. As an example, in this case, the circuit 310 can be the circuit illustrated in Fig. 4, wherein the gate 416 is omitted and the signal sig2 is available directly on the output 412 of the circuit 402. Figure 4

[0116] In yet other examples, not illustrated, in the second operating mode, each duration Tload is equal to the duration of the corresponding time period Toff, and the circuit 310 determines the signal sig2 based on the signal sigL only. As an example, in this case, the circuit 310 can be the circuit illustrated in Fig. 4, wherein the gate 416 is omitted and the signal sig2 is available directly on the output 414 of the circuit 404. Figure 4

[0117] As an example, the circuit 310 of the regulator 3 of Fig. 3 can correspond to the circuit 310 of the regulator 3 of Fig. 4, wherein the circuit 402 and 404 are omitted. Figure 3 Figure 4 As an example, the circuit 310 of the regulator 3 of Fig. 3 can correspond to the circuit 310 of the regulator 3 of Fig. 4, wherein the circuit 402 and 404 are omitted.

[0118] Although specific implementation modes of the circuit 310 have been described with respect to Figs. 3 to 4, other implementations of the circuit 410 can be provided by the person skilled in the art on the basis of the indications given in the present disclosure, for example on the basis of the functional indications given in the present application. Figure 4

[0119] According to an embodiment, the regulator 3 of Fig. 3 forms part of an integrated circuit chip, and the element L is arranged outside the chip. In this case, the outputs 300 and 400 of the regulator 3 correspond for example to two input / output terminals of the integrated circuit chip. Moreover, the load 301 can form part of the same integrated circuit chip as the regulator, or, conversely, be arranged outside the chip. Figure 4

[0120] The assembly of the regulator 3, the elements C and L, and the load 301 forms an electronic device.

[0121] Although the element C (C1, C2) and the element L (L1, L2) are illustrated in Figs. 3 to 4 as being connected in series, other configurations can be provided, for example in parallel. Figure 3 Figure 4 As an example, the element C (C1, C2) and the element L (L1, L2) can be connected in parallel. Figure 4 ​​​​​​) have been described above as not forming part of the regulator 3, but in embodiments, this or these elements can form part of the regulator 3.

[0122] Figure 5 An example of the operation of the regulator of Figure 4 is illustrated in a timing diagram. In this example, each time period Tload corresponds to the sum of a corresponding time period Ton and a time period Toff following this time period Ton, or in other words, the signal sig2 used to control the current source 304 is determined based on two signals sigH and sigL. In this example, the circuit 310 is implemented in the manner illustrated in Figure 4 . In this example, the first binary state of each of the signals sig1, sigH, sigL and sig2 corresponds to a high state of this signal, and the second binary state corresponds to a low state of this signal.

[0123] In this embodiment, when the signal sig1 indicates that the voltage Vout is lower than the voltage Vref, the circuit 310 is configured to generate a voltage ramp Vp, compare the ramp Vp to a first threshold voltage (in this example, the voltage Vref, however in other examples not illustrated, the first threshold voltage can be different from the voltage Vref), and set the signal sigH to its first state from the start of the ramp Vp until the first ramp intersects the first threshold voltage, generate a voltage ramp Vn, compare the ramp Vn to a second threshold voltage (in this example, the voltage Vref, however in other examples not illustrated, the second threshold voltage can be different from the voltage Vref, and for example different from the first threshold voltage), and set the signal sigL to its first state from the start of the ramp Vn until the ramp Vn intersects the second threshold voltage.

[0124] In this example, the ramp Vp is an upwardly sloping ramp, and the ramp Vn is a downwardly sloping ramp. However, in other examples, the ramp Vp can be downwardly sloping, and / or the ramp Vn can be upwardly sloping.

[0125] Thus, in Figure 5 , at time t1, the voltage Vout (not illustrated) becomes lower than the voltage Vref (not illustrated), whereby the signal sig1 switches to its first binary state (in this example, a high state). Then, the circuit 212 generates a ramp Vp starting at time t1, and at the same time switches the signal sigH to its first binary state (in this example, a high state). Thus, time t1 marks the start of the corresponding time period Ton.

[0126] In Figure 4In the meantime, the signal M (not shown) is in its second binary state, whereby the regulator 3 operates according to the second mode. Thus, the signal sigH switches to its first binary state at time tl, causing the signal sig2 to switch to its first binary state (high state in this example) at time tl.

[0127] From time tl, the ramp Vp increases to cross the first threshold voltage (voltage Vref in this example) at time t2, which is after time tl. Thus, at time tl, the circuit 212 switches the signal sigH to its second binary state (low state in this example). Moreover, the circuit 212 then generates the ramp Vn, which starts at time t2, and simultaneously switches the signal sigL to its first binary state (high state in this example).

[0128] Thus, time t2 marks the end of the time period Ton, which has started at time tl, and the beginning of the next time period Toff.

[0129] From time t2, the ramp Vn decreases to cross the second threshold voltage (voltage Vref in this example) at time t3, which is after time t2. Thus, at time t3, the circuit 212 switches the signal sigL to its second binary state (low state in this example).

[0130] Thus, time t3 marks the end of the time period Toff, which started at time t2.

[0131] Between times tl and t3, one or the other of the signals sigL and sigH is in its first binary state, the two signals sigL and sigH being in their second binary state before time tl and after time t3. Thus, in this example, the signal sig2 switches to its first binary state at time tl and remains in its first binary state from time tl to time t3, the signal sig2 switching to its second binary state at time t3. In other words, the time period Tload starts at time tl and ends at time t3, and is equal to the sum of the time period Ton (between times tl and t2) and the time period Toff (between times t2 and t3). Along the time period Tload, the current source 304 delivers the current I to the output 300 of the regulator.

[0132] In the example of Fig. 2, the signal sig2 is in its first binary state at time tl, and the signal sigL is in its second binary state at time tl. Thus, the signal sigH is in its second binary state at time tl, and the signal sig1 is in its first binary state at time tl. Figure 4 In the example of Fig. 2, the signal sig2 is in its first binary state at time tl, and the signal sigL is in its second binary state at time tl. Thus, the signal sigH is in its second binary state at time tl, and the signal sig1 is in its first binary state at time tl.

[0133] In another example not shown, the operations described with respect to times t1, t2, and t3 are repeated starting from time t3 because the voltage Vout is still lower than the voltage Vref at time t3, or in other words, because the signal sig1 is still in its first binary state at time t3 (voltage Vout is lower than voltage Vref).

[0134] According to the embodiment, the slope of each of the ramps Vp and Vn is fixed throughout the operation of the regulator 3 (i.e., permanently set and unchanging), and is in particular independent of the voltage VDD. In this case, Ton, Toff, and Tload are fixed for each time period and are independent of the voltage VDD.

[0135] According to another embodiment, the slope of the ramp Vp is proportional to 1 / (VDD-Vout), such that the time period Ton depends on the voltage VDD, and when the regulator 3 operates according to the first operating mode, the peak current in the inductor L is constant and independent of the voltage VDD.

[0136] Although it has been discussed Figure 5 An example of the operation of regulator 3 corresponding to the second operating mode of regulator 3 is described, but based on... Figure 2 and Figure 5 From the description provided, those skilled in the art will be able to deduce the operation of the regulator 3 in the first operating mode. For example, referring again... Figure 5 In the first operating mode, switch ITH is set to the ON state for a duration of Ton, after which switch ITL is set to the ON state for a duration of Toff. Furthermore, as long as regulator 3 operates according to the first operating mode, signal sig2 remains in its second binary state.

[0137] Furthermore, although it has been discussed Figure 5 An example of the operation of regulator 3 is described, in which each time period Tload corresponds to the sum (or consecutively) of time period Ton and the corresponding time period Toff, but in other examples, each time period Tload corresponds to only one time period Toff, or only one time period Ton.

[0138] Furthermore, those skilled in the art will be able to Figure 5 The example (where each of the signals sig1, sigH, sigL, and sig2 is high in its first binary state) adapts to the example where one or more of these signals sig1, sigH, sigL, and sig2 are low in their first binary state.

[0139] The simulation has shown that when Figure 3 Regulator 3 and Figure 4The regulators 3, when they operate according to the second mode, are able to obtain, for example, very low static power consumption values between two consecutive time periods Tload. For example, the static power consumption measured in simulations is lower than 5% of the average static power consumption of the load 301. For example, for a load 301 with low power consumption, i.e. with an average static power consumption lower than or equal to 3 μΑ, the measured static power consumption of the regulator 3 is lower than 200 nA, even lower than 100 nA. By way of example, according to the second mode, the regulator 3 is able to obtain a static power consumption lower than 100 nA for a load 301 with an average static power consumption lower than 3 μΑ. Figure 4 The regulator 3 of the alternative embodiment is implemented in an electronic system comprising noise-sensitive circuits or applications. In this case, the first operating mode enables the high efficiency of the regulator 3 operating in PFM type switched mode power supply when the noise-sensitive circuit(s) or application(s) are inactive, and, conversely, the second operating mode enables the low noise of the regulator 3 operating when injecting the current I on the load 301 when the noise-sensitive circuit(s) or application(s) are active.

[0140] According to an embodiment, in the regulator 3 of Figure 3 and in the regulator 3 of Figure 4 , it is desirable, for example at the start-up of this regulator, to regulate the inrush current drawn by the load 301 from the regulator output 300.

[0141] According to another embodiment, whether combined or not with the above-mentioned embodiments, in the regulator 3 of Figure 3 operating according to the second operating mode and in the regulator 3 of Figure 4 , it is desirable to measure the average current Im drawn by the load 301 connected to the output 300, i.e. to obtain a signal with a value indicative of the value of this average current Im.

[0142] Figure 6 Another alternative embodiment of the regulator 3 of Figure 3 is shown.

[0143] Figure 6 The regulator 3 of Figure 3 comprises many elements in common with the regulator 3 of Figure 3 and here only the differences between these two regulators are highlighted. More particularly, compared to the regulator 3 of Figure 6 , the regulator 3 of further comprises an inrush current regulation circuit IR-REG and a circuit MES for measuring the average current Im.

[0144] Figure 6The circuit IR-REG, shown in the form of a block, is configured to force the binary signal sigl into its second binary state during a fixed and periodic time period Tlimit when the regulator is in an operating phase WU. The phase WU is a surge current regulation phase. For example, the circuit IR-REG is configured to transmit the signal sigl from the output of the comparator 308 to the circuit 310 by forcing the signal sigl into its second binary state during the periodic time period Tlimit when the regulator is in the operating phase WU.

[0145] As an example, the regulator is in the operating phase WU when the average current I drawn by the load 301 connected to the output 300 of the regulator 3 is too high without regulation of the surge current. In other words, the phase WU corresponds to an operating phase in which it is desired to limit the value of the current supplied by the regulator to the load. As an example, this operating phase WU corresponds to a start-up (or start) phase of the regulator 3, for example when the regulator 3 switches from an off state or from a standby state to an on state, in which the load 301 is to be powered with the voltage Vout regulated at the setpoint value Vref. For example, at the start of each operating phase WU, the voltage Vout is lower than the voltage Vout and is for example zero.

[0146] As an example, the circuit IR-REG receives an indication of the start and end of the operating phase WU.

[0147] As an example, the binary signal IR is in its first binary state for the entire duration of the phase WU, otherwise it has its second binary state. In other words, the circuit IR-REG is configured to periodically force the signal sigl into its second binary state during a fixed time period Tlimit when the signal IR is in its first binary state. For example, the circuit IR-REG receives the signal IR on the input 600. For example, the circuit IR-REG is configured to transmit the signal sigl from the output of the comparator 308 to the circuit 310 by forcing the signal sigl into its second binary state during the periodic time period Tlimit when the binary signal IR is in its first binary state.

[0148] As an example, the signal IR is delivered by a circuit not shown in the middle, which can be external to the regulator 3. Figure 6

[0149] ​According to an embodiment, each operating phase WU ends when the voltage Vout reaches its setpoint value Vref, and the end of a phase WU for example causes the signal IR to switch to its second binary state. As a variant, each operating phase WU has a fixed duration that is identical for all operating phases WU. Preferably however, each phase WU ends when the voltage Vout reaches its setpoint value Vref, as this enables to take into account variations of certain values with respect to respective typical values (for example, variations of the value of the capacitance C).

[0150] According to an embodiment, the circuit IR-REG receives the output signal sigl of the comparator 308 and transmits this signal sigl to the circuit 310: it is not modified when the regulator is not in a phase WU (for example, when the signal IR is in its second binary state); and it is forced into the second binary state during the periodic time period Tlimit during which the regulator is in a phase WU (for example, when the signal IR is in its first binary state).

[0151] As an example, although Figure 6 not detailed in the foregoing, the circuit IR-REG comprises: a switch that receives the output signal sigl of the comparator 308, and a signal (for example, a voltage) that corresponds to the second binary state of the signal sigl, and delivers the signal sigl to the circuit 310. The circuit IR-REG further comprises a circuit configured to deliver a signal for controlling the switch. This switch control circuit receives an indication of the start and end of a phase WU. For example, this control circuit receives the signal IR. When the regulator is not in a phase WU (for example, when the signal IR is in its second binary state), the switch transmits on its output, to the circuit 310, the signal sigl that it receives from the comparator 308 without modifying it. However, when the regulator is in a phase WU (for example, when the signal IR is in its first binary state), the switch control signal is configured so that the switch output receives, during each periodic duration Tlimit, the signal that corresponds to the second binary state of the signal sigl, and outside these time periods Tlimit, the output signal sigl of the comparator 308.

[0152] As another example, although Figure 6The circuit IR-REG comprises a switch configured to pull the signal sigl to its second binary state when the switch is in a conducting state, and configured to avoid modifying the state of the signal sigl when the switch is in an off state. For example, when the second binary state of the signal sigl corresponds to a zero voltage, the switch is connected between the output of the comparator 308 and the node 302. As an alternative example, when the second binary state of the signal sigl corresponds to the voltage VDD, the switch is connected between the output of the comparator 308 and the node 306. Moreover, the circuit IR-REG comprises a switch controlled for controlling the switch, the controlled switch being configured to control the off state of the switch when the regulator is not in the phase WU (for example, when the signal IR is in its second binary state), and to control the conducting state of the switch during each periodic time period Tlimit while the regulator is in the phase WU (for example, when the signal IR is in its first binary state).

[0153] As an example, the signal for controlling the switch of the first example described above or the switch of the second example described above is a binary signal, which is kept in its first binary state when the signal IR is in its second binary state, and which is periodically set to its second binary state during the time period Tlimit when the signal IR is in its first binary state. Thus, when the signal IR is in its first binary state, at each period of the control signal, the control signal is in its second binary state during the time period Tlimit and in its first binary state for the rest of the period. In this case, the second binary state of the control signal forces the second binary state of the signal sigl delivered to the circuit 310.

[0154] As an example, when the regulator is in the phase WU (for example, when the signal IR is in its first binary state), the circuit IR-REG periodically forces the signal sigl to enter its second binary state during the time period Tlimit for a period T greater than the time period Tload.

[0155] As an example, at each phase WU, each beginning of the period T is synchronized with the beginning of the time period Tload. Thus, when the regulator is in the phase WU, the circuit transmits the signal sigl it receives from the comparator 308 without modifying it, which triggers the beginning of the time period Tload. The beginning of this time period Tload causes the beginning of the period T, during which the signal sigl delivered by the circuit IR-REG to the circuit 310 will be forced to enter its second binary state during the time period Tlimit. In this case, the end of the time period Tlimit also marks the end of this time period T. In this case, the time period T can have a duration equal to the duration Tlimit.

[0156] Of course, the implementation of the IR-REG circuit is not limited to the two implementation examples mentioned above, and those skilled in the art will be able to provide many other implementation examples of the IR-REG circuit based on the functional description of the IR-REG circuit described above.

[0157] Preferably, when the regulator 3 includes the circuit IR-REG as described above, the current source 304 is configured to supply a current I with a constant temperature value. This allows surge current management during each stage WU to be independent of temperature. However, it is still possible to provide a current I with a positive temperature coefficient (PTAT) or a negative temperature coefficient (complementary to absolute temperature, CTAT) value, but the accuracy of surge current management will be reduced.

[0158] Preferably, when the regulator 3 includes a circuit such as IR-REG as described above, the duration Tload is fixed and independent of the voltage VDD. This makes surge current management during each phase WU independent of the voltage VDD. However, it is still possible to have a fixed duration Tload determined by the voltage VDD value, but the accuracy of surge current management will be reduced.

[0159] Figure 7 An example of the operation of regulator 3 is illustrated using a timing diagram. More specifically, Figure 7 The diagram illustrates the voltage Vout, the signal sig1 received by circuit 310 (i.e., the signal sig1 available at the output of circuit IR-REG), the signal sig2 used to control current source 304, and the change of signal IR over time.

[0160] In this example, the first binary state of signal sig1 is the high state of signal sig1, the first binary state of signal sig2 is the high state of signal sig2, and the first binary state of signal IR is the high state.

[0161] At time t0, as an example, regulator 3 is off or in standby mode. Voltage Vout is, for example, below the setpoint Vref and decreases. Therefore, signals sig1 and sig2 are in their second binary state ( Figure 7 (Low state in the example). As an example, signal IR is in its second binary state ( Figure 7 (Low state in the example).

[0162] At the next time t1, regulator 3 is activated and the wake-up phase WU begins. Signal IR thus switches to its first binary state ( Figure 7 (High state in the example). Time t1 also marks the start of the period T that the time period Tlimit repeats.

[0163] At time tl, the voltage Vout is lower than the voltage Vref, and the output of the comparator 308 is in its second binary state. In this example, for each period T, the circuit IR-REG is configured to transmit the signal sigl that it receives from the comparator 308 to the circuit 310, without modifying it at the beginning of the period T, then to force this signal sigl into its second binary at the end of a period Tlimit that ends with the period T. Thus, from time tl, the signal sigl received by the circuit 310 is in its first binary state (high state in the example). Figure 7 The first binary state of the signal sigl causes the circuit 310 to set the signal sig2 to the first binary state (high state in the example) during a period Tload that ends at time t2. Figure 7

[0164] During this period Tload, the current source 304 supplies a non-zero current I to the load 301, and the voltage Vout increases.

[0165] At time t2, which ends the period Tload, the voltage Vout is still lower than the voltage Vref, and the output of the comparator 308 is still in its first binary state. However, for the period T that starts at time tl, the period Tlimit starts at time t3, between times tl and t2. Thus, from time t3 until the end of the period Tlimit at time t4, which is after time t2, the circuit IR-REG forces the signal sigl received by the circuit 310 into its second binary state (low state in the example). As a result, between times t3 and t4, the circuit 310 does not switch the signal sig2 to its second binary state during the period Tload, although the voltage Vout is lower than the voltage Vref. The current source 304 does not supply the current I to the load 301, and the voltage Vout decreases. Figure 7

[0166] Time t4 marks the end of the current period T, and thus, in this example, the end of the corresponding period Tlimit and the beginning of a new period T. At time t4, the voltage Vout is lower than the voltage Vref, and the output of the comparator 308 is thus in its first binary state. In this example, at the beginning of this new period T, the circuit IR-REG transmits the signal sigl that it receives from the comparator 308 to the circuit 310, whereby, from time t4, the signal sigl received by the circuit 310 is in its first binary state (high state in the example). Figure 7

[0167] Then, as Figure 7 ​​​As illustrated, during the period T starting from time t4, the operations related to the successive times t1, t2, t3 and t4 within the period T starting at time t1 are repeated for the successive times t4, t6, t5 and t7, then, in the period T starting from time t7, the operations related to this successive times t1, t2, t3 and t4 are again repeated for the successive times t7, t9, t8 and t10.

[0168] Similarly to what described above, a new period T starts at time t10 while the voltage Vout is still lower than the voltage Vref, whereby the output of the comparator 308 is in its first binary state, and therefore the circuit IR-REG transmits to the circuit 310 the signal sig1 which is in its first binary state. Then, the circuit 310 switches the signal sig2 to its first binary state (high state in the example) and the current source 304 supplies the current I to the load 301, whereby the voltage Vout increases. Figure 7

[0169] At the next time t11, during the period Tload the voltage Vout becomes higher than the voltage Vref, which in the example marks the end of the phase WU. The end of the starting phase WU corresponds to the signal IR switching to its second binary state (low state in the example). Therefore, although the period T has started at time t11 and the period Tlimit corresponding to this period T has started at time t12 between times t10 and t11, this period T and this period Tlimit end at time t11 in the expected way. Figure 3

[0170] From time t11, the regulator 3 operates as described with respect to Figure 7 For example, at the next time t13 the voltage Vout becomes lower than the voltage Vref, which causes the output of the comparator 308 to switch to its first binary state. Since the signal IR is in its second binary state, the output of the comparator 308 is transmitted by the circuit IR-REG to the circuit 310 without modification, and the circuit 310 therefore receives the signal sig1 which is in its first binary state (high state in the example). This causes the start of the period Tload, in which the signal sig2 is in its first binary state (high state in the example), the current source 304 delivers the current I, and the voltage Vout increases. Figure 7 Figure 7

[0171] ​​​​During this period Tload, the voltage Vout becomes again higher than the voltage Vref at a time t14 after the time t13, which causes the output of the comparator 308 to switch to its second binary state. Since the signal IR is in its second binary state, the output of the comparator 308 is transmitted, as modified by the circuit IR-REG, to the circuit 310, and the signal sigl received by the circuit 310 switches to its second binary state at the time t14 (example of low state). Figure 6

[0172] The person skilled in the art will be able to adapt the above operational example to the case where the phase WU has a fixed duration and does not end when the voltage Vout becomes greater than the voltage Vref; and / or where the period Tlimit starts at each cycle T for which it is repeated; and / or where each cycle T is synchronized with the start of the corresponding period Tload.

[0173] Returning to Figure 8 In this variant, the regulator 3 also comprises a circuit MES for measuring the average current Im as indicated previously.

[0174] The circuit MES is configured to deliver, at each end of a measurement cycle Tmes, a number NB of periods Tload starting during this cycle Tmes. Preferably, the measurement cycle Tmes is repeated periodically. For example, at each end of the cycle Tmes, a new cycle Tmes starts.

[0175] Since, at least for a given voltage VDD and a given temperature, the amount of charge injected onto the output 300 of the regulator 3 during each period Tload is fixed, the number of periods Tload of each measurement cycle Tmes represents the average current Im supplied to the output 300 during this cycle Tmes.

[0176] The circuit MES thus receives the signal sig2. Indeed, each switch of the signal sig2 to its first binary state corresponds to the start of the corresponding period Tload. In addition, this circuit delivers the number NB, for example in the form of a multi-bit digital signal. As an example, the signal NB corresponds to the output signal COUNT of a counter of the circuit MES, which is reset at each start of the cycle Tmes and incremented at each start of the period Tload. As an example, the circuit MES can comprise a register configured to receive the counter output COUNT and to deliver the signal NB, which is updated based on the output COUNT of the counter at each end of the cycle Tmes.

[0177] ​Preferably, when the regulator 3 comprises the circuit MES as described above, the current source 304 is configured to supply a current I having a temperature constant value. This enables a more accurate average current value to be derived, calculated or determined based on the number of time periods Tload per measurement period Tmes. However, it is still possible to provide a current I having a value with a positive temperature coefficient (PTAT) or a value with a negative temperature coefficient (CTAT), but the error of the average current value derived, calculated or determined based on the number of time periods Tload per measurement period Tmes will depend on the temperature, unless a correction of the average current value is implemented as a function of the temperature.

[0178] Preferably, when the regulator 3 comprises the circuit IR-REG as described above, preferably the time period Tload is fixed and independent of the voltage VDD. This enables a more accurate value of the average current to be derived, calculated or determined based on the number of periods Tload per measurement period Tmes. However, it is still possible to have a fixed duration Tload determined by the value of the voltage VDD, but the error of the average current value derived, calculated or determined based on the number of time periods Tload per measurement period Tmes will depend on the temperature, unless a correction of the average current value is implemented as a function of the voltage VDD.

[0179] As an example, the circuit receives a periodic signal clk with a period Tmes. The time period Tmes is longer than the time period Tload.

[0180] Figure 8 An example of operation of the circuit MES is illustrated in a timing diagram. In this example, the circuit MES comprises a counter and a flip-flop as described above as an example.

[0181] More particularly, Figure 8 The variation of the signal clk of the period Tmes, the signal sig2, the output Count of the counter, and the output signal NB of the register are illustrated as a function of time t.

[0182] At time tO, the signal clk switches to a state (e.g. high state) which marks the beginning of the period Tmes. At time tO, the signal NB is updated with the value of the signal COUNT at time tO (e.g. Figure 8 The output COUNT is reset to 0.

[0183] During the period Tmes starting at time tl, the time periods Tload start at respective consecutive times t2, t3, t4, t5, t6 and t7. Accordingly, the output COUNT is incremented by one unit at each of times t2, t3, t4, t5, t6 and t7.

[0184] Between times t4 and t5, the signal clk switches to the other state (e.g. low state) and then, at time t8, after time t7, the signal clk switches back to its high state. This switching marks the end of the current period Tmes and the beginning of a new period Tmes. Thus, at time t8, the register output NB is updated with the output value COUNT of the register (i.e. Figure 6 The register output COUNT is reset to 0.

[0185] During the period Tmes starting at time t8, the time periods Tload start at respective consecutive times t9, t10 and t11. Thus, the output COUNT is incremented by one unit at each of times t9, t8 and t11.

[0186] Again with reference to Figure 6 , although Figure 3 The regulator 3 of the variant example of

[0187] Moreover, although the operation of the circuit MES and IR-REG in a regulator 3 of the type described in Figure 4 has been illustrated, the person skilled in the art will be able to provide other examples of implementation of the circuit MES and / or of the circuit IR-REG in a regulator 3 of the type described in Figure 4 .

[0188] Moreover, although examples of implementation of the circuits MES and IR-REG have been described, the person skilled in the art will be able to provide other examples of implementation of these circuits on the basis of the above functional description of these circuits. In particular, although the circuit MES has been described which counts the number of time periods Tload per measurement period Tmes on the basis of the switching of the signal sig2, in the case of a regulator of the type ​ , the circuit MES can count the number of time periods Tload per period Tmes on the basis of the switching of the signal sigH or of the signal sigL, which can be advantageous when successive injections are possible.

[0189] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these different embodiments and variants can be combined and that other variants will occur to the person skilled in the art.

[0190] Finally, actual implementations of the described embodiments and variants are within the capabilities of a person skilled in the art, based on the functional indications given above. In particular, as regards the implementation of the circuit 310, the latter is not limited to the implementation comprising the circuit 212, and a person skilled in the art is able to provide other implementations of this circuit 310 based on the functional indications given above. For example, the time periods Ton and Toff can be generated in a manner other than based on respective ramps Vp and Vn. More generally, the present disclosure is not limited to the case of a circuit 310 implemented based on a circuit 212 configured to control high-side and low-side switches in a switch-mode power supply operating in PFM.

Claims

1. A voltage regulator comprising: a first output, said first output intended to be connected to a capacitive element; a current source coupled between said first output and a first node, said first node configured to receive a supply voltage, said current source configured to deliver a first DC current to said first output only in response to a validation of a first binary signal; a comparator configured to deliver a second binary signal in a validated state when a first voltage on said first output is lower than a setpoint voltage; and a first circuit configured to validate said first binary signal for a first fixed time period when said second binary signal is in said validated state, wherein said regulator further comprises a surge current regulation circuit configured to, in a surge current regulation phase, periodically force said second binary signal into a non-validated state for a second fixed time period.

2. The voltage regulator of claim 1, wherein said first fixed time period is fixed and independent of said supply voltage.

3. The voltage regulator of claim 1, wherein said first fixed time period is determined by said supply voltage.

4. The voltage regulator of claim 1, wherein said DC current has a fixed value independent of temperature.

5. The voltage regulator of claim 1, wherein said DC current has a value proportional to the absolute value of temperature.

6. The voltage regulator of claim 1, wherein said first fixed time period and said current source are configured such that the amount of charge supplied to said first output during each first fixed time period is set in dependence of a given temperature value and a supply voltage value.

7. The voltage regulator of claim 1, wherein said regulator comprises a measurement circuit configured to, at the end of each measurement period, supply a number of first fixed time periods started during said measurement period.

8. The voltage regulator of claim 1, wherein said first circuit comprises a second circuit configured to deliver a first control signal and a second control signal to a first switch and a second switch, respectively, of a switch mode converter of the pulse frequency modulation type, each first fixed time period being determined based on at least one of said first control signal and said second control signal.

9. The voltage regulator of claim 8, wherein each first fixed time period is determined based on both said first control signal and said second control signal.

10. The voltage regulator of claim 1: wherein said first output is further intended to be connected to a first terminal of an inductive element; further comprising: a second output, said second output intended to be connected to a second terminal of said inductive element; a first switch connected between said first node and said second output; and a second switch connected between said second output and a second node, said second node configured to receive a reference potential; wherein the first circuit is configured to assert the first control signal for a third time period when the second binary signal is in an asserted state, and then assert the second control signal for a fourth time period at the end of the third time period; wherein the first circuit is further configured to, in a first operating mode, control a conduction state of the first switch when the first control signal is in the asserted state and control a conduction state of the second switch when the second control signal is in the asserted state, and in a second operating mode, set the first binary signal to the asserted state in response to an assertion of the first binary signal or the second control signal being in the asserted state.

11. The voltage regulator of claim 10, wherein the third time period is fixed and determined by the supply voltage.

12. The voltage regulator of claim 10, wherein the third time period is fixed and independent of the supply voltage.

13. The voltage regulator of claim 10, wherein the fourth time period is fixed and determined by the supply voltage.

14. The voltage regulator of claim 10, wherein the fourth time period is fixed and independent of the supply voltage.

15. The voltage regulator of claim 10, wherein the first operating mode is of a pulse frequency modulation type.

16. The voltage regulator of claim 10, wherein when the second binary signal is in the asserted state, the first circuit is configured to: generate a first voltage ramp, compare the first voltage ramp to a first threshold voltage, and assert the first control signal for a time period from a start of the first voltage ramp until the first voltage ramp intersects the first threshold voltage; and generate a second voltage ramp when the first voltage ramp intersects the first threshold voltage, compare the second voltage ramp to a second threshold voltage, and set the second control signal to the asserted state for a time period from a start of the second voltage ramp until the second voltage ramp intersects the second threshold voltage.

17. A voltage regulator comprising: a first output intended to be connected to a capacitive element; a current source coupled between the first output and a first node configured to receive a supply voltage, the current source configured to deliver a first DC current to the first output only in response to an assertion of a first binary signal; a comparator configured to deliver a second binary signal in an asserted state when a first voltage on the first output is lower than a setpoint voltage; and a first circuit configured to assert the first binary signal for a first fixed time period when the second binary signal is in the asserted state, wherein the regulator comprises a measurement circuit configured to, at the end of each measurement period, supply a number of first fixed time periods started during the measurement period.

18. The voltage regulator of claim 17, wherein the first fixed time period is fixed and independent of the supply voltage.

19. The voltage regulator of claim 17, wherein the first fixed time period is determined by the supply voltage.

20. The voltage regulator of claim 17, wherein the DC current has a fixed value independent of temperature.

21. The voltage regulator of claim 17, wherein the DC current has a value proportional to the absolute value of temperature.

22. The voltage regulator of claim 17, wherein the first fixed time period and the current source are configured such that the amount of charge supplied to the first output during each first fixed time period is set dependent on a given temperature value and a supply voltage value.

23. The voltage regulator of claim 17, wherein the first circuit comprises a second circuit configured to deliver a first control signal and a second control signal to a first switch and a second switch, respectively, of a pulse frequency modulation type of switch mode converter, each first fixed time period being determined based on at least one of the first control signal and the second control signal.

24. The voltage regulator of claim 23, wherein each first fixed time period is determined based on both the first control signal and the second control signal.

25. The voltage regulator of claim 17: wherein the first output is further intended to be connected to a first terminal of an inductive element; further comprising: a second output intended to be connected to a second terminal of the inductive element; a first switch connected between the first node and the second output; and a second switch connected between the second output and a second node configured to receive a reference potential; wherein the first circuit is configured to assert a first control signal for a third time period when the first binary signal is in an asserted state, and then to assert a second control signal for a fourth time period at the end of the third time period; wherein the first circuit is further configured to control a conduction state of the first switch when the first control signal is in the asserted state and to control a conduction state of the second switch when the second control signal is in the asserted state in a first operating mode, and to set the first binary signal to the asserted state in response to an assertion of the first binary signal or the second control signal being in the asserted state in a second operating mode.

26. The voltage regulator of claim 25, wherein the third time period is fixed and determined by the supply voltage.

27. The voltage regulator of claim 25, wherein the third time period is fixed and independent of the supply voltage.

28. The voltage regulator of claim 25, wherein the fourth time period is fixed and determined by the supply voltage.

29. The voltage regulator of claim 25, wherein the fourth time period is fixed and independent of the supply voltage.

30. The voltage regulator of claim 25, wherein the first mode of operation is pulse frequency modulation type.

31. The voltage regulator of claim 25, wherein when the second binary signal is in the asserted state, the first circuit is configured to: generate a first voltage ramp, compare the first voltage ramp to a first threshold voltage, and assert the first control signal for a time period from the start of the first voltage ramp until the first voltage ramp intersects the first threshold voltage; and generate a second voltage ramp when the first voltage ramp intersects the first threshold voltage, compare the second voltage ramp to a second threshold voltage, and set the second control signal to the asserted state for a time period from the start of the second voltage ramp until the second voltage ramp intersects the second threshold voltage.

32. A voltage regulator comprising: a first output intended to be connected to a capacitive element; a current source coupled between the first output and a first node configured to receive a supply voltage, the current source configured to deliver a first DC current to the first output only in response to assertion of a first binary signal; a comparator configured to deliver a second binary signal in an asserted state when a first voltage on the first output is lower than a setpoint voltage; and a first circuit configured to assert the first binary signal for a first fixed time period when the second binary signal is in the asserted state, wherein the first circuit comprises a second circuit configured to deliver a first control signal and a second control signal to a first switch and a second switch, respectively, of a pulse frequency modulation type switched mode converter, each first fixed time period being determined based on at least one of the first control signal and the second control signal.

33. The voltage regulator of claim 32, wherein each first fixed time period is determined based on both the first control signal and the second control signal.

34. The voltage regulator of claim 32, wherein the first fixed time period is fixed and independent of the supply voltage.

35. The voltage regulator of claim 32, wherein the first fixed time period is determined by the supply voltage.

36. The voltage regulator of claim 32, wherein the DC current has a fixed value independent of temperature.

37. The voltage regulator of claim 32, wherein the DC current has a value proportional to an absolute value of temperature.

38. The voltage regulator of claim 32, wherein the first fixed time period and the current source are configured such that an amount of charge supplied to the first output during each first fixed time period is set dependent on a given temperature value and a supply voltage value.

39. The voltage regulator of claim 32: wherein the first output is further intended to be connected to a first terminal of an inductive element; further comprising: a second output intended to be connected to a second terminal of the inductive element; a first switch connected between the first node and the second output; and a second switch connected between the second output and a second node configured to receive a reference potential; wherein the first circuit is configured to assert a first control signal for a third time period when the second binary signal is in an asserted state, and then to assert a second control signal for a fourth time period at the end of the third time period; wherein the first circuit is further configured to, in a first operating mode, control a conduction state of the first switch when the first control signal is in the asserted state and control a conduction state of the second switch when the second control signal is in the asserted state, and in a second operating mode, set the first binary signal to the asserted state in response to assertion of the first binary signal or the second control signal being in the asserted state.

40. The voltage regulator of claim 39, wherein the third time period is fixed and determined by the supply voltage.

41. The voltage regulator of claim 39, wherein the third time period is fixed and independent of the supply voltage.

42. The voltage regulator of claim 39, wherein the fourth time period is fixed and determined by the supply voltage.

43. The voltage regulator of claim 39, wherein the fourth time period is fixed and independent of the supply voltage.

44. The voltage regulator of claim 39, wherein the first operating mode is of a pulse frequency modulation type.

45. The voltage regulator of claim 39, wherein when the second binary signal is in the asserted state, the first circuit is configured to: generate a first voltage ramp, compare the first voltage ramp to a first threshold voltage, and assert the first control signal for a time period from a start of the first voltage ramp until the first voltage ramp intersects the first threshold voltage; and generate a second voltage ramp when the first voltage ramp intersects the first threshold voltage, compare the second voltage ramp to a second threshold voltage, and set the second control signal to the asserted state for a time period from a start of the second voltage ramp until the second voltage ramp intersects the second threshold voltage.

46. A voltage regulator comprising: a first output intended to be connected to a capacitive element; a current source coupled between the first output and a first node configured to receive a supply voltage, the current source configured to deliver a first DC current to the first output only in response to assertion of a first binary signal; a second output intended to be connected to a second terminal of the capacitive element; a comparator configured to deliver a second binary signal in an asserted state when a first voltage on the first output is lower than a setpoint voltage; and a first circuit configured to assert the first binary signal for a first fixed time period when the second binary signal is in the asserted state, wherein the first output is further intended to be connected to a first terminal of an inductive element; further comprising: a second output intended to be connected to a second terminal of the inductive element; a first switch connected between the first node and the second output; and a second switch connected between the second output and a second node configured to receive a reference potential; wherein the first circuit is configured to assert a first control signal for a third time period when the second binary signal is in the asserted state, and then to assert a second control signal for a fourth time period at the end of the third time period; wherein the first circuit is further configured to control a conduction state of the first switch when the first control signal is in the asserted state and to control a conduction state of the second switch when the second control signal is in the asserted state in a first operating mode, and to set the first binary signal to the asserted state in response to an assertion of the first binary signal or the second control signal being in the asserted state in a second operating mode.

47. The voltage regulator of claim 46, wherein the third time period is fixed and determined by the supply voltage.

48. The voltage regulator of claim 46, wherein the third time period is fixed and independent of the supply voltage.

49. The voltage regulator of claim 46, wherein the fourth time period is fixed and determined by the supply voltage.

50. The voltage regulator of claim 46, wherein the fourth time period is fixed and independent of the supply voltage.

51. The voltage regulator of claim 46, wherein the first operating mode is of a pulse frequency modulation type.

52. The voltage regulator of claim 46, wherein when the second binary signal is in the asserted state, the first circuit is configured to: generate a first voltage ramp, compare the first voltage ramp to a first threshold voltage, and assert the first control signal for a time period from a start of the first voltage ramp until the first voltage ramp intersects the first threshold voltage; and generate a second voltage ramp when the first voltage ramp intersects the first threshold voltage, compare the second voltage ramp to a second threshold voltage, and set the second control signal to the asserted state for a time period from a start of the second voltage ramp until the second voltage ramp intersects the second threshold voltage.

53. The voltage regulator of claim 46, wherein the first fixed time period is fixed and independent of the supply voltage.

54. The voltage regulator of claim 46, wherein the first fixed time period is determined by the supply voltage.

55. The voltage regulator of claim 46, wherein the DC current has a fixed value independent of temperature.

56. The voltage regulator of claim 46, wherein the DC current has a value proportional to the absolute value of temperature.

57. The voltage regulator of claim 46, wherein the first fixed time period and the current source are configured such that the amount of charge supplied to the first output during each first fixed time period is set dependent on a given temperature value and a supply voltage value.

58. An electronic device comprising: a voltage regulator according to any one of claims 1-45; and a load connected to the first output of the regulator.

59. The electronic device of claim 58, wherein the electronic device further comprises a capacitive element connected to the first output of the regulator.

60. An electronic device comprising: a voltage regulator according to any one of claims 46-57; a load connected to the first output of the voltage regulator; and an inductive element connected between the first output and the second output of the voltage regulator.

61. The electronic device of claim 60, wherein the electronic device comprises an integrated circuit chip comprising the voltage regulator, wherein the inductive element is arranged external to the integrated circuit chip.

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