Linear voltage regulator circuit and chip for applications with fast power supply voltage changes

Abstract

The present invention provides a linear voltage regulator circuit and chip for applications where the power supply voltage rapidly changes. The linear voltage regulator circuit includes a bias generation module for generating a bias voltage; a power stage output module connected to the bias generation module for generating an output voltage under the control of the bias voltage; and a bias regulation module connected to the bias generation module for reversely regulating the bias voltage based on changes in the power supply voltage to maintain a stable output voltage. The linear voltage regulator circuit and chip provided by the present invention address the problem of unstable output voltage caused by rapidly changing power supply voltage in existing FVF-structured LDO circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a linear voltage regulator circuit and chip in applications where power supply voltage changes rapidly. Background Art

[0002] Low-dropout linear regulators (LDOs) are widely used in portable electronic products due to their low ripple, low noise, and compact size. To reduce power consumption, the LDO's quiescent current must be lowered. However, this reduction in quiescent current leads to a sharp decline in the LDO's load capacity and transient response. LDOs with a flipped voltage follower (FVF) structure, on the other hand, can track the output voltage of a reference voltage in steady-state operation, offering a relatively simple circuit structure and excellent transient response.

[0003] In an FVF-structured LDO, due to parasitic capacitance between the gate and drain of the power transistor, when the power supply voltage changes rapidly, the gate voltage of the power transistor cannot fully follow the change, causing the output voltage to fluctuate and take a while to recover. Therefore, how to maintain a stable output voltage when the power supply voltage changes rapidly is a technical problem that those skilled in the art are eager to solve.

[0004] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of the present invention and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the technical background section of the present invention, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a linear voltage regulator circuit and chip for applications in which the power supply voltage changes rapidly, so as to solve the problem that the output voltage of the existing FVF structure LDO circuit is unstable due to the rapid change of the power supply voltage.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides a linear voltage regulator circuit for applications where the power supply voltage changes rapidly, the linear voltage regulator circuit comprising:

[0007] Bias generation module, power level output module and bias regulation module;

[0008] The bias voltage generating module is used to generate a bias voltage;

[0009] The power level output module is connected to the bias voltage generating module and is used to generate an output voltage under the control of the bias voltage;

[0010] The bias voltage regulating module is connected to the bias voltage generating module and is used to reversely regulate the bias voltage according to the change of the power supply voltage to keep the output voltage stable.

[0011] Optionally, the bias voltage generating module includes a current providing unit and a bias voltage generating unit;

[0012] The current providing unit is used to provide the original current to the bias generating unit;

[0013] The bias voltage generating unit is connected to the current providing unit and the bias voltage regulating module, and is configured to generate the bias voltage according to the original current, and regulate the bias voltage by performing a current injection or extraction operation on the original current.

[0014] Optionally, the current providing unit includes a first amplifier, a first PMOS tube, a first resistor and a second resistor, the first input end of the first amplifier is connected to a reference voltage, the second input end of the first amplifier is connected to the second end of the first resistor, the output end of the first amplifier is connected to the gate of the first PMOS tube, the source of the first PMOS tube is connected to the power supply voltage, the drain of the first PMOS tube is connected to the first end of the first resistor and serves as the output end of the current providing unit, and the second end of the first resistor is connected to the reference ground via the second resistor.

[0015] Optionally, the bias generating unit includes a second PMOS transistor and a first current source, the gate of the second PMOS transistor is short-circuited with its drain and serves as the output end of the bias generating unit, the source of the second PMOS transistor is connected to the output end of the current providing unit and the output end of the bias regulating module, and the drain of the second PMOS transistor is connected to the reference ground via the first current source.

[0016] Optionally, the power stage output module includes a third PMOS tube, a fourth PMOS tube and a second current source, the gate of the third PMOS tube is connected to the drain of the fourth PMOS tube and is connected to the reference ground via the second current source, the source of the third PMOS tube is connected to the power supply voltage, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube and serves as the output end of the power stage output module, and the gate of the fourth PMOS tube is connected to the output end of the bias generation module.

[0017] Optionally, the power stage output module includes a first NMOS tube, a third PMOS tube, a fourth PMOS tube, a second current source and a third current source, the gate of the first NMOS tube is connected to a fixed voltage, the drain of the first NMOS tube is connected to the gate of the third PMOS tube and connected to the power supply voltage via the third current source, the source of the first NMOS tube is connected to the drain of the fourth PMOS tube and connected to the reference ground via the second current source, the source of the third PMOS tube is connected to the power supply voltage, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube and serves as the output end of the power stage output module, and the gate of the fourth PMOS tube is connected to the output end of the bias generation module.

[0018] Optionally, the power stage output module includes a first NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a second current source and a third current source, the gate of the first NMOS transistor is connected to the node voltage, the drain of the first NMOS transistor is connected to the gate of the third PMOS transistor and is connected to the power supply voltage via the third current source, the source of the first NMOS transistor is connected to the drain of the fourth PMOS transistor and is connected to the reference ground via the second current source, the source of the third PMOS transistor is connected to the power supply voltage, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor and serves as the output end of the power stage output module, and the gate of the fourth PMOS transistor is connected to the output end of the bias generation module, wherein the node voltage comes from the bias generation module.

[0019] Optionally, the bias regulation module includes a second NMOS transistor, a third NMOS transistor, a fourth current source, a fifth current source, a third resistor and a first capacitor. The gate of the second NMOS transistor is connected to the gate of the third NMOS transistor via the third resistor, the drain of the second NMOS transistor is connected to the power supply voltage via the fourth current source and serves as the output end of the bias regulation module, the source of the second NMOS transistor is connected to the reference ground, the drain of the third NMOS transistor is short-circuited with its gate and connected to the power supply voltage via the fifth current source, the source of the third NMOS transistor is connected to the reference ground, the first end of the first capacitor is connected to the connection node between the gate of the second NMOS transistor and the third resistor, and the second end of the first capacitor is connected to the power supply voltage.

[0020] The present invention further provides a chip, comprising the linear regulator circuit as described above.

[0021] Optionally, the chip comprises a system-on-chip.

[0022] As described above, the linear voltage regulator circuit and chip of the present invention for applications where the power supply voltage changes rapidly accelerate the change speed of the power tube gate voltage by reversely adjusting the bias voltage when the power supply voltage changes rapidly, so that the gate-source voltage of the power tube remains almost unchanged, thereby making the output voltage almost unchanged, thereby achieving stable output voltage when the power supply voltage changes rapidly; the present invention can stabilize the gate-source voltage of the power tube without paying a large area cost, and is also compatible with most FVF structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The figure shows a specific circuit diagram of an LDO circuit with a conventional FVF structure.

[0024] Figure 2 Shown is a structural schematic diagram of the linear voltage regulator circuit of the present invention.

[0025] Figure 3 Shown is a specific circuit diagram of the linear regulator circuit of the present invention.

[0026] Figure 4 FIG. 2 is another specific circuit diagram of the linear regulator circuit of the present invention.

[0027] Figure 5 FIG. 2 is another specific circuit diagram of the linear regulator circuit of the present invention.

[0028] Component number description

[0029] 100 Linear Regulator Circuit

[0030] 110 Bias generation module

[0031] 111 Current supply unit

[0032] 112 Bias voltage generation unit

[0033] 120 Power Level Output Module

[0034] 130 Bias adjustment module DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] See also Figures 1 to 5It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the form, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0037] Figure 1 An existing FVF structure LDO circuit is shown, including a PMOS transistor MP1', a PMOS transistor MP2', a PMOS transistor MP3', a PMOS transistor MP4', a PMOS transistor MP5', a PMOS transistor MP6', an NMOS transistor MN1', an NMOS transistor MN2', a current source Ib', a current source I1', and a current source I2', wherein the gate of the PMOS transistor MP1' is connected to the gate of the PMOS transistor MP2', the source of the PMOS transistor MP1' is connected to the power supply voltage VDD', the drain of the PMOS transistor MP1' is connected to the drain of the NMOS transistor MN1' and the gate of the PMOS transistor MP3', the gate of the PMOS transistor MP2' is short-circuited with its drain, the source of the PMOS transistor MP2' is connected to the power supply voltage VDD', the drain of the PMOS transistor MP2' is connected to the drain of the NMOS transistor MN2', and the gate of the NMOS transistor MN1' is connected to the drain of the NMOS transistor MN2'. The reference voltage VREF' is connected to the source of the NMOS transistor MN1', the source of the NMOS transistor MN2' is connected to the source of the NMOS transistor MN2' and to the reference ground via the current source Ib', the source of the PMOS transistor MP3' is connected to the power supply voltage VDD', the drain of the PMOS transistor MP3' is connected to the gate of the NMOS transistor MN2' and the source of the PMOS transistor MP4', the gate and drain of the PMOS transistor MP4' are short-circuited, the drain of the PMOS transistor MP4' is connected to the reference ground via the current source I1', the gate of the PMOS transistor MP5' is connected to the drain of the PMOS transistor MP6' and to the reference ground via the current source I2', the source of the PMOS transistor MP5' is connected to the power supply voltage VDD', the drain of the PMOS transistor MP5' is connected to the source of the PMOS transistor MP6' and serves as the output end of the LDO circuit with an FVF structure, and the gate of the PMOS transistor MP6' is connected to the gate of the PMOS transistor MP4'.

[0038] In the above-described FVF structure LDO circuit, the PMOS transistors MP1', MP2', NMOS transistors MN1', MN2', and current source Ib' constitute an amplification portion; the PMOS transistors MP3', MP4', and current source I1' constitute a bias portion; and the PMOS transistors MP5', MP6', and current source I2' constitute an FVF structure output portion. By matching the current sources I1' and I2', and the PMOS transistors MP4' and MP6', respectively, that is, by making the current ratio of the current sources I1' and I2' equal to the width-to-length ratio of the PMOS transistors MP4' and MP6', the output voltage VOUT' is made equal to the reference voltage VREF', thereby achieving a voltage regulation function. However, the above circuit also has the following disadvantages: First, the PMOS transistor MP5' is a power transistor, and parasitic capacitance exists between its gate and drain. When the power supply voltage changes rapidly, the gate voltage of the power transistor cannot fully follow the change in the power supply voltage, resulting in a change in the output voltage that requires a certain period of time to recover (for example, when the power supply voltage drops rapidly, the gate voltage of the power transistor cannot fully follow the drop, resulting in a decrease in its gate-source voltage and the output voltage that requires a certain period of time to recover. The same applies when the power supply voltage rises rapidly). Second, the above circuit is generally used in on-chip integrated applications, where there is no large load capacitance. Therefore, the output voltage change caused by rapid changes in the power supply voltage will be obvious. In addition, since the area of ​​the power transistor is generally large, adding capacitance between the gate and source of the power transistor to stabilize the gate-source voltage will incur a significant area cost. Moreover, in other FVF variant structures, the loop compensation scheme is inconsistent with the increased gate-source capacitance.

[0039] Based on this, this embodiment provides a linear voltage regulator circuit 100 for applications in which the power supply voltage changes rapidly, including a bias generating module 110, a power stage output module 120 and a bias regulating module 130. Figure 2 As shown; this embodiment is intended to reduce the change of the output voltage VOUT when the power supply voltage VDD changes rapidly and drastically, keep the output voltage VOUT stable, stabilize the gate-source voltage of the power tube without paying a large area cost, and is also compatible with most FVF structures.

[0040] The bias voltage generating module 110 is used to generate a bias voltage VSET. The bias voltage generating module 110 includes a current providing unit 111 and a bias voltage generating unit 112 .

[0041] The current providing unit 111 is used to provide the original current to the bias generating unit 112. In one embodiment, Figures 3 to 5As shown, the current providing unit 111 includes a first amplifier OP1, a first PMOS transistor MP1, a first resistor R1, and a second resistor R2. The first input terminal of the first amplifier OP1 is connected to a reference voltage VREF, the second input terminal of the first amplifier OP1 is connected to the second terminal of the first resistor R1, the output terminal of the first amplifier OP1 is connected to the gate of the first PMOS transistor MP1, the source of the first PMOS transistor MP1 is connected to the power supply voltage VDD, the drain of the first PMOS transistor MP1 is connected to the first terminal of the first resistor R1 and serves as the output terminal of the current providing unit 111, and the second terminal of the first resistor R1 is connected to the reference ground via the second resistor R2. The first amplifier OP1 is an operational amplifier, the first input terminal of the first amplifier OP1 is a negative input terminal, and the second input terminal of the first amplifier OP1 is a positive input terminal. It should be noted that the circuit structure of the current providing unit 111 is not limited to this, and other circuit structures capable of providing raw current are also applicable to this embodiment.

[0042] The bias generating unit 112 is connected to the current providing unit 111 and the bias regulating module 130, and is used to generate a bias voltage VSET according to the original current, and to regulate the bias voltage VSET by injecting or extracting current from the original current. Figures 3 to 5 As shown, the bias generating unit 112 includes a second PMOS transistor PM2 and a first current source I1. The gate of the second PMOS transistor MP2 is short-circuited with its drain and serves as the output end of the bias generating unit 112. The source of the second PMOS transistor MP2 is connected to the output end of the current providing unit 111 and the output end of the bias regulating module 130. The drain of the second PMOS transistor MP2 is connected to the reference ground via the first current source I1.

[0043] The power stage output module 120 is connected to the bias voltage generation module 110 and is configured to generate an output voltage VOUT under the control of the bias voltage VSET. The power stage output module 120 employs an FVF structure. The term "FVF" does not refer to a specific structure, but rather a general term encompassing all FVF structures. In practice, most FVF structures can be used as the power stage output module 120 of this embodiment. Since it is impossible to enumerate all of them, the following two structures are provided for illustrative purposes.

[0044] In one embodiment, Figure 3As shown, the power stage output module 120 includes a third PMOS transistor MP3, a fourth PMOS transistor MP4 and a second current source I2. The gate of the third PMOS transistor MP3 is connected to the drain of the fourth PMOS transistor MP4 and is connected to the reference ground via the second current source I2. The source of the third PMOS transistor MP3 is connected to the power supply voltage VDD. The drain of the third PMOS transistor MP3 is connected to the source of the fourth PMOS transistor MP4 and serves as the output end of the power stage output module 120. The gate of the fourth PMOS transistor MP4 is connected to the output end of the bias generation module 110. The third PMOS transistor MP3, the fourth PMOS transistor MP4 and the second current source I2 constitute an FVF structure, and the third PMOS transistor MP3 is a power transistor.

[0045] In another embodiment, Figure 4 As shown, the power stage output module 120 includes a first NMOS transistor MN1, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a second current source I2, and a third current source I3. The gate of the first NMOS transistor MN1 is connected to a fixed voltage VS, the drain of the first NMOS transistor MN1 is connected to the gate of the third PMOS transistor MP3 and to the power supply voltage VDD via the third current source I3, the source of the first NMOS transistor MN1 is connected to the drain of the fourth PMOS transistor MP4 and to the reference ground via the second current source I2, and the source of the third PMOS transistor MP3 is connected to the power supply voltage VDD. The drain of the third PMOS transistor MP3 is connected to the source of the fourth PMOS transistor MP4 and serves as the output end of the power stage output module 120. The gate of the fourth PMOS transistor MP4 is connected to the output end of the bias generation module 110. The first NMOS transistor MN1, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the second current source I2, and the third current source I3 form a cascade FVF structure. The third PMOS transistor MP3 is a power transistor, and the first NMOS transistor MN1 is used to raise the gate voltage of the power transistor to take into account the situation where the power supply voltage VDD and the output voltage VOUT differ significantly.

[0046] Of course, in other embodiments, the gate of the first NMOS transistor MN1 may not be connected to the fixed voltage VS, but may be connected to a node voltage, wherein the node voltage may come from the linear regulator circuit 100 of this embodiment or from other circuits, as long as the node voltage is of a moderate magnitude and can saturate the second current source I2 and the fourth PMOS transistor MP4 for normal operation. In one example, the node voltage comes from the bias generating module 110, for example, the gate of the first NMOS transistor MN1 is connected to the output terminal of the current providing unit 111 in the bias generating module 110, such as Figure 5As shown; at this time, the power stage output module 120 includes a first NMOS transistor MN1, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a second current source I2 and a third current source I3, the gate of the first NMOS transistor MN1 is connected to the node voltage, the drain of the first NMOS transistor MN1 is connected to the gate of the third PMOS transistor MP3 and is connected to the power supply voltage VDD via the third current source I3, the source of the first NMOS transistor MN1 is connected to the drain of the fourth PMOS transistor MP4 and is connected to the reference ground via the second current source I2, the source of the third PMOS transistor MP3 is connected to the power supply voltage VDD, the drain of the third PMOS transistor MP3 is connected to the source of the fourth PMOS transistor MP4 and serves as the output end of the power stage output module 120, and the gate of the fourth PMOS transistor MP4 is connected to the output end of the bias generation module 110, wherein the node voltage comes from the bias generation module 110.

[0047] The bias regulation module 130 is connected to the bias generation module 110 and is used to reversely regulate the bias voltage VSET according to the change of the power supply voltage VDD, accelerate the change of the gate voltage of the power tube, and make it completely follow the change of the power supply voltage VDD to keep the output voltage VOUT stable.

[0048] In one embodiment, Figures 3 to 5 As shown, the bias regulation module 130 includes a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth current source I4, a fifth current source I5, a third resistor R3 and a first capacitor C1. The gate of the second NMOS transistor MN2 is connected to the gate of the third NMOS transistor MN3 via the third resistor R3. The drain of the second NMOS transistor MN2 is connected to the power supply voltage VDD via the fourth current source I4 and serves as the output end of the bias regulation module 130. The source of the second NMOS transistor MN2 is connected to the reference ground. The drain of the third NMOS transistor MN3 is short-circuited with its gate and connected to the power supply voltage VDD via the fifth current source I5. The source of the third NMOS transistor MN3 is connected to the reference ground. A first end of the first capacitor C1 is connected to the connection node between the gate of the second NMOS transistor MN2 and the third resistor R3. A second end of the first capacitor C1 is connected to the power supply voltage VDD.

[0049] Next, combine Figure 5 , the working principle of the linear regulator circuit 100 of this embodiment is described.

[0050] In the linear regulator circuit 100 , the current ratio of the first current source I1 to the second current source I2 is equal to the width-to-length ratio of the second PMOS transistor MP2 to the fourth PMOS transistor MP4 , and the current ratio of the fourth current source I4 to the fifth current source I5 is equal to the width-to-length ratio of the second NMOS transistor MN2 to the third NMOS transistor MN3 .

[0051] When the power supply voltage VDD remains unchanged, that is, when the circuit is in a steady state, the currents generated by the fourth current source I4 and the second NMOS transistor MN2 cancel each other out, leaving the voltage at node A unaffected and proportional to the reference voltage VREF. The first amplifier OP1, the first PMOS transistor MP1, the first resistor R1, and the second resistor R2 form a negative feedback structure, with the first PMOS transistor MP1 providing current to the second PMOS transistor MP2. By adjusting the ratio of the first resistor R1 to the second resistor R2, the voltage at node A in the steady state can be controlled. This ensures that the current densities of the fourth PMOS transistor MP4 and the second PMOS transistor MP2 are equal. At this point, the gate-source voltages of the fourth PMOS transistor MP4 and the second PMOS transistor MP2 are approximately equal. Therefore, the output voltage VOUT and the voltage at node A are approximately equal, achieving voltage regulation.

[0052] When the power supply voltage VDD drops rapidly, the gate voltage of the second NMOS transistor MN2 drops due to the high-pass filter formed by the third resistor R3 and the first capacitor C1. This causes the drain-source current of the second NMOS transistor MN2 to drop, which is unable to completely offset the current of the fourth current source I4. The excess current in the fourth current source I4 is injected into the second PMOS transistor MP2. At this time, the voltage at the node A increases, and the gate voltage of the second PMOS transistor MP2 (i.e., the bias voltage VSET) increases. In other words, the gate voltage of the fourth PMOS transistor MP4 increases, causing the drain voltage of the fourth PMOS transistor MP4 to drop. In other words, the source voltage of the first NMOS transistor MN1 drops, which in turn causes the gate voltage of the third PMOS transistor MP3 to drop. This accelerates the drop rate of the gate voltage of the third PMOS transistor MP3, thereby preventing the output voltage VOUT from dropping.

[0053] When the power supply voltage VDD rises rapidly, the gate voltage of the second NMOS transistor MN2 increases under the action of the high-pass filter formed by the third resistor R3 and the first capacitor C1, causing the drain-source current of the second NMOS transistor MN2 to increase. This increases the drain-source current of the second NMOS transistor MN2, which cannot be completely offset by the current of the fourth current source I4 alone. The second NMOS transistor MN2 draws current from the second PMOS transistor MP2 via the node A. At this time, the voltage at the node A drops, and thus the gate voltage of the second PMOS transistor MP2 (i.e., the bias voltage VSET) drops. In other words, the gate voltage of the fourth PMOS transistor MP4 drops, thereby increasing the drain voltage of the fourth PMOS transistor MP4. In other words, the source voltage of the first NMOS transistor MN1 increases, which in turn increases the gate voltage of the third PMOS transistor MP3. This accelerates the rise rate of the gate voltage of the third PMOS transistor MP3, thereby preventing the output voltage VOUT from increasing.

[0054] By properly designing the values ​​of the fourth current source I4, the fifth current source I5, the third resistor R3, and the first capacitor C1, the effect of changes in the power supply voltage VDD on the gate-source voltage of the third PMOS transistor MP3 can be offset. That is, the gate-source voltage of the third PMOS transistor MP3 remains almost unchanged when the power supply voltage VDD changes, thereby keeping the output voltage VOUT almost unchanged.

[0055] This embodiment further provides a chip including a linear voltage regulator circuit 100 , wherein the linear voltage regulator circuit 100 is implemented using the circuit structure described above. In one example, the chip of this embodiment is a system-on-chip (SOC).

[0056] In summary, the present invention provides a linear voltage regulator circuit and chip for applications with rapidly varying power supply voltages. When the power supply voltage rapidly changes, the circuit accelerates the change rate of the power tube gate voltage by reversely adjusting the bias voltage, keeping the gate-source voltage of the power tube nearly constant, and thus the output voltage nearly constant, thus maintaining output voltage stability during rapid power supply voltage changes. The present invention stabilizes the gate-source voltage of the power tube without requiring a large area footprint and is compatible with most FVF structures. Therefore, the present invention effectively overcomes the shortcomings of the prior art and possesses high industrial value.

[0057] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A linear voltage regulator circuit for applications where the power supply voltage changes rapidly, characterized in that: The linear regulator circuit comprises: Bias generation module, power level output module and bias regulation module; The bias voltage generating module is used to generate a bias voltage; The power level output module is connected to the bias voltage generating module and is used to generate an output voltage under the control of the bias voltage; The bias voltage regulating module is connected to the bias voltage generating module and is used to reversely regulate the bias voltage according to the change of the power supply voltage to keep the output voltage stable; The bias regulation module includes a second NMOS transistor, a third NMOS transistor, a fourth current source, a fifth current source, a third resistor and a first capacitor. The gate of the second NMOS transistor is connected to the gate of the third NMOS transistor via the third resistor. The drain of the second NMOS transistor is connected to the power supply voltage via the fourth current source and serves as the output end of the bias regulation module. The source of the second NMOS transistor is connected to the reference ground. The drain of the third NMOS transistor is short-circuited with its gate and connected to the power supply voltage via the fifth current source. The source of the third NMOS transistor is connected to the reference ground. The first end of the first capacitor is connected to the connection node between the gate of the second NMOS transistor and the third resistor, and the second end of the first capacitor is connected to the power supply voltage.

2. The linear voltage regulator circuit for applications where the power supply voltage changes rapidly according to claim 1, wherein: The bias voltage generating module includes a current providing unit and a bias voltage generating unit; The current providing unit is used to provide the original current to the bias generating unit; The bias voltage generating unit is connected to the current providing unit and the bias voltage regulating module, and is configured to generate the bias voltage according to the original current, and regulate the bias voltage by performing a current injection or extraction operation on the original current.

3. The linear voltage regulator circuit for applications where the power supply voltage changes rapidly according to claim 2, wherein: The current providing unit includes a first amplifier, a first PMOS transistor, a first resistor and a second resistor. The first input end of the first amplifier is connected to a reference voltage, the second input end of the first amplifier is connected to the second end of the first resistor, the output end of the first amplifier is connected to the gate of the first PMOS transistor, the source of the first PMOS transistor is connected to a power supply voltage, the drain of the first PMOS transistor is connected to the first end of the first resistor and serves as the output end of the current providing unit, and the second end of the first resistor is connected to a reference ground via the second resistor.

4. The linear voltage regulator circuit for applications where the power supply voltage changes rapidly according to claim 2, wherein: The bias generating unit includes a second PMOS transistor and a first current source. The gate of the second PMOS transistor is short-circuited with its drain and serves as the output end of the bias generating unit. The source of the second PMOS transistor is connected to the output end of the current providing unit and the output end of the bias regulating module. The drain of the second PMOS transistor is connected to the reference ground via the first current source.

5. The linear voltage regulator circuit for applications with rapidly changing power supply voltage according to claim 1, wherein: The power stage output module includes a third PMOS transistor, a fourth PMOS transistor and a second current source. The gate of the third PMOS transistor is connected to the drain of the fourth PMOS transistor and is connected to the reference ground via the second current source. The source of the third PMOS transistor is connected to the power supply voltage. The drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor and serves as the output end of the power stage output module. The gate of the fourth PMOS transistor is connected to the output end of the bias generation module.

6. The linear voltage regulator circuit for applications with rapidly changing power supply voltage according to claim 1, wherein: The power stage output module includes a first NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a second current source, and a third current source. The gate of the first NMOS transistor is connected to a fixed voltage, the drain of the first NMOS transistor is connected to the gate of the third PMOS transistor and is connected to the power supply voltage via the third current source, the source of the first NMOS transistor is connected to the drain of the fourth PMOS transistor and is connected to the reference ground via the second current source, the source of the third PMOS transistor is connected to the power supply voltage, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor and serves as the output end of the power stage output module, and the gate of the fourth PMOS transistor is connected to the output end of the bias generation module.

7. The linear voltage regulator circuit for applications with rapidly changing power supply voltage according to claim 1, wherein: The power stage output module includes a first NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a second current source, and a third current source. The gate of the first NMOS transistor is connected to a node voltage, the drain of the first NMOS transistor is connected to the gate of the third PMOS transistor and is connected to a power supply voltage via the third current source, the source of the first NMOS transistor is connected to the drain of the fourth PMOS transistor and is connected to a reference ground via the second current source, the source of the third PMOS transistor is connected to a power supply voltage, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor and serves as an output end of the power stage output module, and the gate of the fourth PMOS transistor is connected to the output end of the bias generation module, wherein the node voltage comes from the bias generation module.

8. A chip, characterized in that: The chip includes the linear regulator circuit according to any one of claims 1 to 7.

9. The chip according to claim 8, characterized in that The chip comprises a system-on-chip.

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