On-chip AXI bus monitoring method and monitoring module

Abstract

The present invention relates to the field of chip testing technology, and in particular to an on-chip AXI bus monitoring method and a monitoring module, which is executed by a monitoring module and includes: monitoring the start and response timestamps of each transfer operation to obtain the delay of each transfer operation; obtaining the average delay and average bandwidth by counting the delays and data volumes of multiple transfer operations within a time window; when the delay, average delay, average bandwidth or end time of each transfer operation triggers the interrupt mechanism of the target AXI bus, enabling the CPU to obtain the statistical results of the current time window; and outputting the delay, bandwidth and information entries of each transfer operation of the target AXI bus to an ATB bus. The monitoring module of the present invention can retain and provide key deadlock command information even when the CPU is hung, helping to quickly find the root cause, and achieving the goal of not interfering with the operation of business scenarios and obtaining the bus status in real time.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to an on-chip AXI bus monitoring method and a monitoring module. Background Art

[0002] AXI (Advanced eXtensible Interface) is a widely used on-chip bus standard. As a key communication protocol in system-on-chip (SoC), it is responsible for transferring data between various modules within the chip. The performance of the AXI bus directly affects the performance of the entire chip.

[0003] During chip testing and performance tuning, two major challenges arise. First, hardware faults such as bus deadlocks and CPU freezes often occur on chips, but there is a lack of efficient online testing tools to quickly locate the root cause of the problem, because prototype testing makes it difficult to build effective cases to reproduce and locate hardware deadlocks. Second, during performance tuning, although substandard performance can be detected, the necessary observation methods are lacking to accurately identify performance bottlenecks, making it impossible to implement targeted improvements. Although the Arteris NoC bridge can monitor the AXI bus, it may fail in the event of a deadlock, unable to output monitoring information, and the information is lost after reset. In addition, the Arteris NoC bridge has deployment difficulties and functional limitations in monitoring bus bandwidth, such as not supporting detailed bandwidth utilization analysis, which further increases the difficulty of performance tuning.

[0004] Therefore, there is an urgent need for an on-chip non-intrusive AXI bus monitoring method and technology that can obtain the bus status in real time without interfering with the operation of business scenarios. Summary of the Invention

[0005] In view of this, the present invention provides an on-chip AXI bus monitoring method and monitoring module to solve the problem that related technologies cannot obtain the bus status in real time and accurately due to the lack of testing tools and observation means.

[0006] In a first aspect, the present invention provides an on-chip AXI bus monitoring method, the method being executed by a monitoring module in an on-chip AXI bus monitoring system, the method comprising:

[0007] Monitor the start timestamp and response timestamp of each transfer operation on the target AXI bus to obtain the latency of each transfer operation;

[0008] By counting the delays and data volumes of multiple transmission operations within a time window, the average delay and average bandwidth within the time window are obtained;

[0009] When the delay of each transfer operation, the average delay, the average bandwidth, or the end time of the time window triggers an interrupt mechanism of the target AXI bus, causing a CPU processor to obtain statistical results of the current time window to obtain deadlock information, bus error information, or performance status of the target AXI bus;

[0010] The delay, bandwidth and information entry of each transfer operation of the target AXI bus are output to the ATB bus for bus status analysis.

[0011] By monitoring the start timestamp and response timestamp of each transfer operation, the above scheme can calculate and obtain the delay of each operation in real time, thereby realizing real-time monitoring of AXI bus performance; by counting the delay and data volume of multiple transfer operations within a time window, the average delay and average bandwidth are calculated, which helps to identify the changing trend of bus performance; under specific conditions (such as delay timeout, bus error, time window end or performance threshold triggering), the interrupt mechanism can be triggered to enable the CPU processor to obtain the statistical results of the current time window in a timely manner, which not only helps to quickly respond to bus problems, but also can accurately locate the problem by latching the information entries when deadlock or error occurs; the statistical data (including the delay, bandwidth and information entries of each transfer operation) are output to the ATB bus, which is convenient for integration with other systems or tools to achieve more comprehensive bus status analysis and performance monitoring, and improve the flexibility and scalability of the monitoring system.

[0012] In an optional embodiment, before monitoring the start timestamp and response timestamp of each transfer operation on the target AXI bus to obtain the delay of each transfer operation, the method further includes:

[0013] Acquire transfer operations on the target AXI bus and create corresponding information entries for each transfer operation; the information entries include valid information extracted from the AXI command channel.

[0014] The above solution creates an information entry for each transfer operation. When a deadlock or performance problem occurs, the pre-established information entry can quickly help locate the source of the problem, reduce fault diagnosis time, and improve the accuracy of problem analysis.

[0015] In an optional embodiment, monitoring the start timestamp and response timestamp of each transfer operation of the target AXI bus to obtain the delay of each transfer operation includes:

[0016] The start timestamp and the response timestamp of each transmission operation are monitored based on the trigger signal, and the delay of each transmission operation is obtained based on the difference between the start timestamp and the response timestamp.

[0017] The above scheme monitors the timestamps of transmission operations in real time, which can quickly feedback the system performance status and provide a basis for dynamically adjusting the command distribution intensity and bus bandwidth resource allocation.

[0018] In an optional embodiment, obtaining the average delay and average bandwidth in a time window by counting the delays and data volumes of multiple transmission operations in the time window includes:

[0019] Obtaining an average delay of multiple transmission operations by counting delays of the multiple transmission operations within a time window;

[0020] The data volume of each transmission operation within the time window is recorded, and an average bandwidth of the plurality of transmission operations is obtained based on the total data volume within the time window.

[0021] The above solution can provide timely feedback on performance changes by collecting statistics on the latency and data volume of transmission operations within the time window, thereby quickly responding to possible performance degradation or bottleneck problems.

[0022] In an optional embodiment, the interrupt mechanism includes deadlock and error interrupts; when the delay of each transfer operation, the average delay, the average bandwidth, or the end time of the time window triggers the interrupt mechanism of the target AXI bus, the CPU processor is caused to obtain statistical results of the current time window to obtain deadlock information, bus error information, or performance status of the target AXI bus, including:

[0023] When the delay of the transmission operation exceeds a timeout threshold or a bus error is monitored, it is determined that the target AXI bus triggers a deadlock interrupt, and the information entry corresponding to the first transmission operation in which the deadlock or bus error occurs is latched into a software-accessible register, so that the CPU processor obtains the deadlock information or bus error information of the target AXI bus; the register is set to have no reset terminal, and the software resets the register through a clear operation.

[0024] When the delay of a transmission operation exceeds a preset timeout threshold or a bus error is detected, the above scheme can quickly determine whether the target AXI bus has triggered a deadlock interrupt, thereby promptly identifying the occurrence of deadlock. Once a deadlock or bus error is detected, the information entry corresponding to the first transmission operation where the deadlock or bus error occurs is latched into a software-accessible register, allowing the CPU to obtain critical deadlock information or bus error information.

[0025] In an optional embodiment, the interrupt mechanism includes an interrupt at the end of a statistical window; when the delay of each transfer operation, the average delay, the average bandwidth, or the end time of the time window triggers the interrupt mechanism of the target AXI bus, the CPU processor obtains the statistical results of the current time window to obtain deadlock information, bus error information, or performance status of the target AXI bus, including:

[0026] When the time window expires, it is determined that the target AXI bus triggers a statistical window end interrupt, and the CPU processor obtains delay information and bandwidth information of the time window to obtain the performance status of the target AXI bus.

[0027] The above solution notifies the CPU processor to immediately obtain the delay information and bandwidth information of the time window at the end of the time window, thereby obtaining the performance status of the target AXI bus, ensuring the timeliness and accuracy of the data, and providing real-time data support for performance analysis.

[0028] In an optional embodiment, the interrupt mechanism includes a performance threshold interrupt; when the delay of each transfer operation, the average delay, the average bandwidth, or the end time of the time window triggers the interrupt mechanism of the target AXI bus, the CPU processor is caused to obtain statistical results of the current time window to obtain deadlock information, bus error information, or performance status of the target AXI bus, including:

[0029] When the average delay of the time window exceeds the average delay threshold or the average bandwidth is lower than the bandwidth threshold, it is determined that the target AXI bus triggers a performance threshold interrupt, and the CPU processor obtains the delay information and bandwidth information of the time window to obtain the performance status of the target AXI bus.

[0030] The performance threshold interruption of the above solution provides an effective performance guarantee mechanism, which helps to ensure that the AXI bus can maintain a good performance state under various working conditions.

[0031] In an optional embodiment, outputting the latency, bandwidth, and information entry of each transfer operation of the target AXI bus to the ATB bus for bus status analysis includes:

[0032] The latency, bandwidth, and information entries of each transfer operation are output to the ATB bus in a packaged manner and cached in an independent target storage space for bus status analysis.

[0033] By outputting data to the ATB bus, the above solution can comprehensively analyze and monitor the transmission activities on the AXI bus, helping to gain a deeper understanding of the performance status.

[0034] In an optional embodiment, the method further includes:

[0035] Through statistics of multiple time windows, a time-axis-based delay and bandwidth histogram is formed to analyze the overall bus performance bottleneck.

[0036] The above solution can intuitively display the changing trends and bottlenecks of bus performance by forming visualization methods such as timeline-based delay and bandwidth bar charts, providing strong support for in-depth analysis of system performance and formulation of optimization strategies.

[0037] In a second aspect, the present invention provides a monitoring module, which is provided in an on-chip AXI bus monitoring system, wherein the structure of the monitoring module includes an axi_mon interface, a monitoring read bus unit, and a monitoring write bus unit;

[0038] The axi_mon interface of the monitoring module is connected to the target AXI bus interface, the CPU processor interface, the target storage device interface and the CTI cross trigger interface respectively;

[0039] The monitoring read bus unit is used to monitor the read bus of the target AXI bus, and the monitoring write bus unit is used to monitor the write bus of the target AXI bus;

[0040] The monitoring module is used to execute an on-chip AXI bus monitoring method according to the first aspect or any corresponding embodiment thereof.

[0041] In a third aspect, the present invention provides an on-chip AXI bus monitoring system, the system comprising a monitoring module as described above, the monitoring module being configured to be connected to a CPU processor interface and a GDMA master interface, a PCIe AXI interface, a DDR memory and an OCM on-chip memory, and a peripheral channel.

[0042] In a fourth aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, computer instructions being stored in the memory, and the processor executing the computer instructions to thereby execute an on-chip AXI bus monitoring method according to the first aspect or any corresponding embodiment thereof.

[0043] In a fifth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute an on-chip AXI bus monitoring method according to the first aspect or any corresponding embodiment thereof.

[0044] In a sixth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute an on-chip AXI bus monitoring method according to the first aspect or any corresponding embodiment thereof.

[0045] The technical solution provided by the present invention can have the following beneficial effects:

[0046] The present invention can calculate and obtain the delay of each operation in real time by monitoring the start timestamp and response timestamp of each transmission operation, thereby realizing real-time monitoring of AXI bus performance; by counting the delay and data volume of multiple transmission operations in a time window, calculating the average delay and average bandwidth, it is helpful to identify the changing trend of bus performance; under specific conditions (such as delay timeout, bus error, time window end or performance threshold triggering), it is possible to trigger an interrupt mechanism so that the CPU processor can obtain the statistical results of the current time window in time, which not only helps to quickly respond to bus problems, but also can accurately locate the problem by latching the information entry when deadlock or error occurs; the statistical data (including the delay, bandwidth and information entry of each transmission operation) are output to the ATB bus, which is convenient for integration with other systems or tools, realizing more comprehensive bus status analysis and performance monitoring, and improving the flexibility and scalability of the monitoring system. The present invention can also intuitively display the changing trend and bottleneck of bus performance by forming visualization means such as delay and bandwidth histograms based on the time axis, providing strong support for in-depth analysis of system performance and formulation of optimization strategies.

[0047] In addition, the present invention monitors and records bus information in real time. Even in the case of a CPU hang, the monitoring module can retain and provide key deadlock command information to help quickly find the root cause; the monitoring module can capture bus errors in real time. These errors may indicate potential system anomalies or deadlocks, providing first-hand data for problem troubleshooting; the monitoring module allows performance testing to be performed directly on the chip. By tracking and analyzing performance data in real time, it reduces dependence on the laboratory environment and improves testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0049] Figure 1 is a schematic structural diagram of a monitoring module according to an embodiment of the present invention;

[0050] Figure 22 is a schematic structural diagram of an on-chip AXI bus monitoring system according to an embodiment of the present invention;

[0051] Figure 3 is a flow chart of an on-chip AXI bus monitoring method according to an embodiment of the present invention;

[0052] Figure 4 is a flowchart of another on-chip AXI bus monitoring method according to an embodiment of the present invention;

[0053] Figure 5 1. A schematic diagram of bandwidth and delay statistics timing according to an embodiment of the present invention;

[0054] Figure 6 is a schematic diagram of deadlock monitoring according to an embodiment of the present invention;

[0055] Figure 7 2 is a schematic structural diagram of a Trace bus and a bus error packet format according to an embodiment of the present invention;

[0056] Figure 8 2. It is a structural diagram of the Trace deadlock packet format according to an embodiment of the present invention;

[0057] Figure 9 2. It is a schematic diagram of the structure of the Trace bandwidth and delay information packet format according to an embodiment of the present invention;

[0058] Figure 10 is a structural block diagram of an on-chip AXI bus monitoring device according to an embodiment of the present invention;

[0059] Figure 11 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0060] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0061] It should be noted that some key terms in the present invention are first explained:

[0062] A stuck state occurs when a system, device, or process becomes unable to continue executing due to some reason. In this case, the system or device cannot respond to any operations or commands.

[0063] Deadlock: occurs when multiple processes or threads are waiting for each other to release resources, but no process can continue execution.

[0064] CPU: Central Processing Unit, responsible for executing program instructions and processing data.

[0065] IOPS: Input / Output Operations Per Second is an indicator to measure the performance of storage devices, indicating the number of IO operations that the storage device can process per second.

[0066] NoC: Network on Chip is a network architecture used to implement communication between different IP cores in an integrated circuit.

[0067] aw channel: AXI write command channel (AXI Write Address Channel), used to transmit command information of write operations on the AXI bus.

[0068] ar channel: AXI read command channel (AXI Read Address Channel), used to transmit read operation command information on the AXI bus.

[0069] r channel: AXI read response channel (AXI Read Data Channel), used to transmit the return data of the read operation on the AXI bus.

[0070] Channel b: AXI Write Response Channel, used to transmit the confirmation response of the write operation on the AXI bus.

[0071] CTI: Cross Trigger Interface, a component in the Coresight system that enables synchronization and communication between different debugging and tracing components.

[0072] ATB: Advanced Trace Bus is a bus used to transmit system trace information.

[0073] Cmd_tim: Command Timing, which refers to the time when the command is sent in the system.

[0074] Resp_tim: Response Timing, which refers to the time when the system receives the command response.

[0075] RMW: Read-Modify-Write operation is a common data operation mode that reads data, modifies the data, and then writes it back.

[0076] EMU: Emulator is a piece of hardware or software used to simulate the behavior of other systems or devices for testing or development.

[0077] OCM: On-Chip Memory is a storage resource integrated on the chip, used to store instructions and data.

[0078] GDMA: Global Direct Memory Access is a technology that allows certain hardware devices to directly access memory.

[0079] PER: Peripheral Subsystem, a component in the system used to manage and control external devices (such as sensors, displays, etc.).

[0080] Figure 1 is a schematic diagram of the structure of a monitoring module according to an embodiment of the present invention, the monitoring module is provided in an on-chip AXI bus monitoring system, such as Figure 1 As shown, the structure of the monitoring module axi_mon includes an axi_mon interface, a monitoring read bus unit, and a monitoring write bus unit;

[0081] The axi_mon interface of the monitoring module is connected to the target AXI bus interface, the CPU processor interface, the target storage device interface and the CTI cross trigger interface respectively;

[0082] The monitoring read bus unit is used to monitor the read bus of the target AXI bus, and the monitoring write bus unit is used to monitor the write bus of the target AXI bus;

[0083] The monitoring module is used to execute an on-chip AXI bus monitoring method in the following embodiments.

[0084] Furthermore, the signals of the axi_mon interface of the monitoring module include AXI bus channel signals, interrupt request signals, software read / write bus signals, ATB Trace signals, and trigger signals;

[0085] Furthermore, in this embodiment, the monitoring module axi_mon is a monitor for monitoring AXI (Advanced Xtensible Interface) bus activities, and is used to perform performance analysis, deadlock detection, bandwidth and delay statistics on the AXI bus. Figure 1As shown, the interface signals of the monitoring module axi_mon include S1 to S5.

[0086] Among them, S1 is the aw channel: AXI write command channel (AXI Write Address Channel);

[0087] ar channel: AXI read command channel (AXI Read Address Channel);

[0088] r channel: AXI read response channel (AXI Read Data Channel);

[0089] b channel: AXI write response channel (AXI Write Response Channel);

[0090] To achieve non-intrusive functionality, the handshake signals (such as valid) and payload signals (i.e., information entries) of the four channels are input into the monitoring module axi_mon, where the command payload information, sending timestamp, and response timestamp are recorded for recording and analysis.

[0091] S2 is the interrupt request signal (intr). The interrupt mechanism in this embodiment includes deadlock interrupt, statistics window end interrupt, and performance threshold interrupt, corresponding to three scenarios: when a command does not receive a response for a certain period of time, a deadlock interrupt is triggered to notify the CPU to read the deadlock information;

[0092] The time window for statistical bandwidth and latency ends, triggering a statistical window end interrupt to notify the CPU to read;

[0093] When the average bandwidth falls below a threshold or the average latency exceeds a threshold, a performance threshold interrupt is triggered, notifying the CPU to read data and obtain the scene of performance degradation immediately.

[0094] S3 is the software read / write bus signal (Sw_rw). Software reads deadlock information, bus errors, bandwidth, latency information, and the number of transmitted commands through the bus, and configures the time window, timeout threshold, bandwidth threshold, average latency threshold, and trace filtering conditions. The monitoring module axi_mon connects to the CPU through the intr and Sw_rw interfaces. When an interrupt is triggered, the monitoring module axi_mon notifies the CPU through the intr interface to read relevant statistical information. The CPU then reads the relevant statistical information through the Sw_rw interface.

[0095] S4 is the ATB Trace signal. The monitoring module axi_mon is connected to the storage device Memory through the ATB Trace interface to output the monitored AXI bus activities (such as commands, data, timestamps, etc.) to the ATB bus (Advanced Trace Bus) in the form of a trace data stream. It supports outputting trace data to various storage devices such as Flash, on-chip RAM, DDR, and SSD disks.

[0096] S5 is the trigger signal. The monitoring module axi_mon is connected to the Coresight system through the trigger interface to receive the trigger signal from the CTI (Cross-Trigger Interface) or other system events of the Coresight system, thereby triggering the monitoring module axi_mon to start bandwidth and delay statistics or trace command information recording.

[0097] For further information, see Figure 1 From S6 to S8, the data structure of the monitoring module axi_mon includes:

[0098] srcid: source identifier, used to distinguish different master devices or channels;

[0099] address: the destination address of the transfer operation;

[0100] burst_len: burst length, indicating the number of transmissions included in the burst transmission;

[0101] burst_size: burst size, which defines the number of bytes of data in each transmission;

[0102] axi_payload signal: includes other information items, such as protection type (AWPROT / ARPROT), storage attributes (AWCACHE / ARCACHE), etc.

[0103] cmd_tim: command timestamp, recording the time when the command was sent;

[0104] Valid signal: used to indicate whether the transmission is valid.

[0105] Furthermore, the depth of the monitoring module axi_mon refers to the number of outstanding transactions it can track simultaneously, that is, its outstanding transaction capability. axi_mon is divided into two independent parts: read monitoring and write monitoring, which monitor the activities of the read bus and write bus respectively to achieve comprehensive performance evaluation and problem diagnosis of the AXI bus.

[0106] Figure 2FIG. 1 is a schematic diagram of the structure of an on-chip AXI bus monitoring system according to an embodiment of the present invention. Figure 2 As shown, the system includes Figure 1 A monitoring module is shown, which is configured to be connected to the CPU processor interface and GDMAmaster interface, PCIe AXI interface, DDR memory and OCM on-chip memory, and peripheral channel PER.

[0107] Further, such as Figure 2 As shown in N0 to N5, hanging on the CPU processor interface and GDMA master interface can monitor deadlock and bus error, and then find the root cause of the system;

[0108] Attaching to the PCIe AXI interface can not only monitor deadlocks and bus errors, but also link latency and bandwidth, promptly detecting link lags or failures. It can also obtain real-time bandwidth usage of other masters or channels accessing PCIe, helping to analyze the root causes of performance bottlenecks.

[0109] Attached to DDR memory and OCM on-chip memory, it can monitor latency and bandwidth, obtain bus utilization of DDR memory and OCM on-chip memory; monitor the bandwidth usage of multiple masters accessing DDR memory and OCM on-chip memory, and analyze the root cause of performance bottlenecks.

[0110] Hanging on the peripheral channel, you can monitor deadlock and bus error bus conditions.

[0111] According to an embodiment of the present invention, an embodiment of an on-chip AXI bus monitoring method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0112] In this embodiment, an on-chip AXI bus monitoring method is provided. The method is executed by a monitoring module in an on-chip AXI bus monitoring system. Figure 3 FIG. 1 is a flow chart of an on-chip AXI bus monitoring method according to an embodiment of the present invention. Figure 3 As shown, the process includes the following steps:

[0113] Step S301 : monitoring the start timestamp and response timestamp of each transfer operation on the target AXI bus to obtain the delay of each transfer operation.

[0114] Furthermore, when the AXI bus starts a transfer operation (for example, reading data from memory or writing data to a peripheral device), this embodiment records a timestamp at that time point, which marks the start of the operation; when the AXI bus completes the transfer operation and is ready for the next operation, this embodiment records the timestamp at that time point again, which indicates the end of the operation. By comparing the start timestamp and the response timestamp, the delay of each transfer operation can be calculated. The delay of the transfer operation is one of the key indicators for measuring bus performance and efficiency, and can be used to analyze system performance and identify potential bottlenecks.

[0115] In step S302 , the average delay and average bandwidth in a time window are obtained by counting the delays and data volumes of multiple transmission operations in the time window.

[0116] Furthermore, in this embodiment, the time window can be a preset period of time for collecting and analyzing AXI bus performance data or performance status; the length of the time window can be set according to specific needs. Within the target time window, this embodiment collects latency and data volume information for all transmission operations within the time window and calculates the average latency and average bandwidth. The average latency can reflect the average speed of data transmission within the time window, while the average bandwidth indicates the amount of data successfully transmitted per unit time.

[0117] In step S303, when the delay of each transfer operation, the average delay, the average bandwidth, or the end time of the time window triggers the interrupt mechanism of the target AXI bus, the CPU processor obtains the statistical results of the current time window to obtain deadlock information, bus error information, or performance status of the target AXI bus.

[0118] Furthermore, the trigger conditions may include the delay of each transmission operation exceeding a preset threshold, the average delay exceeding an average delay threshold, the average bandwidth being lower than a bandwidth threshold, or the expiration time of the time window being reached; when any of the above conditions is met, the CPU processor will be notified and obtain the statistical results within the current time window. By analyzing these statistical results, it can be determined whether there is a deadlock in the AXI bus (i.e., two or more devices are waiting for each other to release resources and cannot continue to operate), bus error information or performance bottlenecks.

[0119] In step S304 , the delay, bandwidth, and information entry of each transfer operation of the target AXI bus are output to the ATB bus for bus status analysis.

[0120] Furthermore, the Advanced Trace Bus (ATB) bus in this embodiment is an on-chip bus used for tracing and debugging that can capture and transmit a large amount of system status information. This embodiment outputs the latency, bandwidth, and related information items (such as transfer type, target address, etc.) of each transfer operation of the AXI bus to the ATB bus. The Advanced Trace Bus (ATB) bus is a bus used to transmit trace data in the debugging system of the SoC (System on Chip). By outputting the transmission information of the AXI bus to the ATB, the data flow on the bus can be tracked and analyzed.

[0121] In summary, this embodiment can calculate and obtain the delay of each operation in real time by monitoring the start timestamp and response timestamp of each transmission operation, thereby realizing real-time monitoring of AXI bus performance; by counting the delay and data volume of multiple transmission operations within a time window, the average delay and average bandwidth are calculated, which helps to identify the changing trend of bus performance; under specific conditions (such as delay timeout, bus error, time window end or performance threshold triggering), the interrupt mechanism can be triggered so that the CPU processor can obtain the statistical results of the current time window in a timely manner, which not only helps to quickly respond to bus problems, but also can accurately locate the problem by latching the information entry when deadlock or error occurs; the statistical data (including the delay, bandwidth and information entry of each transmission operation) is output to the ATB bus, which is convenient for integration with other systems or tools, realizing more comprehensive bus status analysis and performance monitoring, and improving the flexibility and scalability of the monitoring system. This embodiment also forms a visualization method such as a timeline-based delay and bandwidth bar chart to intuitively display the changing trend and bottleneck of bus performance, providing strong support for in-depth analysis of system performance and formulation of optimization strategies.

[0122] In addition, this embodiment monitors and records bus information in real time. Even in the case of a CPU hang, the monitoring module can retain and provide key deadlock command information to help quickly find the root cause; the monitoring module can capture bus errors in real time. These errors may indicate potential system anomalies or deadlocks, providing first-hand data for problem troubleshooting; the monitoring module allows performance testing to be performed directly on the chip. By tracking and analyzing performance data in real time, it reduces dependence on the laboratory environment and improves testing efficiency.

[0123] In this embodiment, another on-chip AXI bus monitoring method is provided. The method is executed by a monitoring module in an on-chip AXI bus monitoring system. Figure 4 FIG. 1 is a flow chart of another on-chip AXI bus monitoring method according to an embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0124] Step S401 , obtaining transfer operations on the target AXI bus, and creating corresponding information entries for each transfer operation; the information entries include valid information extracted from the AXI command channel.

[0125] Furthermore, in the AXI (Advanced eXtensible Interface) bus protocol, a transfer operation indicates the data exchange between a master device (Master) and a slave device (Slave). This embodiment captures and monitors information about all transfer operations, including the start timestamp, response timestamp, and related data, and establishes an information entry (infoentry) for each transfer operation. The information entry includes valid information extracted from the AXI command channel, such as the source ID and destination address. In other words, this embodiment establishes an info entry for each transfer, including the source ID, destination address, and other payloads in the AXI command channel. When a deadlock occurs, the first entry corresponding to the deadlock and bus error is latched into a software register. These registers are designed to have no reset terminals, but can be cleared by software. After a reset, the transfer information can be read by software. The above registers can be cleared by software, but will not be automatically reset. After a system reset, the software can read the transfer information in these registers to help diagnose and solve the problem.

[0126] Step S402 : monitoring the start timestamp and response timestamp of each transfer operation on the target AXI bus to obtain the delay of each transfer operation.

[0127] In an optional implementation, step S402 includes:

[0128] The start timestamp and response timestamp of each transmission operation are monitored based on the trigger signal, and the delay of each transmission operation is obtained based on the difference between the start timestamp and the response timestamp.

[0129] For further information, see Figure 5 The bandwidth and delay statistics timing diagram shown is as follows: Figure 5 As shown in T0, when an aw / ar transmission request is received, the command timestamp is recorded. When a response is returned from the r / b channel, the recorded command timestamp is subtracted from the response timestamp to obtain the transmission delay of the command. In other words, when an address write request AW or an address read request AR is received on the AXI bus, this embodiment immediately records the command timestamp. Once the read data channel R or the write response channel B returns a response, the response timestamp is immediately recorded, and the command timestamp is subtracted from the response timestamp to obtain the transmission delay cmd_dly of the command.

[0130] In step S403 , the average delay of the multiple transmission operations is obtained by counting the delays of the multiple transmission operations within a time window.

[0131] Further, such as Figure 5 As shown, within a time window (such as Figure 5 The average delay is the sum of the delays of multiple transmission operations (as shown in T1). If the timeout threshold is exceeded and no response is received (as shown in Figure 5 cmd5 in the command), it is considered deadlocked and the first command information is locked in the register. If there are multiple groups of timed-out commands, they are output through the Trace interface.

[0132] That is, in this embodiment, within a time window (T1), the transmission delays cmd_dly of all commands are added together to obtain the total transmission delay Total_dly, which is then divided by the number of transmission commands n to obtain the average delay Ave_dly. Furthermore, within the same time window, the maximum value Max_dly and the minimum value Min_dly of all command transmission delays are found. If a command such as cmd5 still does not receive a response after the timeout threshold, it is considered that a deadlock has occurred. The first piece of information of such a command is stored in a register. If there are multiple timed-out commands, it is output through the Trace interface.

[0133] In this embodiment, the total transmission delay Total_dly is obtained by the following formula:

[0134]

[0135] The sum of all cmd_dly (the sum of the delays of transmission operations) is the total transmission delay within this data window, in cycles.

[0136] In this embodiment, the average delay Ave_dly is obtained by the following formula:

[0137] Ave_dly = total_dly / n;

[0138] The total transmission delay divided by the number of transmission commands is the average delay Ave_dly, in cycles.

[0139] In this embodiment, the maximum delay Max_dly within a time window is obtained by the following formula:

[0140] Max_dly=MAX{cmd_dly0,cmd_dly1,cmd_dlyn-1};

[0141] Among them, {cmd_dly0, cmd_dly1, cmd_dlyn-1} represents the delay of each transmission operation within a time window.

[0142] This embodiment uses the following formula to obtain the minimum delay Min_dly within a time window:

[0143] Min_dly=Min{cmd_dly0,cmd_dly1,cmd_dlyn-1}.

[0144] In step S404 , the data volume of each transmission operation within the time window is recorded, and based on the total data volume within the time window, an average bandwidth of the multiple transmission operations is obtained.

[0145] Furthermore, this embodiment calculates the total data volume of all commands within the time window to obtain the total transmission bandwidth Total_bw (in bytes (B)). The total transmission bandwidth is divided by the length of the time window time_win to obtain the average bandwidth Ave_bw (in bytes per cycle (B / cycle)). If the average bandwidth falls below a set threshold or the average latency exceeds a threshold, an interrupt mechanism is triggered, notifying the CPU to obtain performance information for the current time window.

[0146] This embodiment uses the following formula to obtain the total data volume Total_bw within a time window:

[0147]

[0148] The sum of all cmd data volumes is the total transmission bandwidth within this data window, in B.

[0149] In this embodiment, the average bandwidth Ave_bw within a time window is obtained by the following formula:

[0150] Ave_bw = total_bw / time_win;

[0151] The average bandwidth Ave_bw is the total transmission bandwidth divided by the time window, and the unit is B / cycle.

[0152] In this embodiment, when the average bandwidth falls below a threshold or the average latency exceeds a threshold, an interrupt is triggered to immediately notify the CPU, which then obtains bandwidth and latency information for the current time window and pauses new commands. This helps identify instances of poor bus performance and facilitates subsequent EMU simulation reproduction. Furthermore, this embodiment periodically polls (pooling) the bandwidth and latency information within the time window, generating a bandwidth and latency histogram on a timeline to identify the specific moment of performance issues, providing an effective way to deeply analyze bus performance.

[0153] In step S405 , when the delay of each transfer operation, the average delay, the average bandwidth, or the end time of the time window triggers an interrupt mechanism of the target AXI bus, the CPU processor obtains statistical results of the current time window to obtain deadlock information, bus error information, or performance status of the target AXI bus.

[0154] In an optional implementation, when the interrupt mechanism includes a deadlock interrupt, step S405 includes:

[0155] When the delay of the transmission operation exceeds the timeout threshold or a bus error is monitored, the target AXI bus is determined to have triggered a deadlock interrupt, and the information entry corresponding to the first transmission operation in which the deadlock or bus error occurred is latched into a register accessible to the software, so that the CPU processor obtains the deadlock information or bus error information of the target AXI bus; the register is set to have no reset terminal, and the software resets the register through a clear operation.

[0156] For further information, see Figure 6 The deadlock monitoring diagram shown in the figure, this embodiment establishes a record data buffer in the monitoring module axi_mon, records the start time and command information of each transmission, and uses the current time ( Figure 6 The difference between d0 (Curt_time) and the start time of each buffer entry is calculated and then compared with timeout_th ( Figure 6 If the value is greater than d1, it means timeout. The register without reset terminal will latch the command information and send an interrupt. If there are multiple such timeout commands, ATB trace will be started and output to the on-chip storage space.

[0157] When the patrol times out, if the response of channel B or channel R is incorrect, the command information is locked in the reset-free register and an interrupt is issued. If there are many such incorrect responses, the ATB trace is started and output to the on-chip storage space.

[0158] That is, this embodiment creates a data recording buffer in the monitoring module axi_mon, which is used to store the start time and related command information of each transmission operation on the AXI bus. Whenever the AXI bus initiates a transmission request, the start time and command information of the request are recorded in the buffer, and the current system time (d0) is periodically obtained. For each record in the buffer, this embodiment uses the current time (d0) to subtract the recorded start time to obtain the delay of the command, and compares the calculated delay with the preset timeout threshold (timeout_th, d1 in the figure). If the delay of a command exceeds the timeout threshold, it is considered that a timeout has occurred. The timed-out command information will be latched into a register without a reset terminal (to retain detailed information about the problem command), and an interrupt signal will be issued to notify the CPU that a timeout event has occurred for further processing.

[0159] If multiple timed-out commands are detected, this embodiment activates the Advanced Trace Bus (ATB) tracing function and outputs the timed-out command information to the on-chip storage space for subsequent analysis. At the same time, the response status of the AXI B (write response) channel or R (read data) channel is monitored. If the response indicates an error, the command information is also latched into a register without a reset terminal. For commands with an erroneous response, an interrupt signal is issued to notify the CPU of a bus error event, and the bus error information is output to the on-chip storage space for subsequent analysis.

[0160] In an optional embodiment, the interruption mechanism includes interruption at the end of the statistical window; step S405 includes:

[0161] When the time window ends, it is determined that the target AXI bus triggers a statistical window end interrupt, and the CPU processor obtains the delay information and bandwidth information of the time window to obtain the performance status of the target AXI bus.

[0162] In an optional implementation, the interruption mechanism includes a performance threshold interruption; step S405 includes:

[0163] When the average delay of the time window exceeds the average delay threshold or the average bandwidth is lower than the bandwidth threshold, it is determined that the target AXI bus triggers a performance threshold interrupt, and the CPU processor obtains the delay information and bandwidth information of the time window to obtain the performance status of the target AXI bus.

[0164] Step S406 , through statistics of multiple time windows, a time axis-based delay and bandwidth histogram is formed to analyze the overall performance bottleneck of the bus.

[0165] Furthermore, this embodiment regularly collects bandwidth and delay information within a time window to form a bandwidth and delay histogram based on a time axis to identify the specific moment of performance degradation, thereby facilitating subsequent simulation reproduction and optimization.

[0166] In step S407 , the delay, bandwidth, and information items of each transmission operation are output to the ATB bus in a packaged manner and cached in the target storage device for bus status analysis.

[0167] Furthermore, trace trigger conditions are a series of rules used to determine when to start tracing and recording system behavior. The trace trigger conditions of the ATB bus include:

[0168] Specify IO command execution: When an input / output (IO) device in the system executes a command, a trace may be triggered to monitor the timing and performance of the IO operation.

[0169] Interrupt event: The CPU receives an interrupt indicating increased latency or decreased bandwidth. If the CPU receives an interrupt, it indicates that this embodiment has detected increased transmission latency or decreased bandwidth, which may indicate a performance bottleneck or potential problem and requires further trace analysis.

[0170] Deadlock or Bus Error: Interrupts caused by deadlock timeouts or bus errors. Deadlock timeouts and BusErrors indicate that an operation has waited longer than the scheduled time for a response. These interrupts trigger a trace to record the system status before and after the problem occurs.

[0171] Coresight event: When a specific event occurs in the Coresight system, Coresight is a system-level debugging and tracing solution provided by ARM. Specific events in the Coresight system (such as a trigger counter reaching a threshold) can trigger Trace.

[0172] FIFO backpressure or bus backpressure: When a FIFO (first-in-first-out) queue experiences backpressure—that is, the FIFO is full and cannot write new data—it may indicate a data flow problem, triggering a trace to analyze the cause. Bus backpressure occurs when the data transmission rate on the bus exceeds the system's processing capacity, potentially causing data loss or delays. This triggers a trace to monitor bus status.

[0173] FIFO empty: The command FIFO becomes empty for a long time. If the command FIFO remains empty for a certain period of time, it may indicate a command scheduling problem or idle resources in the system. Triggering a trace can check whether the system is working as expected.

[0174] Specifically, when a trace trigger condition occurs, this embodiment outputs the latency, bandwidth, and information entries for each transfer operation in a packaged manner to the ATB bus and caches them in the target storage device for bus status analysis. Trace trigger conditions include the execution of a specified IO command, deadlock or bus error, Coresight event, FIFO backpressure or bus backpressure, and FIFO emptying.

[0175] Furthermore, after obtaining deadlock information or performance bottlenecks, this embodiment can specifically track and record a certain type of command on the bus to an external storage device for further analysis in order to further find the root cause. Each filter condition in the filter condition table can have multiple groups, and each group of filter conditions can be turned on or off through a mask. As long as the transmission payload meets the trigger condition, it will be tracked and recorded. This embodiment defines the data type that needs to be captured and recorded for the transmission operation through the filter condition table. The filter condition table is shown in Table 1:

[0176] Table 1

[0177]

[0178]

[0179] Furthermore, this embodiment outputs the delay, bandwidth, and information items of each transmission operation to the ATB bus in a packaged manner based on the Trace packet format, and caches them in the target storage device for bus status analysis.

[0180] The trace packet format includes a trace bus packet format, a trace deadlock packet format, and a trace bandwidth and delay information packet format;

[0181] The Trace bus packet format is used to record activity information on the bus. Figure 7 The structure diagram of the Trace bus and bus error packet format is shown. The packet format includes the following fields:

[0182] Packet_head: Used to identify the type of packet, distinguishing between trace bus, deadlock, bus error, or other types of packets.

[0183] AXI_srcid: Indicates the source identifier of the AXI bus transaction.

[0184] burst_len: indicates the length of the burst transmission, that is, the number of data beats transmitted.

[0185] burst_size: indicates the data width of each beat in Burst transmission.

[0186] addr: The destination address of the transfer operation.

[0187] cmd_tim: command timestamp, used to record the time when the command was issued.

[0188] resp_tim: Response timestamp, used to record the arrival time of the response.

[0189] Other payload information: may include other useful information, such as transmitted data content, control signals, etc.

[0190] Figure 7 The Packet_head encoding in is used to distinguish the packet format of Trace bus, deadlock, bus error, or bandwidth and delay.

[0191] See Figure 8 The schematic diagram of the structure of the Trace deadlock packet format is shown. The packet format is the same as the Trace bus packet format, but since no response is returned in the deadlock situation, the resp_tim field is missing.

[0192] See Figure 9 Figure 2 shows the structure of the trace bandwidth and latency information packet format. This packet format is used to indicate performance statistics and provide data for system performance analysis. It may not contain specific AXI transmission details. The packet format includes the following fields:

[0193] Total delay: The sum of all transmission operation delays within a time window.

[0194] Total bandwidth: The total amount of data transmitted within a time window.

[0195] Minimum delay: The minimum transmission delay recorded within the time window.

[0196] Maximum delay: The maximum transmission delay recorded in this time window.

[0197] Number of commands: The total number of transfer operations within the time window.

[0198] In summary, this embodiment can calculate and obtain the delay of each operation in real time by monitoring the start timestamp and response timestamp of each transmission operation, thereby realizing real-time monitoring of AXI bus performance; by counting the delay and data volume of multiple transmission operations within a time window, the average delay and average bandwidth are calculated, which helps to identify the changing trend of bus performance; under specific conditions (such as delay timeout, bus error, time window end or performance threshold triggering), the interrupt mechanism can be triggered so that the CPU processor can obtain the statistical results of the current time window in a timely manner, which not only helps to quickly respond to bus problems, but also can accurately locate the problem by latching the information entry when deadlock or error occurs; the statistical data (including the delay, bandwidth and information entry of each transmission operation) is output to the ATB bus, which is convenient for integration with other systems or tools, realizing more comprehensive bus status analysis and performance monitoring, and improving the flexibility and scalability of the monitoring system. This embodiment also forms a visualization method such as a timeline-based delay and bandwidth bar chart to intuitively display the changing trend and bottleneck of bus performance, providing strong support for in-depth analysis of system performance and formulation of optimization strategies.

[0199] In addition, this embodiment monitors and records bus information in real time. Even in the case of a CPU hang, the monitoring module can retain and provide key deadlock command information to help quickly find the root cause; the monitoring module can capture bus errors in real time. These errors may indicate potential system anomalies or deadlocks, providing first-hand data for problem troubleshooting; the monitoring module allows performance testing to be performed directly on the chip. By tracking and analyzing performance data in real time, it reduces dependence on the laboratory environment and improves testing efficiency.

[0200] In this embodiment, an on-chip AXI bus monitoring device is also provided. The device is executed by a monitoring module in an on-chip AXI bus monitoring system. The device is used to implement the above-mentioned embodiments and preferred implementation methods. The details that have been described will not be repeated here. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0201] This embodiment provides an on-chip AXI bus monitoring device, such as Figure 10 Shown, including:

[0202] The delay calculation unit 1010 is used to monitor the start timestamp and response timestamp of each transfer operation on the target AXI bus to obtain the delay of each transfer operation;

[0203] The average delay and bandwidth calculation unit 1020 is used to obtain the average delay and average bandwidth in a time window by counting the delays and data volumes of multiple transmission operations in the time window;

[0204] The deadlock and performance monitoring unit 1030 is configured to, when the delay of each transfer operation, the average delay, the average bandwidth, or the end time of the time window triggers an interrupt mechanism of the target AXI bus, enable the CPU processor to obtain statistical results of the current time window to obtain deadlock information or performance status of the target AXI bus;

[0205] The statistical result output unit 1040 is used to output the delay, bandwidth and information items of each transfer operation of the target AXI bus to the ATB bus for bus status analysis.

[0206] In some optional embodiments, the device is further used to:

[0207] Acquire the transfer operations on the target AXI bus and create a corresponding information entry for each transfer operation; the information entry includes valid information extracted from the AXI command channel.

[0208] In some optional implementations, the delay calculation unit 1010 is further configured to:

[0209] The start timestamp and response timestamp of each transmission operation are monitored based on the trigger signal, and the delay of each transmission operation is obtained based on the difference between the start timestamp and the response timestamp.

[0210] In some optional implementations, the average delay and bandwidth calculation unit 1020 is further configured to:

[0211] By counting the delays of multiple transmission operations within a time window, the average delay of the multiple transmission operations is obtained;

[0212] The data volume of each transmission operation within the time window is recorded, and based on the total data volume within the time window, an average bandwidth of the multiple transmission operations is obtained.

[0213] In some optional implementations, when the interrupt mechanism includes a deadlock interrupt, the deadlock and performance monitoring unit 1030 is further configured to:

[0214] When the delay of the transmission operation exceeds the timeout threshold or a bus error is monitored, the target AXI bus is determined to have triggered a deadlock interrupt, and the information entry corresponding to the first transmission operation in which the deadlock or bus error occurred is latched into a register accessible to the software, so that the CPU processor obtains the deadlock information or bus error information of the target AXI bus; the register is set to have no reset terminal, and the software resets the register through a clear operation.

[0215] In some optional implementations, when the interrupt mechanism includes a statistical window end interrupt, the deadlock and performance monitoring unit 1030 is further configured to:

[0216] When the time window ends, it is determined that the target AXI bus triggers a statistical window end interrupt, and the CPU processor obtains the delay information and bandwidth information of the time window to obtain the performance status of the target AXI bus.

[0217] In some optional implementations, when the interruption mechanism includes a performance threshold interruption, the deadlock and performance monitoring unit 1030 is further configured to:

[0218] When the average delay of the time window exceeds the average delay threshold or the average bandwidth is lower than the bandwidth threshold, it is determined that the target AXI bus triggers a performance threshold interrupt, and the CPU processor obtains the delay information and bandwidth information of the time window to obtain the performance status of the target AXI bus.

[0219] In some optional implementations, the statistical result output unit 1040 is further configured to:

[0220] The latency, bandwidth, and information entries of each transfer operation are output to the ATB bus in a packaged manner and cached in the target storage device for bus status analysis.

[0221] In some optional embodiments, the device is further used to:

[0222] Through statistics of multiple time windows, a time-axis-based delay and bandwidth histogram is formed to analyze the overall bus performance bottleneck.

[0223] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0224] In summary, this embodiment can calculate and obtain the delay of each operation in real time by monitoring the start timestamp and response timestamp of each transmission operation, thereby realizing real-time monitoring of AXI bus performance; by counting the delay and data volume of multiple transmission operations within a time window, the average delay and average bandwidth are calculated, which helps to identify the changing trend of bus performance; under specific conditions (such as delay timeout, bus error, time window end or performance threshold triggering), the interrupt mechanism can be triggered so that the CPU processor can obtain the statistical results of the current time window in a timely manner, which not only helps to quickly respond to bus problems, but also can accurately locate the problem by latching the information entry when deadlock or error occurs; the statistical data (including the delay, bandwidth and information entry of each transmission operation) is output to the ATB bus, which is convenient for integration with other systems or tools, realizing more comprehensive bus status analysis and performance monitoring, and improving the flexibility and scalability of the monitoring system. This embodiment also forms a visualization method such as a timeline-based delay and bandwidth bar chart to intuitively display the changing trend and bottleneck of bus performance, providing strong support for in-depth analysis of system performance and formulation of optimization strategies.

[0225] In addition, this embodiment monitors and records bus information in real time. Even in the case of a CPU hang, the monitoring module can retain and provide key deadlock command information to help quickly find the root cause; the monitoring module can capture bus errors in real time. These errors may indicate potential system anomalies or deadlocks, providing first-hand data for problem troubleshooting; the monitoring module allows performance testing to be performed directly on the chip. By tracking and analyzing performance data in real time, it reduces dependence on the laboratory environment and improves testing efficiency.

[0226] The present invention also provides a computer device. Figure 11 , Figure 11 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 11 As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 11A processor 10 is taken as an example.

[0227] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0228] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0229] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0230] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0231] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0232] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0233] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0234] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the defined scope.

Claims

1. An on-chip AXI bus monitoring method, characterized in that: The method is performed by a monitoring module in an on-chip AXI bus monitoring system, and the method includes: Monitor the start timestamp and response timestamp of each transfer operation on the target AXI bus to obtain the latency of each transfer operation; By counting the delays and data volumes of multiple transmission operations within a time window, the average delay and average bandwidth within the time window are obtained; the statistics of multiple time windows form a delay and bandwidth histogram based on the time axis; When the delay of each transfer operation, the average delay, the average bandwidth, or the end time of the time window triggers an interrupt mechanism of the target AXI bus, causing a CPU processor to obtain statistical results of the current time window to obtain deadlock information, bus error information, or performance status of the target AXI bus; Outputting the latency, bandwidth, and information entries of each transfer operation of the target AXI bus to the ATB bus for bus status analysis; When the interrupt mechanism includes a deadlock or error interrupt, when the interrupt mechanism of the target AXI bus is triggered by the completion of each transmission operation, the average delay, the average bandwidth, or the end time of the time window, the CPU processor obtains statistical results of the current time window to obtain deadlock information, bus error information, or performance status of the target AXI bus, including: When the delay of the transmission operation exceeds a timeout threshold or a bus error is monitored, the target AXI bus is determined to have triggered a deadlock interrupt, and the information entry corresponding to the first transmission operation in which the deadlock or bus error occurred is latched into a software-accessible register, allowing the CPU processor to obtain the deadlock information or bus error information of the target AXI bus; the register is set to have no reset terminal, and the software resets the register through a clear operation; the information entry includes valid information extracted from the AXI command channel; the valid information includes a source ID, a transmission type, and a destination address.

2. The method according to claim 1, characterized in that Before monitoring the start timestamp and response timestamp of each transfer operation of the target AXI bus to obtain the delay of each transfer operation, the method further includes: Get the transfer operations on the target AXI bus and create corresponding information entries for each transfer operation.

3. The method according to claim 1, characterized in that The monitoring of the start timestamp and response timestamp of each transfer operation of the target AXI bus to obtain the delay of each transfer operation includes: The start timestamp and the response timestamp of each transmission operation are monitored based on the trigger signal, and the delay of each transmission operation is obtained based on the difference between the start timestamp and the response timestamp.

4. The method according to claim 1, wherein The step of obtaining an average delay and an average bandwidth within a time window by counting the delays and data volumes of multiple transmission operations within the time window includes: Obtaining an average delay of multiple transmission operations by counting delays of the multiple transmission operations within a time window; The data volume of each transmission operation within the time window is recorded, and an average bandwidth of the plurality of transmission operations is obtained based on the total data volume within the time window.

5. The method according to claim 2, characterized in that The interrupt mechanism includes an interrupt at the end of a statistical window; when the delay of each transfer operation, the average delay, the average bandwidth, or the end time of the time window triggers the interrupt mechanism of the target AXI bus, the CPU processor obtains the statistical results of the current time window to obtain deadlock information, bus error information, or performance status of the target AXI bus, including: When the time window expires, it is determined that the target AXI bus triggers a statistical window end interrupt, and the CPU processor obtains delay information and bandwidth information of the time window to obtain the performance status of the target AXI bus.

6. The method according to claim 2, characterized in that The interrupt mechanism includes a performance threshold interrupt; when the delay of each transfer operation, the average delay, the average bandwidth, or the end time of the time window triggers the interrupt mechanism of the target AXI bus, the CPU processor obtains the statistical results of the current time window to obtain deadlock information, bus error information, or performance status of the target AXI bus, including: When the average delay of the time window exceeds the average delay threshold or the average bandwidth is lower than the bandwidth threshold, it is determined that the target AXI bus triggers a performance threshold interrupt, and the CPU processor obtains the delay information and bandwidth information of the time window to obtain the performance status of the target AXI bus.

7. The method according to claim 1, characterized in that Outputting the delay, bandwidth, and information entry of each transfer operation of the target AXI bus to the ATB bus for bus status analysis includes: The latency, bandwidth, and information entries of each transfer operation are output to the ATB bus in a packaged manner and cached in the target storage device for bus status analysis.

8. The method according to any one of claims 1 to 7, characterized in that The method further comprises: Through statistics of multiple time windows, a time-axis-based delay and bandwidth histogram is formed to analyze the overall bus performance bottleneck.

9. A monitoring module, characterized in that: The monitoring module is provided in an on-chip AXI bus monitoring system, wherein the structure of the monitoring module includes an axi_mon interface, a monitoring read bus unit, and a monitoring write bus unit; The axi_mon interface of the monitoring module is connected to the target AXI bus interface, the CPU processor interface, the target storage device interface and the CTI cross trigger interface respectively; The monitoring read bus unit is used to monitor the read bus of the target AXI bus, and the monitoring write bus unit is used to monitor the write bus of the target AXI bus; The monitoring module is used to execute the on-chip AXI bus monitoring method according to any one of claims 1 to 8.

10. An on-chip AXI bus monitoring system, characterized in that: The system includes a monitoring module as claimed in claim 9, and the monitoring module is configured to be connected to a CPU processor interface and a GDMA master interface, a PCIe AXI interface, a DDR memory and an OCM on-chip memory, and a peripheral channel.

11. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the on-chip AXI bus monitoring method according to any one of claims 1 to 8 by executing the computer instructions.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the on-chip AXI bus monitoring method according to any one of claims 1 to 8.

13. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to enable a computer to execute an on-chip AXI bus monitoring method according to any one of claims 1 to 8.

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