An IO expansion method, system and device based on xSPI implementation

Abstract

An IO expansion method, system and device based on xSPI implementation, the method includes: the main control CPU of the main control chip runs the first peripheral driver in the memory configured in the main control chip; the main control CPU sends a peripheral driver instruction to the first peripheral through xSPI; wherein the first peripheral is configured in the IO expansion chip and corresponds to the first peripheral driver; in response to receiving the peripheral driver instruction, the first peripheral collects information; if the first peripheral collects data information, the direct memory access module of the IO expansion chip transfers the data information to the main control chip through xSPI. As a result, not only can a variety of IO expansion application scenarios be realized, the diverse needs of complex systems can be met, the cost of software and hardware development can be reduced, and it is helpful to improve the communication speed, and parallel processing is supported, which enhances flexibility. In particular, for increasing the scenarios for IO expansion with different functions, the integration difficulty and cost can be effectively reduced, and the effect is particularly significant.

Description

Technical Field

[0001] The present application relates to the field of vehicle-mounted chip technology, and in particular to an IO expansion method, system and device based on xSPI implementation. Background Art

[0002] xSPI (eXtended Serial Peripheral Interface) is an enhanced version of the Serial Peripheral Interface (SPI). This standard specifies an enhanced serial peripheral interface for non-volatile memory devices, providing higher data rates, lower pin counts, and limited backward compatibility with traditional SPI devices. Combined with the XIP (eXecute in Place) technology of NOR flash (or non-flash memory), the processor can run programs directly on the flash memory device through XIP, so it is often used to integrate NOR Flash into MCU (Microcontroller Unit). Currently, microprocessors expand their input and output ports through IO expansion chips to connect a variety of peripheral devices such as sensors and actuators.

[0003] However, the related technology has certain drawbacks. On the one hand, conventional IO expansion chips are limited in supporting multiple communication protocols and peripheral functions, and can only process serially or maintain IO, which cannot meet the diverse needs of complex systems. On the other hand, IO expansion chips usually communicate with the main control MCU through SPI or I2C (Inter-Integrated Circuit). The main control MCU implements port configuration by configuring conventional IO expansion chips, and its communication speed and flexibility are not enough to support low-latency application requirements.

[0004] Based on this, how to implement an IO expansion method that can meet the needs of diverse and low-latency applications has become an urgent problem to be solved in the industry. Summary of the invention

[0005] In order to solve at least one problem existing in the prior art, the purpose of this application is to provide an IO expansion method, system and device based on xSPI, which can realize multiple IO expansion application scenarios, meet the diverse needs of complex systems, reduce the cost of software and hardware development, and help improve communication speed, and support parallel processing, and enhance flexibility. In particular, for adding scenarios for IO expansion with different functions, it can effectively reduce the integration difficulty and cost, and the effect is particularly significant.

[0006] To achieve the above-mentioned purpose, the IO expansion method based on xSPI provided in the present application is applied to an IO expansion system based on an extended serial peripheral interface xSPI including a main control chip and an IO expansion chip; the method comprises:

[0007] The main control CPU of the main control chip runs the first peripheral driver in the memory; wherein the memory is configured in the main control chip;

[0008] The main control CPU sends a peripheral drive instruction to the first peripheral through xSPI; wherein the first peripheral is configured in the IO expansion chip and corresponds to the first peripheral drive;

[0009] In response to receiving the peripheral device driving instruction, the first peripheral device performs information collection;

[0010] If the first peripheral device collects data information, the direct memory access module of the IO expansion chip transfers the data information to the memory through xSPI.

[0011] Furthermore, the method further comprises:

[0012] If the first peripheral device collects register identification information, the register identification information is written into a corresponding register via xSPI for reading by the main control CPU.

[0013] Furthermore, the method further comprises:

[0014] The main control CPU runs a second peripheral driver in the memory;

[0015] The main control CPU sends a peripheral drive instruction to the second peripheral; wherein the second peripheral is configured in the main control chip and corresponds to the second peripheral drive;

[0016] In response to receiving the peripheral device driving instruction, the second peripheral device performs information collection;

[0017] If the second peripheral device collects data information, the direct memory access module of the main control chip moves the data information to the memory.

[0018] Furthermore, the method further comprises,

[0019] If the second peripheral device collects the register identification information, the register identification information is written into the corresponding register for reading by the main control CPU.

[0020] Furthermore, the method further comprises:

[0021] If there are a first peripheral and a second peripheral using the same peripheral intellectual property core, the main control chip is configured to drive the first peripheral and the second peripheral using the same peripheral intellectual property core based on the same peripheral driver.

[0022] Furthermore, the method further comprises:

[0023] The first peripheral configured in the IO expansion chip includes at least one of a general-purpose input and output unit, an analog-to-digital conversion unit, a pulse width modulation unit, a serial peripheral interface unit, and a controller area network unit; and / or,

[0024] At least one of the second peripheral general-purpose input and output unit, analog-to-digital conversion unit, pulse width modulation unit, serial peripheral interface unit and controller area network unit configured in the main control chip.

[0025] Furthermore, the method further includes, in response to the completion of the data acquisition, the interrupt module of the IO expansion chip sending interrupt information to the interrupt module of the main control chip, so that the interrupt module of the main control chip sends the interrupt information to the main control CPU.

[0026] Furthermore, before the step of the main control CPU of the main control chip running the first peripheral device driver in the memory, the method further includes:

[0027] The main control chip initializes the main control chip end xSPI module;

[0028] The IO expansion chip initializes a clock module, a control chip end xSPI module, an interrupt module and a direct memory access module.

[0029] To achieve the above purpose, the present application also provides an IO expansion system based on xSPI implementation, including:

[0030] A main control chip is configured with a memory; the main control chip is used to run a first peripheral driver in the memory through the main control CPU of the main control chip; and is used to send a peripheral driver instruction to the first peripheral through the main control CPU using xSPI; wherein the first peripheral is configured in the IO expansion chip and corresponds to the first peripheral driver;

[0031] The IO expansion chip is used to collect information through the first peripheral in response to receiving the peripheral driving instruction; and when the first peripheral collects data information, the data information is transferred to the memory through the xSPI through the direct memory access module of the IO expansion chip.

[0032] To achieve the above objectives, the present application also provides an electronic device, including: a memory and a processor, wherein the memory stores computer instructions, and the processor is configured to run the instructions to execute the IO expansion method based on xSPI implementation as described above.

[0033] The present application discloses an IO expansion method, system and device based on xSPI implementation, wherein the main control CPU runs the first peripheral driver in the memory on the main control chip; and the main control CPU sends the peripheral driver instruction to the first peripheral on the IO expansion chip via xSPI; and in response to receiving the peripheral driver instruction, the first peripheral collects information; and when the first peripheral collects data information, the data information is transferred to the main control chip through the direct memory access module of the IO expansion chip via xSPI. Thus, it is possible to realize a variety of IO expansion application scenarios and non-sensing IO expansion of the main control chip, meet the diverse needs of complex systems, reduce the cost of software and hardware development, and help to improve the communication speed, and support parallel processing, and enhance flexibility. In particular, for increasing the scenarios for IO expansion with different functions, it can effectively reduce the difficulty and cost of integration, and the effect is particularly significant.

[0034] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or may be understood by practicing the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings:

[0036] Figure 1 It is a structural block diagram of an IO expansion system based on xSPI implementation according to an embodiment of the present application;

[0037] Figure 2 Flow chart of an IO expansion method based on xSPI implementation according to an embodiment of the present application;

[0038] Figure 3 is a flowchart of an IO expansion method based on xSPI implementation according to another embodiment of the present application;

[0039] Figure 4 is a flowchart of an IO expansion method based on xSPI implementation according to another embodiment of the present application;

[0040] Figure 5 is a structural block diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0041] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be construed as being limited to the embodiments described herein. Instead, these embodiments are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not intended to limit the scope of protection of the present application.

[0042] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0043] It should be noted that the concepts such as "first" and "second" mentioned in this application are only used to distinguish different modules and units, and are not used to limit the order or interdependence of the functions performed by these modules and units.

[0044] It should be noted that the modifications of "one" and "plurality" mentioned in this application are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more". "Plurality" should be understood as two or more.

[0045] First of all, it should be noted that in the relevant technology, conventional IO expansion chips have limitations in supporting multiple communication protocols and peripheral functions. They can only process serially or maintain IO, and cannot meet the diverse needs of complex systems. In addition, IO expansion chips usually communicate with the main control MCU through SPI or I2C. The main control MCU implements port configuration by configuring conventional IO expansion chips. Its communication speed and flexibility are not enough to support low-latency application requirements.

[0046] For example, in the prior art, when the input end of the analog-to-digital converter (ADC) needs to be expanded, only parallel input can be converted to serial processing, and parallel input cannot be converted to parallel processing. The main control MCU cannot directly apply the port of the IO expansion chip to the peripheral device without any sense, and the communication speed is low and the flexibility is insufficient, resulting in high latency.

[0047] Based on this, this application provides an IO expansion method based on xSPI, which can realize multiple IO expansion application scenarios, meet the diverse needs of complex systems, reduce the cost of software and hardware development, and help improve communication speed, and support parallel processing, and enhance flexibility. In particular, for adding scenarios for IO expansion with different functions, it can effectively reduce the integration difficulty and cost, and the effect is particularly significant.

[0048] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0049] It should be noted that the IO expansion method based on xSPI implementation in the present application is applied to the IO expansion system based on xSPI implementation.

[0050] Figure 1 FIG. 1 is a structural block diagram of an IO expansion system based on xSPI implementation according to an embodiment of the present application. Figure 1 As shown, the IO expansion system 100 based on xSPI includes an IO expansion chip 110 and a main control chip 120. The main control chip 120 may be a control chip related to automotive electronics, such as a domain control MCU.

[0051] In the specific example, the IO expansion chip 110 is configured with an expansion CPU 111, a DMA module 112, a first peripheral 113, a first xSPI module 114 and a first interrupt module 115. The main control chip 120 is configured with a main control CPU 121, a memory 122, a second peripheral 123, a second xSPI module 124 and a second interrupt module 125.

[0052] Among them, the first xSPI module 114 includes a corresponding host unit and a slave unit. The first peripheral 113 may specifically include at least one of a general purpose input output unit (GPIO), an analog digital conversion unit (ADC), a pulse width modulation unit (PWM), a serial peripheral interface unit (SPI) and a controller area network unit (CAN). The second xSPI module 124 includes a corresponding host unit and a slave unit. The second peripheral 123 may also specifically include at least one of a general purpose input output unit, an analog digital conversion unit, a pulse width modulation unit, a serial peripheral interface unit and a controller area network unit.

[0053] The xSPI communication, using the JESD251C standard published by the Solid State Technology Association JEDEC, provides higher data rates, low pin counts, and limited backward compatibility with legacy SPI devices compared to SPI communication. xSPI can be used with a single controller and multiple target buses with source synchronous clock capabilities. This standardization helps increase the adoption of xSPI in the automotive, networking, and data center markets, especially for devices with expanded boot code size. Specifically, the general IO voltage options of 1.2V, 1.8V, and 3.3V ensure broad support from mature to advanced process nodes. In terms of data throughput, xSPI can reach 400MB / s per pin on 8-bit IO, which is a 200% performance improvement over Quad-SPI (quad serial peripheral interface). With the XIP function in NOR flash applications, instant display data can be processed without loading the boot code into SRAM (Static Random Access Memory), which is one of the key requirements for cars with large displays.

[0054] Figure 2 The flowchart of the IO expansion method based on xSPI implementation according to the embodiment of the present application is as follows. Figure 2 , the IO expansion method based on xSPI implementation of the present application is described in detail.

[0055] In step 201 , a main control CPU of a main control chip runs a first peripheral device driver in a memory configured in the main control chip.

[0056] The memory may specifically be a RAM (Random Access Memory).

[0057] In the embodiment of the present application, before step 201, the method further includes: the main control chip initializes the main control chip end xSPI module; the IO expansion chip initializes the clock module, the first xSPI module, the interrupt module and the direct memory access module. In a specific example, the extended CPU of the IO expansion chip initializes the operating environment of the IO expansion chip by mainly running the ROM (Random Access Memory, read-only storage) mode.

[0058] In step 202, the main control CPU sends a peripheral driving instruction to the first peripheral through xSPI.

[0059] The first peripheral is configured in the IO expansion chip and corresponds to the first peripheral driver. It is understandable that the first peripheral driver can correspond to one first peripheral or multiple first peripherals, and this application does not make specific restrictions on this.

[0060] Specifically, the main control CPU sends the peripheral drive instruction to the second xSPI module of the main control chip via the BUS bus, and the second xSPI module sends the peripheral drive instruction to the BUS bus inside the IO expansion chip through xSPI communication, so that the corresponding first peripheral receives the peripheral drive instruction.

[0061] In step 203, in response to receiving the peripheral device driving instruction, the first peripheral device collects information.

[0062] That is, if the first peripheral of the IO expansion chip receives the peripheral drive instruction, information collection is performed. It is understandable that the information collected by some first peripherals is data information, such as ADC unit; the information collected by some first peripherals is register identification information, such as GPIO unit.

[0063] In step 204, if the first peripheral device collects data information, the direct memory access module of the IO expansion chip transfers the data information to the memory through xSPI.

[0064] That is, when the first peripheral is a peripheral for collecting data information (such as an ADC unit), the direct memory access module of the IO expansion chip transfers the data information collected by the first peripheral to the memory of the main control chip via the BUS bus and xSPI.

[0065] In the embodiment of the present application, the method may further include: if the first peripheral device collects the register identification information, the register identification information is written into the corresponding register via xSPI for the main control CPU to read. That is, if the first peripheral device is a peripheral device (such as a GPIO unit) that collects the register identification information, the IO expansion chip sends the register identification information to the corresponding register of the main control chip via xSPI.

[0066] According to the IO expansion method based on xSPI implementation of the embodiment of the present application, the first peripheral driver is run through the memory on the main control chip by the main control CPU; and the peripheral driver instruction is sent to the first peripheral on the IO expansion chip through the main control CPU via xSPI; and the first peripheral responds to the receipt of the peripheral driver instruction and performs information collection; and when the first peripheral collects data information, the data information is transferred to the main control chip through the direct memory access module of the IO expansion chip through xSPI. Thus, it is possible to realize a variety of IO expansion application scenarios and senseless IO expansion of the main control chip, meet the diverse needs of complex systems, reduce the cost of software and hardware development, and help to improve the communication speed, and support parallel processing, and enhance flexibility. In particular, for the increase of scenarios for IO expansion with different functions, the integration difficulty and cost can be effectively reduced, and the effect is particularly significant.

[0067] It is understandable that the main control chip may be configured with peripheral devices or may not be configured with peripheral devices, and this application does not impose any specific restrictions on this.

[0068] In the embodiment of the present application, when the main control chip is configured with peripheral devices, such as Figure 3 As shown, the method may further include the following steps:

[0069] Step 301: The main control CPU runs a second peripheral device driver in the memory.

[0070] Step 302: The main control CPU sends a peripheral device driving instruction to the second peripheral device.

[0071] The second peripheral is configured in the main control chip and corresponds to the second peripheral driver. It can be understood that the second peripheral driver can correspond to one second peripheral or multiple second peripherals, and this application does not make specific restrictions on this.

[0072] Step 303: In response to receiving the peripheral device driving instruction, the second peripheral device collects information.

[0073] Step 304: If the second peripheral device collects data information, the direct memory access module of the main control chip moves the data information to the memory.

[0074] Furthermore, the method may also include the following steps:

[0075] Step 305: If the second peripheral device collects the register identification information, the register identification information is written into the corresponding register for the main control CPU to read.

[0076] That is to say, if the main control chip is provided with a second peripheral, the main control chip runs the second peripheral driver corresponding to the second peripheral, and then the main control CPU sends the peripheral driver instruction to the second peripheral via the BUS bus, so that the second peripheral can collect information. In the case where the second peripheral is a peripheral that collects data information (such as an ADC unit), the direct memory access module of the main control chip transfers the data information collected by the second peripheral to the memory of the main control chip through the BUS bus. In the case where the second peripheral is a peripheral that collects register identification information (such as a GPIO unit), the main control chip sends the register identification information to the corresponding register via the BUS bus.

[0077] In an embodiment of the present application, the first peripheral configured in the IO expansion chip may include at least one of a general-purpose input-output unit, an analog-to-digital conversion unit, a pulse width modulation unit, a serial peripheral interface unit, and a controller local area network unit. If a second peripheral is provided on the main control chip, the second peripheral configured in the main control chip may also include at least one of a general-purpose input-output unit, an analog-to-digital conversion unit, a pulse width modulation unit, a serial peripheral interface unit, and a controller local area network unit. It is understandable that the specific types, quantities, and configurations of the first peripheral in the IO expansion chip and the second peripheral in the main control chip may be the same or different. The present application does not impose specific restrictions on this.

[0078] In the embodiment of the present application, if there are a first peripheral and a second peripheral using the same peripheral intellectual property core (IP), the main control chip preferably drives the first peripheral and the second peripheral using the same peripheral intellectual property core based on the same peripheral driver. This can greatly reduce the difficulty of software development and help improve development efficiency.

[0079] In the embodiment of the present application, the method further includes, in response to the completion of data acquisition, the interrupt module of the IO expansion chip sends interrupt information to the interrupt module of the main control chip, so that the interrupt module of the main control chip sends the interrupt information to the main control CPU. Through this interrupt response mechanism, not only can multi-tasking be supported, but also it is conducive to improving real-time performance and reliability.

[0080] The present application will be further explained and illustrated by means of specific embodiments below.

[0081] Figure 4 For a flow chart of the IO expansion method based on xSPI implementation according to this specific embodiment, refer to Figure 4 As shown, the IO expansion method based on xSPI implementation includes the following steps:

[0082] Step 401: The IO expansion chip initializes the clock module.

[0083] Step 402: The IO expansion chip initializes the first xSPI module.

[0084] Step 403: The IO expansion chip initializes the interrupt module and the first DMA module.

[0085] Step 404: The main control chip initializes the second xSPI module.

[0086] Step 405 , the main control CPU runs the first ADC driver in the RAM, and drives the first ADC unit and the second ADC unit to collect information via xSPI communication.

[0087] Step 406: the main control CPU runs the second ADC driver in the RAM to drive the third ADC unit and the fourth ADC unit to collect information.

[0088] Step 407: The first DMA module transfers the data information collected by the first ADC unit and the second ADC unit to the main control chip through xSPI.

[0089] In summary, according to the IO expansion method based on xSPI implementation of the embodiment of the present application, the first peripheral driver is run through the memory on the main control chip by the main control CPU; and the peripheral driver instruction is sent to the first peripheral on the IO expansion chip through the main control CPU via xSPI; and in response to receiving the peripheral driver instruction, the first peripheral performs information collection; and when the first peripheral collects data information, the data information is transferred to the main control chip through the direct memory access module of the IO expansion chip through xSPI. Thus, it is possible to realize a variety of IO expansion application scenarios and senseless IO expansion of the main control chip, meet the diverse needs of complex systems, reduce the cost of software and hardware development, and help to improve the communication speed, and support parallel processing, and enhance flexibility. In particular, for increasing the scene for IO expansion with different functions, it can effectively reduce the difficulty and cost of integration, and the effect is particularly significant.

[0090] This application provides an IO expansion system based on xSPI. Figure 1 As shown, the IO expansion system 100 implemented based on xSPI includes an IO expansion chip 110 and a main control chip 120 .

[0091] The main control chip 120 is configured with a memory 122. The main control chip 120 is used to run the first peripheral driver in the memory 122 through the main control CPU 121 of the main control chip 120; and is used to send a peripheral driver instruction to the first peripheral 113 through the main control CPU 121 using xSPI. The first peripheral 113 is configured in the IO expansion chip 110 and corresponds to the first peripheral driver.

[0092] The IO expansion chip 110 is used to collect information through the first peripheral 113 in response to receiving a peripheral driving instruction; and when the first peripheral 113 collects data information, the data information is transferred to the memory 122 of the main control chip 120 through the direct memory access module 112 of the IO expansion chip 110 via xSPI.

[0093] In the embodiment of the present application, the IO expansion chip 110 is further used to: when the first peripheral 113 collects the register identification information, write the register identification information into the corresponding register through the xSPI for the main control CPU 121 to read.

[0094] In the embodiment of the present application, the main control chip 120 is also used to: run the second peripheral driver in the memory 122 through the main control CPU 121; and send the peripheral driver instruction to the second peripheral 123 through the main control CPU 121; and in response to receiving the peripheral driver instruction, collect information through the second peripheral 123; and when the second peripheral 123 collects data information, the data information is transferred to the memory 122 of the main control chip 120 through the direct memory access module of the main control chip 120.

[0095] The second peripheral device 123 is configured on the main control chip 120 and corresponds to the second peripheral device driver.

[0096] Furthermore, the main control chip 120 is also used for: when the second peripheral device 123 collects the register identification information, writing the register identification information into the corresponding register for the main control CPU 121 to read.

[0097] In the embodiment of the present application, when there are a first peripheral and a second peripheral using the same peripheral intellectual property core, the main control chip 120 is used to drive the first peripheral and the second peripheral using the same peripheral intellectual property core based on the same peripheral driver.

[0098] In the embodiment of the present application, the IO expansion chip 110 can be configured as follows: the first peripheral 113 includes at least one of a general-purpose input and output unit, an analog-to-digital conversion unit, a pulse width modulation unit, a serial peripheral interface unit, and a controller area network unit. The main control chip 120 can also be configured as follows: the second peripheral 123 includes at least one of a general-purpose input and output unit, an analog-to-digital conversion unit, a pulse width modulation unit, a serial peripheral interface unit, and a controller area network unit.

[0099] In the embodiment of the present application, the IO expansion chip 110 is also used to: in response to the completion of data collection, send interrupt information to the second interrupt module 125 of the main control chip 120 through the first interrupt module 115, so that the second interrupt module 125 sends the interrupt information to the main control CPU 121.

[0100] In the embodiment of the present application, before the main control CPU 121 runs the first peripheral driver in the memory 122, the IO expansion chip 110 is also used to initialize the clock module, the first xSPI module 114, the first interrupt module 115 and the direct memory access module 112; the main control chip 120 is also used to initialize the second xSPI module 124.

[0101] It should be noted that the explanation of the IO expansion method based on xSPI in the above embodiment is also applicable to the IO expansion system based on xSPI in the above embodiment, and will not be repeated here.

[0102] Figure 5 FIG. 1 is a structural block diagram of an electronic device according to an embodiment of the present application. Figure 5 As shown, the electronic device 500 includes a memory 501 and a processor 502. The memory 501 stores computer instructions, and the processor 502 is configured to run the instructions to execute the IO expansion method based on xSPI implementation in the above embodiment.

[0103] In the embodiment of the present application, the electronic device may be a driving device. The driving device can be used for private travel tools and public travel tools. Among them, private travel tools include but are not limited to private cars, balance bikes, electric motorcycles, etc. Public travel tools include but are not limited to buses, trains, subways, high-speed railways, airplanes, etc.

[0104] It should be understood that, although the steps in the flowcharts of the accompanying drawings of the specification are displayed in sequence according to the indications of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0105] It should be understood that the systems and methods disclosed in the several embodiments provided in this application are merely illustrative and may be implemented in other ways. For example, the division of modules or units in the embodiments is merely a logical function division, and another division method may be used in actual implementation. For example, multiple units or components may be combined or integrated into another system; some features may be ignored; some steps may not be performed. In addition, the direct coupling connection or communication connection between each other shown or discussed may be an indirect coupling connection or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms of connection.

[0106] It should be noted that the specific numerical values ​​mentioned above are only used as examples to illustrate the implementation of the present application in detail, and should not be understood as limiting the present application. In other examples or implementations or embodiments, other numerical values ​​can be selected according to the present application, and are not specifically limited here.

[0107] Those skilled in the art can understand that the above are only preferred embodiments of the present application and are not intended to limit the present application. Although the present application is described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions recorded in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An IO expansion method based on xSPI, characterized in that: The invention is applied to an IO expansion system based on an extended serial peripheral interface xSPI including a main control chip and an IO expansion chip; the method comprises: The main control CPU of the main control chip runs the first peripheral driver in the memory; wherein the memory is configured in the main control chip; The main control CPU sends the peripheral drive instruction to the second xSPI module of the main control chip via the BUS bus, and the second xSPI module sends the peripheral drive instruction to the first xSPI module inside the IO expansion chip through xSPI communication; The first xSPI module sends the peripheral drive instruction to the first peripheral via the BUS bus of the IO expansion chip; wherein the first peripheral is configured in the IO expansion chip and corresponds to the first peripheral drive; In response to receiving the peripheral device driving instruction, the first peripheral device performs information collection; If the first peripheral device collects data information, the direct memory access module of the IO expansion chip transfers the data information to the memory through the first xSPI module.

2. The method according to claim 1, characterized in that: The method further comprises, If the first peripheral device collects register identification information, the register identification information is written into a corresponding register via xSPI for reading by the main control CPU.

3. The method according to claim 1, characterized in that The method further comprises, The main control CPU runs a second peripheral driver in the memory; The main control CPU sends a peripheral drive instruction to the second peripheral; wherein the second peripheral is configured in the main control chip and corresponds to the second peripheral drive; In response to receiving the peripheral device driving instruction, the second peripheral device performs information collection; If the second peripheral device collects data information, the direct memory access module of the main control chip moves the data information to the memory.

4. The method according to claim 3, characterized in that The method further comprises, If the second peripheral device collects the register identification information, the register identification information is written into the corresponding register for reading by the main control CPU.

5. The method according to claim 3, characterized in that: The method further comprises, If there are a first peripheral and a second peripheral using the same peripheral intellectual property core, the main control chip is configured to drive the first peripheral and the second peripheral using the same peripheral intellectual property core based on the same peripheral driver.

6. The method according to claim 3, characterized in that: The method further comprises, The first peripheral configured in the IO expansion chip includes at least one of a general-purpose input and output unit, an analog-to-digital conversion unit, a pulse width modulation unit, a serial peripheral interface unit, and a controller area network unit; and / or, The second peripheral configured in the main control chip includes at least one of a general-purpose input and output unit, an analog-to-digital conversion unit, a pulse width modulation unit, a serial peripheral interface unit, and a controller area network unit.

7. The method according to claim 1, characterized in that The method further includes, in response to the completion of the data collection, the interrupt module of the IO expansion chip sending interrupt information to the interrupt module of the main control chip, so that the interrupt module of the main control chip sends the interrupt information to the main control CPU.

8. The method according to any one of claims 1 to 7, characterized in that: Before the step of the main control CPU of the main control chip running the first peripheral device driver in the memory, the method further includes: The main control chip initializes the main control chip end xSPI module; The IO expansion chip initializes a clock module, a control chip end xSPI module, an interrupt module and a direct memory access module.

9. An IO expansion system based on xSPI, characterized in that: The system comprises, A main control chip is configured with a memory; the main control chip is used to run a first peripheral device driver in the memory through a main control CPU of the main control chip; And used to send a peripheral drive instruction to a first peripheral through the main control CPU using xSPI; wherein the first peripheral is configured in the IO expansion chip and corresponds to the first peripheral drive; The IO expansion chip is used to collect information through the first peripheral in response to receiving the peripheral driving instruction; and when the first peripheral collects data information, the data information is transferred to the memory through the xSPI through the direct memory access module of the IO expansion chip.

10. An electronic device comprising a memory and a processor, characterized in that: The memory stores computer instructions, and the processor is configured to run the instructions to execute the IO expansion method based on xSPI implementation according to any one of claims 1 to 8.

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