Data buffer structure and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and more particularly to a data buffer structure and memory, comprising: a plurality of cascaded data buffer units, each of which includes: a first sampling circuit configured to generate a sampling signal and a complementary sampling signal based on an input signal and a reference signal; a second sampling circuit configured to generate a data signal and a complementary data signal based on the sampling signal and the complementary sampling signal; an equalization feedback circuit configured to feedback and adjust the sampling signal and the complementary sampling signal based on the data signal and the complementary data signal output by the previous-stage data buffer unit to reduce inter-symbol interference between adjacent input signals; and a compensation circuit connected to the first sampling circuit and configured to increase the rate of change of the sampling signal and the complementary sampling signal to optimize the critical comparison time after the DFE is turned on, thereby improving the symmetry of the digital eye diagram.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a data buffer structure and a memory. Background Art

[0002] In DRAM design, the data buffer circuit (Data buffer) is a channel for data input and output, and is an important interface for receiving external data and reading internal data.

[0003] In DDR5 / LPDDR5 circuits, the data buffer circuit includes a decision feedback equalization (DFE) module. DFE is a method that reduces inter-symbol interference by using previous data to feed back subsequent data. Using DFE technology helps widen the data eye diagram, increasing the time and voltage domain spans, and ensuring that the memory bus can transmit signals at a higher transmission rate.

[0004] For DRAM, the digital eye diagram is used for memory performance analysis. The digital eye diagram can be obtained based on the eye diagram of the waveform at the input end of the data buffer circuit combined with the critical comparison time derivation.

[0005] However, when DFE is enabled, the critical comparison time for data jumping from "0" to "1" is shortened, while the critical comparison time for data jumping from "1" to "0" remains unchanged. This asymmetric change in data jump time causes the asymmetry of the digital eye diagram (left-right asymmetry of the digital eye diagram) to increase when DFE is enabled. Asymmetric digital eye diagrams are not conducive to the training process in memory applications. Summary of the Invention

[0006] The embodiments of the present disclosure provide a data buffer structure and a memory to optimize the critical comparison time after DFE is turned on, thereby improving the symmetry of the digital eye diagram.

[0007] An embodiment of the present disclosure provides a data buffer structure, comprising: a plurality of cascaded data buffer units, each data buffer unit comprising: a first sampling circuit configured to generate a sampling signal and a complementary sampling signal based on an input signal and a reference signal; wherein if the potential of the input signal is greater than the potential of the reference signal, the potential of the generated complementary sampling signal is greater than the potential of the sampling signal; and if the potential of the reference signal is greater than the potential of the input signal, the potential of the generated sampling signal is greater than the potential of the complementary sampling signal; a second sampling circuit configured to generate a data signal and a complementary data signal based on the sampling signal and the complementary sampling signal; wherein if the potential of the sampling signal is greater than the potential of the complementary sampling signal, the potential of the generated complementary data signal is greater than the potential of the data signal; and if the potential of the complementary sampling signal is greater than the potential of the sampling signal, the potential of the generated data signal is greater than the potential of the complementary data signal; an equalization feedback circuit configured to feedback-adjust the sampling signal and the complementary sampling signal based on the data signal and the complementary data signal output by the previous data buffer unit to reduce inter-symbol interference between adjacent input signals; and a compensation circuit connected to the first sampling circuit and configured to increase the rate of change of the sampling signal and the complementary sampling signal.

[0008] Increasing the change rate of the sampling signal and the complementary sampling signal through the compensation circuit is equivalent to shortening the critical comparison time. Therefore, after the compensation circuit is added and the equalization feedback circuit is turned on, the degree of asymmetric change in the critical comparison time is reduced, thereby improving the symmetry of the digital eye diagram to a certain extent.

[0009] For example, a first sampling circuit includes: a first switching transistor, a first terminal for receiving a first power supply signal, and a control terminal for receiving a clock signal; a first P-type transistor, a first terminal coupled to the second terminal of the first switching transistor, and a control terminal for receiving an input signal; a second P-type transistor, a first terminal coupled to the second terminal of the first switching transistor, and a control terminal for receiving a reference signal; a first N-type transistor, a first terminal coupled to the second terminal of the first P-type transistor, and used to output a sampling signal, a second terminal for receiving a second power supply signal, and a control terminal for receiving a clock signal; a second N-type transistor, a first terminal coupled to the second terminal of the second P-type transistor, and used to output a complementary sampling signal, a second terminal for receiving a second power supply signal, and a control terminal for receiving a clock signal; wherein the power supply voltage provided by the first power supply signal is greater than the power supply voltage provided by the second power supply signal.

[0010] For example, the compensation circuit includes: a first current compensation transistor, a first terminal for receiving a third power supply signal, a second terminal coupled to the second terminal of the first switching transistor, and a control terminal for receiving a supplementary control signal; wherein the supplementary control signal is generated based on the data signal or complementary data signal output by the previous level data buffer unit, and the power supply voltage provided by the third power supply signal is greater than the power supply voltage provided by the second power supply signal.

[0011] For example, the compensation circuit includes: a second current compensation transistor, a first terminal coupled to the second terminal of the first N-type transistor and the second N-type transistor, a second terminal for receiving a second power supply signal, and a control terminal for receiving a supplementary control signal; wherein the supplementary control signal is generated based on the data signal and the complementary data signal output by the previous level data buffer unit.

[0012] For example, the compensation circuit includes: a second switching transistor, a first terminal for receiving a first power supply signal, a control end for receiving a first delay signal, the first delay signal is generated based on a clock signal after a preset delay, and the second switching transistor is a P-type transistor; a first control transistor, a first terminal coupled to the second terminal of the second switching transistor, a second terminal coupled to the control end of the second control transistor, and the control end for receiving a sampling signal; a first terminal of the second control transistor is coupled to the second terminal of the second switching transistor, a second terminal coupled to the control end of the first control transistor, and the control end is used to receive a complementary sampling signal.

[0013] For example, the compensation circuit includes: a third control transistor, a first terminal of which is coupled to the control end of the fourth control transistor, and the control end is used to receive a sampling signal; a first terminal of the second control transistor is coupled to the control end of the third control transistor, and the control end is used to receive a complementary sampling signal; a third switching transistor, a first terminal of which is coupled to the second terminals of the third control transistor and the fourth control transistor, a second terminal of which is used to receive a second power supply signal, and a control end of which is used to receive a second delay signal, and the second delay signal is generated based on the clock signal after a preset delay.

[0014] For example, a balanced feedback circuit includes: a fourth switching transistor, a first terminal for receiving a first power supply signal, a control terminal for receiving a balanced clock signal, and the balanced clock signal is used to drive the balanced feedback circuit; a first feedback control transistor, a first terminal coupled to the second terminal of the fourth switching transistor, and a control terminal for receiving a complementary data signal output by a previous-level data buffer unit; a first adjustment transistor group, including a plurality of first adjustment transistors connected in parallel, each first adjustment transistor being controlled based on a first adjustment signal group to change the conduction degree of the first adjustment transistor group; wherein the first terminal of the first adjustment transistor group is coupled to the second terminal of the first feedback control transistor, and the second terminal is coupled to the first terminal of the first N-type transistor; a second feedback control transistor, a first terminal coupled to the second terminal of the fourth switching transistor, and a control terminal for receiving a data signal output by the previous-level data buffer unit; a second adjustment transistor group, including a plurality of second adjustment transistors connected in parallel, each second adjustment transistor being controlled based on a second adjustment signal group to change the conduction degree of the first adjustment transistor group; wherein the first terminal of the second adjustment transistor group is coupled to the second terminal of the second feedback control transistor, and the second terminal is coupled to the first terminal of the second N-type transistor.

[0015] For example, the width-to-length ratio of the first adjustment transistor in the first adjustment transistor group is greater than the width-to-length ratio of the first feedback control transistor, and the width-to-length ratio of the adjustment transistor in the second adjustment transistor group is greater than the width-to-length ratio of the second feedback control transistor.

[0016] For example, the width-to-length ratios of the adjustment transistors in the first adjustment transistor group are sequentially set to be 2 times.

[0017] For example, the balanced feedback circuit also includes: a third feedback control transistor, a first terminal coupled to the second terminal of the first adjustment transistor group, and a control end for receiving a complementary data signal output by the previous-level data buffer unit; a fourth feedback control transistor, a first terminal coupled to the second terminal of the second adjustment transistor group, and a control end for receiving a data signal output by the previous-level data buffer unit; wherein the third feedback control transistor and the first feedback control transistor are of different transistor types, and the fourth feedback control transistor and the second feedback control transistor are of different transistor types; a fifth switching transistor, a first terminal coupled to the second terminals of the third feedback control transistor and the fourth feedback control transistor, a second terminal for receiving a second power supply signal, and a control end for receiving a balanced clock signal, and the balanced clock signal is used to drive the balanced feedback circuit; wherein the power supply voltage provided by the first power supply signal is greater than the power supply voltage provided by the second power supply signal.

[0018] For example, the width-to-length ratio of the third feedback control transistor is smaller than that of the first feedback control transistor, and the width-to-length ratio of the fourth feedback control transistor is smaller than that of the second feedback control transistor.

[0019] For example, a balanced feedback circuit includes: a first adjustment transistor group, including multiple parallel adjustment transistors, each adjustment transistor is controlled based on a first adjustment signal group to change the conduction degree of the first adjustment transistor group; wherein the first terminal of the first adjustment transistor group is coupled to the first terminal of the first N-type transistor; a second adjustment transistor group, including multiple parallel adjustment transistors, each adjustment transistor is controlled based on a second adjustment signal group to change the conduction degree of the first adjustment transistor group; wherein the first terminal of the second adjustment transistor group is coupled to the first terminal of the second N-type transistor; a third feedback control transistor, the first terminal of which is coupled to the second terminal of the first adjustment transistor group, and the control terminal is used to receive a complementary data signal output by a previous-level data buffer unit; a fourth feedback control transistor, the first terminal of which is coupled to the second terminal of the second adjustment transistor group, and the control terminal is used to receive a data signal output by a previous-level data buffer unit; a fifth switching transistor, the first terminal of which is coupled to the second terminals of the third feedback control transistor and the fourth feedback control transistor, the second terminal of which is used to receive a second power supply signal, and the control terminal is used to receive a balanced clock signal, and the balanced clock signal is used to drive the balanced feedback circuit.

[0020] For example, the width-to-length ratio of the adjustment transistors in the first adjustment transistor group is greater than the width-to-length ratio of the third feedback control transistor, and the width-to-length ratio of the adjustment transistors in the second adjustment transistor group is greater than the width-to-length ratio of the fourth feedback control transistor.

[0021] Another embodiment of the present disclosure further provides a memory including the data buffer structure provided by the above embodiment, so as to optimize the critical comparison time after the DFE is turned on, thereby improving the symmetry of the digital eye diagram. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 A schematic diagram of a common data buffer structure provided in an embodiment of the present disclosure;

[0024] Figure 2 A schematic diagram of the principle of obtaining the critical comparison time provided by an embodiment of the present disclosure;

[0025] Figure 3A schematic diagram of a data buffer structure provided in one embodiment of the present disclosure;

[0026] Figure 4 A schematic diagram of the structure of each data buffer unit provided in an embodiment of the present disclosure;

[0027] Figure 5 A schematic structural diagram of a compensation circuit based on a first sampling circuit provided in one embodiment of the present disclosure;

[0028] Figure 6 A schematic structural diagram of another compensation circuit based on the first sampling circuit provided in an embodiment of the present disclosure;

[0029] Figure 7 A schematic structural diagram of an independently arranged compensation circuit provided in one embodiment of the present disclosure;

[0030] Figure 8 A schematic structural diagram of another independently arranged compensation circuit provided in one embodiment of the present disclosure;

[0031] Figure 9 A schematic structural diagram of a balanced feedback circuit controlled by a P-type transistor provided in one embodiment of the present disclosure;

[0032] Figure 10 A schematic diagram of the structure of a balanced feedback circuit using P-type transistors and N-type transistors for simultaneous control according to an embodiment of the present disclosure;

[0033] Figure 11 A schematic structural diagram of a balanced feedback circuit controlled by an N-type transistor provided in one embodiment of the present disclosure;

[0034] Figure 12 This is a schematic structural diagram of a second sampling circuit provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] An embodiment of the present disclosure provides a data buffer structure to optimize the critical comparison time after DFE is turned on, thereby improving the symmetry of the digital eye diagram.

[0036] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0037] Figure 1A schematic diagram of a common data buffer structure provided in this embodiment is shown. Figure 2 A schematic diagram of the principle of obtaining the critical comparison time provided in this embodiment, Figure 3 A schematic diagram of the data buffer structure provided in this embodiment. Figure 4 A schematic diagram of the structure of each data buffer unit provided in this embodiment, Figure 5 A schematic diagram of a compensation circuit based on a first sampling circuit provided in this embodiment is shown in FIG. Figure 6 This is a schematic diagram of the structure of another compensation circuit provided by the present embodiment based on the first sampling circuit. Figure 7 This is a schematic diagram of the structure of an independently set compensation circuit provided in this embodiment. Figure 8 This is a schematic diagram of the structure of another independently arranged compensation circuit provided in this embodiment. Figure 9 This is a schematic diagram of the structure of the balanced feedback circuit controlled by P-type transistors provided in this embodiment. Figure 10 This is a schematic diagram of the structure of the balanced feedback circuit provided by this embodiment using P-type transistors and N-type transistors for simultaneous control. Figure 11 This is a schematic diagram of the structure of the balanced feedback circuit controlled by N-type transistors provided in this embodiment. Figure 12 This is a schematic diagram of the structure of the second sampling circuit provided in this embodiment. The data buffer structure provided in this embodiment is described in detail below in conjunction with the accompanying drawings, as follows:

[0038] For common data buffer structures, refer to Figure 1 The data buffer structure generally includes: a first sampling structure 10, a DFE structure 30 and a second sampling structure 20; wherein the working principles of the first sampling structure 10 and the second sampling structure 20 are as follows:

[0039] When the data to be sampled is "1", that is, the input signal DQ sampled by the first sampling structure 10 is greater than the reference signal Vref, the turn-on degree of the P-type transistor receiving the input signal DQ is less than the turn-on degree of the P-type transistor receiving the reference signal Vref, so that the sampling signal Sn is less than the complementary sampling signal Sp. The sampling signal Sn and the complementary sampling signal Sp serve as driving signals for the N-type transistors in the second sampling structure 20. The sampling signal Sn is less than the complementary sampling signal Sp, so that the intermediate signal Stg2_P is greater than the complementary intermediate signal Stg2_N, and further, the data signal Fbp is greater than the complementary data signal Fbn. The data signal Fbp serves as the positive phase output terminal of the second sampling structure 20 and outputs a high level, while the complementary data signal Fbn serves as the negative phase output terminal of the second sampling structure 20 and outputs a low level.

[0040] When the data to be sampled is "0", that is, the input signal DQ sampled by the first sampling structure 10 is less than the reference signal Vref, the turn-on degree of the P-type transistor receiving the input signal DQ is greater than the turn-on degree of the P-type transistor receiving the reference signal Vref, so that the sampling signal Sn is greater than the complementary sampling signal Sp. The sampling signal Sn and the complementary sampling signal Sp serve as driving signals for the N-type transistors in the second sampling structure 20. The sampling signal Sn is greater than the complementary sampling signal Sp, so that the intermediate signal Stg2_P is less than the complementary intermediate signal Stg2_N, and further, the data signal Fbp is less than the complementary data signal Fbn. The data signal Fbp serves as the positive phase output terminal of the second sampling structure 20 and outputs a low level. The complementary data signal Fbn serves as the negative phase output terminal of the second sampling structure 20 and outputs a high level.

[0041] The operating principle of the DFE structure 30 is as follows: the P-type transistors controlled by the drive control signals Q1 and Q2 are used to adjust the adjustment amplitudes of the sampling signal Sn and the complementary sampling signal Sp. DfeFbn and DfeFbp serve as the complementary data signal Fbn and data signal Fbp output by the previous data buffer structure (the data signal Fbp output by the previous data buffer structure serves as the DfeFbp input of the DFE structure 30 of the current data buffer structure, and the complementary data signal Fbn output by the previous data buffer structure serves as the DfeFbn input of the DFE structure 30 of the current data buffer structure), and are used for feedback adjustment of the current data.

[0042] Specifically, if the DFE structure 30 is in the on state, when the previous data is "1", the output data signal Fbp is greater than the complementary data signal Fbn. For the current data buffer structure, DfeFbp>DfeFbn. Based on the conduction principle of P-type transistors, it can be seen that the increase in the sampling signal Sn is greater than the increase in the complementary sampling signal Sp. In other words, the DFE structure 30 can be regarded as compensating the sampling signal Sn. When the previous data is "0", the output data signal Fbp is less than the complementary data signal Fbn. For the current data buffer structure, DfeFbp<DfeFbn. Based on the conduction principle of P-type transistors, it can be seen that the increase in the complementary sampling signal Sp is greater than the increase in the sampling signal Sn. In other words, the DFE structure 30 can be regarded as compensating the complementary sampling signal Sp.

[0043] For critical comparison times, refer to Figure 2In the rising phase of the input signal DQ, that is, in the process of outputting data "1", in phase (1), the input signal DQ is less than the reference signal Vref. At this time, the charging speed of the sampling signal Sn is greater than the charging speed of the complementary sampling signal Sp. Correspondingly, the discharging speed of the intermediate signal Stg2_P is greater than the discharging speed of the complementary intermediate signal Stg2_N. In phase (2), the input signal DQ is greater than the reference signal Vref. At this time, the charging speed of the sampling signal Sn is less than the charging speed of the complementary sampling signal Sp. Correspondingly, the discharging speed of the intermediate signal Stg2_P is less than the discharging speed of the complementary intermediate signal Stg2_N. ; In the falling phase of the input signal DQ, that is, in the process of outputting data "0", in phase (3), the input signal DQ is greater than the reference signal Vref. At this time, the charging speed of the sampling signal Sn is less than the charging speed of the complementary sampling signal Sp. Correspondingly, the discharging speed of the intermediate signal Stg2_P is less than the discharging speed of the complementary intermediate signal Stg2_N. In phase (4), the input signal DQ is less than the reference signal Vref. At this time, the charging speed of the sampling signal Sn is greater than the charging speed of the complementary sampling signal Sp. Correspondingly, the discharging speed of the intermediate signal Stg2_P is greater than the discharging speed of the complementary intermediate signal Stg2_N.

[0044] When the reference signal Vref is equal to the input signal DQ, the difference between the sampling signal Sn and the complementary sampling signal Sp reaches its maximum. When the areas of the two figures formed by the reference signal Vref, the input signal DQ and the vertical line at the current time are equal (that is, when the integrals are equal), the complementary sampling signal Sp = the sampling signal Sn. Similarly, when the complementary sampling signal Sp and the sampling signal Sn are equal, the difference between the intermediate signal Stg2_P and the complementary intermediate signal Stg2_N reaches its maximum. When the areas of the two figures formed by the sampling signal Sn, the complementary sampling signal Sp and the vertical line at the current time are equal (that is, when the integrals are equal), the intermediate signal Stg2_P = the complementary intermediate signal Stg2_N.

[0045] The critical comparison time is obtained based on a time interval t0 between a time node at which the intermediate signal Stg2_P equals the complementary intermediate signal Stg2_N and a transition node of a clock signal, wherein the clock signal is used to control the enabling of the data buffer structure.

[0046] Furthermore, based on the above discussion, it can be seen that when data transitions from "0" to "1", the DFE structure 30 charges the complementary sampling signal Sp. The complementary sampling signal Sp is derived based on the reference signal Vref, which serves as a reference voltage. Changing the magnitude of the complementary sampling signal Sp is equivalent to adjusting the magnitude of the reference signal Vref, which is equivalent to shortening the critical comparison time. When data transitions from "1" to "0", the DFE structure 30 charges the sampling signal Sn. However, because the input signal DQ is a variable and thus plays a dominant role in the state of the sampling signal Sn, the compensation of the DFE structure 30 has little impact on the state of the sampling signal Sn, and thus has little impact on the critical comparison time. Therefore, when the DFE is enabled, the critical comparison time exhibits asymmetric variations, resulting in increased asymmetry in the digital eye diagram.

[0047] refer to Figure 3 , the data buffer structure provided in this embodiment includes: a plurality of cascaded data buffer units 100, each data buffer unit 100 is used to output a data signal Fbp and a complementary data signal Fbn; Figure 4 Each data buffer unit 100 includes:

[0048] The first sampling circuit 101 is configured to generate a sampling signal Sn and a complementary sampling signal Sp based on an input signal DQ and a reference signal Vref; wherein, if the potential of the input signal DQ is greater than the potential of the reference signal Vref, the potential of the generated complementary sampling signal Sp is greater than the potential of the sampling signal Sn; and if the potential of the reference signal Vref is greater than the potential of the input signal DQ, the potential of the generated sampling signal Sn is greater than the potential of the complementary sampling signal Sp.

[0049] The reference signal Vref, that is, the reference voltage inside the memory, is used to cooperate with the input signal DQ to identify whether the input signal DQ is a high level or a low level. Specifically, when the input signal DQ is greater than the reference signal Vref, the input signal DQ is a high level; when the input signal DQ is less than the reference signal Vref, the input signal DQ is a low level.

[0050] The second sampling circuit 102 is configured to generate a data signal Fbp and a complementary data signal Fbn based on the sampling signal Sn and the complementary sampling signal Sp; wherein, if the potential of the sampling signal is greater than the potential of the complementary sampling signal, the potential of the generated complementary data signal is greater than the potential of the data signal; if the potential of the complementary sampling signal is greater than the potential of the sampling signal, the potential of the generated data signal is greater than the potential of the complementary data signal.

[0051] The equalization feedback circuit 103 is configured to feedback the regulated sampling signal Sn and the complementary sampling signal Sp based on the data signal Fbp and the complementary data signal Fbn outputted by the previous stage data buffer unit 100 to reduce inter-symbol interference between adjacent input signals DQ.

[0052] The compensation circuit 104 is connected to the first sampling circuit 101 and is configured to increase the change rate of the sampling signal Sn and the complementary sampling signal Sp.

[0053] The compensation circuit 104 increases the change rate of the sampling signal Sn and the complementary sampling signal Sp, referring to Figure 2 It can be seen that as the changing rates of the sampling signal Sn and the complementary sampling signal Sp increase, the changing rates of the intermediate signal Stg2_P and the complementary intermediate signal Stg2_N also increase accordingly. That is, the time node at which the intermediate signal Stg2_P equals the complementary intermediate signal Stg2_N is obtained is advanced, and the critical comparison time is reduced overall.

[0054] As previously mentioned, when data transitions from "0" to "1," the equalizing feedback circuit 103 charges the complementary sampling signal Sp, which is derived from the reference signal Vref. Changing the magnitude of the complementary sampling signal Sp is equivalent to adjusting the magnitude of the reference signal Vref, which shortens the critical comparison time. When data transitions from "1" to "0," the equalizing feedback circuit 103 charges the sampling signal Sn, which is derived from DQ. However, because the input signal DQ is a variable and dominates the state of the sampling signal Sn, the compensation of the equalizing feedback circuit 103 has little impact on the state of the sampling signal Sn, and thus on the critical comparison time. This can cause asymmetric variations in the critical comparison time, leading to asymmetry in the digital eye diagram. Therefore, adding the compensation circuit 104 to the equalizing feedback circuit 103 helps mitigate the asymmetric variations in the critical comparison time, thereby improving the symmetry of the digital eye diagram to a certain extent.

[0055] For the first sampling circuit 101, refer to Figure 5 and Figure 6The first sampling circuit 101 includes: a first switching transistor K1, a first terminal for receiving a first power signal D1, and a control terminal for receiving a clock signal WckN; a first P-type transistor P101, a first terminal coupled to the second terminal of the first switching transistor K1, and a control terminal for receiving an input signal DQ; a second P-type transistor P102, a first terminal coupled to the second terminal of the first switching transistor K1, and a control terminal for receiving a reference signal Vref; a first N-type transistor N101, a first terminal coupled to the second terminal of the first P-type transistor P101 and for outputting a sampling signal Sn, a second terminal for receiving a second power signal D2, and a control terminal for receiving the clock signal WckN; a second N-type transistor N102, a first terminal coupled to the second terminal of the second P-type transistor P102 and for outputting a complementary sampling signal Sp, a second terminal for receiving the second power signal D2, and a control terminal for receiving the clock signal WckN; wherein the power supply voltage provided by the first power supply signal D1 is greater than the power supply voltage provided by the second power supply signal D2.

[0056] In some embodiments, the first power signal D1 uses the internal power voltage Vdd of the memory, and the second power signal D2 uses the internal ground potential Vss of the memory.

[0057] In some embodiments, the compensation circuit 104 is configured based on the first sampling circuit 101, referring to Figure 5 and Figure 6 .

[0058] Specifically, refer to Figure 5 In one example, the compensation circuit 104 includes: a first current compensation transistor Kb1, a first terminal for receiving the third power signal D3, a second terminal coupled to the second terminal of the first switch transistor K1, and a control terminal for receiving a supplementary control signal K, wherein the supplementary control signal K is generated based on the data signal Fbp or the complementary data signal Fbn output by the previous-stage data buffer unit 100, and the power voltage provided by the third power signal D3 is greater than the voltage provided by the second power signal D2. Figure 5 For example, when the supplementary control signal K turns on the first current compensation transistor Kb1 and the first sampling circuit 101 works normally, the first current compensation transistor Kb1 is connected in parallel with the first switch transistor K1, which is equivalent to improving the current driving capability of the first switch transistor K1, so that when the potential of the input signal DQ changes, the current and voltage of the sampling signal Sn can respond faster, that is, the current change rate and voltage change rate of the sampling signal Sn and the complementary sampling signal Sp are increased.

[0059] In addition, for Figure 5For example, in some embodiments, the third power signal D3 may be set using the first power signal D1 , that is, the third power signal D3 also uses the internal power voltage Vdd of the memory.

[0060] refer to Figure 6 In another example, the compensation circuit 104 includes: a second current compensation transistor Kb2, a first terminal coupled to the second terminals of the first N-type transistor N101 and the second N-type transistor N102, a second terminal for receiving the second power signal D2, and a control terminal for receiving a supplementary control signal K, wherein the supplementary control signal K is generated based on the data signal Fbp or the complementary data signal Fbn output by the previous-stage data buffer unit 100. Figure 6 For example, when the supplementary control signal K turns on the second current compensation transistor Kb2 and the first sampling circuit 101 operates normally, the second current compensation transistor Kb2 is connected in series with the first N-type transistor N101 and the second N-type transistor N102, which is equivalent to reducing the current driving capability of the first N-type transistor N101 and the second N-type transistor N102, that is, reducing the pull-down capability of the sampling signal Sn and the complementary sampling signal Sp, while the pull-up capability of the first P-type transistor P101 and the second P-type transistor P102 for the sampling signal Sn and the complementary sampling signal Sp remains unchanged. The current change rate of the sampling signal Sn and the complementary sampling signal Sp is determined based on the pull-up rate and the pull-down rate of the sampling signal Sn and the complementary sampling signal Sp. The pull-up rate of the sampling signal Sn and the complementary sampling signal Sp remains unchanged, and the pull-down rate is reduced, that is, the current change rate of the sampling signal Sn and the complementary sampling signal Sp is increased.

[0061] In some embodiments, the compensation circuit 105 is independently configured. Figure 7 and Figure 8 .

[0062] Specifically, refer to Figure 7 In one example, the compensation circuit 104 includes: a second switch transistor K2, a first terminal for receiving a first power signal D1, a control terminal for receiving a first delayed signal WckdlyN, the first delayed signal being generated based on the clock signal WckN after a preset delay, and the second switch transistor K2 being a P-type transistor; a first control transistor KZ1, a first terminal coupled to the second terminal of the second switch transistor K2, a second terminal coupled to the control terminal of the second control transistor KZ2, and a control terminal for receiving a sampling signal Sn; a second control transistor KZ2, a first terminal coupled to the second terminal of the second switch transistor K2, a second terminal coupled to the control terminal of the first control transistor KZ1, and a control terminal for receiving a complementary sampling signal Sp. Figure 7The circuit shown further amplifies the sampling signal Sn and the complementary sampling signal Sp through the differential amplifier circuit, thereby increasing the voltage change rate of the sampling signal Sn and the complementary sampling signal Sp.

[0063] refer to Figure 8 In one example, the compensation circuit 104 includes: a third control transistor KZ3, a first terminal of which is coupled to the control terminal of the fourth control transistor KZ4, and the control terminal is used to receive the sampling signal Sn; a first terminal of the fourth control transistor KZ4 is coupled to the control terminal of the third control transistor KZ3, and the control terminal is used to receive the complementary sampling signal Sp; a third switch transistor K3, a first terminal of which is coupled to the second terminals of the third control transistor KZ3 and the fourth control transistor KZ4, a second terminal of which is used to receive the second power supply signal D2, and a control terminal of which is used to receive the second delay signal WckdlyN, which is generated based on the clock signal WckN after a preset delay. Figure 8 The circuit shown further amplifies the sampling signal Sn and the complementary sampling signal Sp through the differential amplifier circuit, thereby increasing the voltage change rate of the sampling signal Sn and the complementary sampling signal Sp.

[0064] In some embodiments, it is also possible to combine Figure 7 and Figure 8 The setting of the sampling signal Sn and the complementary sampling signal Sp are adjusted at the same time.

[0065] For the balanced feedback circuit 103, refer to Figure 9 The balanced feedback circuit 103 includes: a fourth switch transistor K4, a first terminal of which is used to receive the first power signal D1, and a control terminal of which is used to receive the balanced clock signal Wck1N, the balanced clock signal Wck1N being used to drive the balanced feedback circuit 103; a first feedback control transistor FK1, a first terminal of which is coupled to the second terminal of the fourth switch transistor K4, and a control terminal of which is used to receive the complementary data signal DfeFbn output by the previous-stage data buffer unit 100; a first adjustment transistor group, including a plurality of first adjustment transistors T1 connected in parallel, each of which is controlled based on the first adjustment signal group Tk1<2:0> to change the conduction degree of the first adjustment transistor group; wherein the first terminal of the first adjustment transistor group is coupled to the second terminal of the first feedback control transistor FK1, and the second terminal is coupled to the first N-type transistor N101 (reference Figure 5) to adjust the sampling signal Sn obtained by the first sampling circuit 101. The second feedback control transistor FK2 has a first terminal coupled to the second terminal of the fourth switch transistor K4, and a control terminal for receiving the data signal DfeFbp output by the previous-stage data buffer unit 100; the second adjustment transistor group includes a plurality of second adjustment transistors T2 connected in parallel, each of which is controlled based on the second adjustment signal group Tk2<2:0> to change the conduction degree of the second adjustment transistor group; wherein the first terminal of the second adjustment transistor group is coupled to the second terminal of the second feedback control transistor FK2, and the second terminal is coupled to the second N-type transistor N102 (reference Figure 5 ) to adjust the sampling signal Sp obtained by the first sampling circuit 101.

[0066] It should be noted that, for the balanced clock signal Wck1N, the timing of the balanced clock signal Wck1N received by the balanced feedback circuit 103 included in different data buffer structures is different. The timing of the balanced clock signal Wck1N needs to correspond to the timing of the corresponding first sampling circuit 101 receiving the data signal DQ, and the timing of the data buffer structure receiving the feedback signal (DfeFbn or DfeFbp) receiving the data signal DQ should be one clock cycle later than the timing of the data buffer structure generating the feedback signal (Fbn or Fbp) receiving the data signal DQ, that is, 1UI.

[0067] It should be noted that Figure 9 In the example, the first adjustment transistor group includes three first adjustment transistors T1 and the second adjustment transistor group includes three second adjustment transistors T2. This does not constitute a limitation on the balanced feedback circuit 103. In a specific application, the number of the first adjustment transistors T1 and the number of the second adjustment transistors T2 can be set to r, and r can be set to any integer. Accordingly, the first adjustment signal group is Tk1. <r:0>, the second adjustment signal group is Tk2 <r:0>It should be noted that, in a specific application, the number of the first adjustment transistor T1 and the second adjustment transistor T2 can be set to be equal, or can be set to be unequal.

[0068] In some embodiments, the width-to-length ratio of the first adjustment transistor T1 in the first adjustment transistor group is greater than the width-to-length ratio of the first feedback control transistor FK1, and the width-to-length ratio of the second adjustment transistor T2 in the second adjustment transistor group is greater than the width-to-length ratio of the second feedback control transistor FK2. It is known to those skilled in the art that for transistors with a large width-to-length ratio, the transistors have a stronger ability to conduct charge at the same turn-on level; therefore, when the first adjustment transistor group is connected in series with the first feedback control transistor FK1, the conduction capability of the first adjustment transistor group has a greater impact on the conduction capability of the branch, so that the first adjustment signal group is used to adjust the conduction capability of the branch circuit. <r:0>Adjust the conduction capacity of the first adjustment transistor group, thereby adjusting the adjustment value of the sampling signal Sn; similarly, when the second adjustment transistor group is connected in series with the second feedback control transistor FK2, the conduction capacity of the second adjustment transistor group has a greater impact on the conduction capacity of the branch, so that the second adjustment signal group is Tk2. <r:0>The conduction capability of the second regulating transistor group is adjusted, thereby adjusting the regulation value of the complementary sampling signal Sp.

[0069] In some embodiments, the width-to-length ratio of the first adjustment transistor T1 in the first adjustment transistor group is set to be 2 times, and the width-to-length ratio of the second adjustment transistor T2 in the second adjustment transistor group is set to be 2 times, so as to optimize the adjustment margin of the conduction capability of the first adjustment transistor group and the second adjustment transistor group.

[0070] In some embodiments, reference Figure 10 The balanced feedback circuit 103 further includes: a third feedback control transistor FK3, having a first terminal coupled to the second terminal of the first adjustment transistor group, and a control terminal for receiving the complementary data signal DfeFbp output by the previous-stage data buffer unit 100; a fourth feedback control transistor FK4, having a first terminal coupled to the second terminal of the second adjustment transistor group, and a control terminal for receiving the data signal DfeFbn output by the previous-stage data buffer unit 100; wherein the third feedback control transistor FK3 and the first feedback control transistor FK1 are of different transistor types, and the fourth feedback control transistor FK4 and the second feedback control transistor FK2 are of different transistor types; a fifth switch transistor K5, having a first terminal coupled to the second terminals of the third feedback control transistor FK3 and the fourth feedback control transistor FK4, and a second terminal for receiving the second power supply signal D2; a control terminal for equalizing the clock signal Wck1N, and an equalization enable signal for driving the balanced feedback circuit 103, wherein the power supply voltage provided by the first power supply signal D1 is greater than the power supply voltage provided by the second power supply signal D2.

[0071] Specifically, the first feedback control transistor FK1 and the second feedback control transistor FK2 are P-type transistors, and the third feedback control transistor FK3 and the fourth feedback control transistor FK4 are N-type transistors.

[0072] exist Figure 9 Based on the example, Figure 10 The balanced feedback circuit 103 shown also adjusts the sampling signal Sn and the complementary sampling signal Sp simultaneously through the third feedback control transistor FK3 and the fourth feedback control transistor FK4 of N-type transistors, thereby increasing the balanced amount of the balanced feedback circuit 103 .

[0073] Since the charge and discharge capabilities of NMOS of the same size are stronger than those of PMOS, in order to ensure that the first feedback control transistor FK1 and the second feedback control transistor FK2 regulate the conduction capability of the branch, the width-to-length ratio of the third feedback control transistor FK4 is smaller than that of the first feedback control transistor FK1, and the width-to-length ratio of the fourth feedback control transistor FK4 is smaller than that of the second feedback control transistor FK2.

[0074] In addition, since the charge and discharge capability of NMOS transistors of the same size is stronger than that of PMOS transistors, in some embodiments, the sampling signal Sn and the complementary sampling signal Sp can be adjusted only by the third feedback control transistor FK3 and the fourth feedback control transistor FK4. Figure 11 The balanced feedback circuit 103 includes: a first adjustment transistor group, including a plurality of first adjustment transistors T1 connected in parallel, each of the first adjustment transistors T1 being controlled based on a first adjustment signal group Tk1<2:0> to change the conduction degree of the first adjustment transistor group; wherein a first terminal of the first adjustment transistor group is coupled to a first N-type transistor N101 (reference Figure 5 ) first terminal; a second adjustment transistor group, comprising a plurality of second adjustment transistors T2 connected in parallel, each second adjustment transistor T2 being controlled based on a second adjustment signal group Tk2<2:0> to change the conduction degree of the second adjustment transistor group; wherein the first terminal of the second adjustment transistor group is coupled to the second N-type transistor N102 (reference Figure 5 ) first terminal; a third feedback control transistor FK3, a first terminal coupled to the second terminal of the first adjustment transistor group, a control end for receiving the complementary data signal DfeFbp output by the previous-stage data buffer unit 100; a fourth feedback control transistor FK4, a first terminal coupled to the second terminal of the second adjustment transistor group, a control end for receiving the data signal DfeFbn output by the previous-stage data buffer unit 100; a fifth switching transistor K5, a first terminal coupled to the second terminals of the third feedback control transistor FK3 and the fourth feedback control transistor FK4, a second terminal for receiving the second power supply signal D2, a control end for equalizing the clock signal Wck1N, and the equalizing enable signal for driving the equalizing feedback circuit 103.

[0075] In some embodiments, the width-to-length ratio of the first adjustment transistor T1 in the first adjustment transistor group is greater than the width-to-length ratio of the third feedback control transistor FK3, and the width-to-length ratio of the second adjustment transistor T2 in the second adjustment transistor group is greater than the width-to-length ratio of the fourth feedback control transistor FK4. It is known to those skilled in the art that for transistors with large width-to-length ratios, the transistors have a stronger ability to conduct charge at the same turn-on level; therefore, when the first adjustment transistor group and the third feedback control transistor FK3 are connected in series, the conduction capability of the first adjustment transistor group has a greater impact on the conduction capability of the branch, so that the first adjustment signal group is Tk1. <r:0>Adjust the conduction capacity of the first adjustment transistor group, thereby adjusting the adjustment value of the sampling signal Sn; similarly, when the second adjustment transistor group is connected in series with the fourth feedback control transistor FK4, the conduction capacity of the second adjustment transistor group has a greater impact on the conduction capacity of the branch, so that the second adjustment signal group is Tk2 <r:0>The conduction capability of the second regulating transistor group is adjusted, thereby adjusting the regulation value of the complementary sampling signal Sp.

[0076] It should be noted that for Figure 9 and Figure 10 In some embodiments of the circuit shown, a first enable transistor is further provided on the connection path between the first terminal or the second terminal of the first feedback control transistor FK1, and the control terminal of the first enable transistor is used to receive a first enable signal to enable the source-drain path of the first feedback control transistor FK1 to be turned on based on the first enable signal; similarly, a second enable transistor is further provided on the connection path between the first terminal or the second terminal of the second feedback control transistor FK2, and the control terminal of the second enable transistor is used to receive a second enable signal to enable the source-drain path of the second feedback control transistor FK2 to be turned on based on the second enable signal.

[0077] Correspondingly, for Figure 10 and Figure 11 In some embodiments of the circuit shown, a third enabling transistor is further provided on the connection path between the first terminal or the second terminal of the third feedback control transistor FK3, and the control terminal of the third enabling transistor is used to receive a third enabling signal to enable the compensation path of the third feedback control transistor FK3 to be turned on based on the third enabling signal; similarly, a fourth enabling transistor is further provided on the connection path between the first terminal or the second terminal of the fourth feedback control transistor FK4, and the control terminal of the fourth enabling transistor is used to receive a fourth enabling signal to enable the compensation path of the fourth feedback control transistor FK4 to be turned on based on the fourth enabling signal.

[0078] In some embodiments, the first enable signal and the second enable signal can be set based on the same enable signal, and the third enable signal and the fourth enable signal can be set based on the same enable signal; in some embodiments, the first enable signal, the second enable signal, the third enable signal and the fourth enable signal can be based on the same enable signal.

[0079] For the second sampling circuit 102, refer to Figure 12 The second sampling circuit 102 includes: a third P-type transistor P103, a first terminal for receiving the first power signal D1; a fourth P-type transistor P104, a first terminal for receiving the first power signal D1; a second terminal of the third P-type transistor P103 is coupled to the control terminal of the fourth P-type transistor P104, and is also used to output the data signal Fbp, a second terminal of the fourth P-type transistor P104 is coupled to the control terminal of the third P-type transistor P103, and is also used to output the complementary data signal Fbn; a third N-type transistor N103, a first terminal coupled to the second terminal of the third P-type transistor P103, and a control terminal coupled connected to the second terminal of the fourth P-type transistor P104; the fourth N-type transistor N104, the first terminal is coupled to the second terminal of the fourth P-type transistor P104, and the control end is coupled to the second terminal of the third P-type transistor P103; the fifth N-type transistor N105, the first terminal is coupled to the second terminal of the third N-type transistor N103, the second terminal is used to receive the second power supply signal D2, and the control end is used to receive the sampling signal Sn; the sixth N-type transistor N106, the first terminal is coupled to the second terminal of the fourth N-type transistor N104, the second terminal is used to receive the second power supply signal D2, and the control end is used to receive the complementary sampling signal Sp.

[0080] In some embodiments, the second sampling circuit further includes: a fifth P-type transistor P105, a first terminal for receiving the first power supply signal D1, a second terminal connected to the second terminal of the third P-type transistor P103, and a control terminal for receiving the inverted signal Wck of the enable signal WckN; a sixth P-type transistor P106, a first terminal for receiving the first power supply signal D1, a second terminal connected to the second terminal of the fourth P-type transistor P104, and a control terminal for receiving the inverted signal Wck of the enable signal WckN.

[0081] For the data buffer structure provided in this embodiment,

[0082] The compensation circuit 104 increases the change rate of the sampling signal Sn and the complementary sampling signal Sp, referring to Figure 2 It can be seen that as the changing rates of the sampling signal Sn and the complementary sampling signal Sp increase, the changing rates of the intermediate signal Stg2_P and the complementary intermediate signal Stg2_N also increase accordingly. That is, the time node at which the intermediate signal Stg2_P equals the complementary intermediate signal Stg2_N is obtained is advanced, and the critical comparison time is reduced overall.

[0083] As previously mentioned, when data transitions from "0" to "1," the equalizing feedback circuit 103 charges the complementary sampling signal Sp, which is derived from the reference signal Vref. Changing the magnitude of the complementary sampling signal Sp is equivalent to adjusting the magnitude of the reference signal Vref, which shortens the critical comparison time. When data transitions from "1" to "0," the equalizing feedback circuit 103 charges the sampling signal Sn, which is derived from DQ. However, because the input signal DQ is a variable and dominates the state of the sampling signal Sn, the compensation performed by the equalizing feedback circuit 103 has little impact on the state of the sampling signal Sn, and thus on the critical comparison time. This can cause asymmetric variations in the critical comparison time, leading to asymmetry in the digital eye diagram. Therefore, adding the compensation circuit 104 to the equalizing feedback circuit 103 helps mitigate the asymmetric variations in the critical comparison time, thereby improving the symmetry of the digital eye diagram to a certain extent.

[0084] It should be noted that the features disclosed in the data buffer structure provided in the above embodiments can be arbitrarily combined without conflict to obtain a new data buffer structure embodiment.

[0085] Another embodiment of the present disclosure provides a memory including the data buffer structure provided by the above embodiment, so as to optimize the critical comparison time after the DFE is turned on, thereby improving the symmetry of the digital eye diagram.

[0086] Specifically, for the data buffer structure, increasing the change rate of the sampling signal and the complementary sampling signal through the compensation circuit is equivalent to shortening the critical comparison time. Therefore, after the compensation circuit is added and the equalization feedback circuit is turned on, the degree of asymmetric change in the critical comparison time is reduced, thereby improving the symmetry of the digital eye diagram to a certain extent.

[0087] It should be noted that the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphic double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0088] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A data buffer structure, characterized in that: include: A plurality of cascaded data buffer units, each of the data buffer units comprising: a first sampling circuit configured to generate a sampling signal and a complementary sampling signal based on an input signal and a reference signal; wherein, if the potential of the input signal is greater than the potential of the reference signal, the potential of the generated complementary sampling signal is greater than the potential of the sampling signal; and if the potential of the reference signal is greater than the potential of the input signal, the potential of the generated sampling signal is greater than the potential of the complementary sampling signal; a second sampling circuit configured to generate a data signal and a complementary data signal based on the sampling signal and the complementary sampling signal; wherein, if the potential of the sampling signal is greater than the potential of the complementary sampling signal, the potential of the generated complementary data signal is greater than the potential of the data signal; and if the potential of the complementary sampling signal is greater than the potential of the sampling signal, the potential of the generated data signal is greater than the potential of the complementary data signal; an equalization feedback circuit configured to, based on the data signal and the complementary data signal output by the data buffer unit of the previous stage, feedback-adjust the sampling signal and the complementary sampling signal to reduce inter-symbol interference between adjacent input signals; a compensation circuit, connected to the first sampling circuit, and configured to increase a change rate of the sampling signal and the complementary sampling signal; The first sampling circuit includes: a first switching transistor, a first terminal for receiving a first power supply signal, and a control terminal for receiving a clock signal; a first P-type transistor, a first terminal coupled to the second terminal of the first switching transistor, and a control terminal for receiving the input signal; a second P-type transistor, a first terminal coupled to the second terminal of the first switching transistor, and a control terminal for receiving the reference signal; a first N-type transistor, a first terminal coupled to the second terminal of the first P-type transistor and configured to output the sampling signal, a second terminal for receiving a second power supply signal, and a control terminal for receiving the clock signal; a second N-type transistor, a first terminal coupled to the second terminal of the second P-type transistor and configured to output the complementary sampling signal, a second terminal for receiving the second power supply signal, and a control terminal for receiving the clock signal; wherein a power supply voltage provided by the first power supply signal is greater than a power supply voltage provided by the second power supply signal; The compensation circuit includes: a first current compensation transistor, a first terminal for receiving a third power supply signal, a second terminal coupled to the second terminal of the first switching transistor, and a control terminal for receiving a supplementary control signal; wherein the supplementary control signal is generated based on the data signal or the complementary data signal output by the data buffer unit of the previous stage, and the power supply voltage provided by the third power supply signal is greater than the power supply voltage provided by the second power supply signal; and / or, The first sampling circuit includes: a first switching transistor, a first terminal for receiving a first power supply signal, and a control terminal for receiving a clock signal; a first P-type transistor, a first terminal coupled to the second terminal of the first switching transistor, and a control terminal for receiving the input signal; a second P-type transistor, a first terminal coupled to the second terminal of the first switching transistor, and a control terminal for receiving the reference signal; a first N-type transistor, a first terminal coupled to the second terminal of the first P-type transistor and configured to output the sampling signal, a second terminal for receiving a second power supply signal, and a control terminal for receiving the clock signal; a second N-type transistor, a first terminal coupled to the second terminal of the second P-type transistor and configured to output the complementary sampling signal, a second terminal for receiving the second power supply signal, and a control terminal for receiving the clock signal; wherein a power supply voltage provided by the first power supply signal is greater than a power supply voltage provided by the second power supply signal; The compensation circuit includes: a second current compensation transistor, a first terminal coupled to the second terminals of the first N-type transistor and the second N-type transistor, a second terminal for receiving the second power supply signal, and a control terminal for receiving a supplementary control signal; wherein the supplementary control signal is generated based on the data signal and the complementary data signal output by the data buffer unit of the previous stage; and / or, The compensation circuit includes: a second switching transistor, a first terminal for receiving a first power supply signal, a control terminal for receiving a first delayed signal, the first delayed signal being generated based on a clock signal after a preset delay, the second switching transistor being a P-type transistor; a first control transistor, a first terminal coupled to the second terminal of the second switching transistor, a second terminal coupled to the control terminal of the second control transistor, the control terminal for receiving the sampling signal; a first terminal of the second control transistor coupled to the second terminal of the second switching transistor, a second terminal coupled to the control terminal of the first control transistor, the control terminal for receiving the complementary sampling signal; and / or, The compensation circuit includes: a third control transistor, a first terminal of which is coupled to the control terminal of a fourth control transistor, the control terminal being used to receive the sampling signal; a first terminal of the fourth control transistor is coupled to the control terminal of the third control transistor, the control terminal being used to receive a complementary sampling signal; and a third switching transistor, a first terminal of which is coupled to the second terminals of the third control transistor and the fourth control transistor, a second terminal being used to receive a second power supply signal, and a control terminal being used to receive a second delayed signal, the second delayed signal being generated based on a clock signal after a preset delay.

2. A data buffer structure, characterized in that: include: A plurality of cascaded data buffer units, each of the data buffer units comprising: a first sampling circuit configured to generate a sampling signal and a complementary sampling signal based on an input signal and a reference signal; wherein, if the potential of the input signal is greater than the potential of the reference signal, the potential of the generated complementary sampling signal is greater than the potential of the sampling signal; and if the potential of the reference signal is greater than the potential of the input signal, the potential of the generated sampling signal is greater than the potential of the complementary sampling signal; a second sampling circuit configured to generate a data signal and a complementary data signal based on the sampling signal and the complementary sampling signal; wherein, if the potential of the sampling signal is greater than the potential of the complementary sampling signal, the potential of the generated complementary data signal is greater than the potential of the data signal; and if the potential of the complementary sampling signal is greater than the potential of the sampling signal, the potential of the generated data signal is greater than the potential of the complementary data signal; an equalization feedback circuit configured to, based on the data signal and the complementary data signal output by the data buffer unit of the previous stage, feedback-adjust the sampling signal and the complementary sampling signal to reduce inter-symbol interference between adjacent input signals; a compensation circuit, connected to the first sampling circuit, and configured to increase a change rate of the sampling signal and the complementary sampling signal; The first sampling circuit includes: a first switching transistor, a first terminal for receiving a first power supply signal, and a control terminal for receiving a clock signal; a first P-type transistor, a first terminal coupled to the second terminal of the first switching transistor, and a control terminal for receiving the input signal; a second P-type transistor, a first terminal coupled to the second terminal of the first switching transistor, and a control terminal for receiving the reference signal; a first N-type transistor, a first terminal coupled to the second terminal of the first P-type transistor and configured to output the sampling signal, a second terminal for receiving a second power supply signal, and a control terminal for receiving the clock signal; a second N-type transistor, a first terminal coupled to the second terminal of the second P-type transistor and configured to output the complementary sampling signal, a second terminal for receiving the second power supply signal, and a control terminal for receiving the clock signal; wherein a power supply voltage provided by the first power supply signal is greater than a power supply voltage provided by the second power supply signal; Wherein, the balanced feedback circuit includes: a fourth switch transistor, a first terminal for receiving a first power supply signal, and a control terminal for receiving a balanced clock signal, wherein the balanced clock signal is used to drive the balanced feedback circuit; a first feedback control transistor, a first terminal of which is coupled to the second terminal of the fourth switch transistor, and a control terminal of which is used to receive the complementary data signal output by the data buffer unit of the previous stage; a first adjustment transistor group, comprising a plurality of first adjustment transistors connected in parallel, each of the first adjustment transistors being controlled based on a first adjustment signal group to change a conduction degree of the first adjustment transistor group; Wherein, the first terminal of the first adjustment transistor group is coupled to the second terminal of the first feedback control transistor, and the second terminal is coupled to the first terminal of the first N-type transistor; a second feedback control transistor, a first terminal of which is coupled to the second terminal of the fourth switch transistor, and a control terminal of which is used to receive the data signal output by the data buffer unit of the previous stage; a second adjustment transistor group, comprising a plurality of second adjustment transistors connected in parallel, each of the second adjustment transistors being controlled based on a second adjustment signal group to change a conduction degree of the first adjustment transistor group; The first terminal of the second adjustment transistor group is coupled to the second terminal of the second feedback control transistor, and the second terminal of the second adjustment transistor group is coupled to the first terminal of the second N-type transistor.

3. The data buffer structure according to claim 2, wherein: The width-to-length ratio of the first adjustment transistor in the first adjustment transistor group is greater than the width-to-length ratio of the first feedback control transistor, and the width-to-length ratio of the adjustment transistor in the second adjustment transistor group is greater than the width-to-length ratio of the second feedback control transistor.

4. The data buffer structure according to claim 2 or 3, characterized in that: The width-to-length ratios of the adjustment transistors in the first adjustment transistor group are sequentially set to be 2 times.

5. The data buffer structure according to claim 2, wherein: The balanced feedback circuit further includes: a third feedback control transistor, a first terminal of which is coupled to the second terminal of the first adjustment transistor group, and a control terminal of which is used to receive the complementary data signal output by the data buffer unit of the previous stage; a fourth feedback control transistor, a first terminal coupled to the second terminal of the second adjustment transistor group, and a control end for receiving the data signal output by the data buffer unit of the previous stage; The third feedback control transistor and the first feedback control transistor are of different transistor types, and the fourth feedback control transistor and the second feedback control transistor are of different transistor types; a fifth switch transistor, having a first terminal coupled to the second terminals of the third feedback control transistor and the fourth feedback control transistor, a second terminal for receiving a second power supply signal, and a control terminal for receiving a balanced clock signal, wherein the balanced clock signal is used to drive the balanced feedback circuit; The power voltage provided by the first power signal is greater than the power voltage provided by the second power signal.

6. The data buffer structure according to claim 5, characterized in that: The width-to-length ratio of the third feedback control transistor is smaller than that of the first feedback control transistor, and the width-to-length ratio of the fourth feedback control transistor is smaller than that of the second feedback control transistor.

7. A data buffer structure, characterized in that: include: A plurality of cascaded data buffer units, each of the data buffer units comprising: a first sampling circuit configured to generate a sampling signal and a complementary sampling signal based on an input signal and a reference signal; wherein, if the potential of the input signal is greater than the potential of the reference signal, the potential of the generated complementary sampling signal is greater than the potential of the sampling signal; and if the potential of the reference signal is greater than the potential of the input signal, the potential of the generated sampling signal is greater than the potential of the complementary sampling signal; a second sampling circuit configured to generate a data signal and a complementary data signal based on the sampling signal and the complementary sampling signal; wherein, if the potential of the sampling signal is greater than the potential of the complementary sampling signal, the potential of the generated complementary data signal is greater than the potential of the data signal; and if the potential of the complementary sampling signal is greater than the potential of the sampling signal, the potential of the generated data signal is greater than the potential of the complementary data signal; an equalization feedback circuit configured to, based on the data signal and the complementary data signal output by the data buffer unit of the previous stage, feedback-adjust the sampling signal and the complementary sampling signal to reduce inter-symbol interference between adjacent input signals; a compensation circuit, connected to the first sampling circuit, and configured to increase a change rate of the sampling signal and the complementary sampling signal; The first sampling circuit includes: a first switching transistor, a first terminal for receiving a first power supply signal, and a control terminal for receiving a clock signal; a first P-type transistor, a first terminal coupled to the second terminal of the first switching transistor, and a control terminal for receiving the input signal; a second P-type transistor, a first terminal coupled to the second terminal of the first switching transistor, and a control terminal for receiving the reference signal; a first N-type transistor, a first terminal coupled to the second terminal of the first P-type transistor and configured to output the sampling signal, a second terminal for receiving a second power supply signal, and a control terminal for receiving the clock signal; a second N-type transistor, a first terminal coupled to the second terminal of the second P-type transistor and configured to output the complementary sampling signal, a second terminal for receiving the second power supply signal, and a control terminal for receiving the clock signal; wherein a power supply voltage provided by the first power supply signal is greater than a power supply voltage provided by the second power supply signal; Wherein, the balanced feedback circuit includes: a first adjustment transistor group, comprising a plurality of adjustment transistors connected in parallel, each adjustment transistor being controlled based on a first adjustment signal group to change a conduction degree of the first adjustment transistor group; Wherein, the first terminal of the first adjustment transistor group is coupled to the first terminal of the first N-type transistor; a second adjustment transistor group, comprising a plurality of adjustment transistors connected in parallel, each adjustment transistor being controlled based on a second adjustment signal group to change a conduction degree of the first adjustment transistor group; Wherein, the first terminal of the second adjustment transistor group is coupled to the first terminal of the second N-type transistor; a third feedback control transistor, a first terminal of which is coupled to the second terminal of the first adjustment transistor group, and a control terminal of which is used to receive the complementary data signal output by the data buffer unit of the previous stage; a fourth feedback control transistor, a first terminal of which is coupled to the second terminal of the second adjustment transistor group, and a control terminal of which is used to receive the data signal output by the data buffer unit of the previous stage; A fifth switching transistor has a first terminal coupled to the second terminals of the third feedback control transistor and the fourth feedback control transistor, a second terminal for receiving a second power supply signal, and a control terminal for receiving a balanced clock signal, wherein the balanced clock signal is used to drive the balanced feedback circuit.

8. The data buffer structure according to claim 7, characterized in that: The width-to-length ratio of the adjustment transistors in the first adjustment transistor group is greater than the width-to-length ratio of the third feedback control transistor, and the width-to-length ratio of the adjustment transistors in the second adjustment transistor group is greater than the width-to-length ratio of the fourth feedback control transistor.

9. A memory, characterized in that: The data buffer structure includes any one of claims 1 to 8.

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