Semiconductor gate structure preparation method and semiconductor structure

Abstract

The present application discloses a method for preparing a semiconductor gate structure and a semiconductor structure. The method for preparing a semiconductor gate structure includes: providing a substrate and forming gate polysilicon on the substrate, and during the formation of the gate polysilicon, sinking the well regions on both sides of the gate polysilicon; forming a sidewall structure on both sides of the gate polysilicon along the channel length direction of the semiconductor, wherein the sidewall structure includes a sacrificial layer and a sidewall layer formed outside the sacrificial layer; removing the gate polysilicon and the sacrificial layer to form a first groove, and during the removal of the gate polysilicon, sinking the contact portions of both sides of the gate polysilicon with the shallow trench isolation region along the channel width direction of the semiconductor to form a second groove on the shallow trench isolation region; and performing gate filling on the first groove and the second groove. Through the scheme of the present application, the gate structure of the semiconductor device is modified to achieve effective improvement of the short channel effect of the device.

Description

Technical Field

[0001] The present application generally relates to the field of semiconductor manufacturing processes. More specifically, the present application relates to a method for preparing a semiconductor gate structure and a semiconductor structure. Background Art

[0002] In the prior art, the size of semiconductor devices such as metal oxide semiconductor field effect transistors (MOS) is usually reduced to improve the working performance of semiconductor devices and save costs. However, as the size of semiconductor devices such as MOS is reduced, after the channel length of the semiconductor device is reduced to a certain extent, the proportion of the depletion region of the source and drain junctions in the entire channel increases, and the amount of charge required to form an inversion layer on the silicon surface under the gate decreases, thereby reducing the threshold voltage. At the same time, the charge in the part of the depletion region in the substrate that is laterally widened along the channel width increases the threshold voltage. When the width of the source and drain depletion regions is close to the channel length of the device, the threshold voltage reduction becomes very significant, and semiconductor devices such as MOS will experience a serious short channel effect.

[0003] In view of this, there is an urgent need to provide a solution for improving the short channel effect of semiconductor devices so as to enhance the performance of small-sized semiconductor devices. Summary of the invention

[0004] In order to at least solve one or more of the technical problems mentioned above, the present application proposes solutions that can improve the short channel effect of semiconductor devices in multiple aspects.

[0005] In a first aspect, the present application provides a method for preparing a semiconductor gate structure, comprising: providing a substrate and forming gate polysilicon on the substrate, wherein during the formation of the gate polysilicon, the well regions on both sides of the gate polysilicon are subjected to a sinking treatment; along the channel length direction of the semiconductor, sidewall structures are formed on both sides of the gate polysilicon, wherein the sidewall structures include a sacrificial layer formed on both sides of the gate polysilicon and a sidewall layer formed outside the sacrificial layer; the gate polysilicon and the sacrificial layer are removed to form a first groove, wherein a shallow trench isolation region is also formed in the well region of the substrate, and during the removal of the gate polysilicon, the portions on both sides of the gate polysilicon in contact with the shallow trench isolation region are subjected to a sinking treatment along the channel width direction of the semiconductor to form a second groove on the shallow trench isolation region; and the first groove and the second groove are subjected to a gate filling treatment.

[0006] In some embodiments, sinking the well regions on both sides of the gate polysilicon includes: over-etching the well regions on both sides of the gate polysilicon so that the well regions on both sides of the gate polysilicon sink to a first height.

[0007] In some embodiments, forming the sidewall structure on both sides of the gate polysilicon includes: forming the sacrificial layer of predetermined thickness on both sides of the gate polysilicon; and forming the sidewall layer on the outer side of the sacrificial layer, wherein the sacrificial layer and the sidewall layer are made of different materials.

[0008] In some embodiments, the sacrificial layer is made of silicon oxide.

[0009] In some embodiments, removing the gate polysilicon and the sacrificial layer includes: after forming the sidewall structure, forming an interlayer dielectric on the well region of the substrate so that the interlayer dielectric covers the gate polysilicon and the sidewall structure; removing the gate polysilicon and the interlayer dielectric above the sacrificial layer in the sidewall structure to expose the gate polysilicon and the sacrificial layer; and removing the gate polysilicon and the sacrificial layer to form the first groove.

[0010] In some embodiments, removing the gate polysilicon and the interlayer dielectric above the sacrificial layer in the spacer structure includes: removing the gate polysilicon and the interlayer dielectric above the sacrificial layer in the spacer structure by using chemical mechanical planarization technology.

[0011] In some embodiments, sinking the contact portions of the two sides of the gate polysilicon with the shallow trench isolation region includes: over-etching the contact portions of the two sides of the gate polysilicon with the shallow trench isolation region so that the shallow trench isolation region sinks to a second height to form the second groove.

[0012] In some embodiments, performing gate filling processing on the first groove and the second groove includes: performing high-K dielectric layer filling processing on the first groove and the second groove; and after completing the high-K dielectric layer filling, continuing to perform metal gate filling processing on the first groove and the second groove.

[0013] In a second aspect, the present application provides a semiconductor structure, comprising: a substrate; a gate, a source and a drain formed on the substrate; wherein the gate is made using the preparation method provided in the first aspect, and the channel length of the semiconductor structure is related to the length of the gate polysilicon, the sinking height of the well region on both sides of the gate polysilicon and the thickness of the sacrificial layer, and the channel width of the semiconductor structure is related to the width of the gate polysilicon and the height of the second groove.

[0014] In some embodiments, wherein: the channel length L of the semiconductor structure = l +2h1+2h2, where lrepresents the length of the gate polysilicon, h1 represents the sinking height of the well region on both sides of the gate polysilicon, and h2 represents the thickness of the sacrificial layer; the channel width W of the semiconductor structure is w +2h3, of which, w represents the width of the gate polysilicon, and h3 represents the height of the second groove.

[0015] The unexpected beneficial technical effect of the present application is: through the preparation method and semiconductor structure of the semiconductor gate structure provided above, the embodiment of the present application sinks the well regions on both sides of the gate polysilicon and forms a sacrificial layer on both sides of the gate polysilicon during the preparation process of the semiconductor gate structure, so as to extend the gate length by removing the gate polysilicon and the sacrificial layer. At the same time, during the removal of the gate polysilicon, the contact portions of the two sides of the gate polysilicon with the shallow trench isolation region are sunk to widen the gate width, thereby completing the modification of the gate structure of the semiconductor device. Therefore, the scheme of the present application can effectively increase the length and width of the channel of the semiconductor device by modifying the gate structure of the semiconductor device without adding a new mask or increasing the device area, thereby effectively improving the short channel effect of the device and improving the performance of small-sized semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present application will become easy to understand. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0017] Figure 1a~Figure 1c Schematic diagrams showing the structure of the semiconductor structure in different directions according to an embodiment of the present application;

[0018] Figure 2 A schematic flow chart showing a method for preparing a semiconductor gate structure according to some embodiments of the present application;

[0019] Figure 3 A schematic flow chart showing a method for preparing a semiconductor gate structure according to other embodiments of the present application; and

[0020] Figure 4a~Figure 4f A schematic diagram of a semiconductor cross-sectional structure in a method for preparing a semiconductor gate structure according to some embodiments of the present application is shown. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0022] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present application indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0023] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in this application specification and claims, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to include plural forms. It should also be further understood that the term "and / or" used in this application specification and claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0024] The specific implementation of the present application is described in detail below with reference to the accompanying drawings.

[0025] Figure 1a , Figure 1b and Figure 1c The schematic diagrams of the semiconductor structure in different directions of the embodiment of the present application are shown respectively. It should be noted that: Figure 1a A schematic diagram of the top structure of a semiconductor structure is shown, wherein Figure 1a The X direction in φ represents the channel length direction of the semiconductor structure, and the Y direction represents the channel width direction of the semiconductor structure. Figure 1b Specifically, a schematic cross-sectional view of the semiconductor structure in the X direction (that is, the channel length direction of the semiconductor structure) is shown. Figure 1c Specifically, a schematic cross-sectional view of the semiconductor structure in the Y direction (ie, the channel width direction of the semiconductor structure) is shown.

[0026] The semiconductor structure in the present application may include a Metal Oxide Semiconductor Field Effect Transistor (MOS), a Complementary Metal Oxide Semiconductor (CMOS), and the like.

[0027] like Figure 1b and Figure 1c As shown, the semiconductor structure 100 includes a substrate 101. The substrate 101 may be a silicon substrate, a silicon germanium substrate, or other semiconductor material substrates known to those skilled in the art. For example, MOS transistors, CMOS transistors, etc. generally use silicon substrates, etc.

[0028] A gate, a source and a drain can be formed on the substrate 101. The solution of the present application mainly involves the change of the gate structure. This embodiment focuses on the explanation and display of the gate part. The source and drain can be prepared by using known technology. The solution of the present application does not explain the source and drain in detail.

[0029] In this embodiment, the gate of the semiconductor structure is mainly formed by the following process:

[0030] First, a gate polysilicon is formed on the substrate 101. During the formation of the gate polysilicon, the well regions 102 on both sides of the gate polysilicon are sunk. Next, a sidewall layer 104 can be formed on the sacrificial layer on both sides of the gate polysilicon and on the outside of the sacrificial layer. In the subsequent process, the gate polysilicon and the sacrificial layer can be removed to form a first groove. A shallow trench isolation region 105 is also formed in the well region 102 of the substrate 101. During the removal of the aforementioned gate polysilicon, the portions on both sides of the gate polysilicon in contact with the shallow trench isolation region 105 can be sunk to form a second groove on the shallow trench isolation region 105. Then, the aforementioned first groove and the second groove are gate-filled to complete the preparation of the gate 103. For the specific preparation process of the gate 103, reference can be made to the relevant description below.

[0031] The gate 103 of the semiconductor in the present application has an improved structure relative to the gate prepared by the conventional process. Specifically, the length of the gate 103 in the present application is related to the length of the gate polysilicon, the sinking height of the well region on both sides of the gate polysilicon, and the thickness of the sacrificial layer, while the width of the gate 103 is related to the width of the gate polysilicon and the height of the aforementioned second groove. The length of the gate prepared by the conventional process is only related to the length of the gate polysilicon, and the width of the gate is only related to the width of the gate polysilicon.

[0032] The unexpected beneficial technical effect of the present application is that the gate of the semiconductor in the present application scheme is extended in length and widened in width compared to the gate prepared by traditional technology, so that the length and width of the channel of the semiconductor device are effectively increased by changing the gate structure of the semiconductor device, thereby effectively improving the short channel effect of the device and enhancing the performance of small-size semiconductor devices.

[0033] Figure 2A schematic flow chart of a method 200 for preparing a semiconductor gate structure according to some embodiments of the present application is shown. It should be noted that: Figure 2 It can be understood that Figure 1b and Figure 1c An exemplary process for preparing a gate in a semiconductor structure. Figure 1b and Figure 1c The relevant instructions in also apply to the following.

[0034] like Figure 2 As shown, at step S201, a substrate may be provided and gate polysilicon may be formed on the substrate, wherein during the formation of the gate polysilicon, the well regions on both sides of the gate polysilicon are sunk. As shown above, the substrate may include a silicon substrate, a germanium silicon substrate, or other semiconductor material substrates known to those skilled in the art, and may be specifically configured and adjusted according to the performance requirements of the semiconductor to be prepared.

[0035] In some embodiments, a well region may be first formed on a substrate. The well region may include an N-well, a P-well, or a double-well. For example, a sacrificial oxide layer may be formed on the substrate using a thermal oxidation process, and then a photoresist may be applied over the P / N well region and exposed and developed using a photolithography process, and n / p impurities may be injected using an ion implantation process, and unnecessary photoresist may be removed by ashing. Next, the sacrificial oxide layer is removed, and the P / N well region is annealed and activated to form a P / N well. It should be noted that if the semiconductor structure is a CMOS tube, a P-well and an N-well need to be formed on the substrate to form a double-well. The description of the formation process of the well region here is only an exemplary description, and the solution of the present application is not limited thereto, and other known processes may be used to complete the preparation of the well region.

[0036] After the preparation of the well region is completed, a gate oxide layer of a silicon oxynitride layer or a silicon dioxide layer can be formed on the well region, and a layer of polysilicon gate can be deposited on the gate oxide layer. Then, the pattern on the gate mask is transferred to the substrate using lithography technology to form a photoresist pattern of the gate, and the photoresist is retained on the gate region of the device. Then, the polysilicon not covered by the photoresist can be removed by dry etching and other techniques to form gate polysilicon. Usually, when etching the gate, when etching the gate oxide layer, it will be prompted that the polysilicon etching has been completed. In this embodiment, during the formation of the gate polysilicon, the well regions on both sides of the gate polysilicon need to be sunk. Specifically, the well regions on both sides of the gate polysilicon can be over-etched so that the well regions on both sides of the gate polysilicon sink to a first height. Among them, the first height can be preset, and can be specifically designed according to the performance requirements of the semiconductor device to be prepared.

[0037] At step S202, a sidewall structure can be formed on both sides of the aforementioned gate polysilicon along the channel length direction of the semiconductor. The sidewall structure may include a sacrificial layer formed on both sides of the gate polysilicon and a sidewall layer formed on the outside of the sacrificial layer. In some embodiments, a sacrificial layer of predetermined thickness can be formed on both sides of the gate polysilicon. Then, a sidewall layer is formed on the outside of the sacrificial layer. For example, a plasma chemical vapor deposition method or the like can be used to sequentially form a sacrificial layer and a sidewall layer of different materials on both sides of the gate polysilicon. It should be noted that the solution of the present application does not limit the thickness of the sacrificial layer and the thickness of the sidewall layer, and can be specifically designed according to the performance requirements of the semiconductor device to be prepared.

[0038] The sacrificial layer needs to be removed in the subsequent process, so any material can be used to form the sacrificial layer as long as it is different from the material of the sidewall layer. Preferably, the sacrificial layer can be prepared using materials such as silicon oxide or silicon to increase the adhesion between the sacrificial layer and the gate polysilicon.

[0039] In step S203 , the gate polysilicon and the sacrificial layer may be removed to form a first groove, and a second groove may be formed on the shallow trench isolation region.

[0040] In this embodiment, after forming the sidewall structure, an inter-level dielectric (ILD) can be formed on the well region of the substrate so that the inter-level dielectric covers the gate polysilicon and the sidewall structure. The ILD process refers to the dielectric material formed between the transistor and the first layer of metal to form electrical isolation. The ILD dielectric layer can effectively reduce the parasitic capacitance between the metal and the substrate, and improve the parasitic field effect transistor formed by the metal crossing different regions. In some embodiments, silicon oxide can be used as the dielectric material of the ILD.

[0041] Next, the interlayer dielectric above the gate polysilicon and the sacrificial layer in the sidewall structure can be removed to expose the gate polysilicon and the sacrificial layer. In some embodiments, a chemical mechanical planarization (CMP) technique can be used to remove the interlayer dielectric above the gate polysilicon and the sacrificial layer in the sidewall structure. For example, a chemical mechanical planarization method such as reverse etching, BPSG reflow, and SOG spin-on glass method can be used to polish the interlayer dielectric above the gate polysilicon and the sacrificial layer to remove the interlayer dielectric at the corresponding position, thereby exposing the gate polysilicon and the sacrificial layer relative to other areas.

[0042] Then, the aforementioned gate polysilicon and sacrificial layer are removed to form a first groove. In some embodiments, the gate polysilicon and the sacrificial layer can be processed by an etching process to complete the removal of the gate polysilicon and the sacrificial layer.

[0043] In practical applications, a gate oxide layer is also formed between the gate polysilicon and the substrate, and the formation process of the first groove specifically involves the removal of the gate polysilicon, the gate oxide layer, and the sacrificial layer. If the sacrificial layer and the gate polysilicon are made of the same material (for example, both are made of silicon), the sacrificial layer can be removed simultaneously with the gate polysilicon. If the sacrificial layer and the gate oxide layer are made of the same material (for example, both are made of silicon oxide, etc.), the sacrificial layer can be removed simultaneously with the gate oxide layer. If the sacrificial layer is made of different materials from the gate polysilicon and the gate oxide layer, the gate polysilicon can be removed first, followed by the gate oxide layer, and then the sacrificial layer. It should be noted that the description of the removal process of the gate polysilicon and the sacrificial layer here is only an exemplary description, and the specific removal method can be adjusted according to the specific material of the sacrificial layer.

[0044] In some embodiments, a shallow trench isolation region is also formed in the well region of the substrate. Shallow trench isolation (STI) technology has been gradually widely used to make insulating structures between devices. In some embodiments, a silicon nitride layer can be deposited on the well region of the semiconductor substrate, and then the silicon nitride layer can be patterned to form a hard mask. The substrate is then etched to form steep trenches between adjacent components. Finally, an oxide (such as silicon oxide, etc.) is filled in the trench to form a shallow trench isolation region. In other embodiments, a linear oxide layer can be first oxidized on the well region of the semiconductor substrate, and then a layer of silicon nitride is deposited. Subsequently, the trench area can be defined by photoresist patterning, and the trench can be etched to form a trench, and finally the trench can be filled to form a shallow trench isolation region.

[0045] In this embodiment, during the removal of the gate polysilicon, the portions of the gate polysilicon in contact with the shallow trench isolation region on both sides need to be further sunken along the channel width direction of the semiconductor to form a second groove on the shallow trench isolation region. In some embodiments, the portions of the gate polysilicon in contact with the shallow trench isolation region on both sides may be overetched so that the shallow trench isolation region is sunken to a second height to form a second groove. The second height may be preset and may be specifically designed according to the performance requirements of the semiconductor device being manufactured.

[0046] After forming the first groove and the second groove, at step S204, the first groove and the second groove may be subjected to gate filling treatment. In some embodiments, the gate dielectric layer may be filled in the first groove and the second groove first, and then polysilicon or metal gate may be filled. For example, silicon dioxide or SiON may be filled in the first groove and the second groove as the gate dielectric layer, and then polysilicon or metal gate may be filled on the gate dielectric layer. For another example, silicon oxynitride may be filled in the first groove and the second groove as the gate dielectric layer, and then metal gate may be filled on the gate dielectric layer. For another example, high-k material may be used instead of silicon oxynitride as the gate dielectric layer, and then metal gate may be filled on the gate dielectric layer. Alternatively, in other embodiments, a layer of SiON film may be deposited in the first groove and the second groove first, so as to improve the interface state between the high-k dielectric material and the substrate silicon through the SiON film, and then high-k dielectric material (such as HfO2) may be deposited through atomic layer deposition technology. Then, metal gate may be deposited through atomic layer deposition technology, and low-resistance metal may be deposited through atomic layer deposition technology to fill the gate trench, etc. to complete the gate filling treatment.

[0047] In this embodiment, preferably, the first groove and the second groove are filled with a high-K dielectric layer, that is, a gate dielectric layer of a high-K material is filled in the first groove and the second groove. In some embodiments, the high-K material includes but is not limited to hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HM0), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO) and other materials. After the high-K dielectric layer is filled, the first groove and the second groove are continuously filled with a metal gate. In some embodiments, the metal gate can be made of but is not limited to tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAIN or other suitable materials. Therefore, compared with using other materials as the gate dielectric layer, a gate dielectric layer with a larger physical thickness can be obtained under the condition of the same equivalent gate oxide layer thickness, thereby improving the gate leakage current.

[0048] At this point, the preparation of the gate is completed based on the above steps S201 to S204. Further, the source and drain can be prepared on the well region on the substrate, and finally the preparation of the entire semiconductor structure is completed.

[0049] The unexpected beneficial technical effect of the present application is that through the preparation process of the gate structure shown in this embodiment, the gate structure of the semiconductor can be effectively improved without changing the device area, thereby improving the performance of small-sized semiconductor devices.

[0050] Figure 3 Schematic flow chart of a method 300 for preparing a semiconductor gate structure according to another embodiment of the present application is shown. It should be noted that: Figure 3 It can be understood that Figure 2 A specific implementation of the preparation method shown. Figure 3 The preparation process in the above can be understood as an improvement of the existing technology (such as the post-HK process), where "○" represents the existing process and "●" represents the improved process. The post-HK (HK Last) process in the existing technology is to deposit virtual SiO2 as a virtual dielectric layer in the IL layer and then directly deposit virtual Si as a virtual gate, followed by source and drain embedding GeSi strain, source and drain doping, stress memory (SMT), contact etch barrier layer strain (CESL), sidewall and other processes, and then use CMP process after depositing the ILD layer to expose the virtual Si, etch away the virtual Si and virtual SiO2, and then deposit the IL layer, HK layer, and finally deposit the metal gate.

[0051] like Figure 3 As shown, in step S301, the gate polysilicon can be prepared by, for example, a Poly mask process. For example, a well region can be formed on the substrate. After the preparation of the well region is completed, a gate oxide layer composed of a silicon oxynitride layer or a silicon dioxide layer can be formed on the well region, and a layer of polysilicon gate can be deposited on the gate oxide layer. Specifically, the pattern on the gate mask can be transferred to the substrate using lithography technology to form a photoresist pattern of the gate, and the photoresist is retained on the gate region of the device. Then, the polysilicon not covered by the photoresist is removed using dry etching and other techniques to form gate polysilicon. Among them, the length of the gate polysilicon is l .

[0052] In step S302, during the etching of the gate polysilicon, an appropriate amount of etching may be added to the well regions on both sides of the gate polysilicon. For example, the well regions on both sides of the gate polysilicon may be overetched so that the well regions on both sides of the gate polysilicon sink to a first height (h1).

[0053] refer to Figure 4a As shown, the semiconductor structure includes a substrate 401 and a well region 402. A gate polysilicon 403 is formed on the well region 402. During the etching process of the gate polysilicon 403, the well regions on both sides of the gate polysilicon 403 may be overetched so that the well regions on both sides of the gate polysilicon 403 are sunken by a height of h1 (h1>0).

[0054] return Figure 3 At step S303, polysilicon stripping may be performed. The stripping process (Strip) is a process for removing the photoresist covered by the pattern after the etching process forms a corresponding pattern on the substrate. The process can be implemented using the existing process and will not be described in detail here.

[0055] In step S304, a sacrificial layer may be formed on both sides of the gate polysilicon. For example, a sacrificial layer of silicon oxide, silicon or other materials may be formed on both sides of the gate polysilicon by plasma chemical vapor deposition, and the thickness of the sacrificial layer is h2 (h2>0).

[0056] In step S305, a spacer layer may be formed outside the sacrificial layer. For example, a plasma chemical vapor deposition method may be used to form the spacer layer outside the sacrificial layer. The material used for the spacer layer is different from that of the sacrificial layer.

[0057] refer to Figure 4b The semiconductor structure includes a substrate 401, a well region 402, and a gate polysilicon 403 formed on the well region 402. A sacrificial layer with a thickness of h2 and a sidewall layer 405 are formed on both sides of the gate polysilicon 403.

[0058] return Figure 3 In step S306, a middle stage process may be performed. Generally, the middle stage process may be understood as a process for connecting the front stage device with the first metal layer of the back stage. The middle stage process in this embodiment may use the same or similar process in the prior art, which will not be described in detail here.

[0059] At step S307 , an interlayer dielectric ILD process is performed. For example, an interlayer dielectric ILD may be formed on the well region of the substrate so that the interlayer dielectric ILD covers the gate polysilicon and the spacer structure.

[0060] In step S308 , a chemical mechanical planarization process may be performed on the interlayer dielectric ILD to expose the gate polysilicon and the sacrificial layer.

[0061] In step S309, the gate polysilicon and the sacrificial layer are removed. For example, the gate polysilicon and the sacrificial layer may be removed by etching or other methods to form a first groove.

[0062] In addition, a shallow trench isolation region is formed in the well region of the substrate. During the removal of the gate polysilicon, the portions on both sides of the gate polysilicon that are in contact with the shallow trench isolation region need to be further sunken to form a second groove on the shallow trench isolation region. In some embodiments, the portions on both sides of the gate polysilicon that are in contact with the shallow trench isolation region may be overetched to sink the shallow trench isolation region to a second height to form a second groove.

[0063] refer to Figure 4c The semiconductor structure includes a substrate 401 and a well region 402. A gate polysilicon 403 ( Figure 4c A sacrificial layer 404 (not shown) is formed on both sides of the gate polysilicon 403. Figure 4c (not shown), a spacer layer 405 is formed outside the sacrificial layer 404. After the gate polysilicon 403 and the sacrificial layer 404 are removed, a first groove A can be formed.

[0064] refer to Figure 4d , the semiconductor structure also includes a shallow trench isolation region 406, which is filled with materials such as silicon oxide. The interlayer dielectric 407 can cover the well region 402, the gate polysilicon 403, the sacrificial layer 404 and the sidewall layer. The interlayer dielectric 407 above the gate polysilicon 403 and the sacrificial layer 404 is removed to expose the gate polysilicon and the sacrificial layer, and the gate polysilicon 403 and the sacrificial layer 404 are removed to form a first groove. In the process of removing the gate polysilicon 403, it is necessary to further sink the portions on both sides of the gate polysilicon 403 that are in contact with the shallow trench isolation region 406. That is, the silicon oxide at the corresponding position in the shallow trench isolation region 406 is overetched to form a second groove B on the shallow trench isolation region 406. In the second height of the sinking of the shallow trench isolation region 406 is h3 (h3>0), that is, the height or depth of the second groove B is h3. Among them, the width of the gate polysilicon 403 is w .

[0065] return Figure 3 In step S310, the first groove and the second groove are filled with a gate dielectric layer. For example, silicon dioxide, silicon nitride or various high-K materials can be filled in the first groove and the second groove as the gate dielectric layer.

[0066] In step S311 , after the gate dielectric layer is filled, a metal gate may be continuously filled into the first groove and the second groove.

[0067] The above-mentioned filling operation can be completed with different metal materials. For example, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride or other suitable metal materials can be used to fill the metal gate. The semiconductor structure after filling can refer to Figure 4e and Figure 4f .exist Figure 4e and Figure 4f In the embodiment, silicon dioxide, silicon nitride or various high-K materials can be filled in the first groove and the second groove as the gate dielectric layer 408. Then, after the gate dielectric layer 408 is filled, a metal gate can be continuously filled in the first groove and the second groove to complete the filling of the gate 409. That is, Figure 4eand Figure 4f The gate electrode 408 of the semiconductor shown can be specifically Figure 3 The manufacturing process shown is used to make it.

[0068] In addition, for Figure 4e and Figure 4f The semiconductor structure shown has a channel length (L) and a gate polysilicon length ( l ), the sinking height of the well region on both sides of the gate polysilicon (h1) and the thickness of the sacrificial layer (h2). The channel width (W) of the semiconductor structure is related to the width of the gate polysilicon ( w ) and the height (h3) of the second groove. Specifically, in some embodiments, the channel length L of the semiconductor structure is l +2h1+2h2, the channel width W of the semiconductor structure = w +2h3. The specific values ​​of the parameters h1, h2 and h3 are not limited and can be designed in combination with the performance requirements of the semiconductor device to be manufactured.

[0069] The unexpected beneficial technical effect of the present application is that the solution of the present application can effectively improve the short channel effect by changing the structure of the semiconductor device on the basis of the existing nano-process node. Furthermore, the existing larger nano-process and the solution of the present application can be combined to achieve the improvement of the nano-process node, so that the prepared semiconductor device has the performance of the semiconductor device prepared by the smaller nano-process node. At the same time, the entire preparation process node does not involve changes in the device area, does not increase the number of masks, and does not generate additional production costs.

[0070] It should be noted that although the operations of the method of the present application are described in a specific order in the accompanying drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. On the contrary, the steps depicted in the flow chart can be performed in a different order. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step, and / or one step can be decomposed into multiple steps.

[0071] Although multiple embodiments of the present application have been shown and described herein, it is obvious to those skilled in the art that such embodiments are provided only by way of example. Those skilled in the art can think of many changes, modifications and alternatives without departing from the thought and spirit of the present application. It should be understood that in the process of practicing the present application, various alternatives to the embodiments of the present application described herein can be adopted. The attached claims are intended to limit the scope of protection of the present application, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for preparing a semiconductor gate structure, characterized in that: include: Providing a substrate and forming gate polysilicon on the substrate, wherein during the formation of the gate polysilicon, sinking treatment is performed on the well regions on both sides of the gate polysilicon, wherein the sinking treatment on the well regions on both sides of the gate polysilicon includes over-etching the well regions on both sides of the gate polysilicon, so that the well regions on both sides of the gate polysilicon sink to a first height; Forming a sidewall structure on both sides of the gate polysilicon along the channel length direction of the semiconductor, wherein the sidewall structure comprises a sacrificial layer formed on both sides of the gate polysilicon and a sidewall layer formed outside the sacrificial layer; The gate polysilicon and the sacrificial layer are removed to form a first groove, wherein a shallow trench isolation region is also formed in the well region of the substrate, and during the removal of the gate polysilicon, portions of the gate polysilicon in contact with the shallow trench isolation region on both sides are sunken along the channel width direction of the semiconductor to form a second groove on the shallow trench isolation region, wherein the sinking of portions of the gate polysilicon in contact with the shallow trench isolation region on both sides includes: over-etching portions of the gate polysilicon in contact with the shallow trench isolation region on both sides so that the shallow trench isolation region is sunken to a second height to form the second groove; as well as A gate filling process is performed on the first groove and the second groove.

2. The preparation method according to claim 1, characterized in that: Forming sidewall structures on both sides of the gate polysilicon includes: Forming the sacrificial layer with a predetermined thickness on both sides of the gate polysilicon; and The sidewall layer is formed on the outer side of the sacrificial layer, wherein the sacrificial layer and the sidewall layer are made of different materials.

3. The preparation method according to claim 2, characterized in that: The sacrificial layer is made of silicon oxide.

4. The preparation method according to claim 1, characterized in that: The process of removing the gate polysilicon and the sacrificial layer includes: After forming the sidewall structure, forming an interlayer dielectric on the well region of the substrate so that the interlayer dielectric covers the gate polysilicon and the sidewall structure; Removing the gate polysilicon and the interlayer dielectric above the sacrificial layer in the sidewall structure to expose the gate polysilicon and the sacrificial layer; and The gate polysilicon and the sacrificial layer are removed to form the first groove.

5. The preparation method according to claim 4, characterized in that: Removing the gate polysilicon and the interlayer dielectric above the sacrificial layer in the sidewall structure includes: Chemical mechanical planarization technology is used to remove the gate polysilicon and the interlayer dielectric above the sacrificial layer in the sidewall structure.

6. The preparation method according to any one of claims 1 to 5, characterized in that Performing gate filling processing on the first groove and the second groove includes: Filling the first groove and the second groove with a high-K dielectric layer; and After the high-K dielectric layer is filled, the first groove and the second groove are continuously filled with a metal gate.

7. A semiconductor structure, characterized in that: include: substrate; A gate, a source and a drain are formed on a substrate; wherein, The gate is made by the preparation method described in any one of claims 1 to 6, and the channel length of the semiconductor structure is related to the length of the gate polysilicon, the sinking height of the well region on both sides of the gate polysilicon and the thickness of the sacrificial layer, and the channel width of the semiconductor structure is related to the width of the gate polysilicon and the height of the second groove.

8. The semiconductor structure according to claim 7, characterized in that: in: The channel length L of the semiconductor structure is l +2h1+2h2, where l represents the length of the gate polysilicon, h1 represents the sinking height of the well regions on both sides of the gate polysilicon, and h2 represents the thickness of the sacrificial layer; The channel width W of the semiconductor structure is w +2h3, of which, w represents the width of the gate polysilicon, and h3 represents the height of the second groove.

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