Trench Capacitively Coupled Gate Controlled Junction Field Effect Transistor

Abstract

The embodiment of the present application provides a trench-type capacitive-coupled gate-controlled junction field effect transistor, comprising: a substrate, an epitaxial layer, and a drain; a trench-type gate, wherein the outermost layer of the trench-type gate located in the inner part of the epitaxial layer is a layer structure of the first doping type; two source region deep grooves formed on both sides of the trench-type gate and spaced apart from the trench-type gate, wherein the lower surface of the source region deep groove is lower than the lower surface of the trench-type gate; two source regions of the first doping type, respectively formed downward from the lower surface of the two source region deep grooves; two channel regions of the second doping type, wherein the two channel regions are respectively connected to both sides of the trench-type gate; two first doping type ohmic contact regions, formed on the two source regions, and the first doping type ohmic contact regions on the same side are connected to the channel regions; the source region and the structure located between the two source regions in the epitaxial layer form a PN junction. The present application solves the technical problem of large leakage of the conventional trench-type capacitive-coupled gate-controlled junction field effect transistor.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a trench-type capacitively coupled gate-controlled junction field effect transistor. Background Art

[0002] Silicon carbide devices have the advantages of high voltage resistance, low on-resistance, faster switching speed, higher operating temperature, heat dissipation and good radiation resistance, and have been widely used in power electronic circuits. Silicon carbide devices include MOSFET and JFET. As a three-port device similar to MOSFET, the working principle of JFET device is to use gate voltage to control the reverse bias of PN, so as to achieve the purpose of controlling the opening and closing of the channel. It has the advantages of low noise, small size, and high-frequency response. JFET devices made of silicon carbide materials can also be used in high-power application scenarios, such as new energy vehicles, high-voltage power transmission, etc.

[0003] Improving the reliability of traditional trench-type capacitive-coupled gate-controlled junction field-effect transistors and solving their large channel leakage are technical problems that technical personnel in this field urgently need to solve.

[0004] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0005] The embodiment of the present application provides a trench-type capacitive-coupled gate-controlled junction field effect transistor to solve the technical problem of large leakage of traditional trench-type capacitive-coupled gate-controlled junction field effect transistors.

[0006] The embodiment of the present application provides a trench type capacitive coupled gate controlled junction field effect transistor, comprising:

[0007] A substrate, an epitaxial layer formed on the substrate, and a drain formed on the back side of the substrate;

[0008] A trench gate is formed downward from the upper surface of the epitaxial layer, wherein the outermost layer of the trench gate located in the inner part of the epitaxial layer is a layer structure of the first doping type;

[0009] Two source region deep trenches are respectively formed on both sides of the trench type gate and are spaced apart from the trench type gate, and the lower surface of the source region deep trench is lower than the lower surface of the trench type gate;

[0010] Two source regions of the first doping type are formed downward from the lower surfaces of the two source region deep trenches respectively;

[0011] Two channel regions of the second doping type, the two channel regions being respectively connected to two sides of the trench gate;

[0012] Two first doping type ohmic contact regions are formed on the two source regions respectively, and the first doping type ohmic contact regions and the channel region on the same side are connected;

[0013] Wherein, the source region and the structure located between the two source regions in the epitaxial layer form a PN junction.

[0014] The embodiment of the present application adopts the above technical solution, which has the following technical effects:

[0015] The gate voltage is greater than the threshold voltage (such as 18V), the gate is turned on, and when the drain voltage is applied, the trench capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is turned on, and the current path is as follows Figure 2-1 As shown by the dotted line in .

[0016] When the drain of the trench capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is subjected to a voltage and the gate is at zero volts:

[0017] As the drain voltage gradually increases:

[0018] On the one hand, the bottom of the second doping type channel region 3 and the corner position of the first doping type ohmic contact region 2 form a PN junction, and the bottom of the channel region 3 and the outermost corner position of the trench gate form a PN junction ( Figure 2-1 The position of the two dotted elliptical rings in the upper middle) extends to the middle of the bottom of the channel region 3 until the guide channel at the bottom of the channel region 3 is pinched off; that is, the PN junction formed by the second doping type channel region 3 and the first doping type ohmic contact region 2, and the PN junction formed by the second doping type channel region 3 and the outermost first doping type of the trench gate are in reverse bias. At this time, the trench-type capacitive-coupled gate-controlled junction field effect transistor is protected (that is, the electric field at the bottom of the two channel regions 3 is reduced to prevent the electric field concentration effect of the channel region 3), the leakage current is reduced, and the withstand voltage is improved, thereby making the trench-type capacitive-coupled gate-controlled junction field effect transistor of the embodiment of the present application more reliable.

[0019] On the other hand, the depletion region of the PN junction formed by the structure located between the two source regions 7 in the source region 7 and the epitaxial layer position expands toward the middle between the two source regions 7 (that is, the electric field will be gathered at the corner of the source region 7 to cause the depletion to expand) until the conduction channel of the structure located between the two source regions 7 in the source region 7 and the epitaxial layer position is pinched off, that is, the PN junction formed by the structure located between the two source regions 7 in the source region 7 and the epitaxial layer position is in reverse bias. At this time, the trench-type capacitive-coupled gate-controlled junction field effect transistor is protected (that is, the electric field at the two source regions 7 is reduced to prevent the electric field concentration effect in the channel region 3), the leakage current is reduced, and the withstand voltage is improved, thereby making the trench-type capacitive-coupled gate-controlled junction field effect transistor of the embodiment of the present application more reliable.

[0020] At this point, the PN junction formed by the source region 7 and the structure between the two source regions 7 in the epitaxial layer, the PN junction formed by the bottom of the second doping type channel region 3 and the corner position of the first doping type ohmic contact region 2, and the PN junction formed by the bottom of the channel region 3 and the outermost corner position of the trench gate can all protect the trench type capacitor-coupled gate-controlled junction field effect transistor (i.e., reduce the electric field), reduce leakage current, and improve withstand voltage, thereby making the trench type capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the present application highly reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0022] Figure 1 Schematic diagram of a planar gate SiC MOSFET device in the prior art;

[0023] Figure 2-1 A schematic diagram of a trench type capacitively coupled gate controlled junction field effect transistor according to an embodiment of the present application;

[0024] Figure 2-2 A schematic diagram of a current path of a trench type capacitive coupled gate controlled junction field effect transistor connected to a source voltage according to an embodiment of the present application;

[0025] Figure 3 A schematic diagram of completing step 3 of preparing a trench-type capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0026] Figure 4 A schematic diagram of completing step 4 of preparing a trench-type capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0027] Figure 5 A schematic diagram of completing step 7 of preparing a trench-type capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0028] Figure 6 A schematic diagram of completing step 8 of preparing a trench-type capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0029] Figure 7 A schematic diagram of completing step 9 of preparing a trench-type capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0030] Figure 8 A schematic diagram of the simulation modeling structure of the capacitively coupled gate-controlled junction field effect transistor of the present application;

[0031] Fig. 9 for Figure 8 The forward current density distribution diagram of the capacitively coupled gate controlled junction field effect transistor shown;

[0032] Fig.10 for Figure 8 The forward current curve of the capacitively coupled gate-controlled junction field effect transistor shown;

[0033] Fig.11 for Figure 8 The on-state current density distribution diagram of the capacitively coupled gate-controlled junction field effect transistor when the source voltage is connected;

[0034] Fig.12 for Figure 8 The electric field intensity distribution diagram of the capacitively coupled gate-controlled junction field effect transistor during reverse breakdown is shown;

[0035] Fig.13 for Figure 8 The breakdown voltage curve of the capacitively coupled gate controlled junction field effect transistor is shown.

[0036] Reference numerals:

[0037] In the prior art:

[0038] Substrate 1-1, epitaxial layer 1-2, gate trench 1-31, trench gate 1-32, P-type well region 1-4,

[0039] Source 1-5, gate oxide layer 1-6.

[0040] In this application:

[0041] Source metal 1, first doping type ohmic contact region 2, channel region 3, gate region 4,

[0042] Gate dielectric layer 5, coupling capacitor upper electrode 6, source region 7, drift region 8,

[0043] Current guiding layer 9, current guiding layer first region 91, substrate 10, drain 11, source contact region 15;

[0044] Current guiding layer foundation 90, channel region foundation 120, source contact region foundation 150,

[0045] The source region has a deep trench 14 and the gate region has a trench 13. DETAILED DESCRIPTION

[0046] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. Embodiment 1

[0047] like Figure 2-1 As shown, the trench capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application includes:

[0048] A substrate 10, an epitaxial layer formed on the substrate, and a drain 11 formed on the back side of the substrate;

[0049] A trench gate is formed downward from the upper surface of the epitaxial layer, wherein the outermost layer of the trench gate located in the inner part of the epitaxial layer is a layer structure of the first doping type;

[0050] Two source region deep trenches are respectively formed on both sides of the trench type gate and are spaced apart from the trench type gate, and the lower surface of the source region deep trench is lower than the lower surface of the trench type gate;

[0051] Two channel regions 3 of the second doping type, the two channel regions 3 are respectively connected to two sides of the trench gate;

[0052] Two source regions 7 of the first doping type are formed downward from the lower surfaces of the two source region deep trenches, respectively, and the upper surface of the source region 7 is lower than the lower surface of the gate 4;

[0053] Two first doping type ohmic contact regions 2 are formed on the two source regions 7 respectively, and the first doping type ohmic contact regions 2 and the channel region 3 on the same side are connected;

[0054] The source region 7 and the structure between the two source regions 7 in the epitaxial layer form a PN junction.

[0055] When a voltage is applied to the drain of the trench capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application, the current path is as follows: Figure 2-1 As shown by the dotted line in , the current flows out through the drain 11, the substrate 10, the epitaxial layer, the current guiding layer 9, and the channel region 3.

[0056] The gate voltage is greater than the threshold voltage (such as 18V), the gate is turned on, and when the drain voltage is applied, the trench capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is turned on, and the current path is as follows Figure 2-1 As shown by the dotted line in .

[0057] When the drain of the trench capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is subjected to a voltage and the gate is at zero volts:

[0058] As the drain voltage gradually increases:

[0059] On the one hand, the bottom of the second doping type channel region 3 and the corner position of the first doping type ohmic contact region 2 form a PN junction, and the bottom of the channel region 3 and the outermost corner position of the trench gate form a PN junction ( Figure 2-1 The position of the two dotted elliptical rings in the upper middle) extends to the middle of the bottom of the channel region 3 until the guide channel at the bottom of the channel region 3 is pinched off; that is, the PN junction formed by the second doping type channel region 3 and the first doping type ohmic contact region 2, and the PN junction formed by the second doping type channel region 3 and the outermost first doping type of the trench gate are in reverse bias. At this time, the trench-type capacitive-coupled gate-controlled junction field effect transistor is protected (that is, the electric field at the bottom of the two channel regions 3 is reduced to prevent the electric field concentration effect of the channel region 3), the leakage current is reduced, and the withstand voltage is improved, thereby making the trench-type capacitive-coupled gate-controlled junction field effect transistor of the embodiment of the present application more reliable.

[0060] On the other hand, the depletion region of the PN junction formed by the structure located between the two source regions 7 in the source region 7 and the epitaxial layer position expands toward the middle between the two source regions 7 (that is, the electric field will be gathered at the corner of the source region 7 to cause the depletion to expand) until the conduction channel of the structure located between the two source regions 7 in the source region 7 and the epitaxial layer position is pinched off, that is, the PN junction formed by the structure located between the two source regions 7 in the source region 7 and the epitaxial layer position is in reverse bias. At this time, the trench-type capacitive-coupled gate-controlled junction field effect transistor is protected (that is, the electric field at the two source regions 7 is reduced to prevent the electric field concentration effect in the channel region 3), the leakage current is reduced, and the withstand voltage is improved, thereby making the trench-type capacitive-coupled gate-controlled junction field effect transistor of the embodiment of the present application more reliable.

[0061] At this point, the PN junction formed by the source region 7 and the structure between the two source regions 7 in the epitaxial layer, the PN junction formed by the bottom of the second doping type channel region 3 and the corner position of the first doping type ohmic contact region 2, and the PN junction formed by the bottom of the channel region 3 and the outermost corner position of the trench gate can all protect the trench type capacitor-coupled gate-controlled junction field effect transistor (i.e., reduce the electric field in the channel region 3), reduce leakage current, and improve withstand voltage, thereby making the trench type capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the present application highly reliable.

[0062] The trench-type capacitive-coupled gate-controlled junction field effect transistor device of the embodiment of the present application uses a deep source trench to shield the high electric field at the channel, so that for field effect transistors of the same power, the trench-type capacitive-coupled gate-controlled junction field effect transistor of the embodiment of the present application can be smaller in size and have a smaller unit on-resistance.

[0063] Figure 2-2 Schematic diagram of the current path of the trench capacitively coupled gate-controlled junction field effect transistor connected to the source voltage in the embodiment of the present application. Figure 2-2 As shown, when the trench capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the present application is connected to the source voltage, the body diode is turned on, and the current path is as follows Figure 2-2 As shown by the dotted line in , two current paths coexist. Among them, the current in the channel region 3 is related to the device design.

[0064] In implementation, such as Figure 2-1 As shown, the portion of the epitaxial layer located below the outer bottom surface height of the source region 7 is the drift region 8;

[0065] A trench capacitively coupled gate controlled junction field effect transistor, further comprising:

[0066] The current guiding layer 9 is formed by a portion of the epitaxial layer located above the outer bottom surface height of the source region 7, and a portion of the current guiding layer 9 located between the two source regions 7 is a first region 91 of the current guiding layer; that is, a portion of the epitaxial layer located below the trench gate, below the two channel regions 3, between the two first doping type ohmic contact regions 2, and between the two source regions 7 is doped to form the current guiding layer 9;

[0067] The doping concentration of the current guiding layer 9 is greater than that of the epitaxial layer, and the first region 91 of the current guiding layer and the two source regions 7 form a PN junction for shielding the electric field in the channel region.

[0068] The current guiding layer 9 can be formed in the epitaxial layer by an injection process, and the doping concentration of the current guiding layer 9 is greater than the doping concentration of the epitaxial layer. In this way, the flow of carriers in the current guiding layer 9 is easier than that in the epitaxial layer. That is, the on-resistance of the current guiding layer 9 is smaller.

[0069] Since the doping concentration of the current guiding layer 9 is greater than that of the epitaxial layer, the resistance at the current guiding layer 9 is small, so that the on-resistance of the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is small.

[0070] In the case where current guiding layer 9 is not provided, the structure located between two source regions 7 in the epitaxial layer position is the portion of the epitaxial layer located between the two source regions 7 .

[0071] When the current guiding layer 9 is provided, the structure between the two source regions 7 is the current guiding layer first region 91. The two source regions 7 and the current guiding layer first region 91 form a PN junction.

[0072] In implementation, such as Figure 2-1 As shown, the trench gate is a capacitive coupling gate, and the trench gate includes:

[0073] A trench-type gate region 4 is formed downward from the upper surface of the epitaxial layer;

[0074] A trench-type gate dielectric layer 5 is formed on the bottom wall and side wall of the gate region 4;

[0075] The coupling capacitor upper electrode 6 is filled in the space surrounded by the bottom wall and the side wall of the gate dielectric layer 5;

[0076] The gate region 4 is the outermost layer of the trench gate located in the epitaxial layer.

[0077] In implementation, such as Figure 2-1 As shown, the trench type capacitively coupled gate controlled junction field effect transistor also includes:

[0078] Two source metals 1 are formed on the two source regions 7 respectively, and the source metals 1 on the same side are connected to the first doping type ohmic contact region 2;

[0079] Two source contact regions 15 , the two source contact regions 15 are respectively connected to the channel region 3 , and the source contact regions 15 on the same side are connected to the first doping type ohmic contact region 2 .

[0080] like Figure 2-1 As shown, the gate voltage of the trench type capacitive coupled gate controlled junction field effect transistor of the embodiment of the present application is greater than the threshold voltage (such as 18V), the gate is turned on, and when the voltage is applied to the drain, the trench type capacitive coupled gate controlled junction field effect transistor of the embodiment of the present application is turned on, and the current path is as shown in FIG. Figure 2-1 As shown by the dotted line in , the current flows out through the drain 11, the substrate 10, the drift region 8, the current guiding layer 9, the channel region 3, and the source contact region 15.

[0081] In implementation, the ratio of the length of the source region deep trench in the vertical direction to the length of the gate region 4 in the vertical direction is in the range of greater than or equal to 3 / 2 and less than or equal to 2.5.

[0082] The ratio of the length of the source region deep trench in the vertical direction to the length of the gate region 4 in the vertical direction is greater than or equal to 3 / 2 and less than or equal to 2.5, which can better shield the electric field in the channel region and improve the withstand voltage level of the device.

[0083] As a preferred embodiment, the ratio of the length of the source region deep trench in the vertical direction to the length of the gate region 4 in the vertical direction is 2.

[0084] The ratio of the length of the source region deep trench in the vertical direction to the length of the gate region 4 in the vertical direction is 2, which can better shield the electric field in the channel region and improve the withstand voltage level of the device.

[0085] In practice, the doping concentration of the gate region 4 is greater than 10 18 cm -3 The doping concentration of the current guiding layer (9) is greater than or equal to 10 17 cm -3 Less than or equal to 10 18 cm -3 .

[0086] In practice, the doping concentration of the source region 7 is greater than 10 18 cm -3 ;

[0087] The doping concentration of the current guiding layer 9 is greater than or equal to 10 17 cm -3 Less than or equal to 10 18 cm -3 .

[0088] The source region 7 and the current guiding layer 9 form a PN junction to shield the electric field in the channel region.

[0089] In the implementation, the doping concentration of the first doping type ohmic contact region 2 is on the order of 10 16 cm -3 Less than or equal to 10 17 cm -3 ;

[0090] The doping concentration of the channel region 3 is greater than 10 18 cm -3 ;

[0091] The doping concentration of the gate region 4 is greater than 10 18 cm -3 ;

[0092] A PN junction is formed at the corner between the first doping type ohmic contact region 2 and the bottom of the second doping type channel region 3 , and a PN junction is formed at the bottom of the channel region 3 and the corner of the gate region 4 to shield the electric field of the channel region.

[0093] In implementation, the two channel regions 3 are respectively formed at the intervals between the trench gate and the two source region deep trenches, and correspondingly, the source region 7 and the first doping type ohmic contact region 2 on the same side are flush toward the inner side of the trench gate.

[0094] That is, a channel region 3 is formed between the trench-type gate and the source region deep trench, a source region 7 is arranged at the bottom of the source region deep trench, and a first doping type ohmic contact region 2 is formed by deposition on the source region 7 and on the side wall of the source region deep trench close to the channel region 3. In this way, the first doping type ohmic contact region 2 is formed by deposition, so that the depth of the first doping type ohmic contact region 2 can be deeper.

[0095] In the prior art, the first doping type ohmic contact region is usually formed by implantation, which limits the depth of the first doping type ohmic contact region.

[0096] like Figure 1 As shown, the planar gate SiC MOSFET device in the prior art can reduce the electric field of the gate oxide layer 1-6 through the P-type well regions 1-4 on both sides. In order to ensure the same reliability problem, the source trenches on both sides are etched, and P+ is injected into the source trenches to form the P-type well region 1-4 to shield the electric field spike at the bottom of the gate. Among them, the substrate 1-1, the epitaxial layer 1-2, the gate trench 1-31, the trench gate 1-32, the P-type well region 1-4, the source 1-5, and the gate oxide layer 1-6.

[0097] Figure 1 The P-type well regions 1-4 and the source electrodes 1-5 of the present application Figure 2-1 There are essential differences between the source region 7 and the first doping type ohmic contact region 2:

[0098] Prior art Figure 1 A deep source trench is used to shield the electric field of the gate oxide layer 1-6 at the bottom of the gate, thereby ensuring the reliability of the gate oxide layer.

[0099] The present invention relates to a trench type capacitively coupled gate controlled junction field effect transistor ( Figure 2-1 ) uses a deep source trench (i.e., a deep source trench) to shield the electric field in the channel region 3, and the purpose and function are completely different. And due to the characteristics of the patented structure of this application, there is a P+ gate control region (i.e., gate region 4) around the gate dielectric layer 5. During reverse withstand voltage, the electric field will be gathered at the corner of the gate control P+ region (gate region 4), so that a PN junction is formed at the bottom of the second doped type channel region 3, the first doped type ohmic contact region 2, and the bottom of the second doped type channel region 3. The depletion layer of the PN junction formed at the bottom of the second doped type channel region 3 and the outermost corner of the trench gate is further widened, which again prevents the electric field concentration effect in the channel region and improves the reliability of the device. However, in the prior art Figure 1 The structure in is to avoid the concentration of electric field at the corners of the gate. The direction and function of the device design are completely different.

[0100] If the device structure in the prior art is to achieve the same withstand voltage and on-resistance as the trench type capacitive coupled gate controlled junction field effect transistor of the present application, Figure 1 In the prior art devices, deeper P-type implantation is required to form deeper P-type well regions 1-4 to shield the electric field of the channel. Currently, high-energy ion implantation is required to complete deeper P-type implantation. High-energy ion implantation has many disadvantages:

[0101] First, high-energy ion implantation with a diameter greater than 2 microns can cause great damage to the device surface and affect other processes;

[0102] Secondly, very deep injection makes it difficult to control the morphology of the device, which may cause the size of the source 1-5 to be smaller (which will affect the electrical properties), and the impact will become greater if the device is made smaller.

[0103] Therefore, the trench-type capacitively coupled gate-controlled junction field effect transistor of the present application adopts the method of digging a deep groove to form a source region and then performing ion implantation. The source region 7 can be made very deep, the morphology of the device can be better controlled, and the electrical properties will not be affected.

[0104] like Figure 2-1 As shown, the trench capacitively coupled gate-controlled junction field effect transistor of the present application is taken as an example, the first doping type is P type and the second doping type is N type. The device has a symmetrical structure, the source metal 1 is connected to the P type first doping type ohmic contact region 2 and the P type heavily doped source region 7, and the doping concentration of the P type first doping type ohmic contact region 2 is greater than or equal to 10 16 cm -3 Less than or equal to 10 17 cm -3 , the doping concentration of the P-type heavily doped source region 7 is greater than or equal to 10 18 cm -3 .

[0105] Among them, the first doping type ohmic contact region 2, the channel region 3, and the gate region 4 constitute a basic JFET structure, which is controlled by a single gate region 4, and the depletion region change of the PN junction formed by the P-type heavily doped gate region 4 and the N-type channel region 3 controls the opening and closing of the channel region;

[0106] The PN junction formed by the gate region 4 and the channel region 3 together with the gate dielectric layer 5 and the coupling capacitor upper electrode 6 (as the gate electrode) constitute a capacitively coupled gate-controlled JFET structure, and the JFET region is indirectly controlled by the coupling capacitor upper electrode 6 through the gate dielectric layer 5.

[0107] The trench-type capacitor-coupled gate-controlled junction field-effect transistor of the present application can be normally controlled using the gate control circuit of MOSFET, turned on when the gate-source voltage Vgs=18V, turned off when the gate-source voltage Vgs=0V, and has excellent blocking characteristics, and has no adverse effects on the reliability and electrical properties of the gate oxide layer (i.e., the gate dielectric layer 5).

[0108] Specifically, the upper electrode in the field of semiconductor technology refers to the electrode connected to the voltage. The upper electrode of the coupling capacitor is a name defined according to its function. The lower electrode of the coupling capacitor is not a certain specific component, but other parts of the device. In the field of semiconductor technology, the lower electrode of the coupling capacitor is generally not specifically described.

[0109] The following describes a method for preparing a trench capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application in which the first doping type is P-type and the second doping type is N-type in chronological order, and includes the following steps:

[0110] Step 1: After forming an epitaxial layer on the substrate 10, N-type ion implantation is performed based on a hard mask to form a current guiding layer foundation 90, thereby forming a drift region 8; wherein a drain 11 is formed on the back side of the substrate 10;

[0111] Step 2: Perform a second N-type ion implantation based on the hard mask to form a channel region base 120; wherein the channel region base 120 is used to subsequently form a channel region 3;

[0112] Step 3: Perform a third N-type ion implantation based on the hard mask to form a source contact region base 150; Figure 3 As shown;

[0113] Step 4: Etching to form source region trench 14 and gate region trench 13; Figure 4 As shown;

[0114] Step 5: forming a P-type heavily doped source region 7 by implantation based on a mask;

[0115] Step 6: Based on the mask plate, the lower part of the heavily P-type doped gate region 4 is formed by implantation, and the sidewall is implanted at an oblique angle to form the entire heavily P-type doped gate region 4;

[0116] Step 7: forming a first doping type ohmic contact region 2 based on a P-type implantation at an angle on the sidewall of the mask; annealing the impurities and performing ion implantation activation; Figure 5 As shown;

[0117] Step 8: Generate a gate dielectric layer 5, wherein the bottom thickness of the gate dielectric layer ranges from 80 nm to 120 nm, and the side thickness of the gate dielectric layer ranges from 30 nm to 60 nm; Figure 6 As shown;

[0118] Step 9: Deposit metal to form source metal 1 and coupling capacitor upper electrode 6; Figure 7 shown.

[0119] Figure 8 A schematic diagram of the simulation modeling structure of the capacitively coupled gate-controlled junction field effect transistor of the present application.

[0120] Fig. 9 for Figure 8 The forward current density distribution of the capacitively coupled gate-controlled junction field effect transistor is shown in Figure 1. Fig. 9 It can be seen that the on-current flows through the current guiding layer 9 and the channel region 3 .

[0121] Fig.10 for Figure 8 The forward current curve of the capacitively coupled gate controlled junction field effect transistor is shown. Fig.10 The horizontal axis is the drain-source voltage in V, and the vertical axis is the on-current in A. On-resistance = voltage / current, such as Fig.10 As shown, the on-resistance is a fixed value of 2.55mΩ·cm 2 . It is at the same level as the current MOSFET conduction capability on the market.

[0122] Fig.11 for Figure 8 The capacitance-coupled gate-controlled junction field effect transistor shown in the figure is connected to the source voltage, and the on-current density distribution diagram is shown in the figure. Fig.11 It can be seen that the breakdown current flows through the P heavily doped source region 7 below the source trench and does not pass through the channel region 3 and the gate region 4 .

[0123] Fig.12 for Figure 8 The electric field intensity distribution diagram of the capacitively coupled gate-controlled junction field effect transistor during reverse breakdown is shown in Figure 1. Fig.12 From the distribution of the electric field strength, it can be seen that the PN junction formed by the source region 7 and the first region 91 of the current guiding layer bears most of the withstand voltage;

[0124] At the same time, the PN junction formed at the bottom of the second doping type channel region 3 and the corner formed by the first doping type ohmic contact region 2 and the bottom of the second doping type channel region 3 bears a small part of the withstand voltage;

[0125] Therefore, a double shielding effect is achieved, and leakage current in the channel region 3 is greatly reduced.

[0126] Fig.13 for Figure 8 The breakdown voltage curve of the capacitively coupled gate-controlled junction field effect transistor is shown in FIG. Wherein, the horizontal axis is the drain-source voltage in V, the vertical axis is the on-current in A, and BV is the breakdown voltage.

[0127] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0128] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0129] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0130] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0131] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0132] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A trench capacitively coupled gate controlled junction field effect transistor, characterized in that: include: A substrate (10), an epitaxial layer formed on the substrate, and a drain (11) formed on the back side of the substrate; A trench gate is formed downward from the upper surface of the epitaxial layer, and the outermost layer of the trench gate located in the epitaxial layer is a layer structure of the first doping type; Two source region deep trenches are respectively formed on both sides of the trench type gate and are spaced apart from the trench type gate, and the lower surface of the source region deep trench is lower than the lower surface of the trench type gate; Two source regions (7) of the first doping type are formed downward from the lower surfaces of the two source region deep trenches respectively; Two channel regions (3) of the second doping type, the two channel regions (3) being respectively connected to two sides of the trench gate; Two first doping type ohmic contact regions (2) are respectively formed on the two source regions (7), and the first doping type ohmic contact regions (2) and the channel region (3) on the same side are connected; The source region (7) and the structure located between the two source regions (7) in the epitaxial layer form a PN junction.

2. The field effect transistor according to claim 1, characterized in that Also includes: A current guiding layer (9), wherein a portion of the epitaxial layer located above the outer bottom surface height of the source region (7) forms the current guiding layer, and a portion of the current guiding layer (9) located between the two source regions (7) is a first region (91) of the current guiding layer; The doping concentration of the current guiding layer (9) is greater than that of the epitaxial layer, and the first region (91) of the current guiding layer and the two source regions (7) form a PN junction.

3. The field effect transistor according to claim 2, characterized in that: The trench gate is a capacitive coupling gate, and the trench gate comprises: A trench-type gate region (4) formed downward from the upper surface of the epitaxial layer; A trench-type gate dielectric layer (5) formed on the bottom wall and side walls of the gate region (4); A coupling capacitor upper electrode (6) is filled in the space enclosed by the bottom wall and the side wall of the gate dielectric layer (5); The gate region (4) is the outermost layer of the trench gate located in the epitaxial layer.

4. The field effect transistor according to claim 3, characterized in that: The bottom of the second doping type channel region (3) and the corner position of the first doping type ohmic contact region (2) form a PN junction, and the bottom of the channel region (3) and the corner position of the gate region (4) form a PN junction.

5. The field effect transistor according to claim 4, characterized in that: The ratio of the length of the source region deep trench in the vertical direction to the length of the gate region (4) in the vertical direction is in the range of greater than or equal to 3 / 2 and less than or equal to 2.

5.

6. The field effect transistor according to claim 4, characterized in that: The ratio of the length of the source region deep trench in the vertical direction to the length of the gate region (4) in the vertical direction is 2.

7. The field effect transistor according to claim 4, characterized in that: The doping concentration of the source region (7) is greater than 10 18 cm -3 ; The doping concentration of the current guiding layer (9) is greater than or equal to 10 17 cm -3 Less than or equal to 10 18 cm -3 .

8. The field effect transistor according to claim 7, characterized in that: The doping concentration of the first doping type ohmic contact region (2) is on the order of 10 16 cm -3 Less than or equal to 10 17 cm -3 ; The doping concentration of the channel region (3) is greater than 10 18 cm -3 ; The doping concentration of the gate region (4) is greater than 10 18 cm -3 .

9. The field effect transistor according to claim 4, characterized in that: Also includes: Two source metals (1) are respectively formed on the two source regions (7), and the source metals (1) on the same side are connected to the first doping type ohmic contact region (2); Two source contact regions (15), the two source contact regions (15) are respectively connected to the channel region (3), and the source contact region (15) on the same side is connected to the first doping type ohmic contact region (2).

10. The field effect transistor according to claim 4, characterized in that: The two channel regions (3) are respectively formed at the intervals between the trench gate and the two source region deep trenches, and correspondingly, the source region (7) and the first doping type ohmic contact region (2) on the same side are flush with the inner side of the trench gate.

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