Complete machine cable misinsertion detection method, device and equipment and storage medium

Abstract

The invention discloses a complete machine cable misinsertion detection method, device and equipment and a storage medium, and the detection method comprises the steps: controlling a backboard CPLD to transmit preset first pulse signals to a plurality of first connectors, and carrying out the cable numbering of the first pulse signals through the backboard CPLD; each second connector receives a second pulse signal transmitted from the high-speed cable, and the mainboard CPLD performs cable numbering processing on each second pulse signal; and controlling the mainboard BMC to respectively obtain cable numbers of the backboard CPLD and the mainboard CPLD, and judging a detection result according to the obtained cable numbers. Compared with the prior art, error correction can be carried out on the cables in the assembling process of the multiple cables, the single signal line is adopted for wiring, other signal positions do not need to be occupied, the requirement for cable connection detection of production equipment can be met through the mode, the cable detection accuracy is improved, effective reuse of resources can be achieved, and the production cost is reduced. And hardware cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to a method, device, equipment and storage medium for detecting cable misinsertion in a whole machine. Background Art

[0002] In the data center and high-performance computing fields, with the rapid development of technology and the shortening of product iteration cycles, system design has become more and more complex and flexible. These systems usually contain a large number of boards and components, which are interconnected by high-speed cables to achieve high-speed data transmission and signal synchronization. However, while this multi-cable direct connection method brings high efficiency, it also brings the risk of problems such as wrong or missed cable insertion, which are particularly prominent during the assembly and operation and maintenance of the whole machine. Summary of the invention

[0003] The purpose of the present invention is to provide a whole machine cable misinsertion detection method, device, equipment and storage medium, aiming to solve the technical problems of cable misinsertion and missed insertion in existing high-speed cable interconnection.

[0004] In order to solve the above technical problems, the purpose of the present invention is achieved through the following technical solutions:

[0005] A first aspect of the present application provides a method for detecting cable misinsertion of a whole machine, which is applied to a server architecture design. The server architecture is implemented based on a hardware configuration. The hardware configuration includes a server mainboard and a hard disk backplane. The server mainboard includes a mainboard CPLD and a mainboard BMC. The hard disk backplane includes a backplane CPLD. The backplane CPLD is connected to a plurality of first connectors. The mainboard CPLD is connected to a plurality of second connectors. The first connectors are connected to the second connectors one by one through a high-speed cable. The method is characterized in that:

[0006] Controlling the backplane CPLD to send preset first pulse signals to the plurality of first connectors respectively, and the backplane CPLD performs cable numbering processing on the first pulse signals;

[0007] Each of the second connectors receives a second pulse signal transmitted from the high-speed cable, and the mainboard CPLD performs cable numbering processing on each of the second pulse signals;

[0008] The mainboard BMC is controlled to obtain the cable numbers of the backplane CPLD and the mainboard CPLD respectively, and the detection result is determined according to the obtained cable numbers.

[0009] In a possible implementation, controlling the backplane CPLD to send preset first pulse signals to the plurality of first connectors respectively, and the backplane CPLD performing cable numbering processing on each of the first pulse signals includes:

[0010] Setting each of the first pulse signals to have a different pulse width according to the sequence of the first connectors for transmission;

[0011] The pulse width of the first pulse signal is measured by a sampling clock on the backplane CPLD, and different cable numbers are identified according to the measurement results.

[0012] In a possible implementation, measuring the pulse width of the first pulse signal by using a sampling clock on the backplane CPLD, and identifying different cable numbers according to the measurement results, includes:

[0013] sampling the low level width of the first pulse signal received according to the sampling clock;

[0014] Comparing the low level width of the sampled first pulse signal with the clock period of the sampling clock;

[0015] The cables detected by the first connector are sorted and numbered according to the number of clock cycles included in the low level width of the first pulse signal.

[0016] In a possible implementation, each of the second connectors receives a second pulse signal transmitted from the high-speed cable, and each of the mainboard CPLDs performs cable numbering processing on the second pulse signal, including:

[0017] Controlling the mainboard CPLD to analyze the pulse width of the received second pulse signal;

[0018] The pulse width of the second pulse signal is measured by a sampling clock on the mainboard CPLD, and different cable numbers are identified according to the measurement results.

[0019] In a possible implementation, measuring the pulse width of the second pulse signal by using a sampling clock on the mainboard CPLD, and identifying different cable numbers according to the measurement results, including:

[0020] sampling the low level width of the second pulse signal received according to the sampling clock;

[0021] Comparing the low level width of the sampled second pulse signal with the clock period of the sampling clock;

[0022] The cables detected by the second connector are sorted and numbered according to the number of clock cycles included in the low level width of the second pulse signal.

[0023] In a possible implementation, controlling the mainboard BMC to respectively obtain the cable numbers of the backplane CPLD and the mainboard CPLD, and judging the detection result according to the obtained cable numbers includes:

[0024] Determine whether the cable numbers of the backplane CPLD and the mainboard CPLD respectively obtained by the mainboard BMC are the same;

[0025] If they are the same, it is determined that the high-speed cable between the first connector and the second connector is not inserted incorrectly;

[0026] If they are not the same, it is determined that the high-speed cable between the first connector and the second connector is incorrectly plugged in or missing.

[0027] A second aspect of the present application provides a whole-machine cable misplug detection device, which is applied to server architecture design. The server architecture is implemented based on hardware configuration. The hardware configuration includes a server mainboard and a hard disk backplane. The server mainboard includes a mainboard CPLD and a mainboard BMC. The hard disk backplane includes a backplane CPLD. The backplane CPLD is connected to a plurality of first connectors. The mainboard CPLD is connected to a plurality of second connectors. The first connectors are connected to the second connectors one by one through high-speed cables. The device includes:

[0028] A signal sending unit, used for controlling the backplane CPLD to send preset first pulse signals to the plurality of first connectors respectively, and the backplane CPLD performs cable numbering processing on the first pulse signals;

[0029] A signal receiving unit, configured for each of the second connectors to receive a second pulse signal transmitted from the high-speed cable, wherein the mainboard CPLD performs cable numbering processing on each of the second pulse signals;

[0030] The judgment and analysis unit is used to control the mainboard BMC to obtain the cable numbers of the backplane CPLD and the mainboard CPLD respectively, and judge the detection result according to the obtained cable numbers.

[0031] In a possible implementation manner, the signal sending unit includes:

[0032] A signal sending module, used for setting each of the first pulse signals to different pulse widths for sending according to the sequence of the first connectors;

[0033] The signal analysis module 1 is used to measure the pulse width of the first pulse signal through the sampling clock on the backplane CPLD, and identify different cable numbers according to the measurement results.

[0034] A third aspect of the present application provides a computer device, characterized in that the computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the method described in the first aspect when executing the computer program.

[0035] A fourth aspect of the present application provides a computer-readable storage medium, wherein the storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the method described in the first aspect above can be implemented.

[0036] The beneficial effects of the present invention compared with the prior art are as follows: the present invention provides a method for detecting cable misinsertion of a whole machine, including: controlling the backplane CPLD to send a preset first pulse signal to multiple first connectors respectively, and the backplane CPLD performs cable numbering on the first pulse signal; each second connector receives a second pulse signal transmitted from a high-speed cable, and the mainboard CPLD performs cable numbering on each second pulse signal; controlling the mainboard BMC to obtain the cable numbers of the backplane CPLD and the mainboard CPLD respectively, and judging the detection result according to the obtained cable numbers. Compared with the prior art, the present invention is composed of a general high-speed cable and a CPLD device to form a rapid detection system, and the backplane end CPLD sends a clock pulse signal, and the mainboard CPLD receives a pulse signal as a basis for comparison data, so as to realize cable error correction during the assembly of multiple cables, and a single signal line is used for routing without occupying other signal positions. This method can not only meet the needs of production equipment to detect cable connections and improve the accuracy of cable detection, but also realize effective resource reuse and reduce hardware costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0038] Figure 1 A schematic diagram of the hardware framework structure of the whole machine cable misinsertion detection device provided by an embodiment of the present invention;

[0039] Figure 2 Schematic diagram of the process of the whole machine cable misinsertion detection method provided by the embodiment of the present invention Figure 1 ;

[0040] Figure 3 Schematic diagram of the process of the whole machine cable misinsertion detection method provided by the embodiment of the present invention Figure 2 ;

[0041] Figure 4A schematic diagram of pulse signals and sampling clock signal pulses in a method for detecting cable misinsertion in a whole machine provided by an embodiment of the present invention;

[0042] Figure 5 Schematic diagram of the process of the whole machine cable misinsertion detection method provided by the embodiment of the present invention Figure 3 ;

[0043] Figure 6 Schematic diagram of the process of the whole machine cable misinsertion detection method provided by the embodiment of the present invention Figure 4 ;

[0044] Figure 7 Schematic diagram of the process of the whole machine cable misinsertion detection method provided by the embodiment of the present invention Figure 5 ;

[0045] Figure 8 Schematic diagram of the process of the whole machine cable misinsertion detection method provided by the embodiment of the present invention Figure 6 ;

[0046] Fig. 9 A connector pin diagram of the whole machine cable misinsertion detection device provided by an embodiment of the present invention;

[0047] Fig.10 A schematic diagram of a method for detecting cable mis-insertion in a whole machine provided by an embodiment of the present invention;

[0048] Fig.11 A schematic block diagram of a whole machine cable misinsertion detection device provided by an embodiment of the present invention;

[0049] Fig.12 A schematic block diagram of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0052] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0053] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0054] The embodiments of the present application provide a method, device, equipment and storage medium for detecting cable misinsertion in a whole machine.

[0055] The executor of the whole-machine cable misplugging detection method may be the whole-machine cable misplugging detection device provided in the embodiment of the present application, or a computer device integrating the whole-machine cable misplugging detection device, wherein the whole-machine cable misplugging detection device may be implemented in hardware or software, the computer device may be a terminal or a server, and the terminal may be a smart phone, a tablet computer, a PDA, or a laptop computer, etc.

[0056] Figure 1 Schematic diagram of the hardware framework structure of the whole machine cable misplug detection device provided by the embodiment of the present application. Figure 1 As shown, the hardware configuration includes: a server mainboard and a hard disk backplane, the server mainboard includes a mainboard CPLD and a mainboard BMC, the hard disk backplane includes a backplane CPLD, the backplane CPLD is connected to multiple first connectors, the mainboard CPLD is connected to multiple second connectors, and the first connectors and the second connectors are connected one by one through high-speed cables.

[0057] Specifically, Fig. 9 As shown, in this embodiment, in order to meet the needs of detecting cable connections of production equipment, the hard disk backplane and the server motherboard are directly connected by cable to perform a cable connection test. The MCIO interface on the existing server motherboard does not have a signal definition for cable connection detection. The original CPRSNTB# signal defines the presence information of the PCIE device, but in the hard disk backplane design, the hard disk presence information has been processed by the backplane CPLD and does not need to be passed to the motherboard for processing. Therefore, the CPRSNTB# signal is used as a cable detection signal without occupying other signal positions, avoiding the need to introduce a new signal line separately for cable connection detection, thereby simplifying system design and wiring complexity, and also reducing hardware costs.

[0058] The server motherboard and the hard disk backplane are both equipped with MCIO interfaces. The first connector and the second connector are respectively connected to the MCIO interfaces to realize the signal communication between the motherboard CPLD and the backplane CPLD. In order to realize the detection signal transmission in the system, the pin pins of the first connector and the second connector are defined as follows: Fig. 9 As shown in the figure, the B27 pin is defined as the cable detection signal pin. The entire system has unified specifications and is implemented accordingly.

[0059] In the system, the backplane CPLD assigns a unique pulse width signal to each MCIO interface. This pulse width signal serves as the "identity mark" of the cable and is used to distinguish different cables during signal transmission. As the transmission medium of the signal, the high-speed cable transmits the pulse width signal generated by the backplane CPLD to the mainboard CPLD. Under normal circumstances, each cable is connected to a specific backplane MCIO interface and a mainboard MCIO interface to form a fixed transmission path. The mainboard CPLD uses the same sampling clock to detect the low-level width (i.e., pulse width) of the received signal. Based on the pulse width, the mainboard CPLD can identify which cable is connected to which interface on the mainboard and mark the cable number accordingly. The mainboard BMC determines whether the cable is plugged in incorrectly or not by checking the cable detection results collected from the mainboard CPLD and the backplane CPLD.

[0060] Figure 2 This is a schematic diagram of the process of the whole machine cable misplug detection method provided by the embodiment of the present application Figure 1 .like Figure 2 As shown, the method includes the following steps S110-S130.

[0061] S110, controlling the backplane CPLD to send preset first pulse signals to the multiple first connectors respectively, and the backplane CPLD performs cable numbering processing on the first pulse signals;

[0062] Specifically, after the system is started or reset, the backplane CPLD is initialized and prepares to send a preset first pulse signal. The backplane CPLD generates multiple first pulse signals according to a preset sequence or pattern. These pulse signals are simple level changes, such as high level to low level, which are used to identify different cables or channels. For each first pulse signal, the backplane CPLD will attach a unique cable number, which is implemented through internal logic to ensure that each pulse signal can be uniquely identified to its corresponding cable or channel. The backplane CPLD sends the pulse signals with cable numbers to the high-speed cables connected to each of them through multiple first connectors (such as slots, ports, etc.).

[0063] S120, each second connector receives a second pulse signal transmitted from the high-speed cable, and the mainboard CPLD performs cable numbering processing on each second pulse signal;

[0064] Specifically, each second connector receives a second pulse signal transmitted from the high-speed cable. The second pulse signal is the result of the first pulse signal sent by the backplane CPLD being transmitted through the high-speed cable. The second connector performs level conversion or format adjustment on the received signal to ensure that the mainboard CPLD can correctly identify it. After the mainboard CPLD receives the second pulse signal, it also performs cable numbering processing.

[0065] S130 , controlling the mainboard BMC to obtain the cable numbers of the backplane CPLD and the mainboard CPLD respectively, and determining the detection result according to the obtained cable numbers.

[0066] Specifically, the motherboard BMC reads the stored cable number information from the backplane CPLD and the motherboard CPLD respectively. The motherboard BMC compares the cable number sent by the backplane CPLD with the cable number received by the motherboard CPLD. If the two match, it means that the cable is connected correctly; if they do not match, it may indicate that the cable is connected incorrectly or the cable is damaged. The BMC records the comparison results and feeds back the detection results to the system administrator or user as needed. If an error is detected, an alarm can be triggered or other corrective measures can be taken.

[0067] like Figure 3 As shown, in a more specific embodiment, executing step S110 further specifically includes executing steps S111 - S112 .

[0068] S111, setting each first pulse signal to a different pulse width according to a sequence of the first connector for transmission;

[0069] S112: Measure the pulse width of each first pulse signal by using a sampling clock on the backplane CPLD, and identify different cable numbers according to the measurement results.

[0070] Specifically, Figure 4 As shown, during the programming or configuration phase of the backplane CPLD, a pulse width sequence corresponding to the first connector sequence is defined. For example, the system has six first connectors, and the pulse widths are defined as a sequence of 2 clock cycles, 3 clock cycles, ..., 7 clock cycles. The backplane CPLD generates a first pulse signal of a corresponding width for each first connector according to the defined pulse width sequence. The backplane CPLD sends the generated pulse signal to the high-speed cable connected to it through each first connector. The pulse signal sent by each connector has a unique pulse width, which is used to identify the first connector and the cable connected to it.

[0071] like Figure 5 As shown, in a more specific embodiment, executing step S112 further specifically includes executing steps S1121-S1123.

[0072] S1121, sampling the low level width of the received first pulse signal according to the sampling clock;

[0073] S1122, comparing the low level width of the sampled first pulse signal with the clock period of the sampling clock;

[0074] S1123. Sort and number the cables detected by the first connector according to the number of clock cycles contained in the low level width of the first pulse signal.

[0075] like Figure 6 As shown, in a more specific embodiment, executing step S120 further specifically includes executing steps S121-S122.

[0076] S121, controlling the main board CPLD to analyze the pulse width of the received second pulse signal;

[0077] S122, measuring the pulse width of the second pulse signal by using the sampling clock on the mainboard CPLD, and identifying different cable numbers according to the measurement results.

[0078] Specifically, the mainboard CPLD receives a second pulse signal transmitted from the high-speed cable to the second connector through its input pin. The mainboard CPLD and the backplane CPLD are configured with the same sampling clock. The internal logic of the mainboard CPLD measures the pulse width of the sampled second pulse signal according to the sampling clock period. Through the pulse width measurement, the mainboard CPLD can identify the measurement result to number the high-speed cable at the second connector.

[0079] like Figure 7 As shown, in a more specific embodiment, executing step S122 further specifically includes executing steps S1221-S1222.

[0080] S1221, sampling the low level width of the received second pulse signal according to the sampling clock;

[0081] S1222, comparing the low level width of the sampled second pulse signal with the clock period of the sampling clock;

[0082] S1223. Sort and number the cables detected by the second connector according to the number of clock cycles contained in the low level width of the second pulse signal.

[0083] like Figure 8 As shown, in a more specific embodiment, executing step S130 further specifically includes executing steps S131-S133.

[0084] S131, determining whether the cable numbers of the backplane CPLD and the mainboard CPLD respectively obtained by the mainboard BMC are the same;

[0085] S132: If they are the same, determine that the high-speed cable between the first connector and the second connector is not incorrectly plugged in;

[0086] S133: If they are not the same, it is determined that the high-speed cable between the first connector and the second connector is incorrectly plugged in or missing.

[0087] Specifically, Fig.10 As shown, the motherboard BMC confirms whether the high-speed cable between the connectors is plugged in incorrectly by comparing the difference between the pre-designed cable number and the cable number detected at the second connector interface. If the cable numbers of the two are the same, it indicates that the cable connection between the connectors is correct; if the cable numbers are different, it indicates that there is an error in the cable connection between the connectors. The main reasons for the error are: cable damage, cable plugging error, and missing plugging.

[0088] Fig.11 is a schematic block diagram of a whole machine cable misplug detection device provided by an embodiment of the present application. Fig.11 As shown, corresponding to the above whole machine cable misplugging detection method, the present application also provides a whole machine cable misplugging detection device 200. The whole machine cable misplugging detection device 200 includes a unit for executing the above whole machine cable misplugging detection method, and the device can be configured in a desktop computer, tablet computer, laptop computer, etc.

[0089] Specifically, see Fig.11 The whole machine cable misinsertion detection device 200 comprises:

[0090] A signal sending unit 210, used for controlling the backplane CPLD to send preset first pulse signals to the plurality of first connectors respectively, and the backplane CPLD performs cable numbering processing on the first pulse signals;

[0091] The signal receiving unit 220 is used for each second connector to receive a second pulse signal transmitted from the high-speed cable, and the mainboard CPLD performs cable numbering processing on each second pulse signal;

[0092] The judgment and analysis unit 230 is used to control the mainboard BMC to obtain the cable numbers of the backplane CPLD and the mainboard CPLD respectively, and judge the detection result according to the obtained cable numbers.

[0093] In addition, more specifically, the signal sending unit 210 also includes a signal sending module 211, which is used to set each first pulse signal to a different pulse width according to the sequence of the first connector for sending; a signal analysis module 212, which is used to measure the pulse width of the first pulse signal through the sampling clock on the backplane CPLD, and identify different cable numbers according to the measurement results.

[0094] The signal analysis module 212 includes: sampling the low level width of the first pulse signal received according to the sampling clock; comparing the low level width of the sampled first pulse signal with the clock period of the sampling clock; and sorting and numbering the cables detected by the first connector according to the number of clock periods contained in the low level width of the first pulse signal.

[0095] The signal receiving unit 220 includes a signal receiving module 221, which is used to control the mainboard CPLD to analyze the pulse width of the received second pulse signal; a signal analysis module 222, which is used to measure the pulse width of the second pulse signal through the sampling clock on the mainboard CPLD, and identify different cable numbers according to the measurement results.

[0096] Signal analysis module two includes: sampling the low level width of the second pulse signal received according to the sampling clock; comparing the low level width of the sampled second pulse signal with the clock period of the sampling clock; and sorting and numbering the cables detected by the second connector according to the number of clock periods contained in the low level width of the second pulse signal.

[0097] The judgment and analysis unit 230 includes a judgment module 231, which is used to judge whether the cable numbers of the backplane CPLD and the mainboard CPLD obtained by the mainboard BMC are the same; if they are the same, it is determined that the high-speed cable between the first connector and the second connector is not incorrectly plugged in; if they are not the same, it is determined that the high-speed cable between the first connector and the second connector is incorrectly plugged in or missing.

[0098] It should be noted that technicians in the relevant field can clearly understand that the specific implementation process of the above-mentioned whole-machine cable misinsertion detection device and each unit can refer to the corresponding description in the aforementioned method embodiment, and for the convenience and brevity of description, it will not be repeated here.

[0099] The above-mentioned whole machine cable misinsertion detection device 200 can be implemented in the form of a computer program. The computer program can be used in Fig.12 Runs on the computer device shown.

[0100] See also Fig.12 , Fig.12 300 is a schematic block diagram of a computer device provided in an embodiment of the present application. The computer device 300 may be a terminal or a server, wherein the terminal may be an electronic device with communication functions such as a smart phone, a tablet computer, a laptop computer, a desktop computer, a personal digital assistant, and a wearable device. The server may be an independent server or a server cluster composed of multiple servers.

[0101] See also Fig.12The computer device 300 includes a processor 302 , a memory and a network interface 305 connected via a system bus 301 , wherein the memory may include a non-volatile storage medium 303 and an internal memory 304 .

[0102] The non-volatile storage medium 303 can store an operating system 3031 and a computer program 3032. The computer program 3032 includes program instructions, and when the program instructions are executed, the processor 302 can execute a method for detecting cable misinsertion in a whole machine.

[0103] The processor 302 is used to provide computing and control capabilities to support the operation of the entire computer device 300 .

[0104] The internal memory 304 provides an environment for the operation of the computer program 3032 in the non-volatile storage medium 303. When the computer program 3032 is executed by the processor 302, the processor 302 can execute a method for detecting cable misinsertion of the entire machine.

[0105] The network interface 305 is used to communicate with other devices over the network. Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device 300 to which the solution of the present application is applied. The specific computer device 300 may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0106] It should be understood that in the embodiment of the present application, the processor 302 may be a central processing unit (CPU), and the processor 302 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0107] It can be understood by those skilled in the art that all or part of the processes in the method for implementing the above embodiment can be completed by instructing the relevant hardware through a computer program. The computer program includes program instructions, and the computer program can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiment of the above method.

[0108] Therefore, the present application also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor, the processor executes the following steps:

[0109] The control backplane CPLD sends preset first pulse signals to the plurality of first connectors respectively, and the backplane CPLD performs cable numbering processing on the first pulse signals;

[0110] Each second connector receives a second pulse signal transmitted from the high-speed cable, and the mainboard CPLD performs cable numbering processing on each second pulse signal;

[0111] The control mainboard BMC obtains the cable numbers of the backplane CPLD and the mainboard CPLD respectively, and determines the detection result according to the obtained cable numbers.

[0112] The storage medium may be any computer-readable storage medium that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk.

[0113] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0114] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of each unit is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0115] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs. The units in the device of the embodiment of the present application can be combined, divided and deleted according to actual needs. In addition, the functional units in the various embodiments of the present application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0116] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, terminal, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present application.

[0117] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for detecting cable mis-insertion in a whole machine, characterized in that: Applied to server architecture design, the server architecture is implemented based on hardware configuration, the hardware configuration includes a server mainboard and a hard disk backplane, the server mainboard includes a mainboard CPLD and a mainboard BMC, the hard disk backplane includes a backplane CPLD, the backplane CPLD is connected to a plurality of first connectors, the mainboard CPLD is connected to a plurality of second connectors, and the first connectors are connected to the second connectors one by one through high-speed cables; the method includes: Controlling the backplane CPLD to send preset first pulse signals to the plurality of first connectors respectively, and the backplane CPLD performs cable numbering processing on the first pulse signals; Each of the second connectors receives a second pulse signal transmitted from the high-speed cable, and the mainboard CPLD performs cable numbering processing on each of the second pulse signals; The mainboard BMC is controlled to obtain the cable numbers of the backplane CPLD and the mainboard CPLD respectively, and the detection result is determined according to the obtained cable numbers.

2. The whole machine cable misinsertion detection method according to claim 1, characterized in that: Controlling the backplane CPLD to send preset first pulse signals to the plurality of first connectors respectively, wherein the backplane CPLD performs cable numbering processing on each of the first pulse signals, including: Setting each of the first pulse signals to have a different pulse width according to the sequence of the first connectors for transmission; The pulse width of the first pulse signal is measured by a sampling clock on the backplane CPLD, and different cable numbers are identified according to the measurement results.

3. The whole machine cable misinsertion detection method according to claim 2, characterized in that: The pulse width of the first pulse signal is measured by a sampling clock on the backplane CPLD, and different cable numbers are identified according to the measurement results, including: sampling the low level width of the first pulse signal received according to the sampling clock; Comparing the low level width of the sampled first pulse signal with the clock period of the sampling clock; The cables detected by the first connector are sorted and numbered according to the number of clock cycles included in the low level width of the first pulse signal.

4. The whole machine cable misinsertion detection method according to claim 1, characterized in that: Each of the second connectors receives a second pulse signal transmitted from the high-speed cable, and each of the mainboard CPLDs performs cable numbering processing on the second pulse signal, including: Controlling the mainboard CPLD to analyze the pulse width of the received second pulse signal; The pulse width of the second pulse signal is measured by a sampling clock on the mainboard CPLD, and different cable numbers are identified according to the measurement results.

5. The whole machine cable misinsertion detection method according to claim 4, characterized in that: The pulse width of the second pulse signal is measured by a sampling clock on the mainboard CPLD, and different cable numbers are identified according to the measurement results, including: sampling the low level width of the second pulse signal received according to the sampling clock; Comparing the low level width of the sampled second pulse signal with the clock period of the sampling clock; The cables detected by the second connector are sorted and numbered according to the number of clock cycles included in the low level width of the second pulse signal.

6. The method for detecting cable misinsertion of a whole machine according to claim 1, characterized in that: Controlling the mainboard BMC to respectively obtain the cable numbers of the backplane CPLD and the mainboard CPLD, and judging the detection result according to the obtained cable numbers, including: Determine whether the cable numbers of the backplane CPLD and the mainboard CPLD respectively obtained by the mainboard BMC are the same; If they are the same, it is determined that the high-speed cable between the first connector and the second connector is not inserted incorrectly; If they are not the same, it is determined that the high-speed cable between the first connector and the second connector is incorrectly plugged in or missing.

7. A whole machine cable mis-insertion detection device, characterized in that: Applied to server architecture design, the server architecture is implemented based on hardware configuration, the hardware configuration includes a server mainboard and a hard disk backplane, the server mainboard includes a mainboard CPLD and a mainboard BMC, the hard disk backplane includes a backplane CPLD, the backplane CPLD is connected to a plurality of first connectors, the mainboard CPLD is connected to a plurality of second connectors, the first connectors are connected to the second connectors one by one through a high-speed cable, and the device includes: A signal sending unit, used for controlling the backplane CPLD to send preset first pulse signals to the plurality of first connectors respectively, and the backplane CPLD performs cable numbering processing on the first pulse signals; A signal receiving unit, configured for each of the second connectors to receive a second pulse signal transmitted from the high-speed cable, wherein the mainboard CPLD performs cable numbering processing on each of the second pulse signals; The judgment and analysis unit is used to control the mainboard BMC to obtain the cable numbers of the backplane CPLD and the mainboard CPLD respectively, and judge the detection result according to the obtained cable numbers.

8. The whole machine cable misinsertion detection device according to claim 7, characterized in that: The signal sending unit comprises: A signal sending module, used for setting each of the first pulse signals to different pulse widths for sending according to the sequence of the first connectors; The signal analysis module 1 is used to measure the pulse width of the first pulse signal through the sampling clock on the backplane CPLD, and identify different cable numbers according to the measurement results.

9. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 6 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the method according to any one of claims 1 to 6 can be implemented.

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