A reference voltage generator and its manufacturing method

Abstract

The present invention discloses a reference voltage generating circuit and a method for manufacturing the same. The circuit includes a first enhancement-mode MOS transistor and a Schottky diode connected in series between a first power supply voltage terminal and a second power supply voltage terminal. The connection end of the first enhancement-mode MOS transistor and the Schottky diode serves as the output end of the reference voltage generating circuit. The first enhancement-mode MOS transistor is configured to operate in a subthreshold region. The output current of the first enhancement-mode MOS transistor is positively correlated with temperature, and the voltage of the Schottky diode is negatively correlated with temperature, so that the output end of the reference voltage generating circuit outputs a stable reference voltage. Utilizing the above circuit structure, by operating the first enhancement-mode MOS transistor in the subthreshold region, the reference voltage generated by the circuit is insensitive to temperature changes, ensuring that a stable reference voltage can be generated even at high temperatures. This improves the stability of the reference voltage generating circuit, makes it compact and easy to integrate, and reduces the on-resistance of the first enhancement-mode MOS transistor and circuit losses.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a reference voltage generator and a manufacturing method thereof. Background Art

[0002] With the development of GaN devices and processes, more and more GaN integrated circuits have been introduced. Integrated circuits often require multiple reference voltages of varying values ​​to ensure proper circuit function. However, the typical supply voltage for integrated circuits is 48V, which cannot meet the power requirements of some GaN circuits. Therefore, GaN reference voltage generators are needed to generate different reference voltages to ensure the proper operation of different GaN circuits.

[0003] Existing GaN-based reference voltage generators include enhancement-mode and depletion-mode GaN devices fabricated using etching techniques. Temperature compensation is achieved by ensuring that the absolute value of the threshold change of the enhancement-mode and depletion-mode GaN devices is the same at high temperatures. However, both enhancement-mode and depletion-mode GaN devices operate in the saturation region, and etching can cause channel damage during fabrication. The resulting GaN devices also have a high on-resistance, resulting in significant power loss and making it difficult to generate a stable reference voltage at high temperatures. Summary of the Invention

[0004] The present invention provides a reference voltage generator and a preparation method thereof. By operating a first enhancement-mode MOS transistor in a subthreshold region, the current of the first enhancement-mode MOS transistor is positively correlated with temperature. In combination with the fact that the voltage of a Schottky diode is negatively correlated with temperature, the temperature compensation principle is utilized to make the generated reference voltage insensitive to temperature changes, thereby ensuring that a stable reference voltage can still be generated at high temperatures, improving the stability of the reference voltage generating circuit, and achieving small size and easy integration. At the same time, the on-resistance and circuit loss of the first enhancement-mode MOS transistor are reduced.

[0005] In a first aspect, the present invention provides a reference voltage generating circuit, comprising a first enhancement mode MOS transistor and a Schottky diode connected in series between a first power supply voltage terminal and a second power supply voltage terminal, wherein the connection end of the first enhancement mode MOS transistor and the Schottky diode serves as an output end of the reference voltage generating circuit;

[0006] The first enhancement mode MOS transistor is configured to operate in a subthreshold region;

[0007] The inverse of the threshold voltage of the first enhancement mode MOS transistor is positively correlated with the temperature, and the voltage of the Schottky diode is negatively correlated with the temperature, so that the output end of the reference voltage generating circuit outputs a stable reference voltage.

[0008] Optionally, the reference voltage generating circuit further includes a PN junction diode;

[0009] The input end of the PN junction diode is electrically connected to the second electrode of the first enhancement mode MOS transistor, and the input end of the PN junction diode is electrically connected to the input end of the Schottky diode.

[0010] Optionally, the reference voltage generating circuit includes a second enhancement mode MOS transistor;

[0011] The first electrode of the first enhancement mode MOS transistor is electrically connected to the first power supply voltage terminal, and the second electrode is electrically connected to the gate of the second enhancement mode MOS transistor and serves as the output terminal of the reference voltage generating circuit;

[0012] The first electrode and the second electrode of the second enhancement mode MOS transistor are electrically connected to form a Schottky diode and a PN junction diode.

[0013] Optionally, the gate of the first enhancement mode MOS transistor receives a bias voltage signal, and the bias voltage signal is configured to control the first enhancement mode MOS transistor to operate in a subthreshold region.

[0014] Optionally, the bias voltage signal Vbias satisfies: 1V≤Vbias≤1.5V.

[0015] Optionally, the second power supply voltage is a ground voltage.

[0016] In a second aspect, the present invention provides a method for preparing a reference voltage generating circuit, comprising:

[0017] preparing a first enhancement mode MOS transistor;

[0018] Preparation of Schottky diodes;

[0019] The first enhancement mode MOS transistor and the Schottky diode are electrically connected and connected in series between the first power supply voltage terminal and the second power supply voltage terminal, and the connection end of the first enhancement mode MOS transistor and the Schottky diode serves as the output end of the reference voltage generating circuit;

[0020] The first enhancement-mode MOS transistor is configured to operate in a subthreshold region; the inverse of the threshold voltage of the first enhancement-mode MOS transistor is positively correlated with temperature, and the voltage of the Schottky diode is negatively correlated with temperature, so that the output end of the reference voltage generating circuit outputs a stable reference voltage.

[0021] Optionally, the reference voltage generating circuit includes a second enhancement mode MOS transistor;

[0022] A Schottky diode is prepared, comprising:

[0023] preparing a second enhancement mode MOS transistor;

[0024] electrically connecting the first electrode and the second electrode of the second enhancement mode MOS transistor to form a Schottky diode and a PN junction diode connected in series at the gate of the second enhancement mode MOS transistor;

[0025] The first enhancement mode MOS transistor and the Schottky diode are electrically connected and connected in series between the first power supply voltage terminal and the second power supply voltage terminal, and the connection end of the first enhancement mode MOS transistor and the Schottky diode serves as the output end of the reference voltage generating circuit, including:

[0026] The first enhancement mode MOS transistor and the second enhancement mode MOS transistor are electrically connected and connected in series between the first power supply voltage terminal and the second power supply voltage terminal. The connection end of the first enhancement mode MOS transistor and the second enhancement mode MOS transistor serves as the output end of the reference voltage generating circuit.

[0027] Optionally, preparing the first enhancement mode MOS transistor and preparing the second enhancement mode MOS transistor are performed simultaneously;

[0028] The method of preparing a first enhancement-mode MOS transistor and preparing a second enhancement-mode MOS transistor includes:

[0029] Providing a substrate, and sequentially depositing a buffer layer, a barrier layer, and a p-GaN layer on the surface of the substrate;

[0030] Etching the buffer layer, the barrier layer, and the p-GaN layer respectively to form an active region of the first enhancement-mode MOS transistor and an active region of the second enhancement-mode MOS transistor;

[0031] Performing a secondary etching on the etched p-GaN layer to remove the p-GaN layer outside the gate region of the first enhancement mode MOS transistor and the p-GaN layer outside the gate region of the second enhancement mode MOS transistor, while exposing the first and second electrode regions of the first enhancement mode MOS transistor and the first and second electrode regions of the second enhancement mode MOS transistor;

[0032] A gate isolation layer is deposited on the active region of the first enhancement mode MOS transistor and the active region of the second enhancement mode MOS transistor on a side away from the substrate;

[0033] Opening holes in the gate isolation layer so that the openings are aligned with the gate region, the first electrode region, and the second electrode region of the first enhancement-mode MOS transistor, and the gate region, the first electrode region, and the second electrode region of the second enhancement-mode MOS transistor;

[0034] Depositing ohmic metal on the first and second electrode regions of the first enhancement mode MOS transistor, and on the first and second electrode regions of the second enhancement mode MOS transistor, away from the substrate, so that the ohmic metal and the barrier layer form ohmic contacts of the first enhancement mode MOS transistor and ohmic contacts of the second enhancement mode MOS transistor;

[0035] Gate metal is deposited on the gate region of the first enhancement mode MOS transistor and the gate region of the second enhancement mode MOS transistor to form the gate of the first enhancement mode MOS transistor and the gate of the second enhancement mode MOS transistor, so as to form the first enhancement mode MOS transistor and the second enhancement mode MOS transistor.

[0036] Optionally, connecting the first electrode and the second electrode of the second enhancement mode MOS transistor and electrically connecting the first enhancement mode MOS transistor and the Schottky diode are performed simultaneously;

[0037] Connecting the first electrode and the second electrode of the second enhancement mode MOS transistor and electrically connecting the first enhancement mode MOS transistor and the Schottky diode includes:

[0038] A passivation layer is deposited on the surface of the first enhancement mode MOS transistor and the second enhancement mode MOS transistor away from the substrate;

[0039] Etching the passivation layer to expose the gate, the first electrode, and the second electrode of the first enhancement-mode MOS transistor, and the gate, the first electrode, and the second electrode of the second enhancement-mode MOS transistor;

[0040] A conductive metal layer is deposited on the exposed surfaces of the gate, first electrode, and second electrode of the first enhancement-mode MOS transistor, as well as the gate, first electrode, and second electrode of the second enhancement-mode MOS transistor, which are away from the substrate, so that the second electrode of the first enhancement-mode MOS transistor is electrically connected to the gate of the second enhancement-mode MOS transistor and connected in series between the first power supply voltage terminal and the second power supply voltage terminal, and the first electrode of the second enhancement-mode MOS transistor is electrically connected to the second electrode of the second enhancement-mode MOS transistor.

[0041] The technical solution of the present invention connects a first enhancement-mode MOS transistor and a Schottky diode in series between a first power supply voltage terminal and a second power supply voltage terminal, and uses the connection end of the first enhancement-mode MOS transistor and the Schottky diode as the output end of a reference voltage generation circuit, so that the first enhancement-mode MOS transistor operates in a subthreshold region. When the temperature rises, the characteristic curve of the Schottky diode shifts leftward, i.e., the voltage at the output end of the reference voltage generation circuit decreases, achieving negative temperature compensation. Simultaneously, the current of the first enhancement-mode MOS transistor increases, achieving positive temperature compensation. As the current increases, the voltage of the Schottky diode slowly increases, gradually offsetting the voltage drop caused by the leftward shift of the Schottky diode characteristic curve when the temperature rises, and ultimately becoming equal to the voltage at the output end of the reference voltage generation circuit. Utilizing this structure, the generated reference voltage is insensitive to temperature changes, ensuring that a stable reference voltage can be generated even at high temperatures, improving the stability of the reference voltage generation circuit, and making it compact and easy to integrate, while also reducing the on-resistance of the first enhancement-mode MOS transistor and circuit losses.

[0042] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 A schematic structural diagram of a reference voltage generating circuit provided by an embodiment of the present invention;

[0045] Figure 2 A schematic structural diagram of a second reference voltage generating circuit provided by an embodiment of the present invention;

[0046] Figure 3 A schematic structural diagram of a third reference voltage generating circuit provided by an embodiment of the present invention;

[0047] Figure 4 A flowchart of a method for preparing a reference voltage generating circuit provided by an embodiment of the present invention;

[0048] Figure 5 A flowchart of a method for preparing a second reference voltage generating circuit provided by an embodiment of the present invention;

[0049] Figure 6 A flowchart of a method for preparing a third reference voltage generating circuit provided by an embodiment of the present invention;

[0050] Figure 7 The present invention provides a flowchart of a process for preparing a reference voltage generating circuit. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] In one embodiment, Figure 1 This is a schematic diagram of a reference voltage generating circuit provided by an embodiment of the present invention. This embodiment is applicable to the case where a stable reference voltage output is ensured at high temperatures. Figure 1 As shown, the circuit includes a first enhancement mode MOS transistor M1 and a Schottky diode N1 connected in series between a first power supply voltage terminal VDD and a second power supply voltage terminal GND. The connection terminal of the first enhancement mode MOS transistor M1 and the Schottky diode N1 serves as an output terminal Vref of a reference voltage generating circuit. The first enhancement mode MOS transistor M1 is configured to operate in a subthreshold region. The inverse of the threshold voltage of the first enhancement mode MOS transistor is positively correlated with temperature, and the voltage of the Schottky diode is negatively correlated with temperature, so that the output terminal of the reference voltage generating circuit outputs a stable reference voltage Vref.

[0054] The first power supply voltage terminal VDD is used to provide an operating voltage to the first enhancement-mode MOS transistor M1 and the Schottky diode N1. In this embodiment, the first power supply voltage terminal VDD can be the positive electrode of the power supply, and the second power supply voltage terminal GND can be the negative electrode of the power supply. The second power supply voltage terminal GND is ground voltage. Therefore, the first power supply voltage terminal VDD, the second power supply voltage terminal GND, the first enhancement-mode MOS transistor M1, and the Schottky diode N1 form a complete circuit. The first enhancement-mode MOS transistor M1 is a field-effect transistor that only conducts when the voltage between the gate and the first electrode exceeds the turn-on voltage. In this embodiment, the first enhancement-mode MOS transistor M1 is an NMOS transistor and utilizes a p-type gallium nitride substrate. P-type gallium nitride substrates have the characteristic of high-voltage operation and can operate stably at 0 to 100V. Furthermore, due to the inherent high-temperature resistance of gallium nitride, p-type gallium nitride substrates can operate within a temperature range of 0 to 300°C. Schottky diode N1, short for Schottky Barrier Diode (SBD), is a hot-carrier diode. It utilizes the metal-semiconductor junction principle formed by the contact between metal and semiconductor to create a low-power, high-current, ultra-high-speed semiconductor device. Its forward conduction voltage drop is small, meaning that large current changes result in small voltage changes, thus providing a clamping effect. The subthreshold region is the operating area of ​​the first enhancement-mode MOS transistor M1. The bias voltage connected to the gate of the first enhancement-mode MOS transistor M1 can be adjusted to maintain stable operation in the subthreshold region.

[0055] Specifically, the connection terminal of the first enhancement-mode MOS transistor M1 and the Schottky diode N1 serves as the output terminal of the reference voltage generating circuit. To ensure that the output terminal of the reference voltage generating circuit can output a stable reference voltage Vref, in this embodiment, the first enhancement-mode MOS transistor M1 and the Schottky diode N1 are connected in series between the first power supply voltage VDD and the second power supply voltage GND, and the first enhancement-mode MOS transistor M1 is configured to operate in a subthreshold region. At this time, the first enhancement-mode MOS transistor M1 is turned on and generates a constant current of a certain magnitude. After flowing out of the first enhancement-mode MOS transistor M1, the current flows into the Schottky diode N1. According to the current-voltage characteristic curve of the Schottky diode N1, the abscissa represents voltage and the ordinate represents current. When the current increases, the voltage rises very little, thereby slowing down the trend of the reference voltage increasing. Furthermore, since the reference voltage generating circuit must ensure a stable reference voltage Vref output even at high temperatures, and the inverse of the threshold voltage of the first enhancement-mode MOS transistor M1 is positively correlated with temperature, and the threshold voltage of the first enhancement-mode MOS transistor M1 is negatively correlated with current, the current of the first enhancement-mode MOS transistor M1 is positively correlated with temperature. That is, the higher the temperature, the greater the current flowing through the first enhancement-mode MOS transistor M1, and the lower the temperature, the smaller the current flowing through the first enhancement-mode MOS transistor M1. Furthermore, the characteristic curve of the Schottky diode N1 will shift due to temperature. As the temperature increases, the characteristic curve of the Schottky diode N1 will shift to the left, and as the temperature decreases, the characteristic curve of the Schottky diode N1 will shift to the right. When the temperature rises, the current flowing through the first enhancement-mode MOS transistor M1 increases, and the output end of the first enhancement-mode MOS transistor M1 outputs a voltage of a certain magnitude, thereby achieving positive temperature compensation. At the same time, the increased current flows into the Schottky diode N1. At this time, the characteristic curve of the Schottky diode N1 shifts to the left, that is, the output end voltage of the reference voltage generating circuit decreases. When the temperature rises, the voltage of the Schottky diode N1 slowly rises along the left-shifted characteristic curve. When the current increases to a certain value, the voltage of the Schottky diode N1 is equal to the output voltage of the first enhancement-mode MOS transistor M1, thereby achieving negative temperature compensation. Furthermore, according to the temperature compensation principle, the output end of the reference voltage generating circuit always outputs a stable reference voltage Vref at high temperatures.

[0056] The technical solution of the embodiment of the present invention enables the first enhancement-mode MOS transistor to operate in the subthreshold region by connecting a first enhancement-mode MOS transistor and a Schottky diode in series between a first power supply voltage terminal and a second power supply voltage terminal, and using the connection between the first enhancement-mode MOS transistor and the Schottky diode as the output terminal of a reference voltage generation circuit. When the temperature rises, the characteristic curve of the Schottky diode shifts leftward, i.e., the voltage at the output terminal of the reference voltage generation circuit decreases, achieving negative temperature compensation. Simultaneously, the current of the first enhancement-mode MOS transistor increases, achieving positive temperature compensation. As the current increases, the voltage of the Schottky diode slowly increases, gradually offsetting the voltage drop caused by the leftward shift of the Schottky diode characteristic curve when the temperature rises, and ultimately becoming equal to the voltage at the output terminal of the reference voltage generation circuit. This structure makes the generated reference voltage insensitive to temperature changes, ensuring that a stable reference voltage can be generated even at high temperatures, improving the stability of the reference voltage generation circuit, making it compact and easy to integrate, and reducing the on-resistance of the first enhancement-mode MOS transistor and circuit losses.

[0057] In another specific embodiment, optionally, Figure 2 A schematic diagram of the structure of a second reference voltage generating circuit provided by an embodiment of the present invention, referring to Figure 2 As shown, the reference voltage generating circuit further includes a PN junction diode N2; the input end of the PN junction diode N2 is electrically connected to the second electrode of the first enhancement mode MOS transistor M1, and the input end of the PN junction diode N2 is electrically connected to the input end of the Schottky diode N1.

[0058] Among them, the PN junction diode N2 is a device that uses different doping processes to make P-type semiconductors and N-type semiconductors on the same semiconductor substrate through diffusion. The space charge region formed at the interface between the P-type semiconductor and the N-type semiconductor is called a PN junction.

[0059] Specifically, in this embodiment, the PN junction diode N2 and the Schottky diode N1 are connected in series back-to-back. The current generated by the first enhancement-mode MOS transistor M1 will flow into the cathode of the PN junction diode N2. Since the PN junction diode N2 has a high doping concentration and can be reverse-conducted, the current will flow through the PN junction diode N2 and then into the Schottky diode N1. Since the current of the PN junction diode N2 is very small when it is reverse-conducted, the generated voltage is also very small, which can play a voltage stabilizing role in the reference voltage generating circuit.

[0060] In another specific embodiment, optionally, Figure 3 A schematic diagram of the structure of a third reference voltage generating circuit provided by an embodiment of the present invention, referring to Figure 2 and Figure 3As shown, the reference voltage generating circuit includes a second enhancement mode MOS transistor M2; the first electrode of the first enhancement mode MOS transistor M2 is electrically connected to the first power supply voltage terminal VDD, and the second electrode is electrically connected to the gate of the second enhancement mode MOS transistor M2 and serves as the output terminal of the reference voltage generating circuit; the first electrode and the second electrode of the second enhancement mode MOS transistor M2 are electrically connected to form a Schottky diode N1 and a PN junction diode N2.

[0061] The second enhancement-mode MOS transistor M2 is a field-effect transistor that conducts only when the voltage between the gate and the first electrode exceeds the conduction voltage. In this embodiment, the second enhancement-mode MOS transistor M2 is an NMOS transistor and utilizes a p-type gallium nitride substrate. MOS transistors with p-type gallium nitride substrates are characterized by high voltage operation and can operate stably at 0 to 100V. Furthermore, due to the inherent high-temperature resistance of gallium nitride, p-type gallium nitride substrates can operate within a temperature range of 0 to 300°C.

[0062] Specifically, by electrically connecting the first electrode and the second electrode of the second enhancement mode MOS transistor M2, a PN junction diode N2 and a Schottky diode N1 connected in series back to back are formed at the gate of the second enhancement mode MOS transistor M2. The equivalent circuit can be referred to as Figure 2 As shown, at this time, the current of the first enhancement mode MOS transistor M1 is positively correlated with the temperature, realizing positive temperature compensation, and the voltage of the Schottky diode N1 is negatively correlated with the temperature, realizing negative temperature compensation, thereby ensuring that the output end of the reference voltage generating circuit can output a stable reference voltage Vref. For the specific implementation principle, reference may be made to the above embodiment and will not be repeated here.

[0063] Optional, reference Figure 1 The gate of the first enhancement mode MOS transistor M1 receives a bias voltage signal Vbias, and the bias voltage signal Vbias is configured to control the first enhancement mode MOS transistor M1 to operate in a subthreshold region.

[0064] Optionally, the bias voltage signal Vbias satisfies: 1V≤Vbias≤1.5V.

[0065] Specifically, the gate of the first enhancement-mode MOS transistor M1 is configured to receive a bias voltage signal Vbias. By inputting different bias voltages, the first enhancement-mode MOS transistor M1 can be operated in different regions. In this embodiment, the bias voltage signal Vbias can be configured to enable the first enhancement-mode MOS transistor M1 to operate in a subthreshold region. In this embodiment, the bias voltage signal Vbias satisfies the following conditions: 1V ≤ Vbias ≤ 1.5V. Exemplarily, Vbias can be 1V, 1.1V, 1.2V, 1.3V, 1.4V, and 1.5V. The specific value can be determined based on actual conditions and is not limited here.

[0066] Based on the same inventive concept, an embodiment of the present invention further provides a method for preparing a reference voltage generating circuit. Figure 4 A flowchart of a method for preparing a reference voltage generating circuit provided by an embodiment of the present invention, referring to Figure 4 As shown, the preparation method comprises:

[0067] S110: Prepare a first enhancement-mode MOS transistor.

[0068] S120. Prepare a Schottky diode.

[0069] S130. Electrically connect the first enhancement mode MOS transistor and the Schottky diode, and connect them in series between the first power supply voltage terminal and the second power supply voltage terminal. The connection end of the first enhancement mode MOS transistor and the Schottky diode serves as the output end of the reference voltage generating circuit.

[0070] The first enhancement-mode MOS transistor is configured to operate in a subthreshold region; the inverse of the threshold voltage of the first enhancement-mode MOS transistor is positively correlated with temperature, and the voltage of the Schottky diode is negatively correlated with temperature, so that the output end of the reference voltage generating circuit outputs a stable reference voltage.

[0071] Specifically, when preparing the reference voltage generating circuit, a first enhancement-mode MOS transistor and a Schottky diode need to be prepared. The preparation sequence may include, but is not limited to, simultaneously preparing the first enhancement-mode MOS transistor and the Schottky diode on a substrate, or preparing the first enhancement-mode MOS transistor first and then preparing the Schottky diode after the first enhancement-mode MOS transistor is prepared. The specific preparation sequence can be determined based on actual conditions and is not limited here. After the first enhancement-mode MOS transistor and the Schottky diode are prepared, the first enhancement-mode MOS transistor and the Schottky diode are electrically connected by depositing a conductive metal on the second electrode of the first enhancement-mode MOS transistor and the input end of the Schottky diode. The first enhancement-mode MOS transistor and the Schottky diode are then connected in series between a first power supply voltage and a second power supply voltage. The connection end of the first enhancement-mode MOS transistor and the Schottky diode serves as the output end of the reference voltage generating circuit. This completes the preparation of the reference voltage generating circuit. The operating principle of the prepared reference voltage generating circuit can be referred to the above embodiment and will not be further described here.

[0072] The technical solution of the embodiment of the present invention comprises preparing a first enhancement-mode MOS transistor; preparing a Schottky diode; and electrically connecting the first enhancement-mode MOS transistor and the Schottky diode in series between a first power supply voltage terminal and a second power supply voltage terminal. The connection between the first enhancement-mode MOS transistor and the Schottky diode serves as the output terminal of a reference voltage generation circuit. This method achieves the preparation of a reference voltage generation circuit, providing a foundation for achieving a stable reference voltage output based on the prepared reference voltage generation circuit.

[0073] In another optional embodiment, the reference voltage generating circuit includes a second enhancement mode MOS transistor; Figure 5 Flowchart of a method for preparing a second reference voltage generating circuit provided by an embodiment of the present invention, with reference to Figure 5 As shown, the preparation method comprises:

[0074] S210: Prepare a first enhancement-mode MOS transistor.

[0075] S220 , preparing a second enhancement-mode MOS transistor.

[0076] S230 , electrically connecting the first electrode and the second electrode of the second enhancement mode MOS transistor to form a Schottky diode and a PN junction diode connected in series at the gate of the second enhancement mode MOS transistor.

[0077] S240: electrically connect the first enhancement mode MOS transistor and the second enhancement mode MOS transistor, and connect them in series between the first power supply voltage terminal and the second power supply voltage terminal, and use the connection end of the first enhancement mode MOS transistor and the second enhancement mode MOS transistor as the output end of the reference voltage generating circuit.

[0078] Specifically, when preparing a first enhancement-mode MOS transistor and a Schottky diode, considering the simplicity of the preparation process, the Schottky diode can be prepared by preparing a second enhancement-mode MOS transistor. The preparation method of the first enhancement-mode MOS transistor and the preparation method of the second enhancement-mode MOS transistor can be the same or different, and can be prepared simultaneously on a substrate or separately. The specific method can be determined based on actual conditions and is not limited here. After the second enhancement-mode MOS transistor is prepared, the first and second electrodes of the second enhancement-mode MOS transistor are electrically connected. Specifically, a conductive metal layer, such as aluminum or copper, can be deposited on the second enhancement-mode MOS transistor. After the first and second electrodes of the second enhancement-mode MOS transistor are electrically connected, a PN junction diode and a Schottky diode are formed in series back-to-back connection at the gate of the second enhancement-mode MOS transistor. Current can flow from the PN junction diode to the Schottky diode, achieving a delayed voltage increase. After the first enhancement-mode MOS transistor and the Schottky diode are prepared, the first enhancement-mode MOS transistor and the Schottky diode need to be electrically connected. In essence, the first enhancement-mode MOS transistor and the second enhancement-mode MOS transistor can be electrically connected. The electrical connection method can be achieved by referring to the above-mentioned deposition of the conductive metal layer. The first enhancement-mode MOS transistor and the second enhancement-mode MOS transistor are connected in series between the first power supply voltage terminal and the second power supply voltage terminal. The connection terminal between the first enhancement-mode MOS transistor and the second enhancement-mode MOS transistor serves as the output terminal of the reference voltage generating circuit. In this way, the preparation of the reference voltage generating circuit is completed, providing a basis for achieving a stable reference voltage output based on the prepared reference voltage generating circuit.

[0079] The technical solution of the embodiment of the present invention comprises preparing a first enhancement-mode MOS transistor; preparing a second enhancement-mode MOS transistor; electrically connecting the first and second electrodes of the second enhancement-mode MOS transistor to form a series-connected Schottky diode and a PN junction diode at the gate of the second enhancement-mode MOS transistor; electrically connecting the first and second enhancement-mode MOS transistors and connecting them in series between a first power supply voltage terminal and a second power supply voltage terminal, with the connection end of the first and second enhancement-mode MOS transistors serving as the output end of a reference voltage generating circuit. Using the above method, the Schottky diode is prepared by electrically connecting the first and second electrodes of the second enhancement-mode MOS transistor, and the reference voltage generating circuit is prepared by electrically connecting the first and second enhancement-mode MOS transistors. This provides a basis for achieving a stable reference voltage output based on the prepared reference voltage generating circuit, while also increasing the equivalent impedance of the reference voltage generating circuit and improving the anti-interference capability of the reference voltage generating circuit.

[0080] In another specific embodiment, Figure 6 A flowchart of a method for preparing a third reference voltage generating circuit provided by an embodiment of the present invention, Figure 7 A flowchart of a manufacturing process of a reference voltage generating circuit provided by an embodiment of the present invention, wherein the manufacturing of a first enhancement mode MOS transistor and the manufacturing of a second enhancement mode MOS transistor are performed simultaneously, the connection of the first electrode and the second electrode of the second enhancement mode MOS transistor and the electrical connection of the first enhancement mode MOS transistor and the Schottky diode are performed simultaneously; Figure 6 and Figure 7 As shown, the preparation method comprises:

[0081] S310 , providing a substrate, and sequentially depositing a buffer layer, a barrier layer, and a p-GaN layer on the surface of the substrate.

[0082] Specifically, refer to Figure 7In Figure a), the material of the substrate 1 may include but is not limited to single crystal silicon, polycrystalline silicon, silicon germanium, silicon germanium or silicon carbide, etc., which can be determined according to actual conditions and is not limited here. The buffer layer 2 is formed on the surface of one side of the substrate, and the material of the buffer layer 2 may include but is not limited to gallium nitride, etc. The barrier layer 3 is formed on the surface of the buffer layer 2 away from the substrate 1. The material of the barrier layer 3 may include but is not limited to an alloy film layer formed by one or more materials selected from aluminum (Al), indium (In) and gallium (Ga) and nitrogen (N). It may be an AlN binary alloy layer, or an AlGaN, AlInN or InGaN ternary alloy layer, or an AlInGaN quaternary alloy layer. In this embodiment, the material of the barrier layer 3 may be AlGaN. In addition, the thickness of the barrier layer 3 is relatively thin to ensure that an enhanced mode can be achieved. The p-gallium nitride layer 4 is formed on the surface of the barrier layer 3 away from the substrate 1, including an active region and a passive region. Methods for forming the buffer layer 2 , the barrier layer 3 and the p-GaN layer 4 may include, but are not limited to, physical vapor deposition, chemical vapor deposition or atomic deposition, etc., which are not limited here.

[0083] S320 , etching the buffer layer, the barrier layer, and the p-GaN layer respectively to form an active region of the first enhancement mode MOS transistor and an active region of the second enhancement mode MOS transistor.

[0084] Specifically, refer to Figure 7 In FIG. b), after forming the buffer layer 2, barrier layer 3, and p-GaN layer 4, the buffer layer 2, barrier layer 3, and p-GaN layer 4 are etched. The etching process may include, but is not limited to, inductively coupled plasma (ICP) etching. When etching the buffer layer 2, barrier layer 3, and p-GaN layer 4, the inactive regions of the first and second enhancement mode MOS transistors are removed, leaving only the active regions of the first and second enhancement mode MOS transistors, i.e., the regions where the first and second enhancement mode MOS transistors are located.

[0085] S330, performing a secondary etching on the etched p-GaN layer to remove the p-GaN layer outside the gate region of the first enhancement mode MOS transistor and the p-GaN layer outside the gate region of the second enhancement mode MOS transistor, while exposing the first and second electrode regions of the first enhancement mode MOS transistor and the first and second electrode regions of the second enhancement mode MOS transistor.

[0086] Specifically, refer to Figure 7In Figure c), after forming the active regions of the first and second enhancement-mode MOS transistors, the etched p-GaN layer 4 needs to be subjected to a secondary etching process. The secondary etching process may include, but is not limited to, ICP etching. After the secondary etching, the p-GaN layer 4 outside the gate region of the first enhancement-mode MOS transistor and the p-GaN layer 4 outside the gate region of the second enhancement-mode MOS transistor are removed, leaving only the p-GaN layer 4 in the gate region to restore the conductive channels of the first and second enhancement-mode MOS transistors. At the same time, the first and second electrode regions of the first enhancement-mode MOS transistor, as well as the first and second electrode regions of the second enhancement-mode MOS transistor, are exposed, providing a foundation for the subsequent preparation of the first and second electrodes.

[0087] S340 , depositing a gate isolation layer on the surface of the active region of the first enhancement mode MOS transistor and the active region of the second enhancement mode MOS transistor away from the substrate.

[0088] Specifically, refer to Figure 7 d), after forming the gate region of the first enhancement mode MOS transistor and the gate region of the second enhancement mode MOS transistor, and simultaneously exposing the first and second electrode regions of the first enhancement mode MOS transistor, as well as the first and second electrode regions of the second enhancement mode MOS transistor, a gate isolation layer 5 is formed on the surface of the active region of the first enhancement mode MOS transistor and the active region of the second enhancement mode MOS transistor away from the substrate 1. This prevents gate leakage, improves the electric field structure, reduces the peak electric field, and improves the withstand voltage capability of the first enhancement mode MOS transistor and the second enhancement mode MOS transistor. The gate isolation layer 5 may be formed by methods including, but not limited to, physical vapor deposition, chemical vapor deposition, or atomic deposition, and the material of the gate isolation layer 5 may include, but is not limited to, silicon nitride or aluminum oxide.

[0089] S350 , opening holes in the gate isolation layer so that the openings are aligned with the gate region, the first electrode region and the second electrode region of the first enhancement mode MOS transistor, and the gate region, the first electrode region and the second electrode region of the second enhancement mode MOS transistor.

[0090] Specifically, refer to Figure 7 In FIG e), after the gate isolation layer 5 is formed, holes are opened in the gate isolation layer 5. The method of opening the holes may include but is not limited to etching the holes using a reactive ion etching (RIE) device. The positions of the openings may be the gate region, the first electrode region, and the second electrode region of the first enhancement mode MOS transistor, and the gate region, the first electrode region, and the second electrode region of the second enhancement mode MOS transistor, so that the gate region, the first electrode region, and the second electrode region of the first enhancement mode MOS transistor and the second enhancement mode MOS transistor are all exposed, providing a basis for subsequent deposition of ohmic metal and gate metal in the gate region, the first electrode region, and the second electrode region.

[0091] S360, depositing an ohmic metal on the first and second pole regions of the first enhancement mode MOS transistor, and on the first and second pole regions of the second enhancement mode MOS transistor, away from the substrate, so that the ohmic metal and the barrier layer form an ohmic contact of the first enhancement mode MOS transistor and an ohmic contact of the second enhancement mode MOS transistor.

[0092] Specifically, refer to Figure 7 f), after exposing the first electrode region and the second electrode region of the first enhancement mode MOS transistor, and the first electrode region and the second electrode region of the second enhancement mode MOS transistor, an ohmic metal needs to be formed. Specifically, the ohmic metal of the first electrode and the second electrode can be deposited in the first electrode region and the second electrode region. The deposition method can include but is not limited to deposition using electron beam evaporation technology, and the formed ohmic metal is rapidly annealed to promote the ohmic metal and the barrier layer 3 to form an ohmic contact of the first enhancement mode MOS transistor and an ohmic contact of the second enhancement mode MOS transistor, avoid channel damage caused by etching, reduce the on-resistance of the first enhancement mode MOS transistor and the second enhancement mode MOS transistor, and thus reduce the loss of the reference voltage generating circuit. Among them, the material of the ohmic metal can be any one or more combinations of titanium (Ti), aluminum (Al), nickel (Ni) and gold (Au), or any one or more combinations of titanium (Ti), aluminum (Al), nickel (Ni) and titanium nitride (TiN), preferably any one or more combinations of titanium, aluminum, nickel and titanium nitride; the annealing conditions can be an annealing temperature of 500°C-1050°C, preferably a temperature of 900°C, which can be determined according to actual conditions and is not specifically limited here.

[0093] S370 , depositing gate metal on the gate region of the first enhancement mode MOS transistor and the gate region of the second enhancement mode MOS transistor to form the gate of the first enhancement mode MOS transistor and the gate of the second enhancement mode MOS transistor, so as to form the first enhancement mode MOS transistor and the second enhancement mode MOS transistor.

[0094] Specifically, refer to Figure 7As shown in FIG. g), after forming the first and second electrodes of the first enhancement-mode MOS transistor and the first and second electrodes of the second enhancement-mode MOS transistor, it is necessary to form the gate of the first enhancement-mode MOS transistor and the gate of the second enhancement-mode MOS transistor. Specifically, gate metal can be deposited in the gate region of the first enhancement-mode MOS transistor and the gate region of the second enhancement-mode MOS transistor to form the gate of the first enhancement-mode MOS transistor and the gate of the second enhancement-mode MOS transistor. The resulting gate structure is a T-shaped gate as shown in FIG. g. After forming the gate, the first and second electrodes, the first enhancement-mode MOS transistor and the second enhancement-mode MOS transistor are formed. The material of the gate metal can include, but is not limited to, a metal combination of nickel (Ni) and titanium nitride (TiN), a metal combination of nickel (Ni) and gold (Au), etc., preferably a metal combination of nickel (Ni) and titanium nitride (TiN). The method of depositing the gate metal can include, but is not limited to, deposition using electron beam evaporation technology and other methods, which are not specifically limited here.

[0095] S380 , forming a passivation layer by depositing a surface on a side of the first enhancement mode MOS transistor and the second enhancement mode MOS transistor away from the substrate.

[0096] Specifically, refer to Figure 7 In FIGh), after the first enhancement mode MOS transistor and the second enhancement mode MOS transistor are formed, it is necessary to set the connection relationship between the first enhancement mode MOS transistor and the second enhancement mode MOS transistor. In this embodiment, it is necessary to first deposit a passivation layer 6 on the surface of the first enhancement mode MOS transistor and the second enhancement mode MOS transistor away from the substrate to serve as an isolation layer for circuit connection to prevent circuit short circuit. The material of the passivation layer 6 may include but is not limited to silicon nitride or silicon oxide, and the method of forming the passivation layer 6 may include but is not limited to physical vapor deposition, chemical vapor deposition, or atomic deposition.

[0097] S390 , etching the passivation layer to expose the gate, the first electrode, and the second electrode of the first enhancement-mode MOS transistor, and the gate, the first electrode, and the second electrode of the second enhancement-mode MOS transistor.

[0098] Specifically, refer to Figure 7 In FIG. i), after the passivation layer 6 is formed, the passivation layer 6 is etched. The etching method may include but is not limited to reactive ion etching, inductively coupled plasma etching (ICPE), buffered oxide etching (BOE), etc. After etching, the gate, the first electrode and the second electrode of the first enhancement mode MOS transistor, as well as the gate, the first electrode and the second electrode of the second enhancement mode MOS transistor are exposed to facilitate subsequent circuit connection.

[0099] S400: Depositing a conductive metal layer on the exposed surfaces of the gate, first electrode, and second electrode of the first enhancement mode MOS transistor, as well as the gate, first electrode, and second electrode of the second enhancement mode MOS transistor, away from the substrate, so that the second electrode of the first enhancement mode MOS transistor is electrically connected to the gate of the second enhancement mode MOS transistor and connected in series between the first power supply voltage terminal and the second power supply voltage terminal, and the first electrode of the second enhancement mode MOS transistor is electrically connected to the second electrode of the second enhancement mode MOS transistor.

[0100] Specifically, refer to Figure 7 In Figure j), after exposing the gate, first electrode, and second electrode of the first enhancement-mode MOS transistor, as well as the gate, first electrode, and second electrode of the second enhancement-mode MOS transistor, a conductive metal layer is deposited on the exposed surfaces of the gate, first electrode, and second electrode of the first enhancement-mode MOS transistor, as well as the gate, first electrode, and second electrode of the second enhancement-mode MOS transistor, away from the substrate. The material of the conductive metal layer may include, but is not limited to, aluminum or copper, and the conductive metal layer may be formed by deposition using, but is not limited to, electron beam evaporation. By depositing the conductive metal layer, the second electrode of the first enhancement-mode MOS transistor is electrically connected to the gate of the second enhancement-mode MOS transistor, and the first electrode of the second enhancement-mode MOS transistor is electrically connected to the second electrode of the second enhancement-mode MOS transistor. The first enhancement-mode MOS transistor and the second enhancement-mode MOS transistor are then connected in series between the first power supply voltage terminal and the second power supply voltage terminal, thereby completing the preparation of a reference voltage generation circuit and providing a basis for achieving a stable reference voltage output based on the prepared reference voltage generation circuit.

[0101] The technical solution of the embodiment of the present invention comprises providing a substrate, and sequentially depositing a buffer layer, a barrier layer, and a p-GaN layer on the surface of the substrate; etching the buffer layer, the barrier layer, and the p-GaN layer to form an active region of a first enhancement-mode MOS transistor and an active region of a second enhancement-mode MOS transistor; performing a secondary etching on the etched p-GaN layer to remove the p-GaN layer outside the gate region of the first enhancement-mode MOS transistor and the p-GaN layer outside the gate region of the second enhancement-mode MOS transistor, thereby exposing the first and second electrode regions of the first enhancement-mode MOS transistor, as well as the first and second electrode regions of the second enhancement-mode MOS transistor; depositing a gate isolation layer on the surface of the active region of the first enhancement-mode MOS transistor and the active region of the second enhancement-mode MOS transistor away from the substrate; opening a hole in the gate isolation layer so that the opening is aligned with the gate region, the first and second electrode regions of the first enhancement-mode MOS transistor, and the gate region, the first and second electrode regions of the second enhancement-mode MOS transistor; and exposing the first and second electrode regions of the first enhancement-mode MOS transistor and the first and second electrode regions of the second enhancement-mode MOS transistor away from the substrate. Ohmic metal is deposited on the side surface so that the ohmic metal and the barrier layer form ohmic contacts of the first enhancement mode MOS transistor and ohmic contacts of the second enhancement mode MOS transistor; gate metal is deposited on the gate region of the first enhancement mode MOS transistor and the gate region of the second enhancement mode MOS transistor to form the gates of the first enhancement mode MOS transistor and the second enhancement mode MOS transistor, thereby forming the first enhancement mode MOS transistor and the second enhancement mode MOS transistor; a passivation layer is deposited on the surface of the first enhancement mode MOS transistor and the second enhancement mode MOS transistor away from the substrate; the passivation layer is etched to expose the gate, first electrode and second electrode of the first enhancement mode MOS transistor, and the gate, first electrode and second electrode of the second enhancement mode MOS transistor; a conductive metal layer is deposited on the exposed surface of the gate, first electrode and second electrode of the first enhancement mode MOS transistor, and the gate, first electrode and second electrode of the second enhancement mode MOS transistor away from the substrate, so that the second electrode of the first enhancement mode MOS transistor is electrically connected to the gate of the second enhancement mode MOS transistor and connected in series between the first power supply voltage terminal and the second power supply voltage terminal, and the first electrode of the second enhancement mode MOS transistor is electrically connected to the second electrode of the second enhancement mode MOS transistor. The above method realizes the preparation of a reference voltage generating circuit, providing a basis for realizing stable reference voltage output based on the prepared reference voltage generating circuit. At the same time, channel damage caused by etching is avoided, the on-resistance of the first enhancement-mode MOS transistor and the second enhancement-mode MOS transistor is reduced, and the loss of the reference voltage generating circuit is greatly reduced, thereby improving the integration of the reference voltage generating circuit.

[0102] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0103] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A reference voltage generating circuit, characterized in that: comprising a first enhancement mode MOS transistor and a Schottky diode connected in series between a first power supply voltage terminal and a second power supply voltage terminal, wherein the connection end of the first enhancement mode MOS transistor and the Schottky diode serves as the output end of the reference voltage generating circuit; The first enhancement mode MOS transistor is configured to operate in a subthreshold region; The inverse of the threshold voltage of the first enhancement mode MOS transistor is positively correlated with temperature, and the voltage of the Schottky diode is negatively correlated with temperature, so that the output end of the reference voltage generating circuit outputs a stable reference voltage.

2. The reference voltage generating circuit according to claim 1, wherein: Also includes PN junction diodes; The input end of the PN junction diode is electrically connected to the second electrode of the first enhancement mode MOS transistor, and the input end of the PN junction diode is electrically connected to the input end of the Schottky diode.

3. The reference voltage generating circuit according to claim 1, wherein: including a second enhancement mode MOS transistor; The first electrode of the first enhancement mode MOS transistor is electrically connected to the first power supply voltage terminal, and the second electrode is electrically connected to the gate of the second enhancement mode MOS transistor and serves as the output terminal of the reference voltage generating circuit; The first electrode and the second electrode of the second enhancement mode MOS transistor are electrically connected to form the Schottky diode and the PN junction diode.

4. The reference voltage generating circuit according to claim 1, wherein: The gate of the first enhancement mode MOS transistor receives a bias voltage signal, and the bias voltage signal is configured to control the first enhancement mode MOS transistor to operate in the subthreshold region.

5. The reference voltage generating circuit according to claim 4, wherein: The bias voltage signal Vbias satisfies: 1V≤Vbias≤1.5V.

6. The reference voltage generating circuit according to claim 1, wherein: The second power supply voltage is a ground voltage.

7. A method for preparing a reference voltage generating circuit, characterized in that: include: preparing a first enhancement mode MOS transistor; Preparation of Schottky diodes; The first enhancement mode MOS transistor and the Schottky diode are electrically connected and connected in series between the first power supply voltage terminal and the second power supply voltage terminal, and the connection end of the first enhancement mode MOS transistor and the Schottky diode serves as the output end of the reference voltage generating circuit; The first enhancement mode MOS transistor is configured to operate in a subthreshold region; the inverse of the threshold voltage of the first enhancement mode MOS transistor is positively correlated with temperature, and the voltage of the Schottky diode is negatively correlated with temperature, so that the output end of the reference voltage generating circuit outputs a stable reference voltage.

8. The preparation method according to claim 7, characterized in that The reference voltage generating circuit includes a second enhancement mode MOS transistor; A Schottky diode is prepared, comprising: preparing the second enhancement mode MOS transistor; electrically connecting the first electrode and the second electrode of the second enhancement-mode MOS transistor to form the Schottky diode and the PN junction diode connected in series at the gate of the second enhancement-mode MOS transistor; The first enhancement mode MOS transistor and the Schottky diode are electrically connected and connected in series between a first power supply voltage terminal and a second power supply voltage terminal, and the connection end of the first enhancement mode MOS transistor and the Schottky diode serves as the output end of the reference voltage generating circuit, including: The first enhancement mode MOS transistor and the second enhancement mode MOS transistor are electrically connected and connected in series between the first power supply voltage terminal and the second power supply voltage terminal, and the connection end of the first enhancement mode MOS transistor and the second enhancement mode MOS transistor serves as the output end of the reference voltage generating circuit.

9. The preparation method according to claim 8, characterized in that The first enhancement mode MOS transistor and the second enhancement mode MOS transistor are prepared simultaneously; The method of preparing a first enhancement-mode MOS transistor and preparing a second enhancement-mode MOS transistor includes: Providing a substrate, and sequentially depositing a buffer layer, a barrier layer, and a p-GaN layer on the surface of the substrate; Etching the buffer layer, the barrier layer, and the p-GaN layer respectively to form an active region of the first enhancement-mode MOS transistor and an active region of the second enhancement-mode MOS transistor; Performing a secondary etching on the etched p-type gallium nitride layer to remove the p-type gallium nitride layer outside the gate region of the first enhancement mode MOS transistor and the p-type gallium nitride layer outside the gate region of the second enhancement mode MOS transistor, while exposing the first and second polar regions of the first enhancement mode MOS transistor and the first and second polar regions of the second enhancement mode MOS transistor; Depositing a gate isolation layer on a surface of the active region of the first enhancement mode MOS transistor and the active region of the second enhancement mode MOS transistor away from the substrate; Opening a hole in the gate isolation layer so that the opening is aligned with the gate region, the first electrode region, and the second electrode region of the first enhancement-mode MOS transistor, and the gate region, the first electrode region, and the second electrode region of the second enhancement-mode MOS transistor; Depositing an ohmic metal on the first electrode region and the second electrode region of the first enhancement mode MOS transistor, and on the first electrode region and the second electrode region of the second enhancement mode MOS transistor, which are away from the substrate, so that the ohmic metal and the barrier layer form an ohmic contact of the first enhancement mode MOS transistor and an ohmic contact of the second enhancement mode MOS transistor; Gate metal is deposited on the gate region of the first enhancement mode MOS transistor and the gate region of the second enhancement mode MOS transistor to form the gate of the first enhancement mode MOS transistor and the gate of the second enhancement mode MOS transistor, so as to form the first enhancement mode MOS transistor and the second enhancement mode MOS transistor.

10. The preparation method according to claim 9, characterized in that Connecting the first electrode and the second electrode of the second enhancement mode MOS transistor and electrically connecting the first enhancement mode MOS transistor and the Schottky diode are performed simultaneously; Connecting the first electrode and the second electrode of the second enhancement mode MOS transistor and electrically connecting the first enhancement mode MOS transistor and the Schottky diode includes: Depositing a passivation layer on the surface of the first enhancement mode MOS transistor and the second enhancement mode MOS transistor away from the substrate; Etching the passivation layer to expose the gate, the first electrode, and the second electrode of the first enhancement-mode MOS transistor, and the gate, the first electrode, and the second electrode of the second enhancement-mode MOS transistor; The gate, the first electrode and the second electrode of the exposed first enhancement mode MOS transistor, and A conductive metal layer is deposited on the surface of the gate, the first electrode, and the second electrode of the second enhancement mode MOS transistor away from the substrate, so that the second electrode of the first enhancement mode MOS transistor is electrically connected to the gate of the second enhancement mode MOS transistor and connected in series between the first power supply voltage terminal and the second power supply voltage terminal, and the first electrode of the second enhancement mode MOS transistor is electrically connected to the second electrode of the second enhancement mode MOS transistor.

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