A VCSEL chip and a manufacturing method thereof

Abstract

The present invention relates to the technical field of semiconductor chip preparation, and specifically to a VCSEL chip and a method for making the same. The VCSEL chip includes a substrate, an epitaxial layer, an oxide layer, a passivation film, and a P-type electrode. During the manufacturing process, a groove and a mesa platform are formed on the epitaxial layer, and a diffusion barrier layer is formed in the groove to prevent subsequent atomic diffusion through the active area and the oxide layer. Then, chemical vapor deposition is used to perform horizontal atomic diffusion from the side through the groove, so that a diffusion zone is formed at the top of the P-type DBR in the inner and outer areas of the groove, and the reflection capability is lost. The front edge of the diffusion zone formed by the side diffusion of the present invention is a cylindrical surface, and the diffusion depth is relatively easy to control; and through the side atomic diffusion, the contact area of ​​the non-destructive P-type DBR in the vertical direction of the light-emitting hole is greatly increased, which is conducive to the VCSEL chip still working in a single transverse mode under a large output power, and is conducive to increasing the gas detection range or increasing the sensitivity of the signal.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip preparation, and in particular to a method for preparing a VCSEL chip. Background Art

[0002] VCSEL chip is a vertical cavity surface emitting laser chip, which is widely used in optical communication, optoelectronic equipment and other optical fields. VCSEL chip has the advantages of low threshold current, circular spot, chip manufacturing and detection without cleavage, easy to realize high-density two-dimensional array and optoelectronic integration.

[0003] In VCSEL (Vertical Cavity Surface Emitting Laser) chips, diffusion technology is mainly used to improve the single transverse mode performance of the laser beam and optimize its application. Through specific structure and material processing, the light beam undergoes multiple reflections and amplifications in the non-diffusion area of ​​the VCSEL chip, eventually forming a single transverse mode light output and reducing the divergence angle of the light beam. This technology helps to improve the optical properties of the laser, making it more suitable for high-speed data transmission, improving gas detection sensitivity, communications, and other application scenarios that require precise control of the light beam.

[0004] At present, the general VCSEL chip has the characteristics of single longitudinal film and multiple transverse modes. Its diffusion technology forms a diffusion zone through the chip surface. The front edge of the diffusion zone is similar to a spherical surface, and the diffusion depth is not easy to control. The laser used for gas detection requires working in a single mode. This requirement limits the working current of the VCSEL chip, and then limits the output power of the chip, which directly affects the detection range of the detector and the sensitivity of the signal. Therefore, the present invention develops a VCSEL chip and a manufacturing method thereof to solve the problems existing in the prior art. Summary of the invention

[0005] The purpose of the present invention is to provide a VCSEL chip and a manufacturing method thereof, so as to solve the problem in the prior art that the output power of the VCSEL chip is limited due to the influence of the manufacturing process, and further overcome the problem of limited detection range and signal sensitivity.

[0006] The technical solution of the present invention is: a method for manufacturing a VCSEL chip, the manufacturing method is as follows:

[0007] a. Select a substrate and form an epitaxial layer on the substrate, wherein the epitaxial layer includes an N-type buffer layer, an N-type DBR, an active region, an oxide layer, a P-type DBR and an ohmic contact layer;

[0008] b. depositing a dielectric film on the surface of the epitaxial layer, and forming a groove and a mesa platform on the epitaxial layer by etching; the groove having an etching depth goes downward over the oxide layer;

[0009] c. Oxidizing the etched epitaxial wafer;

[0010] d. forming a diffusion barrier layer in the trench, wherein the diffusion barrier layer fills the bottom of the trench and covers the active area and the oxide layer from the side;

[0011] e. The structure in step d is subjected to horizontal atomic diffusion from the side through the groove by chemical vapor deposition, so that the P-type DBR in the inner and outer areas of the groove forms a diffusion zone locally and loses its reflective ability;

[0012] f. Prepare P-type electrode.

[0013] Preferably, in step b, the groove having the etching depth is formed in the dielectric film, the ohmic contact layer, the P-type DBR, the oxide layer and the active area;

[0014] The diffusion barrier layer in step d is filled in the trench along the vertical direction from the top interface of the N-type DBR, and the top of the diffusion barrier layer goes upward over the oxide layer.

[0015] Preferably, in step e, atomic diffusion is performed from the side using MOCVD, CVD or VPD, and the front edge of the diffusion zone formed by the diffusion is structured as a cylindrical surface.

[0016] Preferably, in step f, the dielectric film on the surface of the epitaxial wafer after diffusion in step e is removed, and a passivation film is re-deposited; then, the passivation film at the top interface of the P-type DBR connected to the ohmic contact layer is etched away, and finally a P-type electrode is prepared.

[0017] Preferably, after the preparation of the P-type electrode is completed, the epitaxial wafer is thinned, polished, back-gold plated and RTA annealed.

[0018] Preferably, in step a, the substrate is selected from any one of semiconductor GaAs, InP or GaN substrates, and the epitaxial layer is grown by MOCVD growth technology.

[0019] Preferably, in step b, the dielectric film is formed by PECVD deposition, and the groove is formed by photolithography, RIE or ICP process.

[0020] Preferably, the diffusion barrier layer in step d is formed in the groove by evaporation, sputtering or PECVD.

[0021] The present invention also discloses a VCSEL chip, which is manufactured by using the above-mentioned method for manufacturing a VCSEL chip, and comprises:

[0022] substrate;

[0023] An epitaxial layer, the epitaxial layer comprising an N-type buffer layer, an N-type DBR, an active region, an oxide layer, a P-type DBR and an ohmic contact layer arranged in sequence from bottom to top in a vertical direction; the oxide layer is formed between the active region and the P-type DBR;

[0024] Passivation film and P-type electrode;

[0025] A groove is formed by etching on the epitaxial layer, and the groove has an etching depth that goes downward over the oxide layer; a diffusion barrier layer is made in the groove, and the top of the diffusion barrier layer goes upward over the oxide layer, and the side surface covers the active area and the oxide layer.

[0026] Preferably, the P-type DBR in the inner and outer regions of the groove partially forms a diffusion region and loses its reflection capability.

[0027] Compared with the prior art, the advantages of the present invention are:

[0028] (1) The present invention forms a groove on the epitaxial layer to achieve horizontal atomic diffusion from the side through the groove using chemical vapor deposition. The front edge of the diffusion zone formed by the side diffusion is a cylindrical surface, and the diffusion depth is relatively easy to control. In addition, through the side atomic diffusion, the non-destructive P-type DBR contact area in the vertical direction between the front edge of the diffusion zone and the light output hole is greatly increased, which is beneficial for the VCSEL chip to still work in a single transverse mode under a large output power, and is beneficial for increasing the gas detection range or increasing the sensitivity of the signal.

[0029] (2) By controlling the etching depth of the trench, the oxide layer is exposed to facilitate oxidation. At this time, the bottom of the trench will inevitably reach the active area. Therefore, a diffusion barrier layer is made in the trench to prevent atoms from diffusing through the active area and the oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

[0031] Figure 1 A cross-sectional view of a method for manufacturing a VCSEL chip according to the present invention, in which an epitaxial layer is formed on a substrate;

[0032] Figure 2 A cross-sectional view of etching a groove and a mesa platform on an epitaxial layer in a method for manufacturing a VCSEL chip according to the present invention;

[0033] Figure 3 It is a structural schematic diagram of etching a groove and a mesa platform on an epitaxial layer in a method for manufacturing a VCSEL chip according to the present invention;

[0034] Figure 4This is a cross-sectional view of the structure of the oxide layer after oxidation in the method for manufacturing a VCSEL chip according to the present invention;

[0035] Figure 5 A cross-sectional view of forming a diffusion barrier layer in a groove in a method for manufacturing a VCSEL chip according to the present invention;

[0036] Figure 6 A schematic diagram of the structure of forming a diffusion barrier layer in a groove in a method for manufacturing a VCSEL chip according to the present invention;

[0037] Figure 7 A cross-sectional view of a diffusion zone formed by atomic diffusion in a method for manufacturing a VCSEL chip according to the present invention;

[0038] Figure 8 It is a schematic structural diagram of a diffusion zone formed by atomic diffusion in a method for manufacturing a VCSEL chip according to the present invention;

[0039] Fig. 9 A cross-sectional view of forming a passivation film and a P-type electrode in a method for manufacturing a VCSEL chip according to the present invention;

[0040] Fig.10 This is a schematic structural diagram of a VCSEL chip described in the present invention.

[0041] in:

[0042] 100, substrate;

[0043] 200, epitaxial layer, 201, N-type buffer layer, 202, N-type DBR, 203, active region, 204, oxide layer, 205, P-type DBR, 2051, diffusion region, 206, ohmic contact layer;

[0044] 300, dielectric film;

[0045] 400, groove;

[0046] 500, diffusion barrier;

[0047] 600, passivation film;

[0048] 700, P-type electrode;

[0049] 800, Gold on the back. DETAILED DESCRIPTION

[0050] The present invention is further described in detail below in conjunction with specific embodiments:

[0051] A method for manufacturing a VCSEL chip is as follows:

[0052] (1) Selecting a substrate and preparing an epitaxial layer;

[0053] The substrate 100 is selected from any one of semiconductor GaAs, InP or GaN substrates, and the epitaxial layer 200 is grown by MOCVD growth technology; Figure 1 As shown, the epitaxial layer 200 includes an N-type buffer layer 201 , an N-type DBR 202 , an active region 203 , an oxide layer 204 , a P-type DBR 205 and an ohmic contact layer 206 .

[0054] The N-type DBR 202 includes an N-type high refractive index layer and an N-type low refractive index layer that are alternately arranged; the P-type DBR includes a P-type high refractive index layer and a P-type low refractive index layer that are alternately arranged. The active region 203 includes a quantum well structure and a confinement layer. The oxide layer 204 is formed between the active region 203 and the P-type DBR 205.

[0055] (2) Formation of dielectric film;

[0056] A dielectric film 300 is formed on the surface of the epitaxial layer 200 by PECVD deposition. The dielectric film 300 is generally made of silicon oxide, silicon nitride, etc. and is formed above the ohmic contact layer 206. The dielectric film 300 plays a protective role to prevent the chip from being disturbed and damaged by the external environment.

[0057] (3) Etching to form grooves and mesa platforms;

[0058] Combination Figure 2 , Figure 3 As shown, a groove 400 and a mesa platform (table-type structure) are formed on the epitaxial layer 200 by using photolithography, RIE or ICP technology; the groove 400 is in a circular shape, and the inner and outer wall surfaces are both cylindrical surfaces; the groove 400 with an etching depth goes downward over the oxide layer 204 and is formed in the dielectric film 300, the ohmic contact layer 206, the P-type DBR 205, the oxide layer 204 and the active area 203, so that the corresponding top interface of the N-type DBR 202 is exposed.

[0059] (4) Oxidation treatment;

[0060] The etched epitaxial wafer is debonded, cleaned, dried, and placed in an oxidation furnace for oxidation. Figure 4 As shown, the oxide layer 204 is oxidized and acts as an insulating layer, effectively isolating different circuits and preventing current from leaking and flowing.

[0061] (5) preparing a diffusion barrier layer;

[0062] like Figure 5 , Figure 6As shown, a diffusion barrier layer 500 is formed in the groove 400 by evaporation, sputtering, PECVD or other methods. The diffusion barrier layer 500 is filled at the bottom of the groove 400 and is filled in the vertical direction from the top interface of the N-type DBR 202. The top of the diffusion barrier layer 500 goes over the oxide layer 204 upward and covers the active area 203 and the oxide layer 204 from the side to prevent atoms from diffusing through the active area 203 and the oxide layer 204 in subsequent processes.

[0063] (6) Atomic diffusion;

[0064] Chemical vapor deposition (including MOCVD, CVD or VPD technology) is used to diffuse atoms horizontally from the side of the groove 400, so that the P-type DBR in the inner and outer areas of the groove 400 partially forms a diffusion area 2051 and loses its reflection ability. Figure 7 , Figure 8 As shown; the front edge of the diffusion zone 2051 formed by diffusion is structured as a cylindrical surface, and the diffusion depth is relatively easy to control; and through the side atomic diffusion, the contact area between the front edge of the diffusion zone 2051 and the non-destructive P-type DBR in the vertical direction of the light output hole is greatly increased, which is beneficial for the VCSEL chip to still work in a single transverse mode under a large output power, and is beneficial for increasing the gas detection range or increasing the sensitivity of the signal.

[0065] (7) Prepare P-type electrode.

[0066] like Fig. 9 , Fig.10 As shown, the dielectric film on the surface of the epitaxial wafer after diffusion is removed by RIE process, and a passivation film 600 is deposited by PECVD; then the passivation film 600 at the top interface of the P-type DBR connected to the ohmic contact layer 206 is etched away, and finally the P-type electrode 700 of the chip is manufactured by processes such as lithography, Ebeam, stripping, and RTA.

[0067] (8) Post-processing;

[0068] After the P-type electrode 700 is prepared, the epitaxial wafer is thinned, polished, back-gold plated 800 and RTA annealed.

[0069] By adopting the above-mentioned VCSEL chip manufacturing method, based on the formation of the groove 400, atomic diffusion from the side is realized, which has significant advantages in output power, detection range and sensitivity. By adopting the above-mentioned manufacturing method, the present invention also discloses a VCSEL chip, such as Fig.10 As shown, it includes a back gold 800 , a substrate 100 , an epitaxial layer 200 , a passivation film 600 and a P-type electrode 700 .

[0070] The substrate 100 is made of any one of semiconductors GaAs, InP or GaN.

[0071] The epitaxial layer 200 includes an N-type buffer layer 201, an N-type DBR 202, an active region 203, an oxide layer 204, a P-type DBR 205, and an ohmic contact layer 206 arranged in sequence from bottom to top in the vertical direction; the N-type DBR 202 includes an N-type high refractive index layer and an N-type low refractive index layer arranged alternately; the P-type DBR 205 includes a P-type high refractive index layer and a P-type low refractive index layer arranged alternately. The active region 203 includes a quantum well structure and a confinement layer; the oxide layer 204 is formed between the active region 203 and the P-type DBR 205.

[0072] A trench 400 is formed by etching the epitaxial layer 200. The trench 400 has an etching depth that passes through the oxide layer 204 and is formed in the ohmic contact layer 206, the P-type DBR 205, the oxide layer 204 and the active area 203. The P-type DBR in the trench 400 and the peripheral area partially forms a diffusion area 2051 and loses its reflective ability.

[0073] The diffusion barrier layer 500 fills the trench 400 . The top of the diffusion barrier layer 500 goes over the oxide layer 204 and covers the active region 203 and the oxide layer 204 on the side.

[0074] The passivation film 600 is deposited on the surface of the epitaxial layer 200 after atomic diffusion, and the passivation film 600 at the top interface of the P-type DBR connected to the ohmic contact layer 206 is etched away.

[0075] The P-type electrode 700 is made on the top layer of the entire structure and has a light exit hole.

[0076] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with this technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the scope of protection of the present invention. For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention. Therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is limited by the attached claims rather than the above description, and it is intended to include all changes within the meaning and scope of the equivalent elements of the claims in the present invention.

Claims

1. A method for manufacturing a VCSEL chip, characterized in that: The production method is as follows: a. Select a substrate and form an epitaxial layer on the substrate, wherein the epitaxial layer includes an N-type buffer layer, an N-type DBR, an active region, an oxide layer, a P-type DBR and an ohmic contact layer; b. depositing a dielectric film on the surface of the epitaxial layer, and forming a groove and a mesa platform on the epitaxial layer by etching; the groove having an etching depth goes downward over the oxide layer; c. Oxidizing the etched epitaxial wafer; d. forming a diffusion barrier layer in the trench, the diffusion barrier layer filling the bottom of the trench and covering the active area and the oxide layer from the side; wherein the diffusion barrier layer is filled in the trench along the vertical direction from the top interface of the N-type DBR, and the top of the diffusion barrier layer goes over the oxide layer upward; e. The structure in step d is subjected to horizontal atomic diffusion from the side through the groove by chemical vapor deposition, so that the P-type DBR in the inner and outer areas of the groove forms a diffusion zone locally and loses its reflective ability; f. Prepare P-type electrode.

2. The method for manufacturing a VCSEL chip according to claim 1, characterized in that: In step b, the trench having an etching depth is formed in the dielectric film, the ohmic contact layer, the P-type DBR, the oxide layer and the active area.

3. The method for manufacturing a VCSEL chip according to claim 1, characterized in that: In step e, atomic diffusion is performed from the side using MOCVD, CVD or VPD, and the front edge of the diffusion zone formed by the diffusion is structured as a cylindrical surface.

4. The method for manufacturing a VCSEL chip according to claim 1, characterized in that: In step f, the dielectric film on the surface of the epitaxial wafer after diffusion in step e is removed, and a passivation film is re-deposited; then the passivation film at the top interface of the P-type DBR connected to the ohmic contact layer is etched away, and finally a P-type electrode is prepared.

5. The method for manufacturing a VCSEL chip according to claim 4, characterized in that: After the P-type electrode is prepared, the epitaxial wafer is thinned, polished, back-plated with gold and subjected to RTA annealing.

6. The method for manufacturing a VCSEL chip according to claim 1, characterized in that: In step a, the substrate is selected from any one of semiconductor GaAs, InP or GaN substrates, and the MOCVD growth technology is used to grow an epitaxial layer.

7. The method for manufacturing a VCSEL chip according to claim 1, characterized in that: In step b, the dielectric film is formed by PECVD deposition, and the groove is formed by photolithography, RIE or ICP process.

8. The method for manufacturing a VCSEL chip according to claim 1, characterized in that: In step d, the diffusion barrier layer is formed in the groove by evaporation, sputtering or PECVD.

9. A VCSEL chip, characterized in that: The method for manufacturing a VCSEL chip according to any one of claims 1 to 8 is used to manufacture the chip, comprising: substrate; An epitaxial layer, the epitaxial layer comprising an N-type buffer layer, an N-type DBR, an active region, an oxide layer, a P-type DBR and an ohmic contact layer arranged in sequence from bottom to top in a vertical direction; the oxide layer is formed between the active region and the P-type DBR; Passivation film and P-type electrode; A groove is formed by etching on the epitaxial layer, and the groove has an etching depth that goes downward over the oxide layer; a diffusion barrier layer is made in the groove, and the top of the diffusion barrier layer goes upward over the oxide layer, and the side surface covers the active area and the oxide layer.

10. A VCSEL chip according to claim 9, characterized in that: The P-type DBR in the inner and outer regions of the groove partially forms a diffusion region and loses its reflection capability.

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