Pulse Width Modulation and Commutation Control Method for a Heterogeneous Switching Three-Phase Five-Level Inverter

Abstract

The invention discloses a pulse width modulation and commutation control method for a heterogeneous-switch three-phase five-level inverter, belonging to the field of power electronic converters. The heterogeneous-switch three-phase five-level inverter is divided into two forms: 4-SiC arm and 2-SiC arm. The commutation control method optimizes the switching action sequence of the power switch tubes during the commutation process of the three-phase arm, so that the silicon carbide metal oxide field effect transistors in the heterogeneous-switch three-phase five-level inverter topology bear most of the switching losses, and the silicon insulated gate bipolar transistors only bear the conduction losses and a small amount of diode losses, optimizing the loss distribution of the inverter topology and improving the conversion efficiency and economic benefits of the inverter. The discontinuous pulse width modulation method reduces the switching times of the power switch tubes, and at the same time realizes the natural balance of the filter capacitor voltage on the DC bus side of the heterogeneous-switch three-phase five-level inverter and low switching losses, improving the conversion efficiency of the inverter.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic converters, and particularly relates to a pulse width modulation method for a heterogeneous-switch three-phase five-level inverter and a commutation control method for a heterogeneous-switch three-phase five-level inverter. Background Art

[0002] Power electronic converters have always pursued high efficiency, high power density, and high economic benefits. At high switching frequencies, the switching losses of the converters will increase and the efficiency will decrease. Converters based on traditional silicon devices are limited by the performance bottlenecks of silicon devices themselves and it is difficult to significantly improve in terms of power and efficiency. Although the performance of silicon carbide devices has been greatly improved compared with traditional silicon devices, their costs will increase significantly. Compared with converters using all silicon carbide devices, converters with a hybrid of silicon carbide and silicon devices can better balance performance and cost.

[0003] Active-neutral-point-clamp (ANPC) type inverters and their evolved circuits have become hot research objects for the hybrid application of silicon carbide and silicon devices in recent years due to their advantages of simple structure and multiple redundant modes. At the same time, multilevel converters can achieve higher voltage levels and can be applied in larger power scenarios. Applying the active-neutral-point-clamp type inverter with a hybrid of silicon carbide and silicon devices and its evolved circuits to the five-level converter topology can greatly improve the conversion efficiency and economic benefits of the converter.

[0004] However, the voltage imbalance of the DC bus capacitors is an inherent problem of the active-neutral-point-clamp type inverter. The voltage imbalance of the DC bus capacitors will lead to output current disturbances and an increase in the voltage stress of some switching devices.

[0005] In the prior art document 1: "A SiC and Si Hybrid Five-Level Unidirectional Rectifier for Medium Voltage Applications", a silicon carbide / silicon hybrid five-level rectifier topology is proposed. The topology consists of four silicon carbide MOSFETs and four silicon diodes. The voltage stress of the power devices is low and the topology is simple, but there are flying capacitors and buffer capacitors, and the converter can only operate in the rectification mode.

[0006] In the prior art document 2: "Five-level Hybrid Active-NPC H-bridge Converter with Novel Space-vector-modulation Scheme", for the five-level full-bridge topology composed of two groups of ANPC bridge arms, a corresponding mixing scheme was proposed, and the overall loss of the topology was reduced through the modulation strategy, improving the converter efficiency. However, in the full-bridge topology of the prior art document 2, the number of power switching tubes is large, the economic benefit is poor, and there is a common-mode voltage problem.

[0007] In the prior art document 3: "A Novel Carrier-Overlapped PWM Method for Four-Level Neutral-Point Clamped Converters", by overlapping carrier signals with different amplitudes, an overlapping carrier modulation strategy was designed, enabling a three-level voltage to be used in one phase bridge arm within a switching period. At the same time, the duty ratios of the levels were configured to eliminate the DC current component flowing through the intermediate capacitor, achieving the balance of the DC bus intermediate filter capacitor voltage within the switching period and the balance of the outer filter capacitor voltage within the power frequency period. The above voltage balance strategy achieved the balance of the DC bus capacitor voltage under full power factor and full modulation ratio conditions, but the switching times of the inverter increased significantly, resulting in higher switching losses in high-frequency applications.

[0008] In the prior art document 4: "Carrier-based Closed-loop DC-link Voltage Balancing Algorithm for Four Level NPC Converters Based on Redundant Level Modulation", the method of combining zero-sequence component injection and capacitor voltage balancing based on redundant levels was adopted. On the basis of injecting zero-sequence components to balance the DC bus capacitor voltage, only one phase bridge arm adopted the redundant level modulation algorithm, reducing the switching times while balancing the DC bus capacitor voltage. However, this scheme still belongs to a continuous pulse width modulation scheme, and the phase with the largest output current still needs to switch at a high frequency within the switching period, resulting in relatively high switching losses.

[0009] In summary, it is necessary to study a high-efficiency and high-economic-benefit heterogeneous-switching three-phase five-level inverter, as well as a low-switching-loss pulse width modulation method suitable for the natural balance of the DC bus capacitor voltage of the heterogeneous-switching three-phase five-level inverter and a commutation control method that can optimize the inverter switching loss distribution and maximize the inverter conversion efficiency and economic benefits. Summary of the Invention

[0010] To solve the above technical problems, the present invention proposes a pulse width modulation method with low switching loss for natural balance of the DC bus capacitor voltages of a heterogeneous-switch three-phase five-level inverter, and a commutation control method for optimizing the switching loss distribution of a heterogeneous-switch three-phase five-level inverter.

[0011] To achieve the above technical objectives, the present invention adopts the following technical solutions:

[0012] The present invention relates to a pulse width modulation method for a heterogeneous-switch three-phase five-level inverter. The pulse width modulation method is a discontinuous pulse width modulation method, including:

[0013] Step S1: Obtain the maximum value u max of the three-phase sinusoidal modulation signals and the minimum value u min of the three-phase sinusoidal modulation signals from the three-phase sinusoidal modulation signals, and then obtain the superimposed component u z0 ; The three-phase sinusoidal modulation signals include the A-phase sinusoidal modulation signal u ref_A , the B-phase sinusoidal modulation signal u ref_B , and the C-phase sinusoidal modulation signal u ref_C , and their expressions are:

[0014]

[0015] The calculation expression of the maximum value u max of the three-phase sinusoidal modulation signals is:

[0016] u max = max{u ref_A , u ref_B , u ref_C}

[0017] The calculation expression of the minimum value u min of the three-phase sinusoidal modulation signals is:

[0018] u min = min{u ref_A , u ref_B , u ref_C}

[0019] The calculation expression of the superimposed component u z0 is:

[0020]

[0021] where M is the modulation ratio, determined by the inverter closed-loop control loop, f g is the grid frequency, and t is the time variable;

[0022] Step S2: Apply the superimposed component u z0Superimposed on the three-phase sinusoidal modulation signal, complete peak clamping is performed to obtain the completely peak-clamped modulation signal u mX , and the calculation expression is:

[0023] u mX = u ref_X + u z0 , X = A, B, C

[0024] Among them, u ref_X represents the X-phase sinusoidal modulation signal (X = A, B, C), and u mX represents the completely peak-clamped modulation signal of the X phase; Step S3, perform algorithm correction on the completely peak-clamped modulation signal u mX of the X phase to obtain the discontinuous pulse width modulation signal of the heterogeneous switch three-phase five-level inverter, and the calculation expression is:

[0025]

[0026]

[0027] Among them, u refA_cr1 , u refB_cr1 and u refC_cr1 respectively represent the first discontinuous pulse width modulation signal of the A phase, the first discontinuous pulse width modulation signal of the B phase, and the first discontinuous pulse width modulation signal of the C phase, u refA_cr2 , u refB_cr2 and u refC_cr2 respectively represent the second discontinuous pulse width modulation signal of the A phase, the second discontinuous pulse width modulation signal of the B phase, and the second discontinuous pulse width modulation signal of the C phase, u refA_cr3 , u refB_cr3 and u refC_cr3 respectively represent the third discontinuous pulse width modulation signal of the A phase, the third discontinuous pulse width modulation signal of the B phase, and the third discontinuous pulse width modulation signal of the C phase, u refA_cr4 , u refB_cr4 and u refC_cr4 respectively represent the fourth discontinuous pulse width modulation signal of the A phase, the fourth discontinuous pulse width modulation signal of the B phase, and the fourth discontinuous pulse width modulation signal of the C phase.

[0028] In the above pulse width modulation method of the heterogeneous switch three-phase five-level inverter, the heterogeneous switch three-phase five-level inverter includes a DC power supply, a first DC bus filter capacitor, a second DC bus filter capacitor, a third DC bus filter capacitor, a fourth DC bus filter capacitor, an A-phase bridge arm, a B-phase bridge arm, a C-phase bridge arm, an A-phase filter inductor, a B-phase filter inductor, a C-phase filter inductor, an A-phase filter capacitor, a B-phase filter capacitor, and a C-phase filter capacitor; the positive pole of the DC power supply is connected to point 4 on the DC side, and the negative pole is connected to point 0 on the DC side; the positive pole of the first DC bus filter capacitor is connected to point 4 on the DC side, and the negative pole is connected to point 3 on the DC side; the positive pole of the second DC bus filter capacitor is connected to point 3 on the DC side, and the negative pole is connected to point O on the DC side; the positive pole of the third DC bus filter capacitor is connected to point O on the DC side, and the negative pole is connected to point 1 on the DC side; the positive pole of the fourth DC bus filter capacitor is connected to point 1 on the DC side, and the negative pole is connected to point 0 on the DC side; one end of the A-phase filter inductor is connected to the output point A of the A-phase bridge arm, and the other end is connected to the first end of the A-phase filter capacitor and the first end of the A-phase AC power supply; one end of the B-phase filter inductor is connected to the output point B of the B-phase bridge arm, and the other end is connected to the first end of the B-phase filter capacitor and the first end of the B-phase AC power supply; one end of the C-phase filter inductor is connected to the output point C of the C-phase bridge arm, and the other end is connected to the first end of the C-phase filter capacitor and the first end of the C-phase AC power supply; the second ends of the A-phase filter capacitor, the B-phase filter capacitor, and the C-phase filter capacitor are connected together to form a star-connected three-phase filter capacitor; the second ends of the A-phase AC power supply, the B-phase AC power supply, and the C-phase AC power supply are connected together to form a star-connected three-phase power grid.

[0029] In the above pulse width modulation method of the heterogeneous switch three-phase five-level inverter, the voltage U of the X-phase bridge arm of the heterogeneous switch three-phase five-level inverter XO , (X = A, B, C), outputs five levels, corresponding to five switching states of the X-phase bridge arm, and the expression is:

[0030]

[0031] Among them, U dc represents the DC power supply voltage; the switching state P2 means that the output point X of the X-phase bridge arm is connected to point 4 on the DC side through a power switch tube, and the voltage between the output point X of the X-phase bridge arm and point 0 on the DC side is half of the DC power supply voltage U dc ; the switching state P1 means that the output point X of the X-phase bridge arm is connected to point 3 on the DC side through a power switch tube, and the voltage between the output point X of the X-phase bridge arm and point 0 on the DC side is the DC power supply voltage U dcOne quarter; the switch state O means that the output point X of the X-phase bridge arm is connected to the DC side O point through a power switch tube, and the voltage between the output point X of the X-phase bridge arm and the DC side O point is zero; the switch state N1 means that the output point X of the X-phase bridge arm is connected to the DC side 1 point through a power switch tube, and the voltage between the output point X of the X-phase bridge arm and the DC side O point is the DC power supply voltage U dc The opposite of one quarter; the switch state N2 means that the output point X of the X-phase bridge arm is connected to the DC side 0 point through a power switch tube, and the voltage between the output point X of the X-phase bridge arm and the DC side O point is the DC power supply voltage U dc The opposite of one half.

[0032] In the pulse width modulation method of the above heterogeneous switch three-phase five-level inverter, during the process of performing complete peak clamping in step S2, when the absolute value of the maximum value u of the three-phase sinusoidal modulation signal max is greater than the absolute value of the minimum value u of the three-phase sinusoidal modulation signal min , the minimum value u of the three-phase sinusoidal modulation signal min is located in the regions on both sides of the peak of the negative half cycle of the three-phase sinusoidal modulation signal. At this time, the superimposed component u is superimposed on the three-phase sinusoidal modulation signal z0 . In the regions on both sides of the peak of the negative half cycle of the three-phase sinusoidal modulation signal, the minimum phase of the three-phase modulation signal is clamped to negative one to obtain the complete peak clamping modulation signal u mX . In the heterogeneous switch three-phase five-level inverter, the X-phase bridge arm is clamped to the N2 switch state; when the absolute value of the maximum value u of the three-phase sinusoidal modulation signal max is less than the absolute value of the minimum value u of the three-phase sinusoidal modulation signal min , the maximum value u of the three-phase sinusoidal modulation signal max is located in the regions on both sides of the peak of the positive half cycle of the three-phase sinusoidal modulation signal. At this time, the superimposed component u is superimposed on the three-phase sinusoidal modulation signal z0 . In the regions on both sides of the peak of the positive half cycle of the three-phase sinusoidal modulation signal, the maximum phase of the three-phase modulation signal is clamped to one to obtain the complete peak clamping modulation signal u mX . In the heterogeneous switch three-phase five-level inverter, the X-phase bridge arm is clamped to the P2 switch state.

[0033] In the pulse width modulation method of the above heterogeneous switch three-phase five-level inverter, the discontinuous pulse width modulation signal of the heterogeneous switch three-phase five-level inverter after algorithm correction is modulated with its corresponding four-way carrier signals to obtain the switch states of the three-phase bridge arms, realizing the natural balance of the DC bus filter capacitor voltage of the heterogeneous switch three-phase five-level inverter; the four-way carrier signals are in-phase triangular carrier signals, and the four-way carrier signals include carrier signal one u st1 , carrier signal two u st2 , carrier signal three u st3, and carrier signal four u st4 ; The peak-to-peak value range of carrier signal one u st1 is from one-half to one, and the peak-to-peak value range of carrier signal two u st2 is from zero to one-half, and the peak-to-peak value range of carrier signal three u st3 is from the opposite of one-half to zero, and the peak-to-peak value range of carrier signal four u st4 is from the opposite of one to the opposite of one-half.

[0034] The present invention also relates to a commutation control method for a heterogeneous-switch three-phase five-level inverter. The heterogeneous-switch three-phase five-level inverter includes a first power switch tube, a second power switch tube, a third power switch tube, a fourth power switch tube, a fifth power switch tube, a sixth power switch tube, a seventh power switch tube, an eighth power switch tube, a ninth power switch tube, a tenth power switch tube, an eleventh power switch tube, a twelfth power switch tube, a thirteenth power switch tube, a fourteenth power switch tube, a fifteenth power switch tube, a sixteenth power switch tube, a seventeenth power switch tube, an eighteenth power switch tube, a nineteenth power switch tube, a twentieth power switch tube, a twenty-first power switch tube, a twenty-second power switch tube, a twenty-third power switch tube, and a twenty-fourth power switch tube; The first power switch tube to the eighth power switch tube are connected to form an A-phase bridge arm; The ninth power switch tube to the sixteenth power switch tube are connected to form a B-phase bridge arm; The seventeenth power switch tube to the twenty-fourth power switch tube are connected to form a C-phase bridge arm;

[0035] The X-phase bridge arm is a 4-SiC bridge arm (X = A, B, C), which is composed of 4 SiC metal oxide semiconductor field effect transistors and 4 Si insulated gate bipolar transistors;

[0036] The fifth power switch tube, the sixth power switch tube, the seventh power switch tube, the eighth power switch tube, the thirteenth power switch tube, the fourteenth power switch tube, the fifteenth power switch tube, the sixteenth power switch tube, the twenty-first power switch tube, the twenty-second power switch tube, the twenty-third power switch tube, and the twenty-fourth power switch tube use SiC metal oxide semiconductor field effect transistors; The first power switch tube, the second power switch tube, the third power switch tube, the fourth power switch tube, the ninth power switch tube, the tenth power switch tube, the eleventh power switch tube, the twelfth power switch tube, the seventeenth power switch tube, the eighteenth power switch tube, the nineteenth power switch tube, and the twentieth power switch tube use Si insulated gate bipolar transistors;

[0037] The commutation control method uses the discontinuous pulse width modulation signal of the heterogeneous-switch three-phase five-level inverter obtained by the above pulse width modulation method; The commutation control method further includes configuring a dead time signal one t dead1, dead time signal two t dead2 , and dead time signal three t dead3 , used to implement the dead time mode when the switching state of the X-phase bridge arm changes. In the dead time mode, the X-phase bridge arm is in the switching state O;

[0038] When the discontinuous PWM signal one u of phase A refA_cr1 is greater than the carrier signal one u st1 , or when the sum of the discontinuous PWM signal one u of phase A refA_cr1 and the dead time signal three t dead3 is less than the carrier signal one u st1 and the discontinuous PWM signal two u of phase A refA_cr2 is greater than the carrier signal two u st2 , the drive signal of the seventh power switch tube is high, otherwise it is low; when the sum of the discontinuous PWM signal one u of phase A refA_cr1 and the dead time signal one t dead1 is greater than the carrier signal one u st1 , the drive signal of the first power switch tube is high, otherwise it is low; when the sum of the discontinuous PWM signal one u of phase A refA_cr1 and the dead time signal two t dead2 is less than the carrier signal one u st1 , the drive signal of the second power switch tube is high, otherwise it is low; when the discontinuous PWM signal two u of phase A refA_cr2 is less than the carrier signal two u st2 , the drive signal of the sixth power switch tube is high, otherwise it is low; when the discontinuous PWM signal four u of phase A refA_cr4 is less than the carrier signal four u st4 , or when the difference between the discontinuous PWM signal four u of phase A refA_cr4 and the dead time signal three t dead3 is greater than the carrier signal four u st4 and the discontinuous PWM signal three u of phase A refA_cr3 is less than the carrier signal three u st3 , the drive signal of the eighth power switch tube is high, otherwise it is low; when the difference between the discontinuous PWM signal four u of phase A refA_cr4 and the dead time signal one t dead1 is less than the carrier signal four u st4 , the drive signal of the fourth power switch tube is high, otherwise it is low; when the difference between the discontinuous PWM signal four u of phase A refA_cr4 and the dead time signal two t dead2 is greater than the carrier signal four u st4 , the drive signal of the third power switch tube is high, otherwise it is low; when the discontinuous PWM signal three u of phase A refX_cr3 is less than the carrier signal three u st3When it is, the drive signal of the fifth power switch tube is high; otherwise, it is low.

[0039] When the discontinuous pulse width modulation signal of phase B - u refB_cr1 is greater than the carrier signal - u st1 or when the sum of the discontinuous pulse width modulation signal of phase B - u refX_cr1 and the dead - time signal - t dead3 is less than the carrier signal - u st1 and the discontinuous pulse width modulation signal of phase B - u refB_cr2 is greater than the carrier signal of phase B - u st2 the drive signal of the fifteenth power switch tube is high; otherwise, it is low. When the discontinuous pulse width modulation signal of phase B - u refB_cr1 and the dead - time signal - t dead1 the sum is greater than the carrier signal - u st1 the drive signal of the ninth power switch tube is high; otherwise, it is low. When the discontinuous pulse width modulation signal of phase B - u refB_cr1 and the dead - time signal - t dead2 the sum is less than the carrier signal - u st1 the drive signal of the tenth power switch tube is high; otherwise, it is low. When the discontinuous pulse width modulation signal of phase B - u refB_cr2 is less than the carrier signal of phase B - u st2 the drive signal of the fourteenth power switch tube is high; otherwise, it is low. When the discontinuous pulse width modulation signal of phase B - u refB_cr4 is less than the carrier signal of phase B - u st4 or the difference between the discontinuous pulse width modulation signal of phase B - u refB_cr4 and the dead - time signal - t dead3 is greater than the carrier signal of phase B - u st4 and the discontinuous pulse width modulation signal of phase B - u refB_cr3 is less than the carrier signal of phase B - u st3 the drive signal of the sixteenth power switch tube is high; otherwise, it is low. When the difference between the discontinuous pulse width modulation signal of phase B - u refB_cr4 and the dead - time signal - t dead1 is less than the carrier signal of phase B - u st4 the drive signal of the twelfth power switch tube is high; otherwise, it is low. When the difference between the discontinuous pulse width modulation signal of phase B - u refB_cr4 and the dead - time signal - t dead2 is greater than the carrier signal of phase B - u st4 the drive signal of the eleventh power switch tube is high; otherwise, it is low. When the discontinuous pulse width modulation signal of phase B - u refB_cr3 is less than the carrier signal of phase B - u st3 the drive signal of the thirteenth power switch tube is high; otherwise, it is low.

[0040] When the C-phase discontinuous pulse width modulation signal -u refC_cr1 is greater than the carrier signal -u st1 or when the sum of the C-phase discontinuous pulse width modulation signal -u refC_cr1 and the dead time signal -t dead3 is less than the carrier signal -u st1 and the C-phase discontinuous pulse width modulation signal -u refC_cr2 is greater than the carrier signal -u st2 the drive signal of the twenty-third power switch is high, otherwise it is low; when the sum of the C-phase discontinuous pulse width modulation signal -u refC_cr1 and the dead time signal -t dead1 is greater than the carrier signal -u st1 the drive signal of the seventeenth power switch is high, otherwise it is low; when the sum of the C-phase discontinuous pulse width modulation signal -u refC_cr1 and the dead time signal -t dead2 is less than the carrier signal -u st1 the drive signal of the eighteenth power switch is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal -u refC_cr2 is less than the carrier signal -u st2 the drive signal of the twenty-second power switch is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal -u refC_cr4 is less than the carrier signal -u st4 or when the difference between the three-phase discontinuous pulse width modulation signal -u refC_cr4 and the dead time signal -t dead3 is greater than the carrier signal -u st4 and the three-phase discontinuous pulse width modulation signal -u refC_cr3 is less than the carrier signal -u st3 the drive signal of the twenty-fourth power switch is high, otherwise it is low; when the difference between the C-phase discontinuous pulse width modulation signal -u refC_cr4 and the dead time signal -t dead1 is less than the carrier signal -u st4 the drive signal of the twentieth power switch is high, otherwise it is low; when the difference between the C-phase discontinuous pulse width modulation signal -u refC_cr4 and the dead time signal -t dead2 is greater than the carrier signal -u st4 the drive signal of the nineteenth power switch is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal -u refC_cr3 is less than the carrier signal -u st3 the drive signal of the twenty-first power switch is high, otherwise it is low.

[0041] The present invention also relates to a commutation control method for a heterogeneous-switch three-phase five-level inverter. The heterogeneous-switch three-phase five-level inverter includes a first power switch, a second power switch, a third power switch, a fourth power switch, a fifth power switch, a sixth power switch, a seventh power switch, an eighth power switch, a ninth power switch, a tenth power switch, an eleventh power switch, a twelfth power switch, a thirteenth power switch, a fourteenth power switch, a fifteenth power switch, a sixteenth power switch, a seventeenth power switch, an eighteenth power switch, a nineteenth power switch, a twentieth power switch, a twenty-first power switch, a twenty-second power switch, a twenty-third power switch, and a twenty-fourth power switch. The first to eighth power switches are connected to form an A-phase bridge arm. The ninth to sixteenth power switches are connected to form a B-phase bridge arm. The seventeenth to twenty-fourth power switches are connected to form a C-phase bridge arm.

[0042] The X-phase bridge arm (X = A, B, C) is a 2-SiC bridge arm, which is composed of 2 SiC metal-oxide-semiconductor field-effect transistors and 6 Si insulated-gate bipolar transistors. The seventh, eighth, fifteenth, sixteenth, twenty-third, and twenty-fourth power switches use SiC metal-oxide-semiconductor field-effect transistors. The first, second, third, fourth, fifth, sixth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, seventeenth, eighteenth, nineteenth, twentieth, twenty-first, and twenty-second power switches use Si insulated-gate bipolar transistors.

[0043] The commutation control method uses the discontinuous pulse-width modulation signal of the heterogeneous-switch three-phase five-level inverter obtained by the above-mentioned pulse-width modulation method. The commutation control method further includes configuring dead-time signal one u refA_cr1 , dead-time signal two t dead2 , and dead-time signal three t dead3 to implement the dead-time mode when the switch state of the X-phase bridge arm is switched. In the dead-time mode, the X-phase bridge arm is in the switch state O.

[0044] When the A-phase discontinuous pulse-width modulation signal one u refA_cr1 is greater than the carrier signal one u st1 , or when the A-phase discontinuous pulse-width modulation signal one u refA_cr1 and the dead-time signal three t dead3The sum is less than the carrier signal one u st1 and the discontinuous PWM signal two u of phase A refA_cr2 is greater than the carrier signal two u st2 the drive signal of the seventh power switch is high, otherwise it is low; when the discontinuous PWM signal one u of phase A refA_cr1 and the dead time signal one t dead1 the sum is greater than the carrier signal one u st1 the drive signal of the first power switch is high, otherwise it is low; when the discontinuous PWM signal one u of phase A refA_cr1 and the dead time signal two t dead2 the sum is less than the carrier signal one u st1 the drive signal of the second power switch is high, otherwise it is low; when the discontinuous PWM signal two u of phase A refA_cr2 is greater than zero, the drive signal of the sixth power switch is low, otherwise it is high; when the discontinuous PWM signal four u of phase A refA_cr4 is less than the carrier signal four u st4 or when the discontinuous PWM signal four u of phase A refA_cr4 and the dead time signal three t dead3 the difference is greater than the carrier signal four u st4 and the discontinuous PWM signal three u of phase A refA_cr3 is less than the carrier signal three u st3 the drive signal of the eighth power switch is high, otherwise it is low; when the discontinuous PWM signal four u of phase A refA_cr4 and the dead time signal one t dead1 the difference is less than the carrier signal four u st4 the drive signal of the fourth power switch is high, otherwise it is low; when the discontinuous PWM signal four u of phase A refA_cr4 and the dead time signal two t dead2 the difference is greater than the carrier signal four u st4 the drive signal of the third power switch is high, otherwise it is low; when the discontinuous PWM signal three u of phase A refX_cr3 is less than zero, the drive signal of the fifth power switch is low, otherwise it is high;

[0045] When the discontinuous PWM signal one u of phase B refB_cr1 is greater than the carrier signal one u st1 or when the discontinuous PWM signal one u of phase B refX_cr1 and the dead time signal three t dead3 the sum is less than the carrier signal one u st1 and the discontinuous PWM signal two u of phase B refB_cr2 is greater than the carrier signal two u st2When the drive signal of the fifteenth power switch tube is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B - u refB_cr1 and the dead - time signal - t dead1 sum is greater than the carrier signal - u st1 the drive signal of the ninth power switch tube is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B - u refB_cr1 and the dead - time signal two - t dead2 sum is less than the carrier signal - u st1 the drive signal of the tenth power switch tube is high, otherwise it is low; when the discontinuous pulse width modulation signal two of phase B - u refA_cr2 is greater than zero, the drive signal of the fourteenth power switch tube is low, otherwise it is high; when the discontinuous pulse width modulation signal four of phase B - u refB_cr4 is less than the carrier signal four - u st4 or when the discontinuous pulse width modulation signal four of phase B - u refB_cr4 and the difference between the dead - time signal three - t dead3 is greater than the carrier signal four - u st4 and the discontinuous pulse width modulation signal three of phase B - u refB_cr3 is less than the carrier signal three - u st3 the drive signal of the sixteenth power switch tube is high, otherwise it is low; when the discontinuous pulse width modulation signal four of phase B - u refB_cr4 and the difference between the dead - time signal one - t dead1 is less than the carrier signal four - u st4 the drive signal of the twelfth power switch tube is high, otherwise it is low; when the discontinuous pulse width modulation signal four of phase B - u refB_cr4 and the difference between the dead - time signal two - t dead2 is greater than the carrier signal four - u st4 the drive signal of the eleventh power switch tube is high, otherwise it is low; when the discontinuous pulse width modulation signal two of phase B - u refA_cr2 is less than zero, the drive signal of the thirteenth power switch tube is low, otherwise it is high;

[0046] When the discontinuous pulse width modulation signal one of phase C - u refC_cr1 is greater than the carrier signal one - u st1 or when the discontinuous pulse width modulation signal one of phase C - u refC_cr1 and the dead - time signal three - t dead3 sum is less than the carrier signal one - u st1 and the discontinuous pulse width modulation signal two of phase C - u refC_cr2 is greater than the carrier signal two - u st2 the drive signal of the twenty - third power switch tube is high, otherwise it is low; when the discontinuous pulse width modulation signal one of phase C - u refC_cr1 and the dead - time signal one - t dead1 sum is greater than the carrier signal one - ust1 When it is, the driving signal of the seventeenth power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal -u refC_cr1 and the dead time signal two t dead2 The sum is less than the carrier signal one u st1 When it is, the driving signal of the eighteenth power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal two u refA_cr2 is greater than zero, the driving signal of the twenty-second power switch tube is low, otherwise it is high; when the C-phase discontinuous pulse width modulation signal four u refC_cr4 is less than the carrier signal four u st4 When it is, or the three-phase discontinuous pulse width modulation signal four u refC_cr4 and the dead time signal three t dead3 The difference is greater than the carrier signal four u st4 and the three-phase discontinuous pulse width modulation signal three u refC_cr3 is less than the carrier signal three u st3 When it is, the driving signal of the twenty-fourth power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal four u refC_cr4 and the dead time signal one t dead1 The difference is less than the carrier signal four u st4 When it is, the driving signal of the twentieth power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal four u refC_cr4 and the dead time signal two t dead2 The difference is greater than the carrier signal four u st4 When it is, the driving signal of the nineteenth power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal two u refA_cr2 is less than zero, the driving signal of the twenty-first power switch tube is low, otherwise it is high.

[0047] Beneficial effects brought by adopting the above technical solutions:

[0048] In the pulse width modulation method of the present invention, the DC bus capacitor voltage of the heterogeneous switch three-phase five-level inverter can be naturally balanced. At the same time, the switch state of one phase bridge arm is clamped, the number of switchings is small, the switching loss is small, and the converter efficiency is high. Therefore, the modulation method and circuit involved in the present invention are applicable to occasions such as renewable power generation, and have broad application prospects in the fields of photovoltaic power generation and the like.

[0049] In the commutation control method of the present invention, by optimizing the switching action sequence of the power switch tubes during the commutation process of the three-phase bridge arm, the silicon carbide metal oxide field effect transistor in the heterogeneous switch three-phase five-level inverter topology bears most of the switching losses, and the silicon insulated gate bipolar transistor realizes zero-current turn-on and turn-off, only bearing the on-state loss and a small amount of diode loss, optimizing the loss distribution of the inverter topology, and improving the conversion efficiency and economic benefits of the inverter.

[0050] In order to make the above - mentioned features and advantages of the invention more obvious and understandable, specific embodiments are given below and will be described in detail in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a circuit schematic diagram of the main power topology and its control circuit of a heterogeneous - switch three - phase five - level inverter.

[0052] Figure 2 It is a steady - state operation simulation waveform diagram of an example of the pulse - width modulation method of the heterogeneous - switch three - phase five - level inverter using the present invention.

[0053] Figure 3 It is a circuit modal diagram of the commutation process when the switching state of the A - phase bridge arm of the heterogeneous - switch three - phase five - level inverter of the present invention switches between P1 and P2 in the case where 4 silicon carbide metal - oxide semiconductor field - effect transistors are used in each phase bridge arm.

[0054] Figure 4 It is a circuit modal diagram of the commutation process when the switching state of the A - phase bridge arm of the heterogeneous - switch three - phase five - level inverter of the present invention switches between P1 and O in the case where 4 silicon carbide metal - oxide semiconductor field - effect transistors are used in each phase bridge arm.

[0055] Figure 5 It is a circuit modal diagram of the commutation process when the switching state of the A - phase bridge arm of the heterogeneous - switch three - phase five - level inverter of the present invention switches between P1 and P2 in the case where 2 silicon carbide metal - oxide semiconductor field - effect transistors are used in each phase bridge arm.

[0056] Figure 6 It is a circuit modal diagram of the commutation process when the switching state of the A - phase bridge arm of the heterogeneous - switch three - phase five - level inverter of the present invention switches between P1 and O in the case where 2 silicon carbide metal - oxide semiconductor field - effect transistors are used in each phase bridge arm. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0057] In order to make the objectives and technical solutions of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0058] Figure 1 It is a circuit schematic diagram of the main power topology and its control circuit of a heterogeneous - switch three - phase five - level inverter.

[0059] As Figure 1 shown, a three-phase five-level inverter 10 is connected to a three-phase power grid 30. The three-phase power grid 30 includes an A-phase AC power supply u sA , a B-phase AC power supply u sB , and a C-phase AC power supply u sC .

[0060] The three-phase five-level inverter 10 includes a DC power supply group 101, a DC bus filter capacitor group 102, a power switch tube group 103, a three-phase filter inductor group 104, and a three-phase filter capacitor group 105.

[0061] Among them, the DC power supply group 101 includes a DC power supply U dc ; the DC bus filter capacitor group 102 includes a first DC bus filter capacitor C dc1 , a second DC bus filter capacitor C dc2 , a third DC bus filter capacitor C dc3 , and a fourth DC bus filter capacitor C dc4 ; the power switch tube group 103 includes a first power switch tube S1, a second power switch tube S2, a third power switch tube S3, a fourth power switch tube S4, a fifth power switch tube S5, a sixth power switch tube S6, a seventh power switch tube S7, an eighth power switch tube S8, a ninth power switch tube S9, a tenth power switch tube S 10 , an eleventh power switch tube S 11 , a twelfth power switch tube S 12 , a thirteenth power switch tube S 13 , a fourteenth power switch tube S 14 , a fifteenth power switch tube S 15 , a sixteenth power switch tube S 16 , a seventeenth power switch tube S 17 , and an eighteenth power switch tube S 18 , a nineteenth power switch tube S 19 , a twentieth power switch tube S 20 , a twenty-first power switch tube S 21 , a twenty-second power switch tube S 22 , a twenty-third power switch tube S 23 , and a twenty-fourth power switch tube S 24 ; the three-phase filter inductor group 104 includes an A-phase filter inductor L fa , a B-phase filter inductor L fb , and a C-phase filter inductor L fc ; the three-phase filter capacitor group 105 includes an A-phase filter capacitor C fa , a B-phase filter capacitor C fb, and the C-phase filter capacitor C fc .

[0062] The positive pole of the DC power supply U dc is connected to point 4 on the DC side, and the negative pole is connected to point 0 on the DC side; the positive pole of the first DC bus filter capacitor C dc1 is connected to point 4 on the DC side, and the negative pole is connected to point 3 on the DC side; the positive pole of the second DC bus filter capacitor C dc2 is connected to point 3 on the DC side, and the negative pole is connected to point O on the DC side; the positive pole of the third DC bus filter capacitor C dc3 is connected to point O on the DC side, and the negative pole is connected to point 1 on the DC side; the positive pole of the fourth DC bus filter capacitor C d4 is connected to point 1 on the DC side, and the negative pole is connected to point 0 on the DC side.

[0063] In the power switch tube group 103, the first power switch tube S1 to the eighth power switch tube S8 are connected to form an A-phase bridge arm; the ninth power switch tube S9 to the sixteenth power switch tube S 16 are connected to form a B-phase bridge arm; the seventeenth power switch tube S 17 to the twenty-fourth power switch tube S 24 are connected to form a C-phase bridge arm.

[0064] In the present invention, the three-phase five-level inverter 10 adopts a heterogeneous-switch three-phase five-level inverter. Among the eight power switch tubes in each phase bridge arm, 4 or 2 silicon carbide metal-oxide-semiconductor field-effect transistors can be used, and the other power switch tubes still select silicon insulated-gate bipolar transistors.

[0065] When 4 silicon carbide metal-oxide-semiconductor field-effect transistors are used in each phase bridge arm, that is, in the 4-silicon carbide bridge arm main power topology circuit of the heterogeneous-switch three-phase five-level inverter, in the A-phase bridge arm, the first power switch tube S1 to the fourth power switch tube S4 are preferably silicon insulated-gate bipolar transistors, and the fifth power switch tube S5 to the eighth power switch tube S8 are preferably silicon carbide metal-oxide-semiconductor field-effect transistors; in the B-phase bridge arm, the ninth power switch tube S9 to the twelfth power switch tube S 12 are preferably silicon insulated-gate bipolar transistors, and the thirteenth power switch tube S 13 to the sixteenth power switch tube S 16 are preferably silicon carbide metal-oxide-semiconductor field-effect transistors; in the C-phase bridge arm, the seventeenth power switch tube S 17 to the twentieth power switch tube S 20 are preferably silicon insulated-gate bipolar transistors, and the twenty-first power switch tube S 21 to the twenty-fourth power switch tube S 24Preferably, a silicon carbide metal oxide semiconductor field effect transistor is adopted.

[0066] In each phase bridge arm, 2 silicon carbide metal oxide semiconductor field effect transistors are used. That is, in the 2-silicon carbide bridge arm main power topology circuit of the heterogeneous switch three-phase five-level inverter, in the A-phase bridge arm, the first power switch tube S1 to the sixth power switch tube S6 preferably adopt silicon insulated gate bipolar transistors, and the seventh power switch tube S7 to the eighth power switch tube S8 preferably adopt silicon carbide metal oxide semiconductor field effect transistors; in the B-phase bridge arm, the ninth power switch tube S9 to the fourteenth power switch tube S 14 Preferably, a silicon insulated gate bipolar transistor is adopted, and the fifteenth power switch tube S 15 to the sixteenth power switch tube S 16 Preferably, a silicon carbide metal oxide semiconductor field effect transistor is adopted; in the C-phase bridge arm, the seventeenth power switch tube S 17 to the twenty-second power switch tube S 22 Preferably, a silicon insulated gate bipolar transistor is adopted, and the twenty-third power switch tube S 23 to the twenty-fourth power switch tube S 24 Preferably, a silicon carbide metal oxide semiconductor field effect transistor is adopted.

[0067] The main power topology circuits of the heterogeneous switch three-phase five-level inverter 2-silicon carbide bridge arm and the heterogeneous switch three-phase five-level inverter 4-silicon carbide bridge arm have the same structure. Taking the 2-silicon carbide bridge arm main power topology circuit as an example, the topological connection structure of the main power circuit is described.

[0068] In the A-phase bridge arm, the collector of the first power switch tube S1 is connected to the positive pole of the DC power supply U dc , the emitter of the first power switch tube S1 is connected to the collector of the second power switch tube S2, the emitter of the second power switch tube S2 is connected to the common terminal of the first DC bus filter capacitor C dc1 and the second DC bus filter capacitor C dc2 , the collector of the third power switch tube S3 is connected to the common terminal of the third DC bus filter capacitor C dc3 and the fourth DC bus filter capacitor C dc4 , the emitter of the third power switch tube S3 is connected to the collector of the fourth power switch tube S4, the emitter of the fourth power switch tube S4 is connected to the negative pole of the DC power supply U dc , the collector of the fifth power switch tube S5 is connected to the common terminal of the second DC bus filter capacitor C dc2 and the third DC bus filter capacitor C dc3The common terminal is connected, the emitter of the fifth power switch tube S5 is connected to the emitter-collector of the sixth power switch tube S6, the drain of the seventh power switch tube S7 is connected to the common terminal of the first power switch tube S1 and the second power switch tube S2, the source of the seventh power switch tube S7 is connected to the drain of the eighth power switch tube S8, the source of the eighth power switch tube S8 is connected to the common terminal of the third power switch tube S3 and the fourth power switch tube S4, and the common terminal of the seventh power switch tube S7 and the eighth power switch tube S8 is connected to the collector of the sixth power switch tube S6; the connection point of the seventh power switch tube S7 and the eighth power switch tube S8 is the A-phase bridge arm output point A.

[0069] In the B-phase bridge arm, the collector of the ninth power switch tube S9 is connected to the positive pole of the DC power supply U dc The emitter of the ninth power switch tube S9 is connected to the collector of the tenth power switch tube S 10 The emitter of the tenth power switch tube S 10 Is connected to the common terminal of the first DC bus filter capacitor C dc1 And the second DC bus filter capacitor C dc2 The collector of the eleventh power switch tube S 11 Is connected to the common terminal of the third DC bus filter capacitor C dc3 And the fourth DC bus filter capacitor C dc4 The emitter of the eleventh power switch tube S 11 Is connected to the collector of the twelfth power switch tube S 12 The emitter of the twelfth power switch tube S 12 Is connected to the negative pole of the DC power supply U dc The collector of the thirteenth power switch tube S 13 Is connected to the common terminal of the second DC bus filter capacitor C dc2 And the third DC bus filter capacitor C dc3 The emitter of the thirteenth power switch tube S 13 Is connected to the emitter of the fourteenth power switch tube S 14 The drain of the fifteenth power switch tube S 15 Is connected to the common terminal of the ninth power switch tube S9 and the tenth power switch tube S 10 The source of the fifteenth power switch tube S 15 Is connected to the drain of the sixteenth power switch tube S 16 The source of the sixteenth power switch tube S 16 Is connected to the common terminal of the eleventh power switch tube S 11 And the twelfth power switch tube S 12 The source of the fifteenth power switch tube S 15 And the sixteenth power switch tube S 16The common terminal and the fourteenth power switch tube S 14 are connected to the collector; the fifteenth power switch tube S 15 and the sixteenth power switch tube S 16 The connection point is the output point B of the B-phase bridge arm.

[0070] In the C-phase bridge arm, the collector of the seventeenth power switch tube S 17 is connected to the positive pole of the DC power supply U dc , the emitter of the seventeenth power switch tube S 17 is connected to the collector of the eighteenth power switch tube S 18 , the emitter of the eighteenth power switch tube S 18 is connected to the common terminal of the first DC bus filter capacitor C dc1 and the second DC bus filter capacitor C dc2 , the collector of the nineteenth power switch tube S 19 is connected to the common terminal of the third DC bus filter capacitor C dc3 and the fourth DC bus filter capacitor C dc4 , the emitter of the nineteenth power switch tube S 19 is connected to the collector of the twentieth power switch tube S 20 , the emitter of the twentieth power switch tube S 20 is connected to the negative pole of the DC power supply U dc , the collector of the twenty-first power switch tube S 21 is connected to the common terminal of the second DC bus filter capacitor C dc2 and the third DC bus filter capacitor C dc3 , the emitter of the twenty-first power switch tube S 21 is connected to the emitter of the twenty-second power switch tube S 22 , the drain of the twenty-third power switch tube S 23 is connected to the common terminal of the seventeenth power switch tube S 17 and the eighteenth power switch tube S 18 , the source of the twenty-third power switch tube S 23 is connected to the drain of the eighth power switch tube S8, the source of the twenty-fourth power switch tube S 24 is connected to the common terminal of the nineteenth power switch tube S 19 and the twentieth power switch tube S 20 , the common terminal of the twenty-third power switch tube S 23 and the twenty-fourth power switch tube S 24 is connected to the collector of the twenty-second power switch tube S 22 ; the common terminal of the twenty-third power switch tube S 23 and the twenty-fourth power switch tube S 24 The connection point is the output point C of the C-phase bridge arm.

[0071] The filtering inductor L of phase A fa has one end connected to the output point A of the phase A bridge arm and the other end connected to the first end of the filtering capacitor C of phase A fa and the first end of the AC power supply u of phase A sA ; The filtering inductor L of phase B fb has one end connected to the output point B of the phase B bridge arm and the other end connected to the first end of the filtering capacitor C of phase B fb and the first end of the AC power supply u of phase B sB ; The filtering inductor L of phase C fc has one end connected to the output point C of the phase C bridge arm and the other end connected to the first end of the filtering capacitor C of phase C fc and the first end of the AC power supply u of phase C sC ; The second end of the filtering capacitor C of phase A fa , the second end of the filtering capacitor C of phase B fb , and the second end of the filtering capacitor C of phase C fc are connected together to form a star-connected three-phase filtering capacitor; The second end of the AC power supply u of phase A sA , the second end of the AC power supply u of phase B sB , and the second end of the AC power supply u of phase C sC are connected together to form a star-connected three-phase power grid, and the connection point is n.

[0072] The three-phase bridge arm voltage U XO , where X is equal to A, B, and C, outputs five levels, corresponding to five switching states of a single-phase bridge arm, and the expression is:

[0073]

[0074] Among them, the switching state P2 means that the output point X of the X-phase bridge arm is connected to point 4 of the DC side through a power switch tube, and the voltage between the output point X of the X-phase bridge arm and point O of the DC side is half of the DC power supply voltage; the switching state P1 means that the output point X of the X-phase bridge arm is connected to point 3 of the DC side through a power switch tube, and the voltage between the output point X of the X-phase bridge arm and point O of the DC side is one-fourth of the DC power supply voltage; the switching state O means that the output point X of the X-phase bridge arm is connected to point O of the DC side through a power switch tube, and the voltage between the output point X of the X-phase bridge arm and point O of the DC side is zero; the switching state N1 means that the output point X of the X-phase bridge arm is connected to point 1 of the DC side through a power switch tube, and the voltage between the output point X of the X-phase bridge arm and point O of the DC side is the opposite of one-fourth of the DC power supply voltage; the switching state N2 means that the output point X of the X-phase bridge arm is connected to point 0 of the DC side through a power switch tube, and the voltage between the output point X of the X-phase bridge arm and point O of the DC side is the opposite of half of the DC power supply voltage;

[0075] The control circuit 20 is connected to the three-phase five-level inverter 10. The control circuit 20 includes a power switch tube driving unit 201, an inductor current sampling unit 202, a grid voltage sampling unit 203, and a DSP control unit 204.

[0076] The DSP control unit 204 includes a commutation controller 2040, a first abc / dq converter 2041, a second abc / dq converter 2042, a phase-locked loop 2043, a first subtractor 2044, a second subtractor 2045, a reactive current PI regulator 2046, an active current PI regulator 2047, a dq / abc converter 2048, and a DPWM controller 2049.

[0077] The three input terminals of the grid voltage sampling unit 203 are respectively connected to the connection point of the phase-A filter capacitor C fa and the phase-A AC power supply u sA , the connection point of the phase-B filter capacitor C fb and the phase-B AC power supply u sB , and the connection point of the phase-C filter capacitor C fc and the phase-C AC power supply u sC ; the three output signals u sA , u sB and u sB of the grid voltage sampling unit 203 are connected to the first, second, and third input terminals of the first abc / dq converter 2041; the three input terminals of the inductor current sampling unit 202 are correspondingly connected to the connection point of the phase-A filter inductor L fa and the phase-A bridge arm output voltage point A, the connection point of the phase-B filter inductor L fc and the phase-B bridge arm output voltage point B, and the connection point of the phase-C filter inductor L fc and the phase-C bridge arm output voltage point C. The three output signals i LA , i LB and i LC of the inductor current sampling unit 202 are connected to the first, second, and third input terminals of the second abc / dq converter 2042.

[0078] The two output signals u d , u q of the first abc / dq converter 2041 are respectively connected to the two input terminals of the phase-locked loop 2043. The output signal θ of the phase-locked loop 2043 is connected to the fourth input terminal of the first abc / dq converter 2041, the fourth input terminal of the second abc / dq converter 2042, and the first input terminal of the dq / abc converter 2048; the second output signal i qConnected to the first input terminal of the first subtractor 2044, the second input terminal of the first subtractor 2044 inputs a given reference value of 0, and the output terminal of the second subtractor 2045 is connected to the input terminal of the reactive current PI regulator 2046; the first output signal i of the second abc / dq converter 2042 d Connected to the first input terminal of the second subtractor 2045, the second input terminal of the second subtractor 2045 inputs a given reference value i d_ref , and the output terminal of the second subtractor 2045 is connected to the input terminal of the active current PI regulator 2047; the second input terminal and the third input terminal of the dq / abc converter 5048 are respectively connected to the output signal u of the reactive current PI regulator 2046 q1 and the output signal u of the active current PI regulator 2047 d1 ; the three output signals of the dq / abc converter 2048, namely the sinusoidal modulation signal u of phase A ref_A , the sinusoidal modulation signal u of phase B ref_B , and the sinusoidal modulation signal u of phase C ref_C are respectively connected to the three input terminals of the discontinuous pulse width modulation controller 2049; the 12 output signals u of the discontinuous pulse width modulation controller 2049 refA_cr1～4 , u refB_cr1～4 , u refC_cr1～4 are connected to the input terminal of the commutation controller 2040, and the input terminal of the commutation controller 2040 is also connected to four carrier signals u st1～4 ; the 24 output signals of the commutation controller 2040 are respectively connected to the respective input terminals of the power switch tube drive unit 201, and the 24 output signals u of the power switch tube drive unit 201 gs1～ u gs24 are respectively connected to the drive poles of the first power switch tube S1 to the twenty-fourth power switch tube S 24 for outputting the drive signals corresponding to the respective power switch tubes.

[0079] Based on the above control circuit of the heterogeneous switch three-phase five-level inverter, the present invention proposes a discontinuous pulse width modulation method for the discontinuous pulse width modulation controller 2049 in the control circuit 20 of the above three-phase five-level inverter, specifically including the following steps:

[0080] Step S1: Obtain the maximum value u of the three-phase sinusoidal modulation signal and the minimum value u of the three-phase sinusoidal modulation signal according to the three-phase sinusoidal modulation signal, and then obtain the superimposed component u max and the minimum value u of the three-phase sinusoidal modulation signal min , and then obtain the superimposed component u z0 ;

[0081] The three-phase sinusoidal modulation signal includes the sinusoidal modulation signal u of phase A ref_A , the sinusoidal modulation signal u of phase Bref_B , and the sine modulation signal u of phase C ref_C , and its expression is:

[0082]

[0083] The maximum value u of the three-phase sine modulation signal max The calculation expression is:

[0084] u max = max{u ref_A , u ref_B , u ref_C}

[0085] The minimum value u of the three-phase sine modulation signal min The calculation expression is:

[0086] u min = min{u ref_A , u ref_B , u ref_C}

[0087] The calculation expression of the superimposed component u z0 is:

[0088]

[0089] where M is the modulation ratio, determined by the inverter closed-loop control loop, f g is the grid frequency, and t is the time variable;

[0090] Step S2: Superimpose the superimposed component u z0 onto the three-phase sine modulation signal and perform full peak clamping to obtain the fully peak-clamped modulation signal u mX , and the calculation expression is:

[0091] u mX = u ref_X + u z0 , X = A, B, C

[0092] where u ref_X represents the sine modulation signal of phase X (X = A, B, C), and u mX represents the fully peak-clamped modulation signal of phase X;

[0093] Step S3, perform algorithm correction on the fully peak-clamped modulation signal u mX to obtain the discontinuous pulse width modulation signal of the heterogeneous switch three-phase five-level inverter, and the calculation expression is:

[0094]

[0095] where u refA_cr1, u refB_cr1 and u refC_cr1 respectively represent the first discontinuous pulse width modulation signal of phase A, the first discontinuous pulse width modulation signal of phase B, and the first discontinuous pulse width modulation signal of phase C, u refA_cr2 , u refB_cr2 and u refC_cr2 respectively represent the second discontinuous pulse width modulation signal of phase A, the second discontinuous pulse width modulation signal of phase B, and the second discontinuous pulse width modulation signal of phase C, u refA_cr3 , u refB_cr3 and u refC_cr3 respectively represent the third discontinuous pulse width modulation signal of phase A, the third discontinuous pulse width modulation signal of phase B, and the third discontinuous pulse width modulation signal of phase C, u refA_cr4 , u refB_cr4 and u refC_cr4 respectively represent the fourth discontinuous pulse width modulation signal of phase A, the fourth discontinuous pulse width modulation signal of phase B, and the fourth discontinuous pulse width modulation signal of phase C;

[0096] The present invention also relates to a commutation control method for a heterogeneous-switch three-phase five-level inverter, which is used for the commutation controller 2040 in the control circuit 20 of the above three-phase five-level inverter. The commutation controller 2040 collects the first to fourth discontinuous pulse width modulation signals u refX_cr1～ u refX_cr4 and the first to fourth carrier signals u st1～ u st4 , and configures the first dead time signal t dead1 ~the third dead time signal t dead3 , which is used to implement the dead time mode when the bridge arm switch mode is switched. In the dead time mode, the bridge arm switch state corresponds to the O state.

[0097] The case where 4 or 2 silicon carbide metal oxide semiconductor field effect transistors are used in each phase bridge arm is described. The specific implementation process is as follows:

[0098] When 4 silicon carbide metal oxide semiconductor field effect transistors are used in each phase bridge arm, the commutation control method is as follows.

[0099] When the first discontinuous pulse width modulation signal u of phase A refA_cr1 is greater than the first carrier signal u st1 , or when the sum of the first discontinuous pulse width modulation signal u of phase A refA_cr1 and the third dead time signal t dead3 is less than the first carrier signal u st1 and the second discontinuous pulse width modulation signal u of phase A refA_cr2 is greater than the second carrier signal u st2 , the drive signal of the seventh power switch tube S7 is high, otherwise it is low; when the first discontinuous pulse width modulation signal u of phase A refA_cr1The sum of the dead time signal -t dead1 is greater than the carrier signal -u st1 The drive signal of the first power switch tube S1 is high; otherwise, it is low. When the A-phase discontinuous pulse width modulation signal -u refA_cr1 The sum of the dead time signal -t dead2 is less than the carrier signal -u st1 The drive signal of the second power switch tube S2 is high; otherwise, it is low. When the A-phase discontinuous pulse width modulation signal -u refA_cr2 is less than the carrier signal -u st2 The drive signal of the sixth power switch tube S6 is high; otherwise, it is low. When the A-phase discontinuous pulse width modulation signal -u refA_cr4 is less than the carrier signal -u st4 or when the difference between the A-phase discontinuous pulse width modulation signal -u refA_cr4 and the dead time signal -t dead3 is greater than the carrier signal -u st4 and the A-phase discontinuous pulse width modulation signal -u refA_cr3 is less than the carrier signal -u st3 The drive signal of the eighth power switch tube S8 is high; otherwise, it is low. When the difference between the A-phase discontinuous pulse width modulation signal -u refA_cr4 and the dead time signal -t dead1 is less than the carrier signal -u st4 The drive signal of the fourth power switch tube S4 is high; otherwise, it is low. When the difference between the A-phase discontinuous pulse width modulation signal -u refA_cr4 and the dead time signal -t dead2 is greater than the carrier signal -u st4 The drive signal of the third power switch tube S3 is high; otherwise, it is low. When the A-phase discontinuous pulse width modulation signal -u refX_cr3 is less than the carrier signal -u st3 The drive signal of the fifth power switch tube S5 is high; otherwise, it is low.

[0100] When the B-phase discontinuous pulse width modulation signal -u refB_cr1 is greater than the carrier signal -u st1 or when the sum of the B-phase discontinuous pulse width modulation signal -u refX_cr1 and the dead time signal -t dead3 is less than the carrier signal -u st1 and the B-phase discontinuous pulse width modulation signal -u refB_cr2 is greater than the carrier signal -u st2 The drive signal of the fifteenth power switch tube S 15 is high; otherwise, it is low. When the sum of the B-phase discontinuous pulse width modulation signal -u refB_cr1 and the dead time signal -t dead1 is greater than the carrier signal -ust1 When the driving signal of the ninth power switch tube S9 is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B -u refB_cr1 and the dead - time signal two t dead2 sum is less than the carrier signal one u st1 the driving signal of the tenth power switch tube S 10 is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B two u refB_cr2 is less than the carrier signal two u st2 the driving signal of the fourteenth power switch tube S 14 is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B four u refB_cr4 is less than the carrier signal four u st4 or when the discontinuous pulse width modulation signal of phase B four u refB_cr4 and the dead - time signal three t dead3 difference is greater than the carrier signal four u st4 and the discontinuous pulse width modulation signal of phase B three u refB_cr3 is less than the carrier signal three u st3 the driving signal of the sixteenth power switch tube S 16 is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B four u refB_cr4 and the dead - time signal t dead1 one difference is less than the carrier signal four u st4 the driving signal of the twelfth power switch tube S 12 is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B four u refB_cr4 and the dead - time signal two t dead2 difference is greater than the carrier signal four u st4 the driving signal of the eleventh power switch tube S 11 is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B three u refB_cr3 is less than the carrier signal three u st3 the driving signal of the thirteenth power switch tube S 13 is high, otherwise it is low.

[0101] When the discontinuous pulse width modulation signal of phase C one u refC_cr1 is greater than the carrier signal one u st1 or when the discontinuous pulse width modulation signal of phase C one u refC_cr1 and the dead - time signal three t dead3 sum is less than the carrier signal one u st1 and the discontinuous pulse width modulation signal of phase C two u refC_cr2 is greater than the carrier signal two u st2 the driving signal of the twenty - third power switch tube S 23 is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase C one urefC_cr1 When the sum of the dead time signal -t dead1 is greater than the carrier signal -u st1 the drive signal of the seventeenth power switch tube S 17 is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal -u refC_cr1 and the dead time signal -t dead2 the sum is less than the carrier signal -u st1 the drive signal of the eighteenth power switch tube S 18 is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal -u refC_cr2 is less than the carrier signal -u st2 the drive signal of the twenty-second power switch tube S 22 is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal -u refC_cr4 is less than the carrier signal -u st4 or when the C-phase discontinuous pulse width modulation signal -u refC_cr4 and the dead time signal -t dead3 the difference is greater than the carrier signal -u st4 and the three-phase discontinuous pulse width modulation signal -u refC_cr3 is less than the carrier signal -u st3 the drive signal of the twenty-fourth power switch tube S 24 is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal -u refC_cr4 and the dead time signal -t dead1 the difference is less than the carrier signal -u st4 the drive signal of the twentieth power switch tube S 20 is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal -u refC_cr4 and the dead time signal -t dead2 the difference is greater than the carrier signal -u st4 the drive signal of the nineteenth power switch tube S 19 is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal -u refC_cr3 is less than the carrier signal -u st3 the drive signal of the twenty-first power switch tube S 21 is high, otherwise it is low.

[0102] When 2 silicon carbide metal oxide semiconductor field effect transistors are used in each phase leg, the commutation control method is as follows.

[0103] When the A-phase discontinuous pulse width modulation signal -u refA_cr1 is greater than the carrier signal -u st1 or when the A-phase discontinuous pulse width modulation signal -u refA_cr1 and the dead time signal -tdead3 The sum is less than the carrier signal one u st1 And the discontinuous PWM signal two u of phase A refA_cr2 Is greater than the carrier signal two u st2 When it is, the driving signal of the seventh power switch tube S7 is high, otherwise it is low; when the discontinuous PWM signal one u of phase A refA_cr1 And the dead time signal one t dead1 The sum is greater than the carrier signal one u st1 When it is, the driving signal of the first power switch tube S1 is high, otherwise it is low; when the discontinuous PWM signal one u of phase A refA_cr1 And the dead time signal two t dead2 The sum is less than the carrier signal one u st1 When it is, the driving signal of the second power switch tube S2 is high, otherwise it is low; when the discontinuous PWM signal two u of phase A refA_cr2 Is greater than zero, the driving signal of the sixth power switch tube S6 is low, otherwise it is high; when the discontinuous PWM signal four u of phase A refA_cr4 Is less than the carrier signal four u st4 When it is, or when the discontinuous PWM signal four u of phase A refA_cr4 And the dead time signal three t dead3 The difference is greater than the carrier signal four u st4 And the discontinuous PWM signal three u of phase A refA_cr3 Is less than the carrier signal three u st3 When it is, the driving signal of the eighth power switch tube S8 is high, otherwise it is low; when the discontinuous PWM signal four u of phase A refA_cr4 And the dead time signal t dead1 The difference one is less than the carrier signal four u st4 When it is, the driving signal of the fourth power switch tube S4 is high, otherwise it is low; when the discontinuous PWM signal four u of phase A refA_cr4 And the dead time signal two t dead2 The difference is greater than the carrier signal four u st4 When it is, the driving signal of the third power switch tube S3 is high, otherwise it is low; when the discontinuous PWM signal three u of phase A refX_cr3 Is less than zero, the driving signal of the fifth power switch tube is low, otherwise it is high.

[0104] When the discontinuous PWM signal one u of phase B refB_cr1 Is greater than the carrier signal one u st1 When it is, or when the discontinuous PWM signal one u of phase B refX_cr1 And the dead time signal three t dead3 The sum is less than the carrier signal one u st1 And the discontinuous PWM signal two u of phase B refB_cr2 Is greater than the carrier signal two u st2When it is time, the driving signal of the fifteenth power switch tube S 15 is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B - u refB_cr1 and the dead - time signal - t dead1 sum is greater than the carrier signal - u st1 the driving signal of the ninth power switch tube S9 is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B - u refB_cr1 and the dead - time signal two t dead2 sum is less than the carrier signal - u st1 the driving signal of the tenth power switch tube S 10 is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B two u refA_cr2 is greater than zero, the driving signal of the fourteenth power switch tube S 14 is low, otherwise it is high; when the discontinuous pulse width modulation signal of phase B four u refB_cr4 is less than the carrier signal four u st4 or when the discontinuous pulse width modulation signal of phase B four u refB_cr4 and the dead - time signal three t dead3 difference is greater than the carrier signal four u st4 and the discontinuous pulse width modulation signal of phase B three u refB_cr3 is less than the carrier signal three u st3 the driving signal of the sixteenth power switch tube S 16 is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B four u refB_cr4 and the dead - time signal one t dead1 difference is less than the carrier signal four u st4 the driving signal of the twelfth power switch tube S 12 is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B four u refB_cr4 and the dead - time signal two t dead2 difference is greater than the carrier signal four u st4 the driving signal of the eleventh power switch tube S 11 is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B two u refA_cr2 is less than zero, the driving signal of the thirteenth power switch tube S 13 is low, otherwise it is high.

[0105] When the discontinuous pulse width modulation signal of phase C one u refC_cr1 is greater than the carrier signal one u st1 or when the discontinuous pulse width modulation signal of phase C one u refC_cr1 and the dead - time signal three t dead3 sum is less than the carrier signal one u st1 and the discontinuous pulse width modulation signal of phase C two u refC_cr2 is greater than the carrier signal two ust2 When the time is the twenty-third power S 23 The drive signal of the switching tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal is -u refC_cr1 And the dead time signal is -t dead1 The sum is greater than the carrier signal -u st1 When the time is the seventeenth power switch tube S 17 The drive signal is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal is -u refC_cr1 And the dead time signal two is t dead2 The sum is less than the carrier signal -u st1 When the time is the eighteenth power switch tube S 18 The drive signal is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal two is u refA_cr2 When it is greater than zero, the drive signal of the twenty-second power switch tube S 22 Is low, otherwise it is high; when the C-phase discontinuous pulse width modulation signal four is u refC_cr4 Is less than the carrier signal four u st4 When, or when the three-phase discontinuous pulse width modulation signal four is u refC_cr4 And the difference from the dead time signal three is t dead3 Is greater than the carrier signal four u st4 And the three-phase discontinuous pulse width modulation signal three is u refC_cr3 Is less than the carrier signal three u st3 When the time is the twenty-fourth power switch tube S 24 The drive signal is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal four is u refC_cr4 And the difference from the dead time signal one is t dead1 Is less than the carrier signal four u st4 When the time is the twentieth power switch tube S 20 The drive signal is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal four is u refC_cr4 And the difference from the dead time signal two is t dead2 Is greater than the carrier signal four u st4 When the time is the nineteenth power switch tube S 19 The drive signal is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal two is u refA_cr2 When it is less than zero, the drive signal of the twenty-first power switch tube S 21 Is low, otherwise it is high.

[0106] Next, taking a specific example, to verify the pulse width modulation method and commutation control method of the heterogeneous switch three-phase five-level inverter of the present invention, the AC power supply u of the three-phase five-level inverter sC The voltage standard is 220V / 50Hz, the DC side input voltage is 800V, the power is 6kW, the switching frequency is 60kHz, and the three-phase five-level inverter operates at a unity power factor.

[0107] Figure 2 It is the steady-state operation simulation waveform diagram of an example adopting the pulse width modulation method of the heterogeneous switch three-phase five-level inverter of the present invention. Figure 2 Among them, u dc1 is the voltage of the first DC bus filter capacitor C dc1 ; u dc2 is the voltage of the second DC bus filter capacitor C dc2 ; u dc3 is the voltage of the third DC bus filter capacitor C dc3 ; u dc4 is the voltage of the fourth DC bus filter capacitor C dc4 ; u AO is the voltage of the A-phase bridge arm, and i a is the output current of the A-phase inverter.

[0108] It can be seen that in Figure 2 , the voltage u dc1 of the first DC bus filter capacitor, the voltage u dc2 of the second DC bus filter capacitor, the voltage u dc3 of the third DC bus filter capacitor, and the voltage u dc4 of the fourth DC bus filter capacitor maintain dynamic balance near one-fourth of the voltage of the DC power supply U dc , that is, U dc / 4, realizing the natural balance of the DC bus capacitor voltage.

[0109] Figure 3 It is the circuit mode diagram of the commutation process when the switching state of the A-phase bridge arm of an example adopting the 4-silicon carbide bridge arm commutation control method of the heterogeneous switch three-phase five-level inverter of the present invention switches between P1 and P2.

[0110] Figure 4 It is the circuit mode diagram of the commutation process when the switching state of the A-phase bridge arm of an example adopting the 4-silicon carbide bridge arm commutation control method of the heterogeneous switch three-phase five-level inverter of the present invention switches between P1 and O.

[0111] Figure 5 It is the circuit mode diagram of the commutation process when the switching state of the A-phase bridge arm of an example adopting the 2-silicon carbide bridge arm commutation control method of the heterogeneous switch three-phase five-level inverter of the present invention switches between P1 and P2.

[0112] Figure 6 It is the circuit mode diagram of the commutation process when the switching state of the A-phase bridge arm of an example adopting the 2-silicon carbide bridge arm commutation control method of the heterogeneous switch three-phase five-level inverter of the present invention switches between P1 and O.

[0113] In Figure 3 andFigure 4 In [reference], the 4-SiC arm commutation control method of the heterogeneous-switching three-phase five-level inverter of the present invention is adopted. During the commutation process, the silicon insulated-gate bipolar transistor in the 4-SiC arm realizes zero-current turn-on and turn-off, only bears the conduction loss and a small amount of diode loss, and the silicon carbide metal-oxide field-effect transistor bears most of the switching losses, optimizing the loss distribution of the inverter topology and improving the conversion efficiency of the inverter.

[0114] In Figure 5 and Figure 6 In [reference], the 2-SiC arm commutation control method of the heterogeneous-switching three-phase five-level inverter of the present invention is adopted. During the commutation process, the silicon insulated-gate bipolar transistor in the 2-SiC arm realizes zero-current turn-on and turn-off, only bears the conduction loss and a small amount of diode loss, and the silicon carbide metal-oxide field-effect transistor bears most of the switching losses, optimizing the loss distribution of the inverter topology and improving the conversion efficiency of the inverter.

[0115] The embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the present invention.

Claims

1. Pulse width modulation method for a heterogeneous switched three-phase five-level inverter, characterized in that, The pulse width modulation method is a discontinuous pulse width modulation method, including Step S1: Obtain the maximum values of the three-phase sinusoidal modulation signals according to the three-phase sinusoidal modulation signals u max and the minimum values of the three-phase sinusoidal modulation signals u min , and then obtain the superimposed component u z0 ; The three-phase sinusoidal modulation signals include a sinusoidal modulation signal of phase A u ref_A , a sinusoidal modulation signal of phase B u ref_B , and a sinusoidal modulation signal of phase C u ref_C , and their expressions are as follows: The maximum value of the three-phase sine modulation signal u max The calculation expression is as follows: Minimum value of three-phase sinusoidal modulation signal u min The calculation expression is as follows: Superimposed component u z0 The calculation expression is as follows: Among them, M is the modulation ratio, which is determined by the inverter closed-loop control loop, f g is the grid frequency, t is the time variable; Step S2: Superimpose the superimposed component u z0 onto the three-phase sine modulation signal, perform full peak clamping, and obtain a fully peak-clamped modulation signal u mX , and the calculation expression is: Among them, u ref_X represents the X-phase sine modulation signal, u mX represents the full peak clamp modulation signal of the X-phase; Step S3, perform algorithm correction on the fully clamped modulation signal of the X phase u mX to obtain the discontinuous pulse width modulation signal of the heterogeneous switched three-phase five-level inverter. The calculation expression is as follows: Among them, u refA_cr1 , u refB_cr1 and u refC_cr1 respectively represent the first discontinuous pulse width modulation signal of phase A, the first discontinuous pulse width modulation signal of phase B, and the first discontinuous pulse width modulation signal of phase C. u refA_cr2 , u refB_cr2 and u refC_cr2 respectively represent the second discontinuous pulse width modulation signal of phase A, the second discontinuous pulse width modulation signal of phase B, and the second discontinuous pulse width modulation signal of phase C. u refA_cr3 , u refB_cr3 and u refC_cr3 respectively represent the third discontinuous pulse width modulation signal of phase A, the third discontinuous pulse width modulation signal of phase B, and the third discontinuous pulse width modulation signal of phase C. u refA_cr4 , u refB_cr4 and u refC_cr4 respectively represent the fourth discontinuous pulse width modulation signal of phase A, the fourth discontinuous pulse width modulation signal of phase B, and the fourth discontinuous pulse width modulation signal of phase C.

2. The pulse width modulation method of the heterogeneous switch three-phase five-level inverter according to claim 1, characterized in that The heterogeneous switch three-phase five-level inverter includes a DC power supply, a first DC bus filter capacitor, a second DC bus filter capacitor, a third DC bus filter capacitor, a fourth DC bus filter capacitor, an A-phase bridge arm, a B-phase bridge arm, a C-phase bridge arm, an A-phase filter inductor, a B-phase filter inductor, a C-phase filter inductor, an A-phase filter capacitor, a B-phase filter capacitor, and a C-phase filter capacitor; The positive pole of the DC power supply is connected to point 4 on the DC side, and the negative pole is connected to point 0 on the DC side; the positive pole of the first DC bus filter capacitor is connected to point 4 on the DC side, and the negative pole is connected to point 3 on the DC side; the positive pole of the second DC bus filter capacitor is connected to point 3 on the DC side, and the negative pole is connected to the DC side O point; the positive pole of the third DC bus filter capacitor is connected to the DC side O point, and the negative pole is connected to point 1 on the DC side; the positive pole of the fourth DC bus filter capacitor is connected to point 1 on the DC side, and the negative pole is connected to point 0 on the DC side; One end of the A-phase filter inductor is connected to the output point A of the A-phase bridge arm, and the other end is connected to the first end of the A-phase filter capacitor and the first end of the A-phase AC power supply; One end of the B-phase filter inductor is connected to the output point B of the B-phase bridge arm, and the other end is connected to the first end of the B-phase filter capacitor and the first end of the B-phase AC power supply; One end of the C-phase filter inductor is connected to the output point C of the C-phase bridge arm, and the other end is connected to the first end of the C-phase filter capacitor and the first end of the C-phase AC power supply; The second ends of the A-phase filter capacitor, the B-phase filter capacitor, and the C-phase filter capacitor are connected together to form a star-connected three-phase filter capacitor; The second ends of the A-phase AC power supply, the B-phase AC power supply, and the C-phase AC power supply are connected together to form a star-connected three-phase power grid.

3. According to the pulse width modulation method of the heterogeneous-switch three-phase five-level inverter described in claim 2, the voltage of the X-phase bridge arm of the heterogeneous-switch three-phase five-level inverter U XO , outputs five levels, corresponding to five switching states of the X-phase bridge arm, and the expression is: Among them, U dc represents the DC power supply voltage; the switch state P2 indicates that the output point X of the X-phase bridge arm is connected to point 4 on the DC side through a power switch tube, and the voltage between the output point X of the X-phase bridge arm and the DC side O point is half of the DC power supply voltage U dc The switch state P1 indicates that the output point X of the X-phase bridge arm is connected to point 3 on the DC side through a power switch tube, and the voltage between the output point X of the X-phase bridge arm and the DC side O point is one-fourth of the DC power supply voltage U dc The switch state O indicates that the output point X of the X-phase bridge arm is connected to the DC side through a power switch tube O point, and the voltage between the output point X of the X-phase bridge arm and the DC side O point is zero; the switch state N1 indicates that the output point X of the X-phase bridge arm is connected to point 1 on the DC side through a power switch tube, and the voltage between the output point X of the X-phase bridge arm and the DC side O point is the opposite of one-fourth of the DC power supply voltage U dc The switch state N2 indicates that the output point X of the X-phase bridge arm is connected to point 0 on the DC side through a power switch tube, and the voltage between the output point X of the X-phase bridge arm and the DC side O point is the opposite of half of the DC power supply voltage U dc of the DC power supply voltage 4. The pulse width modulation method of the heterogeneous switch three-phase five-level inverter according to claim 1, characterized in that During the process of performing complete peak clamping in step S2 When the absolute value of the maximum value of the three-phase sinusoidal modulation signal u max is greater than the absolute value of the minimum value of the three-phase sinusoidal modulation signal u min the minimum value of the three-phase sinusoidal modulation signal u min is located in the regions on both sides of the peak value in the negative half cycle of the three-phase sinusoidal modulation signal. At this time, the superimposed component u z0 is superimposed on the three-phase sinusoidal modulation signal. In the regions on both sides of the peak value in the negative half cycle of the three-phase sinusoidal modulation signal, the minimum phase of the three-phase modulation signal is clamped to -1 to obtain a fully peak-clamped modulation signal u mX and the X-phase bridge arm in the heterogeneous switch three-phase five-level inverter is clamped to the N2 switch state; When the absolute value of the maximum value of the three-phase sinusoidal modulation signal u max is less than the absolute value of the minimum value of the three-phase sinusoidal modulation signal u min the maximum value of the three-phase sinusoidal modulation signal u max is located in the regions on both sides of the peak value in the positive half-cycle of the three-phase sinusoidal modulation signal. At this time, the superimposed component u z0 is superimposed on the three-phase sinusoidal modulation signal. In the regions on both sides of the peak value in the positive half-cycle of the three-phase sinusoidal modulation signal, the maximum phase of the three-phase modulation signal is clamped to one, obtaining a fully peak-clamped modulation signal u mX and the X-phase bridge arm in the heterogeneous-switch three-phase five-level inverter is clamped to the P2 switching state.

5. The pulse width modulation method of the heterogeneous switch three-phase five-level inverter according to claim 1, characterized in that The discontinuous pulse width modulation signal of the heterogeneous switch three-phase five-level inverter after algorithm correction is modulated with its corresponding four-way carrier signal to obtain the switching states of the three-phase bridge arms, realizing the natural balance of the DC bus filter capacitor voltage of the heterogeneous switch three-phase five-level inverter; The four-way carrier signals are in-phase triangular carrier signals, and the four-way carrier signals include Carrier Signal 1 u st1 , Carrier Signal 2 u st2 , Carrier Signal 3 u st3 , and Carrier Signal 4 u st4 ; The peak-to-peak value range of Carrier Signal 1 u st1 is from one-half to one, the peak-to-peak value range of Carrier Signal 2 u st2 is from zero to one-half, the peak-to-peak value range of Carrier Signal 3 u st3 is from the opposite of one-half to zero, and the peak-to-peak value range of Carrier Signal 4 u st4 is from the opposite of one to the opposite of one-half.

6. A commutation control method for a heterogeneous switch three-phase five-level inverter. The heterogeneous switch three-phase five-level inverter includes a first power switch tube, a second power switch tube, a third power switch tube, a fourth power switch tube, a fifth power switch tube, a sixth power switch tube, a seventh power switch tube, an eighth power switch tube, a ninth power switch tube, a tenth power switch tube, an eleventh power switch tube, a twelfth power switch tube, a thirteenth power switch tube, a fourteenth power switch tube, a fifteenth power switch tube, a sixteenth power switch tube, a seventeenth power switch tube, an eighteenth power switch tube, a nineteenth power switch tube, a twentieth power switch tube, a twenty-first power switch tube, a twenty-second power switch tube, a twenty-third power switch tube, and a twenty-fourth power switch tube; The first power switch tube to the eighth power switch tube are connected to form an A-phase bridge arm; The ninth power switch tube to the sixteenth power switch tube are connected to form a B-phase bridge arm; The seventeenth power switch tube to the twenty-fourth power switch tube are connected to form a C-phase bridge arm; Characterized in that The X-phase bridge arm is a 4-SiC bridge arm, which is composed of 4 silicon carbide metal oxide semiconductor field effect transistors and 4 silicon insulated gate bipolar transistors; The fifth power switch tube, the sixth power switch tube, the seventh power switch tube, the eighth power switch tube, the thirteenth power switch tube, the fourteenth power switch tube, the fifteenth power switch tube, the sixteenth power switch tube, the twenty-first power switch tube, the twenty-second power switch tube, the twenty-third power switch tube, and the twenty-fourth power switch tube use silicon carbide metal oxide semiconductor field effect transistors; the first power switch tube, the second power switch tube, the third power switch tube, the fourth power switch tube, the ninth power switch tube, the tenth power switch tube, the eleventh power switch tube, the twelfth power switch tube, the seventeenth power switch tube, the eighteenth power switch tube, the nineteenth power switch tube, and the twentieth power switch tube use silicon insulated gate bipolar transistors; The commutation control method uses the discontinuous pulse width modulation signal of the heterogeneous switch three-phase five-level inverter obtained by the pulse width modulation method described in any one of the above claims 1-5; The commutation control method further includes configuring a dead time signal one t dead1 , a dead time signal two t dead2 , and a dead time signal three t dead3 , which are used to implement the dead time mode when the switching state of the X-phase bridge arm is switched. In the dead time mode, the X-phase bridge arm is in the switching state O; When the discontinuous PWM signal of phase A one u refA_cr1 is greater than the carrier signal one u st1 or when the sum of the discontinuous PWM signal of phase A one u refA_cr1 and the dead-time signal three t dead3 is less than the carrier signal one u st1 and the discontinuous PWM signal of phase A two u refA_cr2 is greater than the carrier signal two u st2 the driving signal of the seventh power switch is high, otherwise it is low; when the discontinuous PWM signal of phase A one u refA_cr1 and the dead-time signal one t dead1 the sum is greater than the carrier signal one u st1 the driving signal of the first power switch is high, otherwise it is low; when the discontinuous PWM signal of phase A one u refA_cr1 and the dead-time signal two t dead2 the sum is less than the carrier signal one u st1 the driving signal of the second power switch is high, otherwise it is low; when the discontinuous PWM signal of phase A two u refA_cr2 is less than the carrier signal two u st2 the driving signal of the sixth power switch is high, otherwise it is low; when the discontinuous PWM signal of phase A four u refA_cr4 is less than the carrier signal four u st4 or the difference between the discontinuous PWM signal of phase A four u refA_cr4 and the dead-time signal three t dead3 is greater than the carrier signal four u st4 and the discontinuous PWM signal of phase A three u refA_cr3 is less than the carrier signal three u st3 the driving signal of the eighth power switch is high, otherwise it is low; when the difference between the discontinuous PWM signal of phase A four u refA_cr4 and the dead-time signal one t dead1 is less than the carrier signal four u st4 When it is, the driving signal of the fourth power switch tube is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase A four u refA_cr4 and the dead time signal two t dead2 The difference from the carrier signal four u st4 When it is greater than the carrier signal four, the driving signal of the third power switch tube is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase A three u refX_cr3 is less than the carrier signal three u st3 When it is, the driving signal of the fifth power switch tube is high, otherwise it is low; When the B-phase discontinuous pulse width modulation signal one u refB_cr1 is greater than the carrier signal one u st1 or when the sum of the B-phase discontinuous pulse width modulation signal one u refX_cr1 and the dead time signal three t dead3 is less than the carrier signal one u st1 and the B-phase discontinuous pulse width modulation signal two u refB_cr2 is greater than the carrier signal two u st2 the drive signal of the fifteenth power switch is high, otherwise it is low; when the B-phase discontinuous pulse width modulation signal one u refB_cr1 and the dead time signal one t dead1 the sum is greater than the carrier signal one u st1 the drive signal of the ninth power switch is high, otherwise it is low; when the B-phase discontinuous pulse width modulation signal one u refB_cr1 and the dead time signal two t dead2 the sum is less than the carrier signal one u st1 the drive signal of the tenth power switch is high, otherwise it is low; when the B-phase discontinuous pulse width modulation signal two u refB_cr2 is less than the carrier signal two u st2 the drive signal of the fourteenth power switch is high, otherwise it is low; when the B-phase discontinuous pulse width modulation signal four u refB_cr4 is less than the carrier signal four u st4 or the difference between the B-phase discontinuous pulse width modulation signal four u refB_cr4 and the dead time signal three t dead3 is greater than the carrier signal four u st4 and the B-phase discontinuous pulse width modulation signal three u refB_cr3 is less than the carrier signal three u st3 the drive signal of the sixteenth power switch is high, otherwise it is low; when the B-phase discontinuous pulse width modulation signal four u refB_cr4 and the dead time signal one t dead1 The difference is less than the carrier signal four u st4 When it is, the drive signal of the twelfth power switch tube is high, otherwise it is low; when the B-phase discontinuous pulse width modulation signal four u refB_cr4 And the dead time signal two t dead2 The difference is greater than the carrier signal four u st4 When it is, the drive signal of the eleventh power switch tube is high, otherwise it is low; when the B-phase discontinuous pulse width modulation signal three u refB_cr3 Is less than the carrier signal three u st3 When it is, the drive signal of the thirteenth power switch tube is high, otherwise it is low; When the C-phase discontinuous pulse width modulation signal one u refC_cr1 is greater than the carrier signal one u st1 or when the sum of the C-phase discontinuous pulse width modulation signal one u refC_cr1 and the dead time signal three t dead3 is less than the carrier signal one u st1 and the C-phase discontinuous pulse width modulation signal two u refC_cr2 is greater than the carrier signal two u st2 the drive signal of the twenty-third power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal one u refC_cr1 and the dead time signal one t dead1 the sum is greater than the carrier signal one u st1 the drive signal of the seventeenth power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal one u refC_cr1 and the dead time signal two t dead2 the sum is less than the carrier signal one u st1 the drive signal of the eighteenth power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal two u refC_cr2 is less than the carrier signal two u st2 the drive signal of the twenty-second power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal four u refC_cr4 is less than the carrier signal four u st4 or when the difference between the three-phase discontinuous pulse width modulation signal four u refC_cr4 and the dead time signal three t dead3 is greater than the carrier signal four u st4 and the three-phase discontinuous pulse width modulation signal three u refC_cr3 is less than the carrier signal three u st3 the drive signal of the twenty-fourth power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal four u refC_cr4 and the dead time signal one t dead1 The difference is less than the carrier signal four u st4 When it is, the drive signal of the twentieth power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal four u refC_cr4 and the dead time signal two t dead2 The difference is greater than the carrier signal four u st4 When it is, the drive signal of the nineteenth power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal three u refC_cr3 is less than the carrier signal three u st3 When it is, the drive signal of the twenty-first power switch tube is high, otherwise it is low.

7. A commutation control method for a heterogeneous switch three-phase five-level inverter, the heterogeneous switch three-phase five-level inverter includes a first power switch tube, a second power switch tube, a third power switch tube, a fourth power switch tube, a fifth power switch tube, a sixth power switch tube, a seventh power switch tube, an eighth power switch tube, a ninth power switch tube, a tenth power switch tube, an eleventh power switch tube, a twelfth power switch tube, a thirteenth power switch tube, a fourteenth power switch tube, a fifteenth power switch tube, a sixteenth power switch tube, a seventeenth power switch tube, an eighteenth power switch tube, a nineteenth power switch tube, a twentieth power switch tube, a twenty-first power switch tube, a twenty-second power switch tube, a twenty-third power switch tube, and a twenty-fourth power switch tube; the first power switch tube to the eighth power switch tube are connected to form an A-phase bridge arm; the ninth power switch tube to the sixteenth power switch tube are connected to form a B-phase bridge arm; the seventeenth power switch tube to the twenty-fourth power switch tube are connected to form a C-phase bridge arm; It is characterized in that The X-phase bridge arm is a 2-silicon carbide bridge arm, which is composed of 2 silicon carbide metal oxide semiconductor field effect transistors and 6 silicon insulated gate bipolar transistors; The seventh power switch tube, the eighth power switch tube, the fifteenth power switch tube, the sixteenth power switch tube, the twenty-third power switch tube, and the twenty-fourth power switch tube use silicon carbide metal oxide semiconductor field effect transistors; the first power switch tube, the second power switch tube, the third power switch tube, the fourth power switch tube, the fifth power switch tube, the sixth power switch tube, the ninth power switch tube, the tenth power switch tube, the eleventh power switch tube, the twelfth power switch tube, the thirteenth power switch tube, the fourteenth power switch tube, the seventeenth power switch tube, the eighteenth power switch tube, the nineteenth power switch tube, the twentieth power switch tube, the twenty-first power switch tube, and the twenty-second power switch tube use silicon insulated gate bipolar transistors; The commutation control method uses the discontinuous pulse width modulation signal of the heterogeneous switch three-phase five-level inverter obtained by the pulse width modulation method described in any one of the above claims 1-5; The commutation control method further includes configuring a dead time signal one u refA_cr1 , a dead time signal two t dead2 , and a dead time signal three t dead3 , which are used to implement the dead time mode during the switching of the switching state of the X-phase bridge arm. In the dead time mode, the X-phase bridge arm is in the switching state O; When the discontinuous PWM signal of phase A one u refA_cr1 is greater than the carrier signal one u st1 or when the sum of the discontinuous PWM signal of phase A one u refA_cr1 and the dead time signal three t dead3 is less than the carrier signal one u st1 and the discontinuous PWM signal of phase A two u refA_cr2 is greater than the carrier signal two u st2 the drive signal of the seventh power switch tube is high, otherwise it is low; when the discontinuous PWM signal of phase A one u refA_cr1 and the dead time signal one t dead1 the sum is greater than the carrier signal one u st1 the drive signal of the first power switch tube is high, otherwise it is low; when the discontinuous PWM signal of phase A one u refA_cr1 and the dead time signal two t dead2 the sum is less than the carrier signal one u st1 the drive signal of the second power switch tube is high, otherwise it is low; when the discontinuous PWM signal of phase A two u refA_cr2 is greater than zero, the drive signal of the sixth power switch tube is low, otherwise it is high; when the discontinuous PWM signal of phase A four u refA_cr4 is less than the carrier signal four u st4 or the difference between the discontinuous PWM signal of phase A four u refA_cr4 and the dead time signal three t dead3 is greater than the carrier signal four u st4 and the discontinuous PWM signal of phase A three u refA_cr3 is less than the carrier signal three u st3 the drive signal of the eighth power switch tube is high, otherwise it is low; when the discontinuous PWM signal of phase A four u refA_cr4 and the dead time signal one t dead1 the difference is less than the carrier signal four u st4 When the time is such, the driving signal of the fourth power switch tube is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase A four u refA_cr4 and the dead time signal two t dead2 the difference is greater than the carrier signal four u st4 When the time is such, the driving signal of the third power switch tube is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase A three u refX_cr3 is less than zero, the driving signal of the fifth power switch tube is low, otherwise it is high; When the B-phase discontinuous pulse width modulation signal one u refB_cr1 is greater than the carrier signal one u st1 or when the sum of the B-phase discontinuous pulse width modulation signal one u refX_cr1 and the dead time signal three t dead3 is less than the carrier signal one u st1 and the B-phase discontinuous pulse width modulation signal two u refB_cr2 is greater than the carrier signal two u st2 the drive signal of the fifteenth power switch tube is high, otherwise it is low; when the B-phase discontinuous pulse width modulation signal one u refB_cr1 and the dead time signal one t dead1 the sum is greater than the carrier signal one u st1 the drive signal of the ninth power switch tube is high, otherwise it is low; when the B-phase discontinuous pulse width modulation signal one u refB_cr1 and the dead time signal two t dead2 the sum is less than the carrier signal one u st1 the drive signal of the tenth power switch tube is high, otherwise it is low; when the B-phase discontinuous pulse width modulation signal two u refA_cr2 is greater than zero, the drive signal of the fourteenth power switch tube is low, otherwise it is high; when the B-phase discontinuous pulse width modulation signal four u refB_cr4 is less than the carrier signal four u st4 or the difference between the B-phase discontinuous pulse width modulation signal four u refB_cr4 and the dead time signal three t dead3 is greater than the carrier signal four u st4 and the B-phase discontinuous pulse width modulation signal three u refB_cr3 is less than the carrier signal three u st3 the drive signal of the sixteenth power switch tube is high, otherwise it is low; when the B-phase discontinuous pulse width modulation signal four u refB_cr4 and the dead time signal one t dead1 the difference is less than the carrier signal four u st4 When the driving signal of the twelfth power switch tube is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B four u refB_cr4 and the dead time signal two t dead2 the difference is greater than the carrier signal four u st4 When the driving signal of the eleventh power switch tube is high, otherwise it is low; when the discontinuous pulse width modulation signal of phase B two u refA_cr2 is less than zero, the driving signal of the thirteenth power switch tube is low, otherwise it is high; When the C-phase discontinuous pulse width modulation signal 1 u refC_cr1 is greater than the carrier signal 1 u st1 or when the sum of the C-phase discontinuous pulse width modulation signal 1 u refC_cr1 and the dead time signal 3 t dead3 is less than the carrier signal 1 u st1 and the C-phase discontinuous pulse width modulation signal 2 u refC_cr2 is greater than the carrier signal 2 u st2 the drive signal of the twenty-third power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal 1 u refC_cr1 and the dead time signal 1 t dead1 the sum is greater than the carrier signal 1 u st1 the drive signal of the seventeenth power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal 1 u refC_cr1 and the dead time signal 2 t dead2 the sum is less than the carrier signal 1 u st1 the drive signal of the eighteenth power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal 2 u refA_cr2 is greater than zero, the drive signal of the twenty-second power switch tube is low, otherwise it is high; when the C-phase discontinuous pulse width modulation signal 4 u refC_cr4 is less than the carrier signal 4 u st4 or when the difference between the three-phase discontinuous pulse width modulation signal 4 u refC_cr4 and the dead time signal 3 t dead3 is greater than the carrier signal 4 u st4 and the three-phase discontinuous pulse width modulation signal 3 u refC_cr3 is less than the carrier signal 3 u st3 the drive signal of the twenty-fourth power switch tube is high, otherwise it is low; when the difference between the C-phase discontinuous pulse width modulation signal 4 u refC_cr4 and the dead time signal 1 t dead1 is less than the carrier signal 4 u st4 When it is, the driving signal of the twentieth power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal four u refC_cr4 and the dead time signal two t dead2 the difference is greater than the carrier signal four u st4 When it is, the driving signal of the nineteenth power switch tube is high, otherwise it is low; when the C-phase discontinuous pulse width modulation signal two u refA_cr2 is less than zero, the driving signal of the twenty-first power switch tube is low, otherwise it is high.

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