A high linearity digital delay circuit
Through the introduction of the correction capacitor array and delayed correction switch sets in the digital circuit, a high -line digital delay circuit was designed to solve the problem of inaccurate control in traditional technologies. Raise the control degree.
Patent Information
- Application Number
- CN202411546581.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2025-01-24
- Estimated Expiration
- 2044-11-01
AI Technical Summary
The linearity of existing digital circuit delay control technology is poor, resulting in large fluctuations in delay increments, making it difficult to achieve high-precision and high-stability delay control.
A high -line digital delay circuit is designed. By introducing the correction capacitor array and a delayed switch set, combined with the connection method of the PMOS tube and the NMOS tube to achieve delayed high -line control.
By introducing the correction capacitor array, the linearity of the digital circuit delay is significantly increased, the control of the delay is increased, and the problem of inaccurate delay control in traditional technologies is solved.
Smart Images
Figure CN119093925B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of integrated circuits, and in particular to a high-linearity digital delay circuit. Background Art
[0002] Inverter delay line is a delay technology commonly used in digital circuits. It introduces a controllable time delay by cascading a series of inverters. Inverter delay lines include fixed inverter delay lines, programmable delay lines, ring oscillator delay lines, and differential inverter delay lines. The above technologies are simple in structure and easy to implement, but they have shortcomings such as temperature and voltage sensitivity, sensitivity to noise and electromagnetic interference, power consumption issues, delay time accuracy limitations, and integrated circuit design complexity. In applications that require high precision, high stability, and low power consumption, it is usually necessary to combine other technical means (such as temperature compensation circuits and low noise designs) to compensate for these shortcomings in order to achieve better performance.
[0003] like Figure 1 As shown in FIG. 1 , it is a circuit schematic diagram of a traditional digital delay control circuit. The digital delay control circuit realizes delay control by controlling the output end of the first inverter, that is, the impedance value of the drain of PM1 and the source of NM1. When the capacitance of the output node is large, the charging and discharging speed of the output node will be slowed down, and vice versa. The relationship between the input capacitance and the output delay is as follows: Figure 2 As shown in the figure, it can be seen that the input capacitance value and the output delay are positively correlated. However, the linearity of the above delay control method is not excellent. Figure 2 Readout: The delay increment controlled by adjacent control code values has a large fluctuation, ranging from 2.78ps to 3.3ps. Summary of the invention
[0004] The purpose of the present invention is to achieve high linearity control of the delay of a digital circuit and increase the controllability of the delay. To this end, a high linearity digital delay circuit is provided.
[0005] In order to achieve the above-mentioned object of the invention, the embodiment of the present invention provides the following technical solutions:
[0006] A high linearity digital delay circuit comprises a PMOS tube PM1, a delay trimming switch group, an inverter circuit and a trimming capacitor array, wherein the source of the PMOS tube PM1 is connected to a power supply VDD, and the drain is respectively connected to the inverter circuit and the trimming capacitor array, one end of the delay trimming switch group is connected to the trimming capacitor array, and the other end is connected to the inverter circuit and grounded, an input end of the inverter circuit is provided with an IN node, and an output end is provided with an OUT node, and the trimming capacitor array is connected to the inverter circuit.
[0007] Furthermore, the trimming capacitor array includes capacitors C1, C2 and C3 arranged in parallel, the upper plates of the capacitors C1, C2 and C3 are all connected to the drain of the PMOS tube PM1, and the upper plates of the capacitors C1, C2 and C3 are also connected to the inverter circuit.
[0008] Further, the delay adjustment switch group includes an NMOS tube NM1, an NMOS tube NM2 and an NMOS tube NM3, the drain of the NMOS tube NM1 is electrically connected to the lower plate of the capacitor C1, the drain of the NMOS tube NM2 is electrically connected to the lower plate of the capacitor C2, the drain of the NMOS tube NM3 is electrically connected to the lower plate of the capacitor C3, the sources of the NMOS tubes NM1, NMOS tubes NM2 and NMOS tubes NM3 are all connected to the inverter circuit and grounded, and the gates of the NMOS tubes NM1, NMOS tubes NM2 and NMOS tubes NM3 are connected to an external adjustment code value.
[0009] Furthermore, the inverter circuit includes a PMOS tube PM2 and an NMOS tube NM4, the source of the PMOS tube PM2 is electrically connected to the drain of the PMOS tube PM1, the upper plate of the capacitor C1, the upper plate of the capacitor C2 and the upper plate of the capacitor C3, respectively, and the source of the NMOS tube NM4 is electrically connected to the source of the NMOS tube NM1, the NMOS tube NM2 and the NMOS tube NM3 and is grounded.
[0010] Furthermore, the drain of the NMOS transistor NM4 is connected to the drain end of the PMOS transistor PM2 and is also connected to the OUT node.
[0011] Furthermore, the gate of the PMOS transistor PM2 is connected to the gate of the NMOS transistor NM4 and is connected to the IN node.
[0012] Furthermore, the gate of the PMOS tube PM1 is connected to a low level and maintains a normally open state.
[0013] Compared with the prior art, the present invention has the following beneficial effects:
[0014] The present invention connects the source of the PMOS tube PM1 to the power supply VDD, and the drain to the inverter circuit and the trimming capacitor array respectively, one end of the delay trimming switch group is connected to the trimming capacitor array, and the other end is connected to the inverter circuit and grounded, the input end of the inverter circuit is provided with an IN node, the output end is provided with an OUT node, and the trimming capacitor array is connected to the inverter circuit. Due to the introduction of the trimming capacitor array, the delay of the digital circuit can be controlled with high linearity, and the controllability of the delay is increased. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0016] Figure 1 It is a circuit schematic diagram of a conventional digital delay control circuit in the background technology of the present invention;
[0017] Figure 2 Is applied to Figure 1 The relationship between the access capacitance and output delay of the traditional digital delay control circuit;
[0018] Figure 3 is a circuit schematic diagram of a high linearity digital delay circuit provided by an embodiment of the present invention;
[0019] Figure 4 The embodiment of the present invention provides an application Figure 3 The relationship between the delay of the falling edge of the OUT node voltage and the capacitance value;
[0020] Figure 5 The embodiment of the present invention provides an application Figure 3 A graph showing the relationship between the input capacitance and output delay of a medium to high linearity digital delay circuit. DETAILED DESCRIPTION
[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.
[0022] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance, or implying any such actual relationship or order between these entities or operations. In addition, the terms "connected", "connected", etc. can be directly connected between elements, or indirectly connected via other elements.
[0023] like Figure 3 As shown, a high linearity digital delay circuit provided by an embodiment of the present invention may include a PMOS tube PM1, a delay trimming switch group, an inverter circuit and a trimming capacitor array. The source of the PMOS tube PM1 is connected to the power supply VDD, and the drain is connected to the inverter circuit and the trimming capacitor array respectively. One end of the delay trimming switch group is connected to the trimming capacitor array, and the other end is connected to the inverter circuit and grounded. The input end of the inverter circuit is provided with an IN node, and the output end is provided with an OUT node, and the trimming capacitor array is connected to the inverter circuit. Due to the introduction of the trimming capacitor array, the delay of the digital circuit can be controlled with high linearity, and the controllability of the delay is increased.
[0024] In this embodiment, the trimming capacitor array includes capacitors C1, C2 and C3 connected in parallel. The upper plates of the capacitors C1, C2 and C3 are all connected to the drain of the PMOS transistor PM1. The upper plates of the capacitors C1, C2 and C3 are also connected to the inverter circuit.
[0025] Furthermore, the delay adjustment switch group includes NMOS tube NM1, NMOS tube NM2 and NMOS tube NM3. Among them, the drain of the NMOS tube NM1 is electrically connected to the lower plate of the capacitor C1, the drain of the NMOS tube NM2 is electrically connected to the lower plate of the capacitor C2, and the drain of the NMOS tube NM3 is electrically connected to the lower plate of the capacitor C3. The sources of the NMOS tubes NM1, NMOS tubes NM2 and NMOS tubes NM3 are all connected to the inverter circuit and grounded. In addition, the gates of the NMOS tubes NM1, NMOS tubes NM2 and NMOS tubes NM3 are connected to the external adjustment code value.
[0026] It should be noted that in Figure 3 In the example, the trimming code value corresponding to the NMOS transistor NM1 is Delay_trim[2], the trimming code value corresponding to the NMOS transistor NM2 is Delay_trim[1], and the trimming code value corresponding to the NMOS transistor NM3 is Delay_trim[0].
[0027] The inverter circuit may include a PMOS transistor PM2 and an NMOS transistor NM4. Specifically, the source of the PMOS transistor PM2 is electrically connected to the drain of the PMOS transistor PM1, the upper plate of the capacitor C1, the upper plate of the capacitor C2, and the upper plate of the capacitor C3. The source of the NMOS transistor NM4 is electrically connected to the sources of the NMOS transistors NM1, NMOS transistors NM2, and NMOS transistors NM3 and is grounded.
[0028] In implementation, the drain of the NMOS transistor NM4 is connected to the drain of the PMOS transistor PM2 and connected to the OUT node. In addition, the gate of the PMOS transistor PM2 is connected to the gate of the NMOS transistor NM4 and connected to the IN node.
[0029] It should be noted that the gate of the PMOS tube PM1 is connected to a low level and remains in a normally open state.
[0030] Based on the above circuit connection relationship, during operation, since the PMOS tube PM1 is normally open, the voltages of the upper plates of capacitors C1, C2 and C3 are all maintained at the power supply VDD. When the falling edge of the clock arrives, the PMOS tube PM2 is turned on and the NMOS tube NM4 is turned off. First, the voltage difference between the upper plates of capacitors C1, C2 and C3 in the trimming capacitor array and the OUT node enables the capacitor array to quickly charge the OUT node, thereby ensuring the linearity of the voltage rise of the OUT node. Then, when the voltage of the OUT node is balanced with the voltage of the upper plates of capacitors C1, C2 and C3, the power supply VDD charges the capacitor array and the OUT node, so that the voltage of the OUT node is raised to the power supply VDD.
[0031] Figure 4 What is shown is that based on the selection of the trim code value (Delay_trim[2:0]), the delay is controlled due to the different speeds at which the inverter output drops. Figure 4 It can be found that after the OUT node finally passes through an inverter output, the delay of the falling edge of the OUT node can increase linearly with the linear increase of the capacitance value.
[0032] By comparison Figure 5 and Figure 3 Compared with the traditional method, the high linearity digital delay circuit provided in this embodiment has a higher linearity control over the delay.
[0033] In summary, the embodiment of the present invention connects the source of the PMOS tube PM1 to the power supply VDD, and the drain to the inverter circuit and the trimming capacitor array respectively, one end of the delay trimming switch group is connected to the trimming capacitor array, and the other end is connected to the inverter circuit and grounded, the input end of the inverter circuit is provided with an IN node, the output end is provided with an OUT node, and the trimming capacitor array is connected to the inverter circuit. Due to the introduction of the trimming capacitor array, the delay of the digital circuit can be controlled with high linearity, and the controllability of the delay is increased.
[0034] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. A high linearity digital delay circuit, characterized in that: The invention comprises a PMOS tube PM1, a delay trimming switch group, an inverter circuit and a trimming capacitor array, wherein the source of the PMOS tube PM1 is connected to a power supply VDD, and the drain is respectively connected to the inverter circuit and the trimming capacitor array, one end of the delay trimming switch group is connected to the trimming capacitor array, and the other end is connected to the inverter circuit and grounded, the input end of the inverter circuit is provided with an IN node, and the output end is provided with an OUT node, and the trimming capacitor array is connected to the inverter circuit; the trimming capacitor array comprises a capacitor C1, a capacitor C2 and a capacitor C3 arranged in parallel, the upper plates of the capacitors C1, C2 and C3 are all connected to the drain of the PMOS tube PM1, and the upper plates of the capacitors C1, C2 and C3 are also connected to the inverter circuit; the delay trimming switch group comprises an NMOS tube NM1, an NMOS tube NM2 and an NMOS tube NM3, the drain of the NMOS tube NM1 is connected to the capacitor C 1, the drain of the NMOS tube NM2 is electrically connected to the lower plate of the capacitor C2, the drain of the NMOS tube NM3 is electrically connected to the lower plate of the capacitor C3, the sources of the NMOS tubes NM1, NMOS tubes NM2 and NMOS tubes NM3 are all connected to the inverter circuit and grounded, and the gates of the NMOS tubes NM1, NMOS tubes NM2 and NMOS tubes NM3 are connected to the external trimming code value; the inverter circuit It comprises a PMOS tube PM2 and an NMOS tube NM4, wherein the source of the PMOS tube PM2 is electrically connected to the drain of the PMOS tube PM1, the upper plate of the capacitor C1, the upper plate of the capacitor C2 and the upper plate of the capacitor C3 respectively, the source of the NMOS tube NM4 is electrically connected to the source of the NMOS tube NM1, the NMOS tube NM2 and the NMOS tube NM3 respectively and is grounded; the gate of the PMOS tube PM1 is connected to a low level and keeps a normally open state.
2. A high linearity digital delay circuit according to claim 1, characterized in that: The drain of the NMOS transistor NM4 is connected to the drain end of the PMOS transistor PM2 and is also connected to the OUT node.
3. A high linearity digital delay circuit according to claim 1, characterized in that: The gate of the PMOS transistor PM2 is connected to the gate of the NMOS transistor NM4 and is also connected to the IN node.
Citation Information
Patent Citations
Trimming circuit used for oscillator
CN108494384A
Apparatuses and methods for dram wordline control with reverse temperature coefficient delay
CN110910927A