A pin multiplexing circuit structure for realizing enable input and communication input

Abstract

The invention discloses a pin multiplexing circuit structure for realizing enable input and communication input. When the enable is turned on, an EN enable signal is at a high level, and a pre-power supply generating circuit generates an output voltage to supply power to subsequent modules; a first comparator outputs a high level according to the high-level EN enable signal, drives a second comparator to output a high level, so that a D flip-flop outputs a high level, and an EN_DLY enable signal output by an RS flip-flop is at a high level, and the enable is normal; thereafter, EN inputs a communication clock signal, the EN enable signal changes from a high level to a low level, and the EN_DLY enable signal remains at a high level, so that the pre-power supply generating circuit supplies power to subsequent modules; the first comparator outputs a low level according to the low-level EN enable signal, and starts a timer of the D flip-flop, until the low level output by the first comparator continues until the D flip-flop outputs a low level, so that the EN_DLY enable signal output by the RS flip-flop changes to a low level, the pre-power supply generating circuit stops supplying power, and the enable stops.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuits and semiconductor integrated circuits, and in particular to a pin multiplexing circuit structure for realizing enable input and communication input. Background Art

[0002] With the rapid development of chip integration and processing technology, the functions and complexity of chips are increasing day by day. The larger the chip area means the higher the manufacturing and application costs. Therefore, reducing the chip area and packaging complexity is an important means to reduce chip costs.

[0003] Chip pins are divided into enable pins and communication pins. Enable pins are control pins widely found in various chips. The chip determines whether the chip function is turned on or off by judging the high and low levels of the enable pins. Communication input pins are digital signal pins that transmit high and low levels, which can realize data input to the chip to control the chip. Existing chips often separate these two to external pins. In the design of integrated circuits, when the chip area and packaging form are selected, the chip pins are also limited. Since each pin needs to occupy a certain area, the chip area will increase, resulting in an increase in chip cost. Summary of the invention

[0004] In view of the problems existing in the prior art, the present invention provides a pin multiplexing circuit structure for realizing enable input and communication input, integrating the enable and communication inputs into one pin, which can save chip space, improve chip integration, and reduce costs.

[0005] To achieve the above technical objectives, the present invention adopts the following technical solutions: a pin multiplexing circuit structure for realizing enable input and communication input, comprising: a pre-power supply generating circuit, a first comparator, an OR gate, a second comparator, a D flip-flop and an RS flip-flop;

[0006] When the enable is turned on, the EN enable signal is high and the EN_DLY enable signal is initially low. The pre-power generation circuit generates an output voltage VDD_PRE according to the input voltage VIN to power the first comparator, the second comparator and the RS trigger; the first comparator determines that the EN enable signal reaches the enable threshold, and the first comparator outputs a high level; the OR gate drives the second comparator according to the high level output of the first comparator to determine that the input voltage VIN reaches the VIN threshold, and the second comparator outputs a high level; the high level output of the first comparator is input into the D trigger, and the D trigger outputs a high level, and the high level output of the D trigger and the high level output of the second comparator are input into the RS trigger, and the EN_DLY enable signal output of the RS trigger becomes a high level, at this time, normal enablement;

[0007] After normal enabling, EN inputs the communication clock signal, the EN enable signal changes from high level to low level, and the EN_DLY enable signal remains high level, so that the pre-power supply generating circuit generates an output voltage VDD_PRE to power the first comparator, the second comparator and the RS trigger; the first comparator determines that the EN enable signal does not reach the enable threshold, and the first comparator outputs a low level, and the OR gate drives the second comparator according to the high level EN_DLY enable signal to determine that the input voltage VIN reaches the VIN threshold, and the second comparator outputs a high level; at the same time, the low level output by the first comparator starts the timer of the D trigger until the low level output by the first comparator continues until the D trigger outputs a low level, and the low level output by the D trigger and the high level output by the second comparator are input into the RS trigger, and the EN_DLY enable signal output by the RS trigger becomes a low level, at which time, the pre-power supply generating circuit stops supplying power and enabling stops.

[0008] Further, the pre-power supply generating circuit includes: a voltage divider circuit of an EN enable signal, a first NMOS tube, a second NMOS tube, a bias current generating circuit, a first current mirror, a first resistor, a source follower circuit and a clamping circuit, wherein the EN enable signal controls the gate terminal voltage of the first NMOS tube through the voltage divider circuit of the EN enable signal, and the EN_DLY enable signal controls the gate terminal voltage of the second NMOS tube, the gate terminal voltage of the first NMOS tube and the gate terminal voltage of the second NMOS tube are both used as bias current generating circuit enable control signals, and the source terminal of the first NMOS tube and the source terminal of the second NMOS tube are both grounded; the bias current generating circuit generates a bias current, the first current mirror feeds the bias current generated by the bias current generating circuit to the first resistor, the source follower circuit generates an output voltage VDD_PRE according to the voltage drop on the first resistor, and the clamping circuit plays a voltage clamping protection role on the bias current generating circuit and the source follower circuit.

[0009] Furthermore, the voltage divider circuit of the EN enable signal is composed of a second resistor and a third resistor, the EN enable signal is connected to one end of the second resistor, the other end of the second resistor and one end of the third resistor are both connected to the gate end of the first NMOS tube, and the other end of the third resistor is grounded.

[0010] Further, the bias current generating circuit includes: a third NMOS tube, a fourth NMOS tube, a fourth resistor, a fifth resistor and a sixth resistor, the source end of the third NMOS tube and one end of the fourth resistor are both connected to the drain end of the first NMOS tube and the drain end of the second NMOS tube, the other end of the fourth resistor and the gate end of the third NMOS tube are both connected to the source end of the fourth NMOS tube, the drain end of the third NMOS tube and the gate end of the fourth NMOS tube are respectively connected to one end of the fifth resistor and the clamping circuit, the other end of the fifth resistor and one end of the sixth resistor are both connected to the input voltage VIN, and the other end of the sixth resistor and the drain end of the fourth NMOS tube are connected to the input end of the first current mirror as the output end of the bias current generating circuit.

[0011] Further, the first current mirror is composed of a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube, the gate end of the first PMOS tube, the drain end of the first PMOS tube, the gate end of the second PMOS tube, the gate end of the third PMOS tube and the gate end of the fourth PMOS tube are jointly used as the input end of the first current mirror, the source end of the first PMOS tube is connected to the drain end of the second PMOS tube, the source end of the second PMOS tube and the source end of the third PMOS tube are both connected to the input voltage VIN, the drain end of the third PMOS tube is connected to the source end of the fourth PMOS tube, the drain end of the fourth PMOS tube is respectively connected to one end of the first resistor, the clamping circuit, and the input end of the source follower circuit, and the other end of the first resistor is grounded.

[0012] Furthermore, the source follower circuit includes: a fifth NMOS tube, a load resistor and a load capacitor, the drain end of the fifth NMOS tube is connected to the input voltage VIN, the gate end of the fifth NMOS tube serves as the input end of the source follower circuit, the source end of the fifth NMOS tube is respectively connected to one end of the load resistor and one end of the load capacitor as the output end of the source follower circuit, and the output voltage VDD_PRE; the other end of the load resistor and the other end of the load capacitor are both grounded.

[0013] Furthermore, the clamping circuit is composed of a first Zener diode and a second Zener diode, the anode of the first Zener diode is connected in parallel with the source end of the third NMOS tube and one end of the fourth resistor, the cathode of the first Zener diode is connected to the drain end of the third NMOS tube, the gate end of the fourth NMOS tube and one end of the fifth resistor, and the first Zener diode is used to clamp the gate terminal voltage of the fourth NMOS tube; the anode of the second Zener diode is grounded, the cathode of the second Zener diode is connected to one end of the first resistor, the gate end of the fifth NMOS tube and the drain end of the fourth PMOS tube, and the second Zener diode is used to clamp the gate terminal voltage of the fifth NMOS tube.

[0014] Further, the first comparator and the second comparator both include: a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a first triode, a second triode, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a seventh resistor, an eighth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a first inverter, a second inverter and a third inverter, one end of the seventh resistor is connected to the drain end of the sixth NMOS tube, the source end of the sixth NMOS tube is respectively connected to one end of the eighth resistor, the base of the first triode, and the base of the second triode, the other end of the eighth resistor is respectively connected to one end of the tenth resistor and the drain end of the ninth NMOS tube, the other end of the tenth resistor and the source end of the ninth NMOS tube are both grounded; the collector of the first triode is respectively connected to the gate end of the fifth PMOS tube, the drain end of the fifth PMOS tube, and the gate end of the sixth PMOS tube, the source end of the fifth PMOS tube and the source end of the sixth PMOS tube are both connected to the voltage VDD_PR E is connected, the drain end of the sixth PMOS tube is connected to the drain end of the seventh NMOS tube, the gate end of the seventh NMOS tube is connected to the gate end of the eighth NMOS tube, and the source end of the seventh NMOS tube and the source end of the eighth NMOS tube are both grounded; the emitter of the first triode is connected to one end of the eleventh resistor, the other end of the eleventh resistor and the emitter of the second triode are both connected to one end of the twelfth resistor, and the other end of the twelfth resistor is grounded; the collector of the second triode is respectively connected to the gate end of the seventh PMOS tube, the drain end of the seventh PMOS tube, and the gate end of the eighth PMOS tube, the source end of the seventh PMOS tube and the source end of the eighth PMOS tube are both connected to the voltage VDD_PRE, the drain end current of the eighth PMOS tube is compared with the drain end current of the eighth NMOS tube by threshold value, and the result of the threshold value comparison is input into the first inverter, the output end of the first inverter is respectively connected to the input end of the second inverter and the gate end of the ninth NMOS tube, and the output end of the second inverter is connected to the input end of the third inverter.

[0015] Further, if it is a first comparator, the other end of the seventh resistor is connected to the EN enable signal, the gate end of the sixth NMOS tube is connected to the voltage VDD_PRE, and the output end of the third inverter is connected to an input end of the OR gate.

[0016] Further, if it is a second comparator, the other end of the seventh resistor is connected to the input voltage VIN, the gate end of the sixth NMOS tube is connected to the output end of the OR gate, the output end of the third inverter and the Q end of the D trigger are both connected to the Rset end of the RS trigger, the Set end of the RS trigger is connected to the output voltage VDD_PRE, and the EN_DLY enable signal output by the RS trigger is respectively connected to the second input end of the OR gate and the gate end of the second NMOS tube in the pre-power generation circuit.

[0017] Furthermore, the D flip-flop is composed of n-stage D flip-flops, the Rset end of each stage of the D flip-flop is connected to the output end of the first stage comparator, the Clk end of the first stage of the D flip-flop is used to set the communication clock signal enabled by EN, and the Q end of the n-stage D flip-flop is connected to the Rset end of the RS flip-flop; the D end of the first n-1 stage of the D flip-flop and The D end of the nth stage D flip-flop and the Clk end of the next stage D flip-flop are connected. End connection.

[0018] Compared with the prior art, the present invention has the following beneficial effects: the first comparator of the pin multiplexing circuit structure of the enable input and the communication input can perform threshold judgment of the enable signal without introducing a reference voltage, thereby reducing the complexity of the chip; at the same time, the pin multiplexing circuit structure composed of the pre-power generation circuit, the first comparator, the second comparator, the D flip-flop and the RS flip-flop can be flexibly compatible with the input communication clock signal, that is, when the enable signal is switched to the communication clock signal, the chip can be kept enabled. The present invention integrates the enable input and the communication input into the same pin circuit, which can save chip space and improve chip integration, thereby greatly reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The overall schematic diagram of the circuit structure for implementing the pin multiplexing of the enable input and the communication input of the present invention;

[0020] Figure 2 A circuit diagram of a pre-power supply generating circuit in the present invention;

[0021] Figure 3 is a circuit diagram of the first comparator or the second comparator in the present invention. DETAILED DESCRIPTION

[0022] The technical solution of the present invention is further explained below in conjunction with the accompanying drawings.

[0023] like Figure 1The overall schematic diagram of the circuit structure for realizing pin multiplexing of enable input and communication input of the present invention, the circuit structure for realizing pin multiplexing of enable input and communication input includes: a pre-power supply generating circuit 101, a first comparator 102, an OR gate 104, a second comparator 105, a D flip-flop and an RS flip-flop;

[0024] When the enable is turned on, the EN enable signal 123 is at a high level, the EN_DLY enable signal 117 is at a low level, and the pre-power supply generating circuit 101 generates an output voltage VDD_PRE118 according to the input voltage VIN115, and supplies power to the first comparator 102, the second comparator 105 and the RS trigger; the first comparator 102 determines that the EN enable signal 123 reaches the enable threshold, and the first comparator 102 outputs EN_OK119 as a high level; the OR gate 104 drives the second comparator 105 according to the high level output of the first comparator 102 to determine that the input voltage VIN115 reaches the VIN threshold, and the second comparator 105 outputs VIN_UVLOB120 as a high level; the high level output of the first comparator 102 is input into the D trigger, and the D trigger outputs a high level 125, and the high level output of the D trigger and the high level output of the second comparator 105 are input into the RS trigger, and the EN_DLY enable signal 117 of the output of the RS trigger becomes a high level. At this time, normal enablement is achieved to realize the enable input;

[0025] After enabling normally, the EN enable signal 123 can input the communication clock signal to realize communication input. When the input communication clock signal is at a high level, it is normally enabled; when the input communication clock signal changes from a high level to a low level, the EN_DLY enable signal 117 is still at a high level, so that the pre-power supply generating circuit 101 generates an output voltage VDD_PRE118 to power the first comparator 102, the second comparator 105 and the RS trigger; the first comparator 102 determines that the EN enable signal 123 does not reach the enable threshold, and the first comparator 102 outputs EN_OK119 as a low level, and the OR gate 104 drives the second comparator 105 according to the high level EN_DLY enable signal 117. The comparator 105 determines that the input voltage VIN115 reaches the VIN threshold, and the second comparator 105 outputs VIN_UVLOB120 as a high level; at the same time, the low level output by the first comparator 102 starts the timer of the D flip-flop until the low level output by the first comparator 102 continues until the D flip-flop outputs a low level 125, and the low level output by the D flip-flop and the high level output by the second comparator 105 are input into the RS flip-flop, and the EN_DLY enable signal 117 output by the RS flip-flop becomes a low level. At this time, the pre-power supply generating circuit 101 stops supplying power and the enable stops.

[0026] The invention designs a pin multiplexing circuit structure for realizing enable input and communication input, and the multiplexed pins can realize both enable input and communication input, which can save chip space, improve chip integration, and reduce costs.

[0027] like Figure 2 In the present invention, the pre-power supply generating circuit 101 includes: a voltage divider circuit of an EN enable signal, a first NMOS tube 211, a second NMOS tube 210, a bias current generating circuit, a first current mirror, a first resistor 218, a source follower circuit and a clamping circuit. The EN enable signal controls the gate terminal voltage of the first NMOS tube 211 through the voltage divider circuit of the EN enable signal, and the EN_DLY enable signal controls the gate terminal voltage of the second NMOS tube 210. When the EN enable signal is switched from a high level to a communication clock signal, the pre-power supply generating circuit 101 can be positively charged by the high level EN_DLY enable signal. It is always enabled and is not affected by the communication clock signal; the gate terminal voltage of the first NMOS tube 211 and the gate terminal voltage of the second NMOS tube 210 are both used as bias current generating circuit enable control signals, and the source terminal of the first NMOS tube 211 and the source terminal of the second NMOS tube 210 are both grounded; the bias current generating circuit generates a bias current, and the first current mirror injects the bias current generated by the bias current generating circuit into the first resistor 218, and the source follower circuit generates an output voltage VDD_PRE according to the voltage drop across the first resistor 218, and the clamping circuit has a voltage clamping effect on the bias current generating circuit and the source follower circuit.

[0028] The voltage divider circuit of the EN enable signal in the present invention is composed of a second resistor 215 and a third resistor 216. The EN enable signal is connected to one end of the second resistor 215, the other end of the second resistor 215 and one end of the third resistor 216 are both connected to the gate end of the first NMOS tube 211, and the other end of the third resistor 216 is grounded.

[0029] The bias current generating circuit of the present invention comprises: a third NMOS transistor 202, a fourth NMOS transistor 203, a fourth resistor 212, a fifth resistor 213 and a sixth resistor 214. The source end of the third NMOS transistor 202 and one end of the fourth resistor 212 are both connected to the drain end of the first NMOS transistor 211 and the drain end of the second NMOS transistor 210. The other end of the fourth resistor 212 and the gate end of the third NMOS transistor 202 are both connected to the source end of the fourth NMOS transistor 203. The drain end of the third NMOS transistor 202 and the gate end of the fourth NMOS transistor 203 are respectively connected to one end of the fifth resistor 213 and the clamping circuit. The other end of the fifth resistor 213 and one end of the sixth resistor 214 are both connected to the input voltage VIN. The other end of the sixth resistor 214 and the drain end of the fourth NMOS transistor 203 are connected to the input end of the first current mirror as the output end of the bias current generating circuit.

[0030] In the present invention, the first current mirror is composed of a first PMOS tube 204, a second PMOS tube 205, a third PMOS tube 206 and a fourth PMOS tube 207. The gate end of the first PMOS tube 204, the drain end of the first PMOS tube 204, the gate end of the second PMOS tube 205, the gate end of the third PMOS tube 206 and the gate end of the fourth PMOS tube 207 are collectively used as the input end of the first current mirror. The source end of the first PMOS tube 204 is connected to the drain end of the second PMOS tube 205. The source end of the second PMOS tube 205 and the source end of the third PMOS tube 206 are both connected to the input voltage VIN. The drain end of the third PMOS tube 206 is connected to the source end of the fourth PMOS tube 207. The drain end of the fourth PMOS tube 207 is respectively connected to one end of the first resistor 218, the clamping circuit and the input end of the source follower circuit. The other end of the first resistor 218 is grounded.

[0031] The source follower circuit in the present invention includes: a fifth NMOS tube 208, a load resistor 217 and a load capacitor 219, the drain end of the fifth NMOS tube 208 is connected to the input voltage VIN, the gate end of the fifth NMOS tube 208 serves as the input end of the source follower circuit, and the first current mirror injects the bias current generated by the bias current generating circuit into the first resistor 218. Since the bias current is relatively stable, a stable gate terminal voltage is provided to the fifth NMOS tube 208; the source end of the fifth NMOS tube 208 is respectively connected to one end of the load resistor 217 and one end of the load capacitor 219 as the output end of the source follower circuit, and the output voltage VDD_PRE is output; the other end of the load resistor 217 and the other end of the load capacitor 219 are both grounded, and the generated output voltage VDD_PRE is kept stable by setting the load resistor 217 and the load capacitor 219.

[0032] The clamping circuit in the present invention is composed of a first Zener diode 201 and a second Zener diode 209. The anode of the first Zener diode 201 is connected in parallel with the source end of the third NMOS tube 202 and one end of the fourth resistor 212. The cathode of the first Zener diode 201 is connected to the drain end of the third NMOS tube 202, the gate end of the fourth NMOS tube 203 and one end of the fifth resistor 213. The first Zener diode 201 is used to clamp the gate end voltage of the fourth NMOS tube 203. The anode of the second Zener diode 209 is grounded. The cathode of the second Zener diode 209 is connected to one end of the first resistor 218, the gate end of the fifth NMOS tube 208 and the drain end of the fourth PMOS tube 207. The second Zener diode 209 is used to clamp the gate end voltage of the fifth NMOS tube 208. The gate end of the fourth NMOS tube 203 and the gate end of the fifth NMOS tube 208 are prevented from being broken down by the clamping circuit.

[0033] In the present invention, the fourth NMOS transistor 203 , the first PMOS transistor 204 , the fourth PMOS transistor 207 , and the fifth NMOS transistor 208 can all use high-voltage transistors to support the input voltage VIN to input a high voltage.

[0034] like Figure 3The first comparator 102 and the second comparator 105 both include: a sixth NMOS tube 301, a seventh NMOS tube 315, an eighth NMOS tube 316, a ninth NMOS tube 317, a first triode 302, a second triode 303, a fifth PMOS tube 311, a sixth PMOS tube 312, a seventh PMOS tube 313, an eighth PMOS tube 314, a seventh resistor 308, an eighth resistor 309, a tenth resistor 310, an eleventh resistor 320, a twelfth resistor 321, a first inverter 318, a second inverter 319 and a third inverter 305, one end of the seventh resistor 308 is connected to the drain end of the sixth NMOS tube 301 The source end of the sixth NMOS transistor 301 is respectively connected to one end of the eighth resistor 309, the base of the first transistor 302, and the base of the second transistor 303. The other end of the eighth resistor 309 is respectively connected to one end of the tenth resistor 310 and the drain end of the ninth NMOS transistor 317. The other end of the tenth resistor 310 and the source end of the ninth NMOS transistor 317 are both grounded. The collector of the first transistor 302 is respectively connected to the gate end of the fifth PMOS transistor 311, the drain end of the fifth PMOS transistor 311, and the gate end of the sixth PMOS transistor 312. The source end of the fifth PMOS transistor 311 and the source end of the sixth PMOS transistor 312 are both connected to the voltage VDD_PRE. , the drain end of the sixth PMOS tube 312 is connected to the drain end of the seventh NMOS tube 315, the gate end of the seventh NMOS tube 315 is connected to the gate end of the eighth NMOS tube 316, and the source end of the seventh NMOS tube 315 and the source end of the eighth NMOS tube 316 are both grounded; the emitter of the first triode 302 is connected to one end of the eleventh resistor 320, the other end of the eleventh resistor 320 and the emitter of the second triode 303 are both connected to one end of the twelfth resistor 321, and the other end of the twelfth resistor 321 is grounded; the collector of the second triode 303 is respectively connected to the gate end of the seventh PMOS tube 313, the drain end of the seventh PMOS tube 313, and the gate end of the eighth PMOS The gate end of the ninth NMOS tube 317 is connected to the gate end of the seventh PMOS tube 314, the source end of the seventh PMOS tube 313 and the source end of the eighth PMOS tube 314 are both connected to the voltage VDD_PRE, the drain current of the eighth PMOS tube 314 is compared with the drain current of the eighth NMOS tube 316 by threshold value, and the result of the threshold comparison is input to the first inverter 318, the output end of the first inverter 318 is respectively connected to the input end of the second inverter 319 and the gate end of the ninth NMOS tube 317, the output end of the first inverter 318 controls the gate end of the ninth NMOS tube 317 to form hysteresis to prevent false triggering caused by noise; the output end of the second inverter 319 is connected to the input end of the third inverter 305.

[0035] If it is the first comparator 102, the other end of the seventh resistor 308 is connected to the EN enable signal, the gate end of the sixth NMOS tube 301 is connected to the voltage VDD_PRE, and the output end of the third inverter 305 is connected to an input end of the OR gate 104. The voltage of the EN enable signal is divided by the seventh resistor 308, the eighth resistor 309, and the tenth resistor 310. When the voltage of the EN enable signal is low, the voltage division 304 is also low, the base voltage of the first transistor 302 and the second transistor 303 is low, the collector current of the first transistor 302 is less than the collector current of the second transistor 303, the drain end of the eighth NMOS tube 316 and the eighth PMOS tube 314 compares the current to obtain a high level, and the third inverter 305 outputs a low level; the voltage of the EN enable signal gradually increases, the voltage division 304 also increases. When the divided voltage 304 increases by more than about 1.2V, the collector current of the first transistor 302 is greater than the collector current of the second transistor 303. The currents of the two are compared at the drain ends of the eighth NMOS tube 316 and the eighth PMOS tube 314 to obtain a low level, and finally the third inverter 305 outputs a high level. In this way, the threshold judgment of the EN enable signal only needs to be set by the divided voltage of the seventh resistor 308, the eighth resistor 309, and the tenth resistor 310, without introducing a reference voltage, thereby reducing the difficulty of comparing the EN enable signal with the enable threshold.

[0036] If it is the second comparator 105, the other end of the seventh resistor 308 is connected to the input voltage VIN, the gate end of the sixth NMOS tube 301 is connected to the output end of the OR gate 104, the output end of the third inverter 305 and the Q end of the D flip-flop are connected to the Rset end of the RS flip-flop, the Set end of the RS flip-flop is connected to the output voltage VDD_PRE, and the EN_DLY enable signal output by the RS flip-flop is respectively connected to the second input end of the OR gate 104 and the gate end of the second NMOS tube 210 in the pre-power generation circuit. Similarly, the threshold comparison of the input voltage VIN is set by the seventh resistor 308, the eighth resistor 309, and the tenth resistor 310 in the second comparator 105, without introducing a reference voltage, which reduces the difficulty of comparing the input voltage VIN with the VIN threshold.

[0037] The D flip-flop in the present invention is composed of n-stage D flip-flops, the Rset end of each stage of the D flip-flop is connected to the output end of the first stage comparator 102, the Clk end of the first stage of the D flip-flop is used to set the communication clock signal enabled by EN, and the Q end of the n-th stage of the D flip-flop is connected to the Rset end of the RS flip-flop; the D end of the first n-1 stage of the D flip-flop and The D terminals of the nth-stage D flip-flop are connected to the Clk terminals of the next-stage D flip-flop. The number of stages of the D flip-flop of the present invention can be adjusted according to the frequency range of the actually compatible communication clock signal, so as to adapt to different communication cycle signals.

[0038] In one technical solution of the present invention, a four-stage D flip-flop is provided, such as Figure 1 The Rset end of the first-stage D flip-flop 107, the Rset end of the second-stage D flip-flop 108, the Rset end of the third-stage D flip-flop 109, and the Rset end of the fourth-stage D flip-flop 110 are all connected to the output end of the first-stage comparator 102, the Clk end of the first-stage D flip-flop 107 is used to set the communication clock signal enabled by EN, and the Q end of the fourth-stage D flip-flop 110 is connected to the Rset end of the RS flip-flop; the D end of the first-stage D flip-flop 107 and The Clk terminal of the second-stage D flip-flop 108 is connected to the D terminal of the second-stage D flip-flop 108. The Clk terminal of the third-stage D flip-flop 109 is connected to the D terminal of the third-stage D flip-flop 109. The D terminal of the fourth-stage D flip-flop 110 is connected to the Clk terminal of the fourth-stage D flip-flop 110. Therefore, when the time when the first comparator 102 outputs EN_OK119 at a low level is less than 4 times the CLK122 cycle, that is, as long as the communication clock signal input by EN is at a low level for less than 4 times the CLK cycle, the chip can still work normally.

[0039] like Figure 1The RS trigger of the present invention includes: a first NAND gate 111, a second NAND gate 112, a third NAND gate 114, a fourth inverter 113 and a fifth inverter 128, the first input terminal and the second input terminal of the first NAND gate 111 are used as the Rset terminal of the RS trigger, and the first input terminal of the first NAND gate 111 is connected to the Q terminal of the D trigger, and the second input terminal of the first NAND gate 111 is connected to the output terminal VIN_UVLOB of the second comparator 105. 120, the output terminal 127 of the first NAND gate 111 is connected to the first input terminal of the second NAND gate 112, the second input terminal of the second NAND gate 112 is connected to the output terminal of the third NAND gate 114, the output terminal of the second NAND gate 112 is respectively connected to the input terminal of the fifth inverter 128 and the first input terminal of the third NAND gate 114, the output terminal EN_DLY128 of the fifth inverter 128 is respectively connected to the second input terminal of the OR gate 104 and the gate terminal of the second NMOS tube 210 in the pre-power supply generating circuit 101; the input terminal of the fourth inverter 113 is connected to the input voltage VDD_PRE as the Set terminal of the RS trigger, and the output terminal of the fourth inverter 113 is connected to the second input terminal of the third NAND gate 114. After the first enablement, as long as the low level time of the communication signal input by the subsequent EN enable signal does not exceed the time when the D trigger outputs the low level, the EN_DLY enable signal output by the RS trigger can maintain a high level, maintain the normal enabling process, so that the chip enablement is not affected by the EN communication signal.

[0040] The specific working process of the present invention to realize the pin multiplexing circuit structure of enable input and communication input is as follows:

[0041] When the enable is turned on, the EN enable signal 123 is at a high level, and the EN_DLY enable signal is initially at a low level. The EN enable signal 123 is divided by the second resistor 215 and the third resistor 216 to turn on the first NMOS tube 211, so that the VGS voltage of the third NMOS tube 202 is divided by the resistance value of the fourth resistor 212 to generate a bias current, and then the current is poured into the first resistor 218 through the first current mirror composed of the first PMOS tube 204, the second PMOS tube 205, the third PMOS tube 206 and the fourth PMOS tube 207, so that the fifth NMOS in the source follower circuit is turned on. The S transistor 208 is turned on and outputs a voltage VDD_PRE to power the first comparator 102, the second comparator 105 and the RS trigger; the voltage VDD_PRE is input to the gate end of the sixth NMOS transistor 301 to turn on the sixth NMOS transistor 301, and the other end of the seventh resistor 308 in the first comparator 102 inputs a high-level EN enable signal 123, and the EN enable signal 123 is divided by the seventh resistor 308, the eighth resistor 309 and the tenth resistor 310. When the divided voltage 304 is higher than 1.2V, the collector current of the first transistor 302 is greater than the collector current of the second transistor 303. The collector current of the first transistor 302 is copied to the eighth NMOS tube 316 through the current mirror composed of the fifth PMOS tube 311 and the sixth PMOS tube 312 and the current mirror composed of the seventh NMOS tube 315 and the eighth NMOS tube 316, and the collector current of the second transistor 303 is copied to the eighth PMOS tube 314 through the current mirror composed of the seventh PMOS tube 313 and the eighth PMOS tube 314, resulting in the drain terminal voltage of the eighth NMOS tube 316 and the eighth PMOS tube 314 being pulled down, and the output EN_OK119 of the first comparator 102 is high level, and EN_OK11 9 The output of the OR gate 104 is made high through the OR gate 104, and the second comparator 105 is enabled. Similarly, the second comparator starts the UVLO threshold comparison of VIN. When the output 120 of the second comparator 105 is high, the D flip-flop input CLK, and EN_OK119 is high, the output 125 of the D flip-flop is high. Since the output 120 of the second comparator 105 is also high, the output 127 of the first AND gate 11 is high, and the RS flip-flop sets the EN_DLY enable signal 117 output by the RS flip-flop high by VDD_PRE. At this time, the whole circuit is enabled normally;

[0042] After enabling normally, the EN enable signal 123 can input the communication clock signal. When the input communication clock signal is at a high level, it is enabled normally. When the input communication clock signal changes from a high level to a low level, the EN_DLY enable signal 117 output by the RS trigger can be maintained at a high level, thereby enabling the pre-power supply generating circuit 101 to normally generate the output VDD_PRE. At this time, the first comparator 102 and the second comparator 105 are not powered off, but EN_OK119 will become low with the EN enable signal 123, and the output 124 of the OR gate 104 will still remain at a high level, so that the output state of the second comparator 105 remains unchanged. When EN_OK119 is low, the D flip-flop timing will be started until EN_OK119 is low for 4 times the CLK cycle, and the output 125 of the D flip-flop becomes low. After passing through the RS flip-flop, the output EN_DLY117 of the RS flip-flop is also set low. At this time, the two enable signals of the pre-power supply generating circuit 101 are low at the same time, so that the pre-power supply generating circuit 101 stops supplying power, causing the output VIN_UVLOB120 of the second comparator 105 to be low. At this time, the enable stops.

[0043] The pin multiplexing circuit of the present invention can realize the multiplexing of enable input and communication input, save pins and reduce costs.

[0044] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A pin multiplexing circuit structure for realizing enable input and communication input, characterized in that: include: A pre-power supply generating circuit (101), a first comparator (102), an OR gate (104), a second comparator (105), a D flip-flop and an RS flip-flop; When the enable is turned on, the EN enable signal is at a high level and the EN_DLY enable signal is initially at a low level. The pre-power supply generating circuit (101) generates an output voltage VDD_PRE according to the input voltage VIN to supply power to the first comparator (102), the second comparator (105) and the RS trigger; the first comparator (102) determines that the EN enable signal reaches the enable threshold, and the first comparator (102) outputs a high level; the OR gate (104) drives the second comparator (105) to determine that the input voltage VIN reaches the VIN threshold according to the high level output by the first comparator (102), and the second comparator (105) outputs a high level; the high level output by the first comparator (102) is input into the D trigger, and the D trigger outputs a high level; the high level output by the D trigger and the high level output by the second comparator (105) are input into the RS trigger, and the EN_DLY enable signal output by the RS trigger becomes a high level, and at this time, normal enablement is achieved; After normal enabling, EN inputs a communication clock signal, the EN enable signal changes from a high level to a low level, and the EN_DLY enable signal remains at a high level, so that the pre-power generation circuit (101) generates an output voltage VDD_PRE to supply power to the first comparator (102), the second comparator (105) and the RS trigger; the first comparator (102) determines that the EN enable signal does not reach the enable threshold, the first comparator (102) outputs a low level, and the OR gate (104) drives the second comparator (105) according to the high level EN_DLY enable signal. 5) When it is determined that the input voltage VIN reaches the VIN threshold, the second comparator (105) outputs a high level; at the same time, the low level output by the first comparator (102) starts the timer of the D flip-flop until the low level output by the first comparator (102) continues until the D flip-flop outputs a low level, and the low level output by the D flip-flop and the high level output by the second comparator (105) are input into the RS flip-flop, and the EN_DLY enable signal output by the RS flip-flop becomes a low level. At this time, the pre-power supply generating circuit (101) stops supplying power, and the enable stops.

2. A pin multiplexing circuit structure for realizing enable input and communication input according to claim 1, characterized in that: The pre-power supply generating circuit (101) comprises: an EN enable signal voltage divider circuit, a first NMOS tube (211), a second NMOS tube (210), a bias current generating circuit, a first current mirror, a first resistor (218), a source follower circuit and a clamping circuit, wherein the EN enable signal controls the gate terminal voltage of the first NMOS tube (211) through the EN enable signal voltage divider circuit, and the EN_DLY enable signal controls the gate terminal voltage of the second NMOS tube (210), and the gate terminal voltages of the first NMOS tube (211) and the second NMOS tube (210) are controlled by the EN enable signal voltage divider circuit. The gate terminal voltage of the S transistor (210) is used as a bias current generating circuit enabling control signal; the source terminal of the first NMOS transistor (211) and the source terminal of the second NMOS transistor (210) are both grounded; the bias current generating circuit generates a bias current; the first current mirror injects the bias current generated by the bias current generating circuit into the first resistor (218); the source follower circuit generates an output voltage VDD_PRE according to a voltage drop across the first resistor (218); and the clamping circuit performs a voltage clamping protection function on the bias current generating circuit and the source follower circuit.

3. A pin multiplexing circuit structure for realizing enable input and communication input according to claim 2, characterized in that: The voltage divider circuit of the EN enable signal is composed of a second resistor (215) and a third resistor (216); the EN enable signal is connected to one end of the second resistor (215); the other end of the second resistor (215) and one end of the third resistor (216) are both connected to the gate end of the first NMOS transistor (211); and the other end of the third resistor (216) is grounded.

4. A pin multiplexing circuit structure for realizing enable input and communication input according to claim 3, characterized in that: The bias current generating circuit comprises: a third NMOS tube (202), a fourth NMOS tube (203), a fourth resistor (212), a fifth resistor (213) and a sixth resistor (214), wherein the source end of the third NMOS tube (202) and one end of the fourth resistor (212) are both connected to the drain end of the first NMOS tube (211) and the drain end of the second NMOS tube (210), and the other end of the fourth resistor (212) and the gate end of the third NMOS tube (202) are both connected to the drain end of the fourth NMOS tube (211). The source end of the NMOS tube (203) is connected, the drain end of the third NMOS tube (202) and the gate end of the fourth NMOS tube (203) are respectively connected to one end of the fifth resistor (213) and the clamping circuit, the other end of the fifth resistor (213) and one end of the sixth resistor (214) are both connected to the input voltage VIN, and the other end of the sixth resistor (214) and the drain end of the fourth NMOS tube (203) are connected to the input end of the first current mirror as the output end of the bias current generating circuit.

5. A pin multiplexing circuit structure for realizing enable input and communication input according to claim 4, characterized in that: The first current mirror is composed of a first PMOS tube (204), a second PMOS tube (205), a third PMOS tube (206) and a fourth PMOS tube (207); the gate end of the first PMOS tube (204), the drain end of the first PMOS tube (204), the gate end of the second PMOS tube (205), the gate end of the third PMOS tube (206) and the gate end of the fourth PMOS tube (207) are collectively used as the input end of the first current mirror; the first PMOS tube (204) The source end of the first PMOS transistor (205) is connected to the drain end of the second PMOS transistor (205), the source end of the second PMOS transistor (205) and the source end of the third PMOS transistor (206) are both connected to the input voltage VIN, the drain end of the third PMOS transistor (206) is connected to the source end of the fourth PMOS transistor (207), the drain end of the fourth PMOS transistor (207) is respectively connected to one end of the first resistor (218), the clamping circuit, and the input end of the source follower circuit, and the other end of the first resistor (218) is grounded.

6. A pin multiplexing circuit structure for realizing enable input and communication input according to claim 5, characterized in that: The source follower circuit comprises: a fifth NMOS transistor (208), a load resistor (217) and a load capacitor (219); the drain end of the fifth NMOS transistor (208) is connected to an input voltage VIN; the gate end of the fifth NMOS transistor (208) serves as an input end of the source follower circuit; the source end of the fifth NMOS transistor (208) is respectively connected to one end of the load resistor (217) and one end of the load capacitor (219) as an output end of the source follower circuit, and outputs a voltage VDD_PRE; the other end of the load resistor (217) and the other end of the load capacitor (219) are both grounded.

7. A pin multiplexing circuit structure for realizing enable input and communication input according to claim 6, characterized in that: The clamping circuit is composed of a first Zener diode (201) and a second Zener diode (209); the anode of the first Zener diode (201) is connected in parallel with the source end of the third NMOS tube (202) and one end of the fourth resistor (212); the cathode of the first Zener diode (201) is connected to the drain end of the third NMOS tube (202), the gate end of the fourth NMOS tube (203) and one end of the fifth resistor (213); the first Zener diode (201) is used to clamp the gate end voltage of the fourth NMOS tube (203); the anode of the second Zener diode (209) is grounded; the cathode of the second Zener diode (209) is connected to one end of the first resistor (218), the gate end of the fifth NMOS tube (208) and the drain end of the fourth PMOS tube (207); the second Zener diode (209) is used to clamp the gate end voltage of the fifth NMOS tube (208).

8. A pin multiplexing circuit structure for realizing enable input and communication input according to claim 7, characterized in that: The first comparator (102) and the second comparator (105) both comprise: a sixth NMOS transistor (301), a seventh NMOS transistor (315), an eighth NMOS transistor (316), a ninth NMOS transistor (317), a first triode (302), a second triode (303), a fifth PMOS transistor (311), a sixth PMOS transistor (312), a seventh PMOS transistor (313), an eighth PMOS transistor (314), a seventh resistor (308), an eighth resistor (309), a tenth resistor (310), an eleventh A resistor (320), a twelfth resistor (321), a first inverter (318), a second inverter (319) and a third inverter (305), one end of the seventh resistor (308) is connected to the drain end of the sixth NMOS transistor (301), the source end of the sixth NMOS transistor (301) is respectively connected to one end of the eighth resistor (309), the base of the first triode (302) and the base of the second triode (303), the other end of the eighth resistor (309) is respectively connected to one end of the tenth resistor (310), the base of the ninth NMOS transistor (303) and the base of the ninth triode (303). The drain end of the tenth resistor (310) and the source end of the ninth NMOS tube (317) are both grounded; the collector of the first triode (302) is respectively connected to the gate end of the fifth PMOS tube (311), the drain end of the fifth PMOS tube (311), and the gate end of the sixth PMOS tube (312); the source end of the fifth PMOS tube (311) and the source end of the sixth PMOS tube (312) are both connected to the voltage VDD_PRE; the drain end of the sixth PMOS tube (312) is connected to the gate end of the seventh NMOS tube (317); ... The drain end of the seventh NMOS tube (315) is connected to the gate end of the eighth NMOS tube (316), the source end of the seventh NMOS tube (315) and the source end of the eighth NMOS tube (316) are both grounded; the emitter of the first triode (302) is connected to one end of the eleventh resistor (320), the other end of the eleventh resistor (320) and the emitter of the second triode (303) are both connected to one end of the twelfth resistor (321), and the other end of the twelfth resistor (321) is grounded;The collector of the second triode (303) is respectively connected to the gate end of the seventh PMOS tube (313), the drain end of the seventh PMOS tube (313), and the gate end of the eighth PMOS tube (314); the source end of the seventh PMOS tube (313) and the source end of the eighth PMOS tube (314) are both connected to the voltage VDD_PRE; the drain end current of the eighth PMOS tube (314) is compared with the drain end current of the eighth NMOS tube (316) by threshold value, and the result of the threshold value comparison is input into the first inverter (318); the output end of the first inverter (318) is respectively connected to the input end of the second inverter (319) and the gate end of the ninth NMOS tube (317); the output end of the second inverter (319) is connected to the input end of the third inverter (305). ; 9. A pin multiplexing circuit structure for realizing enable input and communication input according to claim 8, characterized in that: If it is a first comparator (102), the other end of the seventh resistor (308) is connected to the EN enable signal, the gate end of the sixth NMOS tube (301) is connected to the voltage VDD_PRE, and the output end of the third inverter (305) is connected to an input end of the OR gate (104).

10. A pin multiplexing circuit structure for realizing enable input and communication input according to claim 9, characterized in that: If it is a second comparator (105), the other end of the seventh resistor (308) is connected to the input voltage VIN, the gate end of the sixth NMOS tube (301) is connected to the output end of the OR gate (104), the output end of the third inverter (305) and the Q end of the D trigger are both connected to the Rset end of the RS trigger, the Set end of the RS trigger is connected to the output voltage VDD_PRE, and the EN_DLY enable signal output by the RS trigger is respectively connected to the second input end of the OR gate (104) and the gate end of the second NMOS tube (210) in the pre-power generation circuit.

11. A pin multiplexing circuit structure for realizing enable input and communication input according to claim 10, characterized in that: The D flip-flop is composed of n-stage D flip-flops, the Rset end of each stage of the D flip-flop is connected to the output end of the first comparator (102), the Clk end of the first stage of the D flip-flop is used to set the communication clock signal enabled by EN, and the Q end of the n-stage D flip-flop is connected to the Rset end of the RS flip-flop; the D end of the first n-1 stage of the D flip-flop and The D end of the nth stage D flip-flop and the Clk end of the next stage D flip-flop are connected. End connection.

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