Temperature sensor circuit

Abstract

The present disclosure relates to a temperature sensor circuit comprising: a PTAT voltage circuit; a reference current source; a capacitor; a reset switch connected across the capacitor; a comparator configured to compare a voltage of the capacitor with the PTAT voltage and provide a comparator output (U / D); a counter circuit configured to incrementally or incrementally decrease an output word (Kdig) as a function of the comparator output (U / D) and repeat the following sequential steps: i) providing a reset signal to briefly close the reset switch to discharge the capacitor; ii) counting a number of clock cycles corresponding to the output word (Kdig) while the reference current source charges the capacitor; and iii) incrementing or decrementing the output word (Kdig) as a function of the comparator output (U / D), where the output word (Kdig) converges to a value corresponding to the temperature of the PTAT voltage circuit after repeating the sequential steps.

Description

Technical Field

[0001] The present disclosure relates to temperature sensor circuits. Background Art

[0002] A temperature sensor can be implemented by comparing the amplitude of a temperature-dependent signal and a temperature-independent signal. The ratio between these two amplitudes contains information about the temperature, which can be converted into a digital word.

[0003] In an integrated circuit (IC), for example, when measuring the voltage difference between two nominally identical PN junctions with a fixed current density ratio n (where n≠1), an accurate temperature-dependent voltage can be obtained. For two diodes with a current density ratio n, the voltage difference ΔVd between the two diode voltages is given by:

[0004] ΔVd = VT ln (n)

[0005] Where VT = kT / q, k = 1.38*10-23 J / K (Boltzmann constant), q = 1.6*10-19 C (electron charge), and T is the absolute temperature in degrees Kelvin.

[0006] The only variable in ΔVd is the absolute temperature T. For this reason, this voltage is denoted as a "proportional to absolute temperature" (PTAT) voltage.

[0007] The PTAT voltage is also obtained when taking the difference (ΔVbe) between the two base-to-emitter voltages of two identical bipolar transistors with a fixed collector current density ratio n (where n≠1) or the difference (ΔVgs) between the two gate-to-source voltages of two identical MOS transistors with a fixed drain current density ratio n (where n≠1) and biased in the weak inversion region.

[0008] Inside the IC, the temperature-independent voltage VREF is obtained by taking the voltage drop (Vdiode) across the pn junction and adding it to this (usually amplified) PTAT voltage VPTAT so that the positive temperature coefficient of VPTAT compensates for the negative temperature coefficient of Vdiode. Figure 1 The temperature gradient of VPTAT at room temperature (about 27°C or 300K) is designed to exactly compensate for the temperature gradient of Vdiode. Vdiode and VPTAT are about 600mV each at about 300K, but can vary slightly from this. The negative temperature coefficient of the diode is fairly accurate across process corners, but its absolute voltage can vary. The PTAT voltage is very accurate, but since half of VREF comes from Vdiode, the absolute value of VREF has some inaccuracy across process corners.

[0009] The relationship between the diode voltage Vdiode and temperature is not a straight line. Therefore, the reference voltage VREF obtained (in this example, about 1.2V) is slightly different from the actual 0°K diode voltage (the "bandgap" voltage). VREF is called the "extrapolated bandgap voltage", which is the voltage that would be obtained if the diode temperature characteristic was an ideal straight line.

[0010] Instead of using a diode, VREF can also be generated using the base-to-emitter voltage of a bipolar transistor or the gate-to-source voltage of a MOS transistor.

[0011] Typically, the PTAT and REF quantities are required as currents (which can be obtained by dividing VPTAT and VREF by the internal resistor values). This can be achieved in a variety of ways.

[0012] Existing types of temperature sensors may use a simple up-down counter (UDC) as part of a feedback loop that produces an output digital temperature word. The output word may be determined by a shunt or series resistor network, which may occupy a large area on the IC. In an alternative arrangement, a current comparison may be used to produce a varying duty cycle signal containing information about the ratio between the PTAT current and a reference current, which may be converted into an output digital temperature word.

[0013] A more complex digital iteration solution may be used instead, which may result in a faster settling time. A simple improvement may be achieved by doubling the UDC step size when three consecutive up or down count commands have occurred. With four consecutive up or down commands, the UDC step size may be increased fourfold, and so on. Other solutions may also provide faster settling times.

[0014] The temperature coefficients of the PTAT voltage and the diode voltage are quite accurate, resulting in a reference voltage with very little temperature dependence. Because the forward voltage drop of the diode can vary between IC processes, the absolute value of the reference voltage VREF is not very accurate. This results in unpredictable offsets in the sensor output, which can be corrected by a single-point calibration. The slope of the digital output with respect to temperature can be accurate enough, but the absolute value needs to be corrected by checking and correcting the output at a fixed temperature. This is typical of all sensors based on PTAT and REF (PTAT + diode) quantities.

[0015] The problem with existing temperature sensor circuits is that the slope of the temperature characteristic (i.e., the digital output word versus temperature) will not be completely monotonic due to resistor mismatch. A two-point calibration may be required because switching current sources may cause unpredictable gain errors in the temperature characteristic. Summary of the invention

[0016] According to a first aspect, there is provided a temperature sensor circuit, comprising:

[0017] a proportional to absolute temperature (PTAT) voltage circuit configured to provide a PTAT voltage;

[0018] a reference current source connected between the supply rail and the node;

[0019] a capacitor connected between the node and a common rail;

[0020] a reset switch connected across the capacitor;

[0021] a comparator configured to compare a voltage of the capacitor with the PTAT voltage and provide a comparator output;

[0022] A counter circuit is configured to increment or decrement an output word according to the comparator output, the counter circuit being configured to repeatedly perform the following sequential steps:

[0023] i) providing a reset signal to briefly close the reset switch to discharge the capacitor;

[0024] ii) counting the number of clock cycles corresponding to the output word while the reference current source charges the capacitor; and

[0025] iii) increasing or decreasing the output word according to the comparator output,

[0026] Wherein after repeating the sequential steps, the output word converges to a value corresponding to the temperature of the PTAT voltage circuit.

[0027] The advantage of the temperature sensor circuit is that it does not have the disadvantages of the above examples. The temperature sensor has similar characteristics to the previous example using multiple resistors, but without the corresponding IC area loss due to the use of capacitors instead of multiple resistors.

[0028] In some examples, a first input of the comparator is connected to the node, and a second input of the comparator is connected to receive the PTAT voltage from the PTAT voltage circuit.

[0029] In some examples, the counter circuit includes:

[0030] an up-down counter (UDC) having an input connected to receive the comparator output and configured to provide the output word;

[0031] a down counter connected to receive the output word from the UDC; and

[0032] A clock signal generator is configured to provide a clock signal to the down counter and the UDC.

[0033] In some examples, the temperature sensor circuit includes: a sampling switch connected between the node and the first input of the comparator; and a sampling capacitor connected between the first input of the comparator and the common rail, wherein the counter circuit is configured to provide a sampling signal after step ii) to close the sampling switch, thereby providing the voltage of the capacitor to the first input of the comparator.

[0034] In some examples, the reference current source includes a first PMOS transistor having a source connected to the supply rail and a drain connected to the node. A second PMOS transistor may have a source connected to the supply rail and a gate connected to the gate of the first PMOS transistor.

[0035] In some examples, the temperature sensor may include an amplifier having an output connected to the gates of the first and second PMOS transistors, a first input of the amplifier connected to a drain of the second PMOS transistor, and a second input of the amplifier connected to the capacitor.

[0036] The temperature sensor circuit may additionally include:

[0037] a first resistor and a first diode connected in series between the first input of the amplifier and the common rail;

[0038] a second resistor connected between the first input of the amplifier and the common rail;

[0039] a third resistor connected between the second input of the amplifier and the common rail; and

[0040] A second diode is connected between the second input of the amplifier and the common rail.

[0041] The temperature sensor circuit may additionally include:

[0042] a third PMOS transistor having a source connected to the supply rail and a drain connected to the second input of the comparator; and

[0043] A fourth resistor is connected between the first input of the comparator and the common rail.

[0044] The counter circuit may be configured to output a preset value of the output word when the temperature sensor circuit is activated. The preset value of the output word may correspond to a temperature between 200 and 600K.

[0045] The counter circuit may be configured to increment the output word when the voltage of the capacitor is lower than the PTAT voltage, and to decrement the output word when the voltage of the capacitor is higher than the PTAT voltage.

[0046] According to a second aspect, there is provided a method of operating a temperature sensor circuit, comprising:

[0047] a proportional to absolute temperature (PTAT) voltage circuit configured to provide a PTAT voltage;

[0048] a reference current source connected between the supply rail and the node;

[0049] a capacitor connected between the node and a common rail;

[0050] a reset switch connected across the capacitor;

[0051] a comparator configured to compare a voltage of the capacitor with the PTAT voltage and provide a comparator output; and

[0052] a counter circuit configured to increment or decrement an output word in dependence upon the comparator output,

[0053] The method includes the counter circuit performing the following operations:

[0054] i) providing a reset signal to briefly close the reset switch to discharge the capacitor;

[0055] ii) counting the number of clock cycles corresponding to the output word while the reference current source charges the capacitor;

[0056] iii) increasing or decreasing the output word according to the comparator output; and

[0057] iv) repeating steps i) to iii) so that the output word converges to a value corresponding to the temperature of the PTAT voltage circuit.

[0058] If a preset number of consecutive repetitions of steps i) to iii) causes the output word to be incremented or decremented, the output word may be incremented or decremented, respectively, by a preset number of bits exceeding one bit.

[0059] The preset number of consecutive repetitions may be three or more times, and the preset number of digits may be two or more.

[0060] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Embodiments will be described, by way of example only, with reference to the accompanying drawings, in which:

[0062] Figure 1 It is a schematic curve showing the variation of each voltage with temperature;

[0063] Figure 2 is a schematic diagram of an example temperature sensor circuit;

[0064] Figure 3 is a schematic diagram of an alternative example temperature sensor circuit;

[0065] Figure 4 It is for Figure 3 A schematic curve showing how the voltage of a circuit varies with temperature;

[0066] Figure 5 It has a reference current circuit Figure 2 A schematic diagram of an example temperature sensor circuit;

[0067] Figure 6 is a schematic diagram of another example temperature sensor circuit;

[0068] Figure 7 is a schematic diagram of a calibration mode of an example temperature sensor circuit;

[0069] Figure 8 It is a curve of output temperature-dependent voltage changing with time for different process corners;

[0070] Fig. 9 is a plot of output temperature dependence of voltage versus time during a calibration mode followed by normal operation; and

[0071] Fig.10 It is a curve showing the change of UDC content over time at different temperatures.

[0072] It should be noted that these figures are diagrammatic and not drawn to scale. For the sake of clarity and convenience of the drawings, the relative sizes and proportions of the parts in these figures have been exaggerated or reduced. In modified and different embodiments, the same reference numerals are generally used to refer to corresponding or similar features. DETAILED DESCRIPTION

[0073] Figure 2An example temperature sensor circuit 200 for generating an output digital word Kdig according to a PTAT voltage VPTAT is schematically shown. The temperature sensor circuit 200 includes a PTAT voltage circuit 201 configured to provide a PTAT voltage VPTAT. For example, as discussed above, the PTAT voltage circuit 201 can be based on a voltage difference between two base-to-emitter voltages of the same bipolar transistor with a fixed collector current density ratio n (where n≠1) or a voltage difference between two gate-to-source voltages of two same MOS transistors with a fixed drain current density ratio n (where n≠1) and in a weak inversion region bias.

[0074] Reference current source 202 is connected between supply rail 213 and node 212. Example reference current sources are described in detail below. Capacitor 203 is connected between node 212 and common rail 209. Reset switch 204 is connected across capacitor 203, ie, between node 212 and common rail 209.

[0075] Comparator 205 is configured to compare the voltage of capacitor 203 with the PTAT voltage VPTAT from PTAT voltage source 201 and provide a comparator output U / D. The comparator output is a binary signal provided to counter circuit 206, which is configured to increment or decrement the output digital word Kdig according to the comparator output U / D. If the voltage of capacitor 203 is lower than the PTAT voltage VPTAT, then the comparator output U / D causes counter 206 to increment the output word Kdig. If the voltage of capacitor 203 is higher than the PTAT voltage VPTAT, then the comparator output U / D causes counter 206 to decrement the output word Kdig.

[0076] The counter repeatedly executes a sequence of steps, beginning with providing a reset signal 207 to briefly close the reset switch 204 to discharge the capacitor 203. Once the capacitor 203 is discharged, the reset switch 204 opens, and the counter begins counting the number of clock cycles corresponding to the output word Kdig while the reference current source 202 charges the capacitor 203. Once the number of clock cycles is completed, the counter circuit 206 receives the comparator output U / D and increments or decrements the output word Kdig according to the comparator output U / D.

[0077] Counter circuit 206 repeatedly performs the above sequence of steps so that output word Kdig converges to a value corresponding to the temperature of PTAT voltage circuit 201. When the temperature is stable, output word Kdig tends to oscillate around a stable value, thereby increasing and decreasing the output word at the end of each cycle.

[0078] Figure 3An example temperature sensor circuit 300 is schematically shown, wherein a counter circuit 306 is further shown in detail and provides a sampling scheme for sampling the voltage of a capacitor. Figure 2 In the example circuit of FIG. 3 , the temperature sensor circuit 300 includes a PTAT voltage circuit 301, a reference current source 302 connected between a supply rail 213 and a node 212. A capacitor 303 is connected between the node 312 and the common rail 209. A reset switch 304 is connected across the capacitor 303. A comparator 305 compares the voltage of the capacitor 303 with a PTAT voltage VPTAT and provides a comparator output U / D to a counter circuit 306. A first input 310 of the comparator 305 is connected to the node 312, and a second input of the comparator 305 is connected to receive the PTAT voltage VPTAT from the PTAT voltage circuit 301.

[0079] The comparator provides a comparator output in the form of an up / down (U / D) signal to the counter circuit 306. The counter circuit 306 includes an up / down counter (UDC) 313, a down counter 314, and a clock signal generator 315. The UDC 313 receives the comparator output and provides an output word Kdig to the down counter 314. The clock signal generator 315 provides a clock signal RC clk to the down counter 314 and the UDC 313.

[0080] The sampling switch 316 is connected between the node 312 and the first input 310 of the comparator 305. The sampling capacitor 317 is connected between the second input of the comparator 902 and the common rail 209. The counter circuit 306 provides a sampling signal to close the sampling switch 316 after counting the number of clock cycles corresponding to the output word Kdig, thereby providing the voltage of the capacitor 303 to the first input 310 of the comparator 305.

[0081] The clock signal generator 315 may be a local RC oscillator (i.e., an oscillator using resistors and capacitors inside the IC). The UDC content Kdig is loaded into the down counter 314. After the down counter 314 provides a reset pulse (e.g., having a duration of one clock pulse) to the reset switch 304 to fully discharge the capacitor 303, the down counter 314 counts down from Kdig to zero in a continuous clock cycle. Therefore, the total period of counting down from Kdig to zero may be a time period Kdig·Tclk, i.e., a period determined by multiplying the UDC content by the clock signal period. During this time, the capacitor 303 is charged with a reference current IREF. Once the down counter 314 reaches zero, the voltage of the capacitor 303 is sampled by providing a sampling signal that closes the sampling switch to charge the sampling capacitor 317, thereby providing the voltage of the capacitor 303 to the first input 310 of the comparator 305. For example, the sampling signal may be provided within one clock cycle. Then, the cycle repeats, wherein the content Kdig of the UDC 313 is again provided to the down counter 314.

[0082] After stabilization, the content Kdig of the UDC 313 represents the measured temperature. As described above, the content will switch between two values ​​that differ by one LSB.

[0083] The clock signal generator 315 can be designed so that the clock period Tclk is equal to Rosc·Cosc, where Rosc and Cosc are the resistor and capacitor that define the clock signal frequency in the clock signal generator 315. VPTAT=a·T (where a is a constant and T is absolute temperature), and the reference current IREF=Vref / Rref:

[0084] VPTAT=Iref·Kdig·Tclk / Cint

[0085] T=(Vref·Kdig·Rosc·Cosc) / (a·Rref·Cint)

[0086] Therefore, Kdig=(a·T·Rref·Cint) / (Vref·Rosc·Cosc)=kT.

[0087] Therefore, the UDC content Kdig is proportional to temperature, and the process and temperature variations of the internal resistors and capacitors are offset. Although the absolute values ​​of Rref and Rosc may vary with process and temperature, their ratio can be very accurate. The same is true for the ratio Cint / Cosc.

[0088] The speed of operation of the circuit 300, i.e. the time it takes for the circuit to stabilize, will depend on the difference between the sampled voltage and VPTAT. This is because the UDC contents are first converted with the down counter 314 within the integration time of Cint, and then the instantaneous voltage of Cint is sampled in Chold and compared with the PTAT voltage VPTAT. The comparator output responds with a U / D signal for UDC 313, which will then receive only one clock pulse to count up or down. Low values ​​of Kdig correspond to low integration times, so the circuit is faster for low Kdig values ​​than for high Kdig values. Therefore, preselecting an initial UDC value at startup can reduce the required stabilization time. A further optimization can be to use a different digital iteration routine, where Kdig starts with a larger step size.

[0089] In the above example, Kdig = 0 corresponds to a temperature of 0 K. Figure 4 In the simplified linear diagram shown, the temperature voltage Vtemp is used instead of Vptat to change the Kdig=0 value to a higher initial value of -40°C or 233K.

[0090] Here, the bandgap reference voltage Vref=Vbg (VPTAT+Vdiode) is used as a reference. Vtemp=k.Vbg-Vdiode, where k=0.62, which is selected so that for T=233°K (-40°C), Vtemp=0V, and for T=433°K (160°C), Vtemp=0.33.Vbg (0.4V in this assumption).

[0091] Using Vtemp instead of Vptat in the system yields Kdig=0 where T=-40°C, and dimensioning it in such a way that Kdig=127 (in this example, assuming a 7-bit counter, so 127 is full scale) corresponds to T=160°C.

[0092] The above is just an example to show that any temperature can be selected corresponding to the interval Kdig = 0 to Kdig = 2n-1, where n is the number of bits from the counter. In this example, the voltages are just hypothetical and are chosen to show the calculation method.

[0093] exist Figure 5 Another example temperature sensor circuit 500 is shown in FIG. 5 with an example reference current circuit 501. The reference current circuit 501 generates a PTAT current source from the same PMOS transistor, forcing current through two branches with different multiplication factors.

[0094] As mentioned above about Figure 2 and 3As described in the circuit, the temperature sensor circuit 500 includes a PTAT voltage circuit 501 and a reference current source 502a connected between the supply rail 213 and the node 212. The capacitor 503 is connected between the node and the common rail 209. The reset switch 504 is connected across the capacitor 503. The comparator 505 compares the voltage of the capacitor 503 with the PTAT voltage and provides a comparator output U / D. The counter circuit 506 increments the output word Kdig according to the comparator output and repeatedly performs a series of sequential steps, wherein the reset signal 207 is briefly provided to close the reset switch 504, discharge the capacitor 503, count the number of clock cycles corresponding to the output word when the reference current source 502a charges the capacitor 503, and increment or decrement the output word according to the comparator output.

[0095] The counter circuit 506 includes a UDC 513 having an input connected to receive the comparator output U / D and configured to provide an output word (Kdig). A down counter 514 is connected to receive the output word Kdig from the UDC 513. A clock signal generator 515 is configured to provide a clock signal RC clk to the down counter 514 and the UDC 513.

[0096] Reference current source 501 includes a first PMOS transistor 502a having a source connected to supply rail 213 and a drain connected to node 512. A second PMOS transistor 502b has a source connected to supply rail 213 and a gate connected to the gate of the first PMOS transistor 502a. An amplifier 520 has an output connected to the gates of the first PMOS transistor 502a and the second PMOS transistor 502b. A first input of the amplifier 520 is connected to the drain of the second PMOS transistor 502b, and a second input of the amplifier 520 is connected to the capacitor 503.

[0097] A first resistor R1 521 and a first diode 522 are connected in series between a first input of the amplifier 520 and the common rail 209. A second resistor R2 523 is connected between the first input of the amplifier 520 and the common rail 209. A third resistor 524 is connected between a second input of the amplifier 520 and the common rail 209. A second diode 525 is connected between a second input of the amplifier 520 and the common rail 209.

[0098] The third PMOS transistor 502c has a source connected to the supply rail 213 and a drain connected to the second input 511 of the comparator 505. A fourth resistor 526 is connected between the second input 511 of the comparator 505 and the common rail (209).

[0099] as Figure 3In the circuit 300 in FIG. 5 , a sampling switch 516 is connected between the node 512 and the first input 510 of the comparator 505. A sampling capacitor 517 is connected between the first input 310 of the comparator 505 and the common rail 209. The counter circuit 506 is configured to provide a sampling signal to close the sampling switch 516 after counting the number of clock cycles corresponding to the output word Kdig, thereby providing the voltage of the capacitor 503 to the first input 510 of the comparator 505.

[0100] as Figure 3 300, the counter circuit 506 includes UDC 513, down counter 514 and clock signal generator 515. The operation of the circuit 500 begins with the capacitor Cint 503 being fully discharged by the reset signal to the reset switch 504. Next, the down counter 514 is loaded with the transient contents of UDC 513, after which the down counter 514 begins to count down to zero. During this time, the capacitor Cint 503 is charged with the reference current IREF. When the contents of the down counter 514 reach zero, the sampling switch 516 is closed, and Cint 503 is connected to the sampling capacitor 517. Then, the cycle begins again (reset, count down and charge, sampling, etc.).

[0101] When the system is stable, the voltage at capacitor Chold is V(Chold)=Vd+Vtemp=Vd+Kdig.Tclk.IREF / Cint=IREF.R3 (in this example, it is 0.62.Vbg).

[0102] pass Figure 5 The reference current IREF of the middle PMOS transistor 502a in the circuit is passed through capacitor Cint 503 or through reset switch 504. When the circuit 500 has stabilized, closing the sampling switch 516 does not cause additional current to pass through the sampling switch 516 because the capacitor Chold 517 has already charged to the appropriate value. This means that all current from the middle PMOS transistor 502a passes through the 1x diode 524 and the resistor R2 523 at the same time, thereby ensuring the correct operation of the IREF current source.

[0103] When stable, UDC 513 switches between two subsequent values ​​(an upper and a lower value, which differ by one LSB). The upper or lower value is loaded in down counter 514, depending on the choice made by the designer.

[0104] The temperature sensor circuit 500 can be implemented in various ways. One common feature is that the time taken to charge the capacitor Cint 503 (which is expressed as the number of clock pulses) is proportional to the temperature dependent voltage. Therefore, the number of clock pulses is an indication of the actual temperature.

[0105] For low supply voltages, it may not be possible to use a PN (substrate) diode in the reference current generator, because the diode voltage drop may be too high for an amplifier with a PMOS input stage (the input voltage will be at Vdiode; when the amplifier input is the gate of a PMOS transistor, the source voltage of these transistors is Vdiode+VGS(PMOS), which may be too high when the total supply voltage is extremely low (e.g., 900mV)), and too low for an NMOS input stage (Vdiode-VGS(NMOS) will be too low to implement a tail current source). A solution to this is to implement the reference current generator with only MOS transistors. In this case, the input voltage to the amplifier can be a few hundred millivolts, and an amplifier with PMOS input transistors can be used. Figure 6 A possible implementation is shown by circuit 600 in FIG.

[0106] As in the other examples, the temperature sensor circuit 600 includes a PTAT voltage circuit 601 and a reference current source 602, i.e., transistor M7, connected between the supply rail 213 and the node 212. A capacitor 603 is connected between the node 612 and the common rail 209. A reset switch 604 is connected across the capacitor 603. A comparator 605 compares the voltage of the capacitor 603 with the PTAT voltage, which in this case is Vref, and provides a comparator output U / D to a counter circuit 606. The counter circuit 606 increments or decrements the output word Kdig in accordance with the comparator output U / D and performs the following sequential steps: providing a reset signal 207 to the reset switch to discharge the capacitor 603, counting the number of clock cycles corresponding to the output word while the reference current source 602 charges the capacitor 603, and incrementing or decrementing the output word Kdig in accordance with the comparator output.

[0107] The resistors R1 and R2 in the PTAT voltage circuit 601 may be chosen so that the PMOS current in the transistors M4-M7 is the (temperature independent) reference current. It is also possible to omit the left R1 resistor connected to the drain of transistor M1 (which has some practical advantages) and still have the reference current in the upper PMOS transistors M4-M7.

[0108] Circuit 600 is constructed so that if comparator input 610 is at a voltage where its output is midway between high and low (and its drain current is the same as that of transistor M7), then the voltage at the source of transistor M3 will be Vtemp (k.Vbg-Vgs) as previously described. Vtemp is then again selected so that the low and high temperatures corresponding to Kdig=0 and Kdig maximum are fixed.

[0109] After the reset pulse, capacitor C1 603 is discharged and the comparator input 610 is pulled low. After this, the down counter 614, which has been loaded with the UDC content Kdig, starts counting down to zero. During this time, capacitor C1 603 is charged with the drain current of transistor M7, which is a reference current set at an appropriate value (k.Iref / m, where k and m are multiplication factors of the PMOS transistors indicated in the figure). When the down counter content is zero, the UDC receives a clock pulse that will cause an up or down counting action depending on the comparator (inverter in this case) output. The loop is stable when C1 is charged to a voltage where the drain voltage of M3 starts to rise. In this case:

[0110] Vref=Iref.R3=V(C1)+Vgs(M3)=(Kdig.Tclk.Iref.k / m) / C1+Vgs(M3),

[0111] Where Vgs(M3) is the gate-to-source voltage when the drain current of M3 is k.Iref / m, and its drain voltage is half the supply voltage (the voltage at which the output of the comparator (inverter) changes state). Therefore, here, the designed temperature voltage Vtemp is:

[0112] Vtemp=Vref-Vgs(M3)=Iref.R3-Vgs(M3)

[0113] Therefore, the gate-to-source voltage of the MOS transistor is used instead of the diode voltage.

[0114] The reference voltage Vref can be selected so that at 0°C, Vref = Vgs(M3). This value may vary with the process angle. In the nominal process angle, at 0°C, Vtemp = 0V. There may be an offset between different process angles, but the gain is extremely constant, i.e., the ΔVgs / ΔT slopes are roughly parallel. Therefore, with a single-point calibration, the voltage Vtemp can be used for temperature measurement.

[0115] When Vref is adjusted for different process corners so that Vtemp is the same for each corner at 20°C, the deviation from the nominal curve is approximately -1.2% to +0.9% with a maximum T = 40°C, as shown in the following table

[0116]

[0117] Vtemp can be measured by comparing it to an internally generated reference voltage Vref. The ratio Vtemp / Vref is converted into a digital word Kdig. Then, for T=20°C, a single-point calibration can fix Kdig at 64, as summarized in the following table.

[0118] Kdig SS TT FF 0℃ 2.0 0.5 -0.3 40℃ 123.4 124.7 125.4

[0119] Therefore, measuring Vtemp relative to Vref is sufficient for the required temperature sensor.

[0120] To reduce the settling time, the UDC step size may be doubled when multiple consecutive up-count or down-count commands have occurred, for example three consecutive commands. With four consecutive up- or down-count commands, the UDC step size may be quadrupled.

[0121] As mentioned above, a single point calibration may be performed based on the ratio between the PTAT and REF quantities. Figure 7 A temperature sensor circuit 700 is shown, which is Figure 6 A simplified form of circuit 600 is shown in FIG. 7 . The component values ​​in circuit 700 are chosen so that 0° C. corresponds to Kdig=0 and 40° C. corresponds to Kdig=127. However, this only holds true in typical process corners. For other corners, the NMOS gate-source voltage may be different, resulting in significant offsets. To compensate for these offsets, a calibration mode can be defined: at a temperature of 20° C., UDC is fixed at “64” (the desired Kdig value at this temperature), and a 6-bit calibration up-down counter 721 adjusts the reference current source 702 until the loop is stable. During normal operation, the setting of the calibration UDC 721 is set to the result of the calibration mode. Figure 8 The calibration results for SS, TT and FF process corners are shown. For the SS process corner, the output word converges to 5V, for the TT process corner, it converges to 34V, and for the SS process corner, it converges to 57V.

[0122] exist Fig. 9 In the nominal simulation at 20° C. shown, the system first switches to calibration mode and then to normal operation. The lower result of the calibration mode CAL is transferred to the normal operation mode (lower switching value).

[0123] Fig.10 The curve in shows the UDC content for typical TT process corners when CAL is set to 34 and the temperature is stepped from 0°C to 40°C in 5°C steps. In this example, an ideal RC oscillator based on internal R and C is used.

[0124] Monte Carlo simulations show that if the system is fully calibrated at T = 20°C, the readings at T = 0°C or T = 40°C will deviate by 0.2° (1σ) or 0.6° (3σ) due to mismatch. A temperature sensor circuit based on the examples described herein can thus provide reasonable accuracy with a reduced IC area.

[0125] From reading this disclosure, other variations and modifications will be apparent to the skilled person. These variations and modifications may involve equivalent and other features which are already known in the art of IC temperature sensor circuits, and which may be used instead of or in addition to features already described herein.

[0126] Although the attached claims are directed to specific feature combinations, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel feature combination or any generalization thereof disclosed explicitly or implicitly herein, regardless of whether it relates to the same invention as the present invention claimed in any claim currently or whether it alleviates the same technical problems as any or all of the technical problems alleviated by the present invention.

[0127] Features described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features described in the context of a single embodiment for the sake of brevity may also be provided separately or in any suitable subcombination. Applicants hereby give notice that new claims may be formulated to such features and / or combinations of such features during the prosecution of this application or of any further application derived therefrom.

[0128] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" does not exclude a plurality, a single processor or other unit may fulfil the functions of several components recited in the claims, and the reference signs in the claims should not be construed as limiting the scope of the claims.

Claims

1. A temperature sensor circuit (200, 300, 500, 600), It is characterized in that include: A proportional to absolute temperature PTAT voltage circuit (201, 301, 501, 601) configured to provide a PTAT voltage (VPTAT); a reference current source (202, 302, 502a, 602) connected between the supply rail (213) and the node (212); a capacitor (203, 303, 503, 603) connected between the node (212, 312, 512, 612) and a common rail (209); a reset switch (204, 304, 504, 604) connected across the capacitor (203, 303, 503, 603); a comparator (205, 305, 505, 605) configured to compare the voltage of the capacitor (203, 303, 503, 603) with the PTAT voltage (VPTAT) and provide a comparator output (U / D); A counter circuit (206, 306, 506, 606) is configured to increment or decrement an output word (Kdig) according to the comparator output (U / D), the counter circuit (206, 306, 506, 606) being configured to repeatedly perform the following sequential steps: i) providing a reset signal (207) to temporarily close the reset switch (204, 304, 504, 604) to discharge the capacitor (203, 303, 503, 603); ii) counting the number of clock cycles corresponding to the output word (Kdig) while the reference current source (202, 302, 502a, 602) charges the capacitor (203, 303, 503, 603); as well as iii) increasing or decreasing the output word (Kdig) according to the comparator output (U / D), Wherein after repeating the sequential steps, the output word (Kdig) converges to a value corresponding to the temperature of the PTAT voltage circuit (201, 301, 501, 601).

2. The temperature sensor circuit (200, 300, 500) according to claim 1, Features: A first input (210, 310, 510) of the comparator (205, 305, 505) is connected to the node (212, 312, 512); and A second input (211, 311, 511) of the comparator (205, 305, 505) is connected to receive the PTAT voltage (VPTAT) from the PTAT voltage circuit (201, 301, 501).

3. The temperature sensor circuit (300, 500, 600) according to claim 2, It is characterized in that The counter circuit (306, 506, 606) comprises: an up-down counter UDC (313, 513, 613) having an input connected to receive said comparator output (U / D) and configured to provide said output word (Kdig); a down counter (314, 514, 614) connected to receive the output word (Kdig) from the UDC (313, 513, 613); and A clock signal generator (315, 515, 615) is configured to provide a clock signal (RC clk) to the down counter (314, 514, 614) and the UDC (313, 513, 613).

4. The temperature sensor circuit (300, 500) according to claim 3, It is characterized in that include: a sampling switch (316, 516) connected between the node (312, 512) and the first input (310, 510) of the comparator (305, 505); a sampling capacitor (317, 517) connected between the first input (310, 510) of the comparator (305, 505) and the common rail (209), The counter circuit (306, 506) is configured to provide a sampling signal after step ii) to close the sampling switch (316, 516), thereby providing the voltage of the capacitor (303, 503) to the first input (310, 510) of the comparator (305, 505).

5. The temperature sensor circuit (500) according to claim 4, It is characterized in that The reference current source (501) comprises a first PMOS transistor (502a) having a source connected to the supply rail (213) and a drain connected to the node (512).

6. The temperature sensor circuit (500) according to claim 5, It is characterized in that A second PMOS transistor (502b) is included having a source connected to the supply rail and a gate connected to the gate of the first PMOS transistor (502a).

7. The temperature sensor circuit (500) according to claim 6, It is characterized in that An amplifier (520) is included, the amplifier (520) having outputs connected to the gates of the first PMOS transistor (502a) and the second PMOS transistor (502b), a first input of the amplifier (520) connected to the drain of the second PMOS transistor (502b), and a second input of the amplifier (520) connected to the capacitor (503).

8. The temperature sensor circuit (500) according to claim 7, It is characterized in that include: a first resistor (521) and a first diode (522) connected in series between the first input of the amplifier (520) and the common rail (209); a second resistor (523) connected between the first input of the amplifier (520) and the common rail (209); a third resistor (524) connected between the second input of the amplifier (520) and the common rail (209); as well as A second diode (525) is connected between the second input of the amplifier (520) and the common rail (209).

9. The temperature sensor circuit (500) according to claim 8, It is characterized in that include: a third PMOS transistor (502c) having a source connected to the supply rail (213) and a drain connected to the second input (511) of the comparator (505); as well as A fourth resistor (526) is connected between the first input (511) of the comparator (505) and the common rail (209).

10. A method of operating a temperature sensor circuit (200, 300, 500, 600) according to claim 1, It is characterized in that The method comprises: i) providing the reset signal (207) to temporarily close the reset switch (204, 304, 504, 604) to discharge the capacitor (203, 303, 503, 603); ii) counting the number of clock cycles corresponding to the output word (Kdig) while the reference current source (202, 302, 502a, 602) charges the capacitor (203, 303, 503, 603); iii) increasing or decreasing the output word (Kdig) according to the comparator output (U / D); and iv) repeating steps i) to iii) so that the output word (Kdig) converges to a value corresponding to the temperature of the PTAT voltage circuit (201, 301, 501, 601).

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