Capacitance measuring method and capacitance measuring circuit

Abstract

The invention relates to the technical field of capacitance measurement, in particular to a capacitance measurement method and a capacitance measurement circuit. The capacitance measuring method comprises the steps of connecting a first end of a to-be-measured capacitor to a low level, connecting a second end of the to-be-measured capacitor to a high level for charging, discharging the second end of the to-be-measured capacitor and obtaining corresponding charging time, connecting the second end of the to-be-measured capacitor to the low level, connecting the first end of the to-be-measured capacitor to the high level for charging, and obtaining corresponding charging time. Discharging the first end of the capacitor to be detected and obtaining the corresponding charging time, suspending one end of the capacitor to be detected after discharging, connecting the other end of the capacitor to be detected with a high level and completing charging, discharging the end of the capacitor to be detected connected with the high level and obtaining the corresponding third discharging time, the capacitance value of the to-be-measured capacitor can be obtained by calculating the difference value of each discharge capacitance based on the relationship between the capacitance and the discharge time and performing simultaneous calculation, so that the influence of the parasitic capacitance is completely eliminated, and the capacitance measurement method is simple and can achieve the purpose of thoroughly eliminating the influence of the parasitic capacitance.

Description

Technical Field

[0001] The present invention relates to the technical field of capacitance measurement, and in particular to a capacitance measurement method and a capacitance measurement circuit. Background Art

[0002] With the rapid development of science and technology, capacitive sensors are widely used in humidity, displacement, angle, vibration, speed, pressure measurement and other fields. The capacitance values ​​of these sensors are generally small, usually in the pf (picofarad) level. However, in actual applications, the capacitance of capacitive sensors does not exist alone, but also has parasitic capacitance, such as Figure 1 As shown, the existing parasitic capacitance will affect the detection accuracy, sensitivity, resolution and measurement range of the capacitance of the capacitive sensor.

[0003] In order to eliminate the problem of parasitic capacitance, one method is to eliminate the influence of conventional parasitic capacitance by zero-point calibration, but this method of zero-point calibration increases the complexity of the production process, and in the actual application of products, not all products can be implemented; another method is to reduce the influence of parasitic capacitance by using a dual-port measurement method. This method can simultaneously consider the input port and output port of the capacitive sensor during the measurement process, reducing the influence of parasitic parameters on the measurement results, but this method requires a low-impedance voltage source and a high-gain operational amplifier, increases switch timing control, and the circuit is complex, and it cannot completely eliminate the influence of parasitic capacitance. Therefore, providing an effective circuit for eliminating parasitic capacitance is still a key problem that needs to be solved in the field of capacitance measurement technology. Summary of the invention

[0004] The present invention provides a capacitance measurement method and a capacitance measurement circuit to eliminate the influence of parasitic capacitance.

[0005] To achieve the above object, the present invention provides a capacitance measurement method, comprising:

[0006] Providing a capacitor to be measured, wherein two ends of the capacitor to be measured are equivalently connected to a first parasitic capacitor and a second parasitic capacitor;

[0007] The first terminal of the capacitor to be measured is connected to a low level, the second terminal of the capacitor to be measured is connected to a high level and charging is completed, the second terminal of the capacitor to be measured is discharged through the second terminal of the discharge unit until a low level is output, a corresponding first discharge time is obtained, and a first discharge capacitance difference is calculated based on the relationship between the capacitance and the discharge time, where the first discharge capacitance difference is the sum of the capacitance value of the capacitor to be measured and the capacitance value of the second parasitic capacitance;

[0008] The second terminal of the capacitor to be measured is connected to a low level, the first terminal of the capacitor to be measured is connected to a high level and charging is completed, the first terminal of the capacitor to be measured is discharged through the first terminal of the discharge unit until a low level is output, a corresponding second discharge time is obtained, and a second discharge capacitance difference is calculated based on the relationship between the capacitance and the discharge time, where the second discharge capacitance difference is the sum of the capacitance value of the capacitor to be measured and the capacitance value of the first parasitic capacitance;

[0009] One end of the capacitor to be tested after discharge is suspended, the other end of the capacitor to be tested is connected to a high level and charging is completed, the end of the capacitor to be tested connected to the high level is discharged through the corresponding discharge unit until the end of the capacitor to be tested that is discharged outputs a low level, a corresponding third discharge time is obtained, and a third discharge capacitance difference is calculated based on the relationship between capacitance and discharge time, where the third discharge capacitance difference is the sum of the capacitance value obtained by connecting the first parasitic capacitance and the capacitor to be tested in series and the capacitance value of the second parasitic capacitance, or the sum of the capacitance value obtained by connecting the second parasitic capacitance and the capacitor to be tested in series and the capacitance value of the first parasitic capacitance;

[0010] Based on the first discharge capacitance difference value to the third discharge capacitance difference value and the first discharge time value to the third discharge time value, a capacitance value of the capacitor to be measured is obtained by calculation.

[0011] The present invention further provides a capacitance measurement circuit, which uses the above capacitance measurement method, including:

[0012] A discharge unit, a first charging unit, a second charging unit, and a timing unit;

[0013] The first end of the discharge unit is connected to the first end of the first charging unit and the first input end of the timing unit and is used as the first end of the capacitance measurement circuit to connect the first end of the capacitance to be measured, and the second end of the discharge unit is connected to the first end of the second charging unit and the second input end of the timing unit and is used as the second end of the capacitance measurement circuit to connect the second end of the capacitance to be measured, wherein the two ends of the capacitance to be measured are equivalently connected to the first parasitic capacitance and the second parasitic capacitance;

[0014] The first charging unit is set to be cut off, the first end of the capacitor to be measured is connected to a low level, the capacitor to be measured is charged by the second charging unit, and the second end of the capacitor to be measured is discharged through the second end of the discharge unit until a low level is output to the timing unit, the timing unit obtains a corresponding first discharge time, and calculates a first discharge capacitance difference based on a relationship between capacitance and discharge time, wherein the first discharge capacitance difference is the sum of the capacitance value of the capacitor to be measured and the capacitance value of the second parasitic capacitance;

[0015] The second charging unit is set to be cut off, the second end of the capacitor to be measured is connected to a low level, the capacitor to be measured is charged by the first charging unit, the first end of the capacitor to be measured is discharged through the first end of the discharge unit, until a low level is output to the timing unit, the timing unit obtains a corresponding second discharge time, and a second discharge capacitance difference is calculated based on a relationship between capacitance and discharge time, the second discharge capacitance difference is the sum of the capacitance value of the capacitor to be measured and the capacitance value of the first parasitic capacitance;

[0016] The first charging unit is set to be cut off, the first end of the capacitor to be tested after discharge is suspended, and the second end of the capacitor to be tested is discharged through the second charging unit until the second end of the capacitor to be tested outputs a low level to the timing unit, and the timing unit obtains the corresponding third discharge time, and calculates the third discharge capacitance difference based on the relationship between capacitance and discharge time, and the third discharge capacitance difference is the sum of the capacitance value obtained by connecting the first parasitic capacitance and the capacitor to be tested in series and the capacitance value of the second parasitic capacitance; or the second charging unit is set to be cut off, the second end of the capacitor to be tested after discharge is suspended, and the first end of the capacitor to be tested is discharged through the first charging unit until the first end of the capacitor to be tested outputs a low level to the timing unit, and the timing unit obtains the corresponding third discharge time, and calculates the third discharge capacitance difference based on the relationship between capacitance and discharge time, and the third discharge capacitance difference is the sum of the capacitance value obtained by connecting the second parasitic capacitance and the capacitor to be tested in series and the capacitance value of the first parasitic capacitance;

[0017] Based on the first discharge capacitance difference value to the third discharge capacitance difference value and the first discharge time value to the third discharge time value, a capacitance value of the capacitor to be measured is obtained by calculation.

[0018] In summary, the advantages and beneficial effects of the present invention are:

[0019] The present invention provides a capacitance measurement method and a capacitance measurement circuit. The capacitance measurement method includes: providing a capacitance to be measured, wherein two ends of the capacitance to be measured are equivalently connected with a first parasitic capacitance and a second parasitic capacitance, charging the capacitance to be measured first and then discharging it, and timing the discharge process to obtain a corresponding discharge time, calculating and obtaining a corresponding capacitance value as a corresponding discharge capacitance difference based on the relationship between the capacitance and the discharge time, charging and discharging the capacitance to be measured multiple times, obtaining a corresponding discharge capacitance difference each time, and performing a joint calculation on the corresponding discharge capacitance difference obtained each time to obtain the capacitance value of the capacitance to be measured, thereby completely eliminating the influence of the parasitic capacitance. The capacitance measurement method is simple, and can achieve the purpose of completely eliminating the influence of the parasitic capacitance, and is convenient for production and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Shown is an equivalent schematic diagram of the capacitor to be measured;

[0021] Figure 2 FIG. 1 is a flow chart of a capacitance measurement method provided by an embodiment of the present invention;

[0022] Figure 3 to Figure 9 FIG. 1 is a schematic diagram of a capacitance measurement circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in combination with the specific implementation methods of the present invention and the corresponding drawings. Obviously, the described implementation methods are only part of the implementation methods of the present invention, not all implementation methods. Based on the implementation methods of the present invention, all other implementation methods obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0024] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0025] The present invention provides a capacitance measurement method, such as Figure 2 As shown, including:

[0026] Step S10, providing a capacitor to be measured, wherein two ends of the capacitor to be measured are equivalently connected to a first parasitic capacitor and a second parasitic capacitor;

[0027] Step S20, connecting the first terminal of the capacitor to be measured to a low level, connecting the second terminal of the capacitor to be measured to a high level and completing charging, discharging the second terminal of the capacitor to be measured through the second terminal of the discharge unit until a low level is output, obtaining a corresponding first discharge time, and calculating a first discharge capacitance difference based on a relationship between capacitance and discharge time, wherein the first discharge capacitance difference is the sum of the capacitance value of the capacitor to be measured and the capacitance value of the second parasitic capacitance;

[0028] Step S30, connecting the second terminal of the capacitor to be measured to a low level, connecting the first terminal of the capacitor to be measured to a high level and completing charging, discharging the first terminal of the capacitor to be measured through the first terminal of the discharge unit until a low level is output, obtaining a corresponding second discharge time, and calculating a second discharge capacitance difference based on a relationship between capacitance and discharge time, wherein the second discharge capacitance difference is the sum of the capacitance value of the capacitor to be measured and the capacitance value of the first parasitic capacitance;

[0029] Step S40, the first end of the capacitor to be tested is suspended after discharge, the second end of the capacitor to be tested is connected to a high level and charging is completed, the second end of the capacitor to be tested is discharged through the second end of the discharge unit until the second end of the capacitor to be tested outputs a low level, and a corresponding third discharge time is obtained, and a third discharge capacitance difference is calculated based on the relationship between the capacitance and the discharge time, and the third discharge capacitance difference is the sum of the capacitance value obtained by connecting the first parasitic capacitance and the capacitor to be tested in series and the capacitance value of the second parasitic capacitance;

[0030] Step S50, obtaining the capacitance value of the capacitor to be measured by calculation based on the first discharge capacitance difference value to the third discharge capacitance difference value and the first discharge time to the third discharge time.

[0031] Specifically, step S10 is performed to provide a capacitor to be measured Cx, wherein two ends of the capacitor to be measured Cx are equivalently connected to a first parasitic capacitor C P1 And a first parasitic capacitor CP1.

[0032] In practical applications, the measured capacitance Cx does not exist alone. For example, chip packaging and PCB leads will generate parasitic capacitance. Parasitic capacitance varies randomly in many applications, seriously affecting the measurement accuracy of capacitive sensors. Therefore, the influence of parasitic capacitance needs to be eliminated.

[0033] Step S20 is executed, the first end P10 of the capacitor to be measured Cx is connected to a low level, the second end P11 of the capacitor to be measured Cx is connected to a high level and charging is completed, the second end P11 of the capacitor to be measured Cx is discharged through the second end of the discharge unit until a low level is output, and the corresponding first discharge time T1 is obtained, and a first discharge capacitance difference Cx1 is calculated based on the relationship between capacitance and discharge time, and the first discharge capacitance difference Cx1 is the capacitance value of the capacitor to be measured Cx and the second parasitic capacitance C P2 The sum of the capacitance values.

[0034] In the embodiment of the present invention, the first discharge time T1 corresponds to the first discharge of the measured capacitor Cx, which is recorded as the first discharge of the measured capacitor Cx, and the charging of the measured capacitor Cx before the first discharge is recorded as the first charging of the measured capacitor Cx.

[0035] In the embodiment of the present invention, the first discharge capacitance difference Cx1 is: Cx1=K2*T1...(1),

[0036] in, Cx1=Cx+C p2 , Cx1 is the first discharge capacitance difference Cx1, Cx is the capacitance value of the capacitor to be measured, C p2is the capacitance value of the second parasitic capacitor, T1 is the first discharge time T1, Vtl2 is the discharge voltage value of the low level output by the second end P11 of the capacitor to be measured Cx, R2 is the resistance value of the discharge unit corresponding to the first discharge time T1, and VH1 is the equivalent level value before the first discharge.

[0037] In the embodiment of the present invention, the equivalent level value VH1 of the capacitor to be measured before the first discharge is a voltage value corresponding to the first charge of the capacitor to be measured Cx.

[0038] Step S30 is executed to connect the second terminal P11 of the capacitor to be measured Cx to a low level, connect the first terminal P10 of the capacitor to be measured Cx to a high level and complete charging, the first terminal P10 of the capacitor to be measured Cx is discharged through the first terminal of the discharge unit 20 until a low level is output, and the corresponding second discharge time T2 is obtained, and a second discharge capacitance difference Cx2 is obtained based on the relationship between capacitance and discharge time, and the second discharge capacitance difference Cx2 is the capacitance value of the capacitor to be measured Cx and the first parasitic capacitance C P1 The sum of the capacitance values.

[0039] In the embodiment of the present invention, the second discharge time T2 corresponds to the second discharge of the measured capacitor Cx, which is recorded as the second discharge of the measured capacitor Cx, and the charging of the measured capacitor Cx after the first discharge is recorded as the second charging of the measured capacitor Cx.

[0040] In the embodiment of the present invention, the second discharge capacitance difference Cx2 is: Cx2=K1*T2, ... (2)

[0041] in, Cx2=Cx+C p1 , Cx2 is the second discharge capacitance difference Cx2, Cx is the capacitance value of the capacitor to be measured, C p1 is the capacitance value of the first parasitic capacitor, T2 is the second discharge time T2, Vtl1 is the discharge voltage value of the low level output by the first end P10 of the capacitor to be measured Cx, R1 is the resistance value of the discharge unit corresponding to the second discharge time T2, and VH2 is the equivalent level value before the second discharge.

[0042] In the embodiment of the present invention, the equivalent level value VH2 of the capacitor to be measured before the second discharge is a voltage value corresponding to the second charge of the capacitor to be measured Cx.

[0043] Step S40 is executed to suspend the first terminal P10 of the capacitor to be measured Cx after discharge, connect the second terminal P11 of the capacitor to be measured Cx to a high level and complete charging, and discharge the second terminal P11 of the capacitor to be measured Cx through the corresponding second terminal of the discharge unit until the second terminal P11 of the capacitor to be measured Cx outputs a low level, obtain the corresponding third discharge time T3, and calculate the third discharge capacitance difference Cx3 based on the relationship between the capacitance and the discharge time. The third discharge capacitance difference Cx3 is the first parasitic capacitance C P1 , the capacitance value obtained by connecting the capacitor to be measured Cx in series and the second parasitic capacitor C P2 The sum of the capacitance values.

[0044] In the embodiment of the present invention, the third discharge time T3 corresponds to the third discharge of the capacitor to be measured Cx, which is recorded as the third discharge of the capacitor to be measured Cx, and the charging of the capacitor to be measured Cx after the second discharge is recorded as the third charging of the capacitor to be measured Cx.

[0045] In the embodiment of the present invention, the third discharge capacitance difference Cx3 is: Cx3 = Cs1 + C p2 =K2*T3, ……(3), where Cx3 is the third discharge capacitance difference Cx3, Cx is the capacitance value of the capacitor to be tested, C p1 is the capacitance value of the first parasitic capacitor, C p2 is the capacitance value of the second parasitic capacitor, T3 is the third discharge time T3, Cs1 is the first parasitic capacitor C P1 , the capacitance value obtained after the capacitors to be measured Cx are connected in series.

[0046] In other embodiments, the second end P11 of the capacitor to be measured Cx after discharge is connected to the air, the first end P10 of the capacitor to be measured Cx is connected to a high level and charging is completed, the second end P11 of the capacitor to be measured Cx is suspended, and the first end P10 of the capacitor to be measured Cx is discharged through the first end of the corresponding discharge unit until the first end P10 of the capacitor to be measured Cx outputs a low level, and the corresponding third discharge time T3 is obtained. The third discharge capacitance difference Cx3 is calculated based on the relationship between the capacitance and the discharge time. The third discharge capacitance difference Cx3 is the second parasitic capacitance C P2 , the capacitance value obtained by connecting the capacitor to be measured Cx in series and the first parasitic capacitor C P1 The sum of the capacitance values.

[0047] Step S50 is executed to calculate and obtain the capacitance value of the capacitor to be measured Cx based on the first discharge capacitance difference Cx1 to the third discharge capacitance difference Cx3 and the first discharge time T1 to the third discharge time T3.

[0048] In the embodiment of the present invention, the capacitance value of the capacitor Cx to be measured is obtained by calculation according to formula (1) to formula (3) and the first discharge time T1 to the third discharge time T3:

[0049]

[0050] In the embodiment of the present invention, the operating voltage of the discharge unit corresponding to the first discharge time T1 is equal to the operating voltage of the discharge unit corresponding to the second discharge time T2.

[0051] In other embodiments, the operating voltage of the discharge unit corresponding to the first discharge time T1 is not equal to the operating voltage of the discharge unit corresponding to the second discharge time T2.

[0052] In an embodiment of the present invention, the equivalent level value VH1 before the first discharge of the capacitor to be measured Cx is equal to the equivalent level value VH2 before the second discharge of the capacitor to be measured Cx, and the low-level discharge voltage value Vtl1 output by the first end P10 of the capacitor to be measured Cx is equal to the low-level discharge voltage value Vtl2 output by the second end P11 of the capacitor to be measured Cx.

[0053] In other embodiments, the equivalent level value VH1 before the first discharge of the capacitor to be measured Cx and the equivalent level value VH2 before the second discharge of the capacitor to be measured Cx are not equal, and the low-level discharge voltage value Vtl1 output by the first end P10 of the capacitor to be measured Cx and the low-level discharge voltage value Vtl2 output by the second end P11 of the capacitor to be measured Cx are not equal.

[0054] From equation (4), we can know that: P1 The second parasitic capacitance C P2 The measured result of the capacitance Cx to be measured is only related to the first discharge time T1 to the third discharge time T3 and the constant terms K1 to K2, thereby eliminating the first parasitic capacitance C P1 The second parasitic capacitance C p2 For the purpose of, the constant terms K1~K2 are related to the size of the resistance R1 of the discharge unit corresponding to the first discharge time T1, the size of the resistance R2 of the discharge unit corresponding to the second discharge time T2, the discharge voltage value Vtl1 of the low level output by the first end P10 of the capacitor Cx to be measured, the discharge voltage value Vtl2 of the low level output by the second end P11 of the capacitor Cx to be measured, the equivalent value VH1 of the capacitor Cx to be measured before the first discharge, and the equivalent level value VH2 of the capacitor Cx to be measured before the second discharge and are known quantities.

[0055] In other embodiments, the order of step 2, step 3, and step 4 in the capacitance measurement method is adjustable.

[0056] In the embodiment of the present invention, the capacitor to be measured Cx is a capacitive sensor.

[0057] In other embodiments, the capacitor Cx to be measured is a micro sensor, a micro actuator or other suitable power devices.

[0058] In practical applications, the two ends of the capacitor Cx to be measured are equivalently connected to a first parasitic capacitor C p1 and the second parasitic capacitance C P2 , the first parasitic capacitance C P1 and the second parasitic capacitance C P2 The measurement accuracy of the capacitive sensor is seriously affected, so it is necessary to eliminate the influence of parasitic capacitance on the measurement accuracy. The capacitance to be measured Cx is charged and then discharged, and the discharge is timed to obtain the corresponding discharge time. The corresponding capacitance value is calculated based on the relationship between the capacitance and the discharge time as the corresponding discharge capacitance difference. The capacitance to be measured Cx is charged and discharged multiple times to obtain the corresponding discharge capacitance difference each time. The capacitance value of the capacitance to be measured Cx can be obtained by performing a joint calculation on the corresponding discharge capacitance difference obtained, thereby completely eliminating the influence of the parasitic capacitance. The capacitance measurement method is simple and can achieve the purpose of completely eliminating the influence of the parasitic capacitance. It is convenient for production application and has universal applicability.

[0059] The embodiment of the present invention further provides a capacitance measurement circuit, which applies the above capacitance measurement method, such as Figure 3 As shown, including:

[0060] A discharge unit 20, a first charging unit 30, a second charging unit 40, and a timing unit 50;

[0061] The first end of the discharge unit 20 is connected to the first end of the first charging unit 30 and the first input end P10IN of the timing unit 50 and is used as the first end of the capacitance measurement circuit to connect the first end P10 of the capacitance to be measured Cx. The second end of the discharge unit 20 is connected to the first end of the second charging unit 40 and the second input end P11IN of the timing unit 50 and is used as the second end of the capacitance measurement circuit to connect the second end P11 of the capacitance to be measured Cx. The two ends of the capacitance to be measured Cx are equivalently connected to the first parasitic capacitance C P1 and the second parasitic capacitance C P2 ;

[0062] The first charging unit 30 is set to be turned off, the first terminal P10 of the capacitor to be measured Cx is connected to a low level, the capacitor to be measured Cx is charged by the second charging unit 40, and the second terminal P11 of the capacitor to be measured Cx is discharged through the second terminal of the discharge unit 20 until a low level is output to the timing unit 50, the timing unit 50 obtains the corresponding first discharge time T1, and calculates a first discharge capacitance difference Cx1 based on the relationship between capacitance and discharge time, the first discharge capacitance difference Cx1 being the capacitance value of the capacitor to be measured Cx and the second parasitic capacitance C P2 The sum of the capacitance values;

[0063] The second charging unit 40 is set to be turned off, the second terminal P11 of the capacitor to be measured Cx is connected to a low level, the capacitor to be measured Cx is charged by the first charging unit 30, and the first terminal P10 of the capacitor to be measured Cx is charged by the first terminal of the discharge unit 20 until a low level is output to the timing unit 50, the timing unit 50 obtains the corresponding second discharge time T2, and calculates a second discharge capacitance difference Cx2 based on the relationship between capacitance and discharge time, the second discharge capacitance difference Cx2 is the capacitance value of the capacitor to be measured Cx and the first parasitic capacitance C P1 The sum of the capacitance values;

[0064] The first charging unit 30 is set to be turned off, the first terminal P10 of the capacitor to be measured Cx after discharge is suspended, the capacitor to be measured Cx is charged by the second charging unit 40, and the capacitor to be measured Cx is discharged by the discharge unit 20, until the second terminal P11 of the capacitor to be measured Cx outputs a low level to the timing unit 50, and the timing unit 50 obtains the corresponding third discharge time T3, and calculates and obtains a third discharge capacitance difference Cx3 based on the relationship between the capacitance and the discharge time, and the third discharge capacitance difference Cx3 is the first parasitic capacitance C P1 , the capacitance value obtained by connecting the capacitor to be measured Cx in series and the second parasitic capacitor C P2 The sum of the capacitance values;

[0065] Based on the first discharge capacitance difference Cx1 to the third discharge capacitance difference Cx3 and the first discharge time T1 to the third discharge time T3, the capacitance value of the capacitor to be measured Cx is obtained by calculation.

[0066] In the embodiment of the present invention, the first charging unit 30 and the second charging unit 40 are used to charge the capacitor Cx to be measured and cooperate with the discharge unit 20 to discharge the capacitor Cx to be measured. At the same time, the timing unit 50 is used to time the discharge process. The capacitor Cx to be measured is charged and discharged multiple times by the capacitance measurement circuit to obtain the corresponding first discharge time T1 to the third discharge time T3. The corresponding capacitance value is calculated based on the relationship between the capacitance and the discharge time as the corresponding discharge capacitance difference, that is, the first discharge capacitance difference Cx1 to the third discharge capacitance difference Cx3. The first discharge capacitance difference Cx1 to the third discharge capacitance difference Cx3 are calculated jointly to obtain the capacitance value of the capacitor Cx to be measured, thereby completely eliminating the influence of the parasitic capacitance.

[0067] In the embodiment of the present invention, Figure 4 As shown, the discharge unit 20 includes a first discharge structure 201 and a second discharge structure 202; the first discharge structure 201 includes a first resistor R1 and a first switch K1, the first resistor R1 and the first switch K1 are connected in series to form a first series structure, one end of the first series structure serves as one end of the first discharge structure 201, and the other end of the first series structure serves as the other end of the first discharge structure 201, one end of the first discharge structure 201 is connected to the first end of the first charging unit 30, the first input end P10IN of the timing unit 50, and the first end P10 of the capacitor Cx to be measured, The other end of the first discharge structure 201 is grounded; the second discharge structure 202 includes a second resistor R2 and a second switch K2, the second resistor R2 and the second switch K2 are connected in series to form a second series structure, one end of the second series structure serves as one end of the second discharge structure 202, the other end of the second series structure serves as the other end of the second discharge structure 202, one end of the second discharge structure 202 is connected to the first end of the second charging unit 40, the second input end P11IN of the timing unit 50, and the second end P11 of the capacitor to be measured Cx, and the other end of the second discharge structure 202 is grounded;

[0068] When the first charging unit 30 is turned off and the second charging unit 40 is turned off, the first switch K1 in the first discharge structure 201 is closed and the second switch K2 in the second discharge structure 202 is opened, the first end P10 of the capacitor Cx to be measured is discharged through the first discharge structure; when the first charging unit 30 is turned off and the second charging unit 40 is turned off, the first switch K1 in the first discharge structure 201 is opened and the second switch K2 in the second discharge structure 201 is closed, the second end P11 of the capacitor Cx to be measured is discharged through the second discharge structure.

[0069] In other embodiments, the other end of the first discharging structure and the other end of the second charging structure are both connected to a low level.

[0070] In other embodiments, the low levels connected to the other end of the first discharge structure and the other end of the second charge structure are equal or unequal.

[0071] In the embodiment of the present invention, the first discharge structure 201 and the second discharge structure 202 are the same.

[0072] In other embodiments, Figure 5 As shown, the discharge unit 20 includes a third discharge substructure 203, a third switch K3 and a fourth switch K4, one end of the third discharge substructure 203 is connected to one end of the third switch K3 and one end of the fourth switch K4, the other end of the third switch K3 serves as the first end of the discharge unit 20, and is connected to the first end of the first charging unit 30, the first input end P10IN of the timing unit 50, and the first end P10 of the capacitor to be measured Cx, and the other end of the fourth switch K4 serves as the second end of the discharge unit 20, and is connected to the first end of the second charging unit 40, the second input end P11IN of the timing unit 50, and the second end P11 of the capacitor to be measured Cx;

[0073] When the first charging unit 30 is turned off, the second charging unit 40 is turned off, the third switch K3 is closed, and the fourth switch K4 is opened, the first end P10 of the capacitor Cx to be measured is discharged through the third discharge substructure 203; when the first charging unit 30 is turned off, the second charging unit 40 is turned off, the third switch K3 is opened, and the fourth switch K4 is closed, the second end P11 of the capacitor Cx to be measured is discharged through the third discharge substructure 203.

[0074] In the embodiment of the present invention, Figure 6 As shown, the first charging unit 30 includes a first tri-state gate, the output end of the first tri-state gate is connected to the first end of the discharge unit 20, the first end P10 of the capacitor Cx to be measured, and the first input end P10IN of the timing unit 50, the output end of the first tri-state gate serves as the first end of the first charging unit 30, the enable end of the first tri-state gate is used to receive an enable signal, and the input end of the first tri-state gate is used to input a control signal;

[0075] The second charging unit 40 includes a second three-state gate, the output end of the second three-state gate is connected to the second end of the discharge unit 20, the second end P11 of the capacitor to be measured Cx, and the second input end P11IN of the timing unit 50, the output end of the second three-state gate serves as the first end of the second charging unit 40, the enable end of the second three-state gate is used to receive an enable signal, and the input end of the second three-state gate is used to input a control signal.

[0076] In the embodiment of the present invention, the enable terminal P10OUTEN of the first tri-state gate 301 is used to receive an enable signal. When the enable signal P10OUTEN of the enable terminal P10OUTEN of the first tri-state gate 301 is 0, the first tri-state gate 301 outputs a high impedance state, and the first tri-state gate 301 is in a cut-off state; when the enable signal P10OUTEN of the enable terminal P10OUTEN of the first tri-state gate 301 is 1, the first tri-state gate 301 is in a conducting state, and the first tri-state gate 301 is The input signal of the input terminal P10OUT is the output signal of the output terminal of the first tri-state gate 301, that is, when the enable signal P10OUTEN received by the enable terminal P10OUTEN of the first tri-state gate 301 is 1, and the input signal P10OUT of the input terminal P10OUT of the first tri-state gate 301 is 1, the output terminal OUT1 of the first tri-state gate 301 outputs a high level, so that the first terminal P10 of the capacitor Cx to be measured connected to the output terminal OUT1 of the first tri-state gate 301 is a high level;

[0077] The enable terminal P11OUTEN of the second three-state gate 401 is used to receive an enable signal. When the enable signal P11OUTEN of the enable terminal P11OUTEN of the second three-state gate 401 is 0, the second three-state gate 401 outputs a high impedance state, and the second three-state gate 401 is in a cut-off state; when the enable signal P11OUTEN of the enable terminal P11OUTEN of the second three-state gate 401 is 1, the second three-state gate 401 is in a conducting state, and the input signal of the input terminal P11OUT of the second three-state gate 401 is That is, it is the output signal of the output end of the second three-state gate 401, that is: when the enable signal P11OUTEN received by the enable end P11OUTEN of the second three-state gate 401 is 1, and the input signal P11OUT of the input end P11OUT of the second three-state gate 401 is 1, the output end OUT2 of the second three-state gate 401 outputs a high level, so that the second end P11 of the capacitor to be measured Cx connected to the output end OUT2 of the second three-state gate 401 is a high level, wherein the signal 1 is a high level and the signal 0 is a low level.

[0078] In the embodiment of the present invention, Figure 6As shown, when the first charging unit 30 is the first three-state gate 301 and the second charging unit 40 is the second three-state gate 401:

[0079] The enable end of the first three-state gate 301 is set to control the first three-state gate 301 to be in the off state, the first end P10 of the capacitor Cx to be measured is grounded, and the second three-state gate 401 is used to discharge the capacitor Cx to be measured; the enable end of the first three-state gate 301 and the enable end of the second three-state gate are set to control the first three-state gate and the second three-state gate to be in the off state, the first end P10 of the capacitor Cx to be measured is grounded, and the second end P11 of the capacitor Cx to be measured is discharged through the second discharge structure 201 until a low level is output to the second input end P11IN of the timing unit 50, and the timing unit 50 obtains the corresponding first discharge time T1, and calculates and obtains a first discharge capacitance difference Cx1 based on the relationship between capacitance and discharge time, and the first discharge capacitance difference Cx1 is the capacitance value of the capacitor Cx to be measured and the second parasitic capacitance C P2 The sum of the capacitance values, that is:

[0080] The first discharge capacitance difference Cx1 is: Cx1=K2*T1...(1),

[0081] in, Cx1=Cx+Cp2, Cx1 is the first discharge capacitance difference Cx1, Cx is the capacitance value of the capacitor to be measured, Cp2 is the capacitance value of the second parasitic capacitance, T1 is the first discharge time T1, Vtl2 is the discharge voltage value of the low level output by the second end P11 of the capacitor to be measured Cx, R2 is the resistance value of the discharge unit 20 corresponding to the first discharge time T1, and VH1 is the equivalent level value before the first discharge.

[0082] In the embodiment of the present invention, the first discharge time T1 corresponds to the first discharge of the measured capacitor Cx, which is recorded as the first discharge of the measured capacitor Cx, and the charging of the measured capacitor Cx before the first discharge is recorded as the first charging of the measured capacitor Cx.

[0083] In the embodiment of the present invention, the equivalent level value VH1 of the capacitor to be measured before the first discharge is a voltage value corresponding to the first charge of the capacitor to be measured Cx.

[0084] The enable end of the second three-state gate 401 is set to control the second three-state gate 401 to be in the off state, the second end P11 of the capacitor to be measured Cx is grounded, and the first three-state gate 301 is used to charge the capacitor to be measured Cx; the enable end of the first three-state gate 301 and the enable end of the second three-state gate 401 are set to control the first three-state gate 301 and the second three-state gate 401 to be in the off state, the second end P11 of the capacitor to be measured is grounded, and the first end P10 of the capacitor to be measured Cx is discharged through the first discharge structure until a low level is output to the first input end of the timing unit 50, and the timing unit 50 obtains the corresponding second discharge time T2, and calculates and obtains a second discharge capacitance difference Cx2 based on the relationship between capacitance and discharge time, and the two discharge capacitance differences are the capacitance value of the capacitor to be measured Cx and the first parasitic capacitance C P1 The sum of the capacitance values ​​is:

[0085] The second discharge capacitance difference Cx2 is: Cx2 = K1*T2, ... (2)

[0086] in, Cx2=Cx+Cp1, Cx2 is the second discharge capacitance difference Cx2, Cx is the capacitance value of the capacitor to be measured, Cp1 is the capacitance value of the first parasitic capacitance, T2 is the second discharge time T2, Vtl1 is the discharge voltage value of the low level output by the first end P10 of the capacitor to be measured Cx, R1 is the resistance value of the discharge unit corresponding to the second discharge time T2, and VH2 is the equivalent level value before the second discharge.

[0087] In the embodiment of the present invention, the second discharge time T2 corresponds to the second discharge of the measured capacitor Cx, which is recorded as the second discharge of the measured capacitor Cx, and the charging of the measured capacitor Cx after the first discharge is recorded as the second charging of the measured capacitor Cx.

[0088] In the embodiment of the present invention, the equivalent level value VH2 of the capacitor to be measured before the second discharge is a voltage value corresponding to the second charge of the capacitor to be measured Cx.

[0089] The enable end of the first three-state gate 301 is set to control the first three-state gate 301 to be in the cut-off state, the first end P10 of the capacitor to be measured Cx after discharge is suspended, and the second three-state gate 401 is used to charge the capacitor to be measured Cx; the enable end of the first three-state gate 301 and the enable end of the second three-state gate 401 are set to control the first three-state gate 301 and the second three-state gate 401 to be in the cut-off state, the first end P10 of the capacitor to be measured Cx is suspended, and the second end P11 of the capacitor to be measured Cx is discharged through the corresponding second end of the discharge unit 20 until the second end P11 of the capacitor to be measured Cx outputs a low level to the second input end P11IN of the timing unit 50, and the timing unit 50 obtains the corresponding third discharge time T3, and calculates and obtains a third discharge capacitance difference Cx3 based on the relationship between capacitance and discharge time, and the third discharge capacitance difference Cx3 is the first parasitic capacitance C P1 , the capacitance value obtained by connecting the capacitor to be measured Cx in series and the second parasitic capacitor C P2 The sum of the capacitance values, that is:

[0090] The third discharge capacitance difference Cx3 is: Cx3 = Cs1 + C p2 =K2*T3, ……(3), where Cx3 is the third discharge capacitance difference Cx3, Cx is the capacitance value of the capacitor to be tested, C p1 is the capacitance value of the first parasitic capacitor, C p2 is the capacitance value of the second parasitic capacitor, T3 is the third discharge time T3, Cs1 is the first parasitic capacitor C P1 , the capacitance value obtained after the capacitors to be measured Cx are connected in series.

[0091] In the embodiment of the present invention, the third discharge time T3 corresponds to the third discharge of the capacitor to be measured Cx, which is recorded as the third discharge of the capacitor to be measured Cx, and the charging of the capacitor to be measured Cx after the second discharge is recorded as the third charging of the capacitor to be measured Cx.

[0092] In other embodiments, the enable end of the second three-state gate 401 is set to control the second three-state gate 401 to be in the off state, the second end P11 of the capacitor to be measured Cx after discharge is suspended, and the first three-state gate 301 is used to charge the capacitor to be measured Cx; the enable end of the first three-state gate 301 and the enable end of the second three-state gate 401 are set to control the first three-state gate 301 and the second three-state gate 401 to be in the off state, the second end P11 of the capacitor to be measured Cx is suspended, and the first end P10 of the capacitor to be measured Cx is discharged through the corresponding first end of the discharge unit 20 until the first end P10 of the capacitor to be measured outputs a low level to the first input end P10IN of the timing unit 50, and the timing unit 50 obtains the corresponding third discharge time T3, and calculates the third discharge capacitance difference Cx3 based on the relationship between the capacitance and the discharge time, and the third discharge capacitance difference Cx3 is the second parasitic capacitance C P2 , the capacitance value obtained by connecting the capacitor to be measured Cx in series and the first parasitic capacitor C P1 Since the capacitance measurement circuit is symmetrical, the embodiment of the present invention is described by taking the first end P10 of the capacitor to be measured Cx as suspended and the second end P11 of the capacitor to be measured Cx as being charged by the corresponding second charging structure as an example.

[0093] In the embodiment of the present invention, based on the first discharge capacitance difference Cx1 to the third discharge capacitance difference Cx3 and the first discharge time T1 to the third discharge time T3, the capacitance value of the capacitor to be measured Cx is obtained by calculation, that is:

[0094]

[0095] In the embodiment of the present invention, the operating voltage of the discharge unit 20 corresponding to the first discharge time T1 is equal to the operating voltage of the discharge unit 20 corresponding to the second discharge time T2.

[0096] In other embodiments, the operating voltage of the discharge unit 20 corresponding to the first discharge time T1 is not equal to the operating voltage of the discharge unit 20 corresponding to the second discharge time T2.

[0097] In an embodiment of the present invention, the equivalent level value VH1 before the first discharge of the capacitor to be measured Cx is equal to the equivalent level value VH2 before the second discharge of the capacitor to be measured Cx, and the low-level discharge voltage value Vtl1 output by the first end P10 of the capacitor to be measured Cx is equal to the low-level discharge voltage value Vtl2 output by the second end P11 of the capacitor to be measured Cx.

[0098] In other embodiments, the equivalent level value VH1 before the first discharge of the capacitor to be measured Cx and the equivalent level value VH2 before the second discharge of the capacitor to be measured Cx are not equal, and the low-level discharge voltage value Vtl1 output by the first end P10 of the capacitor to be measured Cx and the low-level discharge voltage value Vtl2 output by the second end P11 of the capacitor to be measured Cx are not equal.

[0099] From equation (4), we can know that: P1 The second parasitic capacitance C P2 The measured result of the capacitance Cx to be measured is only related to the first discharge time T1 to the third discharge time T3 and the constant terms K1 to K2, thereby eliminating the first parasitic capacitance C P1 The second parasitic capacitance C p2 For the purpose of, the constant terms K1~K2 are related to the size of the resistance R1 of the discharge unit 20 corresponding to the first discharge time T1, the size of the resistance R2 of the discharge unit 20 corresponding to the second discharge time T2, the discharge voltage value Vtl1 of the low level output by the first end P10 of the capacitor Cx to be measured, the discharge voltage value Vtl2 of the low level output by the second end P11 of the capacitor Cx to be measured, the equivalent value VH1 of the capacitor Cx to be measured before the first discharge, and the equivalent level value VH2 of the capacitor Cx to be measured before the second discharge and are known quantities.

[0100] In other embodiments, Figure 7 As shown, the first charging unit 30 includes a fifth switch K5, one end of the fifth switch K5 is the first end of the first charging unit 30, connected to the first end of the discharge unit 20, the first end P10 of the capacitor to be measured Cx, and the first input end P10IN of the timing unit 50, and the other end of the fifth switch K5 is the working voltage end of the first charging unit 30; the second charging unit 40 includes a sixth switch K6, one end of the sixth switch K6 is used as the first end of the second charging unit 40, connected to the second end of the discharge unit 20, the second end P11 of the capacitor to be measured Cx, and the second input end P11IN of the timing unit 50, and the other end of the sixth switch K6 is the working voltage end of the second charging unit 40, wherein the working voltage of the working end of the first charging unit 30 and the working voltage of the working end of the second charging unit 40 are both high level;

[0101] The fifth switch K5 is opened and the sixth switch K6 is closed, the first end P10 of the capacitor Cx to be measured is connected to a low level, the second end P11 of the capacitor Cx to be measured is charged through the first end of the second charging unit 40, the fifth switch K5 is opened and the sixth switch K6 is opened, the first end P10 of the capacitor Cx to be measured is connected to a low level, and the second end P11 of the capacitor Cx to be measured is discharged through the second end of the discharge unit 20 until a low level is output to the timing unit 50, the timing unit 50 obtains the corresponding first discharge time T1, and calculates a first discharge capacitance difference Cx1 based on the relationship between capacitance and discharge time, the first discharge capacitance difference Cx1 being the capacitance value of the capacitor Cx to be measured and the second parasitic capacitance C P2 The sum of the capacitance values;

[0102] The fifth switch K5 is set to be closed and the sixth switch K6 is opened, the second end P11 of the capacitor to be measured Cx is connected to a low level, the first end P10 of the capacitor to be measured Cx is charged through the first end of the first charging unit 30, the fifth switch K5 is opened and the sixth switch K6 is opened, the second end P11 of the capacitor to be measured Cx is connected to a low level, and the first end P10 of the capacitor to be measured Cx is discharged through the first end of the discharge unit 20 until a low level is output to the timing unit 50, the timing unit 50 obtains the corresponding second discharge time T2, and calculates and obtains a second discharge capacitance difference Cx2 based on the relationship between the capacitance and the discharge time, and the second discharge capacitance difference is the capacitance value of the capacitor to be measured Cx and the first parasitic capacitance C P1 The sum of the capacitance values;

[0103] The fifth switch K5 is opened and the sixth switch K6 is closed, the first end P10 of the capacitor to be measured Cx after discharge is suspended, the second end P11 of the capacitor to be measured Cx is charged through the first end of the second charging unit 40, the fifth switch K5 is opened and the sixth switch K6 is opened, the first end P10 of the capacitor to be measured Cx is suspended, and the second end P11 of the capacitor to be measured Cx is discharged through the second end of the discharge unit 20, until the second end P11 of the capacitor to be measured Cx outputs a low level to the timing unit 50, the timing unit 50 obtains the corresponding third discharge time T3, and calculates and obtains a third discharge capacitance difference Cx3 based on the relationship between the capacitance and the discharge time, and the third discharge capacitance difference Cx3 is the first parasitic capacitance C P1 , the capacitance value obtained by connecting the capacitor to be measured Cx in series and the second parasitic capacitor C P2or the fifth switch K5 is closed and the sixth switch K6 is opened, the second end P11 of the capacitor to be measured Cx after discharge is suspended, the first end P10 of the capacitor to be measured Cx is charged through the first end of the first charging unit 30, the fifth switch K5 is opened and the sixth switch K6 is opened, the second end P11 of the capacitor to be measured Cx is suspended, and the first end P10 of the capacitor to be measured Cx is discharged through the first end of the corresponding discharge unit 20, until the first end P10 of the capacitor to be measured Cx outputs a low level to the timing unit 50, the timing unit 50 obtains the corresponding third discharge time T3, and calculates and obtains a third discharge capacitance difference Cx3 based on the relationship between the capacitance and the discharge time, and the third discharge capacitance difference Cx3 is the second parasitic capacitance C P2 , the capacitance value obtained by connecting the capacitor to be measured Cx in series and the first parasitic capacitor C P1 The sum of the capacitance values;

[0104] Based on the first discharge capacitance difference Cx1 to the third discharge capacitance difference Cx3 and the first discharge time T1 to the third discharge time T3, the capacitance value of the capacitor to be measured Cx is obtained by calculation.

[0105] In the embodiment of the present invention, the high level of the working terminal VH1 of the first charging unit 30 is equal to the high level of the working terminal VH2 of the second charging unit 40 .

[0106] In other embodiments, the high level of the working end of the first charging unit 30 is not equal to the high level of the working end of the second charging unit 40 .

[0107] In an embodiment of the present invention, the timing unit 50 is used to time the discharge process of the capacitor to be measured Cx. When the capacitor to be measured Cx starts to discharge each time, the timing unit 50 starts timing. When the capacitor to be measured Cx outputs a low level each time, the timing unit 50 stops timing to obtain the corresponding discharge time of the capacitor to be measured Cx.

[0108] In the embodiment of the present invention, Figure 8 As shown, the timing unit 50 includes a MUX (Multiplexer) unit 501 and a counting unit 502, the first input end of the MUX unit 501 serves as the first input end P10IN of the timing unit 50, the second input end of the MUX unit 501 serves as the second input end P11IN of the timing unit 50, and the output end of the MUX unit 501 is connected to the input end of the counting unit; the discharge signal of the capacitor Cx to be measured is output to the counting unit 502 through the MUX unit 501, and the counting unit 502 times the discharge process of the capacitor Cx to be measured.

[0109] In the embodiment of the present invention, Fig. 9 As shown, the capacitance measurement circuit further includes: a first buffer gate and a second buffer gate;

[0110] The input end of the first buffer gate is connected to the first end of the first charging unit 30, the first end of the discharging unit 20, and the first end P10 of the capacitor to be measured Cx, and the output end of the first buffer gate is connected to the first input end P10IN of the timing unit 50; the input end of the second buffer gate is connected to the first end of the second charging unit 40, the second end of the discharging unit 20, and the second end P11 of the capacitor to be measured Cx, and the output end of the second buffer gate is connected to the second input end P11IN of the timing unit 50;

[0111] When the voltage outputted from the first terminal P10 of the capacitor to be measured Cx reaches the threshold value of the first buffer gate, the first buffer gate outputs a low level signal to the timing unit 50, and the timing unit 50 stops timing;

[0112] When the voltage output by the second terminal P11 of the capacitor to be measured Cx reaches the threshold value of the second buffer gate, the second buffer gate outputs a low level signal to the timing unit 50, and the timing unit 50 stops timing, wherein the threshold value of the first buffer gate 60 is set according to the operating voltage corresponding to the second discharge time T2 corresponding to the discharge unit 20, and the threshold value of the second buffer gate 70 is set according to the operating voltage corresponding to the first charging time corresponding to the discharge unit 20.

[0113] In other embodiments, the first buffer gate is a first comparator, and the second buffer gate is a second comparator. When the voltage outputted by the first terminal P10 of the capacitor to be measured Cx is lower than the comparison voltage of the first comparator, the first comparator outputs a low-level signal to the timing unit 50, and the timing unit 50 stops timing. When the voltage outputted by the second terminal P11 of the capacitor to be measured Cx is lower than the comparison voltage of the second comparator, the second comparator outputs a low-level signal to the timing unit 50, and the timing unit 50 stops timing.

[0114] The capacitance measurement circuit provided by the present invention is simple in design, does not require a specially designed circuit, can completely eliminate the influence of parasitic capacitance, and is easy to produce and apply.

[0115] Finally, it is to be noted that any modification or equivalent replacement of part or all of the technical features based on the device structure of the present invention and the technical solution of the described embodiment, which does not deviate from the essence of the corresponding technical solution of the present invention, belongs to the patent scope of the device structure of the present invention and the described implementation scheme.

Claims

1. A capacitance measurement method, characterized in that: include: Providing a capacitor to be measured, wherein two ends of the capacitor to be measured are equivalently connected to a first parasitic capacitor and a second parasitic capacitor; The first terminal of the capacitor to be measured is connected to a low level, the second terminal of the capacitor to be measured is connected to a high level and charging is completed, the second terminal of the capacitor to be measured is discharged through the second terminal of the discharge unit until a low level is output, a corresponding first discharge time is obtained, and a first discharge capacitance difference is calculated based on the relationship between the capacitance and the discharge time, where the first discharge capacitance difference is the sum of the capacitance value of the capacitor to be measured and the capacitance value of the second parasitic capacitance; The second terminal of the capacitor to be measured is connected to a low level, the first terminal of the capacitor to be measured is connected to a high level and charging is completed, the first terminal of the capacitor to be measured is discharged through the first terminal of the discharge unit until a low level is output, a corresponding second discharge time is obtained, and a second discharge capacitance difference is calculated based on the relationship between the capacitance and the discharge time, where the second discharge capacitance difference is the sum of the capacitance value of the capacitor to be measured and the capacitance value of the first parasitic capacitance; One end of the capacitor to be tested after discharge is suspended, the other end of the capacitor to be tested is connected to a high level and charging is completed, the end of the capacitor to be tested connected to the high level is discharged through the corresponding discharge unit until the end of the capacitor to be tested that is discharged outputs a low level, a corresponding third discharge time is obtained, and a third discharge capacitance difference is calculated based on the relationship between capacitance and discharge time, where the third discharge capacitance difference is the sum of the capacitance value obtained by connecting the first parasitic capacitance and the capacitor to be tested in series and the capacitance value of the second parasitic capacitance, or the sum of the capacitance value obtained by connecting the second parasitic capacitance and the capacitor to be tested in series and the capacitance value of the first parasitic capacitance; Based on the first discharge capacitance difference value to the third discharge capacitance difference value and the first discharge time value to the third discharge time value, a capacitance value of the capacitor to be measured is obtained by calculation.

2. A capacitance measurement method as claimed in claim 1, characterized in that: The first end of the capacitor to be measured after discharge is suspended, the second end of the capacitor to be measured is connected to a high level and charging is completed, the second end of the capacitor to be measured is discharged through the second end of the discharge unit until the second end of the capacitor to be measured outputs a low level, and the corresponding third discharge time is obtained. A third discharge capacitance difference is calculated based on the relationship between the capacitance and the discharge time, and the third discharge capacitance difference is the sum of the capacitance value obtained by connecting the first parasitic capacitance and the capacitor to be measured in series and the capacitance value of the second parasitic capacitance.

3. A capacitance measurement method as claimed in claim 2, characterized in that: The first discharge capacitance difference is: Cx1 = K2*T1, in, Cx1=Cx+C p2 , Cx1 is the first discharge capacitance difference, Cx is the capacitance value of the capacitor to be measured, C p2 is the capacitance value of the second parasitic capacitor, T1 is the first discharge time, Vtl2 is the discharge voltage value of the second end of the capacitor to be measured outputting a low level, R2 is the resistance value of the discharge unit corresponding to the first discharge time, and VH1 is the equivalent level value before the first discharge; The second discharge capacitance difference is: Cx2 = K1*T2, in, Cx2=Cx+C p1 , Cx2 is the second discharge capacitance difference, Cx is the capacitance value of the capacitor to be measured, C p1 is the capacitance value of the first parasitic capacitor, T2 is the second discharge time, Vtl1 is the discharge voltage value of the first end of the capacitor to be measured outputting a low level, R1 is the resistance value of the discharge unit corresponding to the second discharge time, and VH2 is the equivalent level value before the second discharge; The third discharge capacitance difference is: Cx3 = Cs1 + C p2 =K2*T3, where Cx3 is the third discharge capacitance difference, Cx is the capacitance value of the capacitor to be tested, C p1 is the capacitance value of the first parasitic capacitor, C p2 is the capacitance value of the second parasitic capacitor, T3 is the third discharge time, Cs1 is the capacitance value obtained by connecting the first parasitic capacitor and the capacitor to be measured in series; The capacitance value of the capacitor to be measured is obtained according to the calculation formula of the first discharge capacitance difference to the third discharge capacitance difference and the first discharge time to the third discharge time:

4. A capacitance measurement method as claimed in claim 1, characterized in that: The capacitor to be measured is a capacitive sensor.

5. A capacitance measurement circuit, characterized in that: A capacitance measurement method according to claim 1, comprising: A discharge unit, a first charging unit, a second charging unit, and a timing unit; The first end of the discharge unit is connected to the first end of the first charging unit and the first input end of the timing unit and is used as the first end of the capacitance measurement circuit to connect the first end of the capacitance to be measured, and the second end of the discharge unit is connected to the first end of the second charging unit and the second input end of the timing unit and is used as the second end of the capacitance measurement circuit to connect the second end of the capacitance to be measured, wherein the two ends of the capacitance to be measured are equivalently connected to the first parasitic capacitance and the second parasitic capacitance; The first charging unit is set to be cut off, the first end of the capacitor to be measured is connected to a low level, the capacitor to be measured is charged by the second charging unit, and the second end of the capacitor to be measured is discharged through the second end of the discharge unit until a low level is output to the timing unit, the timing unit obtains a corresponding first discharge time, and calculates a first discharge capacitance difference based on a relationship between capacitance and discharge time, wherein the first discharge capacitance difference is the sum of the capacitance value of the capacitor to be measured and the capacitance value of the second parasitic capacitance; The second charging unit is set to be cut off, the second end of the capacitor to be measured is connected to a low level, the capacitor to be measured is charged by the first charging unit, the first end of the capacitor to be measured is discharged through the first end of the discharge unit, until a low level is output to the timing unit, the timing unit obtains a corresponding second discharge time, and a second discharge capacitance difference is calculated based on a relationship between capacitance and discharge time, the second discharge capacitance difference is the sum of the capacitance value of the capacitor to be measured and the capacitance value of the first parasitic capacitance; The first charging unit is set to be cut off, the first end of the capacitor to be tested after discharge is suspended, the capacitor to be tested is charged by the second charging unit, and the capacitor to be tested is discharged by the discharge unit until the second end of the capacitor to be tested outputs a low level to the timing unit, the timing unit obtains the corresponding third discharge time, and the third discharge capacitance difference is calculated based on the relationship between capacitance and discharge time, and the third discharge capacitance difference is the sum of the capacitance value obtained by connecting the first parasitic capacitance and the capacitor to be tested in series and the capacitance value of the second parasitic capacitance; or the second charging unit is set to be cut off, the second end of the capacitor to be tested after discharge is suspended, the capacitor to be tested is charged by the first charging unit, and the capacitor to be tested is discharged by the discharge unit until the first end of the capacitor to be tested outputs a low level to the timing unit, the timing unit obtains the corresponding third discharge time, and the third discharge capacitance difference is calculated based on the relationship between capacitance and discharge time, and the third discharge capacitance difference is the sum of the capacitance value obtained by connecting the second parasitic capacitance and the capacitor to be tested in series and the capacitance value of the first parasitic capacitance; Based on the first discharge capacitance difference value to the third discharge capacitance difference value and the first discharge time value to the third discharge time value, a capacitance value of the capacitor to be measured is obtained by calculation.

6. A capacitance measuring circuit as claimed in claim 5, characterized in that: The discharge unit includes a first discharge structure and a second discharge structure; the first discharge structure includes a first resistor and a first switch, the first resistor and the first switch are connected in series to form a first series structure, one end of the first series structure serves as one end of the first discharge structure, and the other end of the first series structure serves as the other end of the first discharge structure, one end of the first discharge structure is connected to the first end of the first charging unit, the first input end of the timing unit, and the first end of the capacitor to be measured, and the other end of the first discharge structure is the working voltage end of the first discharge structure; the second discharge structure includes a second resistor and a second switch, the second resistor and the second switch are connected in series to form a second series structure, one end of the second series structure serves as one end of the second discharge structure, and the other end of the second series structure serves as the other end of the second discharge structure, one end of the second discharge structure is connected to the first end of the second charging unit, the second input end of the timing unit, and the second end of the capacitor to be measured, and the other end of the second discharge structure is the working voltage end of the second discharge structure; When the first charging unit is turned off, the second charging unit is turned off, the first switch in the first discharge structure is closed, and the second switch in the second discharge structure is opened, the first end of the capacitor to be measured is discharged through the first discharge structure; When the first charging unit is turned off, the second charging unit is turned off, the first switch in the first discharge structure is opened, and the second switch in the second discharge structure is closed, the second end of the capacitor to be measured is discharged through the second discharge structure.

7. A capacitance measuring circuit as claimed in claim 5, characterized in that: The discharge unit comprises a third discharge substructure, a third switch and a fourth switch, one end of the third discharge substructure is connected to one end of the third switch and one end of the fourth switch, the other end of the third switch serves as the first end of the discharge unit, is connected to the first end of the first charging unit, the first input end of the timing unit, and the first end of the capacitor to be measured, and the other end of the fourth switch serves as the second end of the discharge unit, is connected to the first end of the second charging unit, the second input end of the timing unit, and the second end of the capacitor to be measured; When the first charging unit is turned off, the second charging unit is turned off, the third switch is closed, and the fourth switch is opened, the first end of the capacitor to be measured is discharged through the third discharge substructure; when the first charging unit is turned off, the second charging unit is turned off, the third switch is opened, and the fourth switch is closed, the second end of the capacitor to be measured is discharged through the third discharge substructure.

8. A capacitance measuring circuit as claimed in claim 5, characterized in that: The first charging unit includes a first tri-state gate, the output end of the first tri-state gate is connected to the first end of the discharge unit, the first end of the capacitor to be measured, and the first input end of the timing unit, the output end of the first tri-state gate serves as the first end of the first charging unit, the enable end of the first tri-state gate is used to receive an enable signal, and the input end of the first tri-state gate is used to input a control signal; The second charging unit includes a second three-state gate, the output end of the second three-state gate is connected to the second end of the discharge unit, the second end of the capacitor to be measured, and the second input end of the timing unit, the output end of the second three-state gate serves as the first end of the second charging unit, the enable end of the second three-state gate is used to receive an enable signal, and the input end of the second three-state gate is used to input a control signal; The enable end of the first three-state gate is set to control the first three-state gate to be in an off state, the first end of the capacitor to be measured is connected to a low level, and the second three-state gate is used to charge the capacitor to be measured; the enable end of the first three-state gate and the enable end of the second three-state gate are set to control the first three-state gate and the second three-state gate to be in an off state, the first end of the capacitor to be measured is grounded, and the second end of the capacitor to be measured is discharged through the second end of the discharge unit until a low level is output to the second input end of the timing unit, the timing unit obtains the corresponding first discharge time, and calculates a first discharge capacitance difference based on the relationship between the capacitance and the discharge time, and the first discharge capacitance difference is the sum of the capacitance value of the capacitor to be measured and the capacitance value of the second parasitic capacitance; The enable end of the second three-state gate is set to control the second three-state gate to be in an off state, the second end of the capacitor to be measured is connected to a low level, and the first three-state gate is used to charge the capacitor to be measured; the enable end of the first three-state gate and the enable end of the second three-state gate are set to control the first three-state gate and the second three-state gate to be in an off state, the second end of the capacitor to be measured is grounded, and the first end of the capacitor to be measured is discharged through the first end of the discharge unit until a low level is output to the first input end of the timing unit, the timing unit obtains the corresponding second discharge time, and calculates a second discharge capacitance difference based on the relationship between the capacitance and the discharge time, and the two discharge capacitance differences are the sum of the capacitance value of the capacitor to be measured and the capacitance value of the first parasitic capacitor; The enable end of the first three-state gate is set to control the first three-state gate to be in the cut-off state, the first end of the capacitor to be measured after discharge is suspended, and the capacitor to be measured is charged by the second three-state gate; the enable end of the first three-state gate and the enable end of the second three-state gate are set to control the first three-state gate and the second three-state gate to be in the cut-off state, and the second end of the capacitor to be measured is discharged through the corresponding second end of the discharge unit until the second end of the capacitor to be measured outputs a low level to the second input end of the timing unit, and the timing unit obtains the corresponding third discharge time, and calculates the third discharge capacitance difference based on the relationship between the capacitance and the discharge time, and the third discharge capacitance difference is the sum of the capacitance value obtained by connecting the first parasitic capacitance and the capacitor to be measured in series and the capacitance value of the second parasitic capacitance; or The enable end of the first three-state gate is set to control the first three-state gate to be in a cut-off state, the second end of the capacitor to be measured after discharge is suspended, and the capacitor to be measured is charged by using the first three-state gate; the enable end of the first three-state gate and the enable end of the second three-state gate are set to control the first three-state gate and the second three-state gate to be in a cut-off state, the first end of the capacitor to be measured is discharged through the corresponding first end of the discharge unit until the first end of the capacitor to be measured outputs a low level to the first input end of the timing unit, the timing unit obtains the corresponding third discharge time, and calculates the third discharge capacitance difference based on the relationship between the capacitance and the discharge time, the third discharge capacitance difference is the sum of the capacitance value obtained by connecting the second parasitic capacitance and the capacitor to be measured in series and the capacitance value of the first parasitic capacitance.

9. A capacitance measuring circuit as claimed in claim 5, characterized in that: The first charging unit includes a fifth switch, one end of the fifth switch is the first end of the first charging unit, connected to the first end of the discharge unit, the first end of the capacitor to be measured, and the first input end of the timing unit, and the other end of the fifth switch is the working voltage end of the first charging unit; the second charging unit includes a sixth switch, one end of the sixth switch is the first end of the second charging unit, connected to the second end of the discharge unit, the second end of the capacitor to be measured, and the second input end of the timing unit, and the other end of the sixth switch is the working voltage end of the second charging unit, wherein the working voltage of the working end of the first charging unit and the working voltage of the working end of the second charging unit are both high level; The fifth switch is opened and the sixth switch is closed, the first end of the capacitor to be measured is connected to a low level, the second end of the capacitor to be measured is charged through the first end of the second charging unit, the fifth switch is opened and the sixth switch is opened, the second end of the capacitor to be measured is discharged through the second end of the discharge unit, until a low level is output to the timing unit, the timing unit obtains a corresponding first discharge time, and calculates a first discharge capacitance difference based on a relationship between capacitance and discharge time, the first discharge capacitance difference being the sum of the capacitance value of the capacitor to be measured and the capacitance value of the second parasitic capacitance; The fifth switch is set to be closed and the sixth switch is set to be opened, the second end of the capacitor to be measured is connected to a low level, the first end of the capacitor to be measured is charged through the first end of the first charging unit, the fifth switch is set to be opened and the sixth switch is set to be opened, the second end of the capacitor to be measured is connected to a low level, and the first end of the capacitor to be measured is discharged through the first end of the discharge unit until a low level is output to the timing unit, the timing unit obtains a corresponding second discharge time, and calculates a second discharge capacitance difference based on a relationship between capacitance and discharge time, the second discharge capacitance difference being the sum of the capacitance value of the capacitor to be measured and the capacitance value of the first parasitic capacitance; The fifth switch is opened and the sixth switch is closed, the first end of the capacitor to be measured is suspended after discharge, the second end of the capacitor to be measured is charged through the first end of the second charging unit, the fifth switch is opened and the sixth switch is opened, the second end of the capacitor to be measured is discharged through the second end of the discharge unit, until the second end of the capacitor to be measured outputs a low level to the timing unit, the timing unit obtains the corresponding third discharge time, and calculates a third discharge capacitance difference based on the relationship between the capacitance and the discharge time, the third discharge capacitance difference being the sum of the capacitance value obtained by connecting the first parasitic capacitance and the capacitor to be measured in series and the capacitance value of the second parasitic capacitance; or the fifth switch is closed and the sixth switch is opened, the second end of the capacitor to be measured after discharge is suspended, the first end of the capacitor to be measured is charged through the first end of the first charging unit, the fifth switch is opened and the sixth switch is opened, the first end of the capacitor to be measured is discharged through the first end of the discharge unit, until the first end of the capacitor to be measured outputs a low level to the timing unit, the timing unit obtains the corresponding third discharge time, and calculates a third discharge capacitance difference based on the relationship between the capacitance and the discharge time, the third discharge capacitance difference being the sum of the capacitance value obtained by connecting the second parasitic capacitance and the capacitor to be measured in series and the capacitance value of the first parasitic capacitance; Based on the first discharge capacitance difference value to the third discharge capacitance difference value and the first discharge time value to the third discharge time value, a capacitance value of the capacitor to be measured is obtained by calculation.

10. A capacitance measuring circuit as claimed in claim 5, characterized in that: The capacitance measurement circuit further includes: a first buffer gate and a second buffer gate; The input end of the first buffer gate is connected to the first end of the first charging unit, the first end of the discharging unit, and the first end of the capacitor to be measured, and the output end of the first buffer gate is connected to the first input end of the timing unit; the input end of the second buffer gate is connected to the first end of the second charging unit, the second end of the discharging unit, and the second end of the capacitor to be measured, and the output end of the second buffer gate is connected to the second input end of the timing unit; When the voltage outputted from the first end of the capacitor to be tested reaches the threshold value of the first buffer gate, the first buffer gate outputs a low level signal to the timing unit, and the timing unit stops timing to obtain the corresponding discharge time; When the voltage outputted from the second end of the capacitor to be measured reaches the threshold of the second buffer gate, the second buffer gate outputs a low level signal to the timing unit, and the timing unit stops timing to obtain the corresponding discharge time.

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